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The document discusses using linear regression models to analyze processor performance by linking it to microarchitectural elements. It describes using Akaike's Information Criteria and iterative modeling to create error-bounded linear models. The models found pipeline depth, reorder buffer size, and issue queue size as the most critical factors impacting processor performance.

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0% found this document useful (0 votes)
9 views

Document 1

The document discusses using linear regression models to analyze processor performance by linking it to microarchitectural elements. It describes using Akaike's Information Criteria and iterative modeling to create error-bounded linear models. The models found pipeline depth, reorder buffer size, and issue queue size as the most critical factors impacting processor performance.

Uploaded by

hazrul9629
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Chapter 2

P.J.Joseph [06] wrote “Construction and use of linear regression model for processor

performance analysis” by explaining establishment of linear regression models using

simulation-based experiments that links processor performance to micro-architectural

elements. Model construction methodology that was apply are:

2.1 Akaike’s Information Criteria ( AIC )

2.2 Measure of model adequacy

2.3 Iterative Procedure

AIC was utilized to select a model that fits well and has a minimal number of parameters,

resulting in the inclusion of the most significant effect in the model and reducing the model

over-fitting problem. Maximum error of estimation coefficients was used as main measure for

model adequacy, the error can be obtained by an equation. The model construction begins

with three inputs, the number of elements tested, the maximum acceptable error and the

desired confidence level, then outputs Error Bounded Linear Models (EBLMs). The steps are

as follow, creating an initial D-optimal experimental design with 2m runs for an initial linear

model that includes all main effects and obtaining the best linear model , measuring the error

variance and maximum error in estimated coefficients and stopping and finalising the model

if the error is below a certain threshold and residual plots show no significant deviations and

finally augmenting the experimental design with additional D-optimal experiments if the

error is not satisfactory and returning to second step to obtain best linear model for the new

augmented design. The approach outlined can be used to generate linear models with

whatever level of precision desired. This approach was built as a MATLAB script that accepts

the necessary inputs and completed simulation experimental data and returns either accurate

coefficient estimations or a prescription for further investigation. The variables inside the

experiments are :
independent variable : 26 of the micro-architectural parameters

dependent variable : EBLM of the weighted mean CPI response computed from the EBLMs

constructed

Summarizing the information gotten from the EBLMs values, pipeline depth, reorder buffer

size, and issue queue size are the three most critical criteria impacting CPI performance of

superscalar processors. The two-factor and three-factor interactions involving these three

parameters are extremely significant. As a result, a processor architect should optimize these

settings simultaneously for optimal system performance. Next, model construction diagnosis

shows understanding actual CPI changes produced by effects in this range, they investigated

them while keeping all other parameters at appropriately chosen center points. They find that

they account for less than 2% of the variation. As a result, error boundaries smaller than 0.01

are only required for examining performance changes at a finer level. The error bounding

approach can be used to build models with any level of precision.

REFERENCE

Joseph, P., Vaswani, K., & Thazhuthaveetil, M. (n.d.). Construction and Use of Linear

Regression Models for Processor Performance Analysis. The Twelfth International

Symposium on High-Performance Computer Architecture, 2006.

https://doi.org/10.1109/hpca.2006.1598116

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