sensors

Article
Simulations and Design of a Single-Photon CMOS
Imaging Pixel Using Multiple Non-Destructive
Signal Sampling
Konstantin D. Stefanov 1, * , Martin J. Prest 1 , Mark Downing 2 , Elizabeth George 2 ,
Naidu Bezawada 2 and Andrew D. Holland 1
1 Centre for Electronic Imaging, The Open University, Walton Hall, Milton Keynes MK7 6AA, UK;
[email protected] (M.J.P.); [email protected] (A.D.H.)
2 European Southern Observatory, Karl-Schwarzschild-Strasse 2, D-85748 Garching, Germany;
[email protected] (M.D.); [email protected] (E.G.); [email protected] (N.B.)
* Correspondence: [email protected]; Tel.: +44-1908-332116




Received: 20 February 2020; Accepted: 2 April 2020; Published: 4 April 2020


Abstract: A single-photon CMOS image sensor (CIS) design based on pinned photodiode (PPD)
with multiple charge transfers and sampling is described. In the proposed pixel architecture, the
photogenerated signal is sampled non-destructively multiple times and the results are averaged.
Each signal measurement is statistically independent and by averaging, the electronic readout noise
is reduced to a level where single photons can be distinguished reliably. A pixel design using this
method was simulated in TCAD and several layouts were generated for a 180-nm CMOS image sensor
process. Using simulations, the noise performance of the pixel was determined as a function of the
number of samples, sense node capacitance, sampling rate and transistor characteristics. The strengths
and limitations of the proposed design are discussed in detail, including the trade-off between noise
performance and readout rate and the impact of charge transfer inefficiency (CTI). The projected
performance of our first prototype device indicates that single-photon imaging is within reach and
could enable ground-breaking performances in many scientific and industrial imaging applications.

Keywords: CMOS image sensors (CIS); single-photon imaging; pinned photodiode

1. Introduction
Single-photon (SP) imaging offers the ultimate performance in an imaging system due to its
ability to capture and register each incoming photon [1,2]. This is particularly valuable in low light
level conditions where every photon is precious, such as in astronomy, adaptive optics, night vision,
surveillance and bio-imaging. In silicon (the most widely used semiconductor for image sensors),
a single-photon with a wavelength between 300 and 1100 nm can generate only one electron–hole
pair. Therefore, for visible and near-infrared light, the task of single-photon detection becomes a task
of single-electron (or hole) detection. This is not easy due to the unavoidable readout noise of the
sensor, which is usually too high for the reliable detection of a single electron. Another difficulty for
room temperature applications are the thermal dark currents, because they are indistinguishable from
photogenerated signals; however, dark signals can be reduced to negligible levels by cooling.
Two main methods for achieving SP sensitivity are used in semiconductor image sensors. In the
first one, the photogenerated charge is amplified internally by a physical process before the conversion
to voltage. In this way, the signal is lifted well above the noise floor, allowing reliable SP detection.
Typical examples are single-photon avalanche photodiodes (SPAD) and electron multiplying CCDs
(EMCCD), in which the primary photogenerated electron undergoes avalanche multiplication. Both

Sensors 2020, 20, 2031; doi:10.3390/s20072031 www.mdpi.com/journal/sensors

Sensors 2020, 20, 2031 2 of 12

can resolve single photons; however, they suffer from shortcomings such as high dark current rates
and after-pulsing in SPADs [3], and spurious charge and excess noise [4] in EMCCDs due to traps and
the use of high voltages.
The second method involves reducing the readout noise of a sensor to a fraction of one electron
RMS equivalent noise charge (ENC). Studies have shown [5] that for a practical single-photon imager
with a negligible error rate that the ENC must be below 0.15 e- RMS. Recent advances in CMOS image
sensor (CIS) technology have reduced readout noise significantly, and CISs with an ENC below 0.3 e-
RMS have been reported [6–8]. These developments are due to the increase of the conversion gain
of the sensors above 200 µV/e- by the use of special design and processing techniques, as well as
by improvements to the noise performance of MOSFETs. Further noise improvements using those
methods are certainly possible, however difficulties increase as the noise approaches the required level
of 0.15 e- RMS.
Recently, a new take on the well-known “skipper CCD” technique [9–11] has demonstrated deep
sub-electron readout noise [12,13]. In skipper CCDs, the charge is transferred under a floating gate in
the buried channel (BC) multiple times and is measured after each transfer. Because the measurements
are non-destructive and nearly statistically independent, averaging reduces the readout noise by the
square root of the number of readouts. In [13], readout noise of only 0.068 e- RMS has been achieved
after 4000 measurements, using an amplifier exhibiting 3.55 e- ENC in a single measurement. A similar
method has been used for DEPFETs [14] to achieve 0.18 e- RMS noise in a sensor with inherent 3.1 e-
ENC. The skipper technique is attractive because it can achieve sub-electron noise performance using
the designs, processes and MOSFETs available today. However, a major disadvantage of the multiple
readouts is the greatly increased readout time, which can take several hours for CCDs [13]. For a more
practical device, the readout time must be reduced to at least a few seconds (e.g., for slow astronomical
imaging), and to few milliseconds for applications requiring a much higher frame rate.
CMOS image sensors could potentially offer the needed increase in speed due to the inherent
parallelism in their readout. In the vast majority of CISs, an entire row of pixels is read out
simultaneously, which could reduce the readout time by three orders of magnitude compared to a
sensor with a single or a smaller number of outputs such as the CCD. In addition, the finer feature
size in modern CISs allows the conversion gain of a floating gate readout circuitry to be much higher
than in CCDs. This finer feature size enables a substantial reduction of the readout noise in a single
measurement, necessitating fewer signal samples to be averaged.
Sub-electron readout noise CMOS image sensors capable of high readout rates would be useful
for many applications. In the field of astronomy, large-format sensors with a size of at least 4K x 4K
pixels, readout at a rate of a few frames a second, would allow measurement of transient phenomena
or observation techniques that require high time resolutions and low noise, such as speckle imaging.
Lucky imaging [15], for example, works best with noiseless image stacking, and could benefit from
this development. Smaller sensors that can be readout at rates of 0.5–1 kHz would replace EMCCDs in
adaptive optics applications. Similarly, in bio-imaging applications such as molecular fluorescence
imaging, these larger format sensors would enable microscope images to cover a larger field with
single-photon sensitivity.
In this paper we investigate the suitability of CIS-based skipper designs to achieving deep
sub-electron readout noise for single-photon visible light imaging. The operating principles and TCAD
simulations are presented in Section 2, followed by a noise analysis in Section 3 and a description of a
proposed layout and its expected performance in Section 4.

2. Operating Principles
The most widely used pixel architecture in modern CISs is based on the pinned photodiode
(PPD) [16]. The PPD achieves very low dark currents due to its pinning implant, low image lag
and high conversion gain, which it achieves by using a small sense node separate from the charge
collection region. The PPD relies on the efficient transfer of charge to the sense node, where the
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characteristics  and  charge  transfer  capabilities,  the  PPD  is  one  candidate  for  constructing  a  pixel 
capable of multiple‐signal sampling. 
conversion to voltage occurs after the charge has been collected. Due to its excellent electro-optical
Another  possibility 
characteristics and chargeis  a transfer
low‐voltage  CCD  manufactured 
capabilities, the PPD is one in  a  CMOS  process, 
candidate as  used  in 
for constructing a time 
pixel
delay 
capable integration  (TDI)  image 
of multiple-signal sampling.sensors.  High‐performance  CCD‐in‐CMOS  devices  use  buried 
channels to achieve efficient multiple charge transfers, and can have high conversion gain and low 
Another possibility is a low-voltage CCD manufactured in a CMOS process, as used in time delay
noise on a par with the PPD thanks to a small sense node. BC process modules are now routinely 
integration (TDI) image sensors. High-performance CCD-in-CMOS devices use buried channels to
offered by several CIS foundries to help the design of TDI imagers. Buried channel CCD‐in‐CMOS 
achieve efficient multiple charge transfers, and can have high conversion gain and low noise on a
devices 
par withhave  demonstrated 
the PPD thanks to charge 
a small transfer  inefficiencies 
sense node. BC process (CTIs)  as  low 
modules are as 
now 10‐5routinely
  per  transfer  [17]. 
offered by
However, their dark currents are much higher than in PPDs because the Si–SiO
several CIS foundries to help the design of TDI imagers. Buried channel CCD-in-CMOS 2 interface at the BC 
devices have
demonstrated charge transfer inefficiencies (CTIs) as low as 10−5 per transfer [17]. However, their dark
is not inverted. 
Based on these considerations, we have chosen the PPD as the photosensitive element in this 
currents are much higher than in PPDs because the Si–SiO2 interface at the BC is not inverted.
development due to its superior dark currents, and have combined it with a BC CCD‐based structure 
Based on these considerations, we have chosen the PPD as the photosensitive element in this
for the multiple‐signal sampling. Figure 1 shows the simplified diagram of the proposed pixel. As 
development due to its superior dark currents, and have combined it with a BC CCD-based structure
performed normally, the charge is transferred from the PPD by the transfer gate (TG). Following the 
for the multiple-signal sampling. Figure 1 shows the simplified diagram of the proposed pixel. As
TG  is  a  BC normally,
performed structure, 
thewhere 
chargethe  charge  is from
is transferred kept, the
transferred 
PPD by theand  sampled 
transfer multiple 
gate (TG). times the
Following non‐
TG
destructively.    where the charge is kept, transferred and sampled multiple times non-destructively.
is a BC structure,

 
Figure 1. Diagram of the proposed pixel. 
Figure 1. Diagram of the proposed pixel.

The first sense gate (SG1) is used to capacitively measure the signal stored under it. The voltage 
The first sense gate (SG1) is used to capacitively measure the signal stored under it. The voltage
on SG1 is buffered by the source follower M1, which connects to the column output line via the row 
on SG1 is buffered by the source follower M1, which connects to the column output line via the row
select transistor M2. Here, output drain (OD) is the DC supply to the source follower and SEL is the 
select transistor M2. Here, output drain (OD) is the DC supply to the source follower and SEL is the
control signal to the gate of the row select transistor. The transistor M5 is used to lower the potential 
control signal to the gate of the row select transistor. The transistor M5 is used to lower the potential
on SG1 to substrate so that the charge can be transferred to SG2. 
on SG1 to substrate so that the charge can be transferred to SG2.  
Figure 
Figure2 2shows 
showsthe thepotential 
potentialdiagrams 
diagramsof  of the 
the pixel 
pixel during 
during its 
its operation. 
operation. Before 
Beforethe thecharge 
chargeis  is
transferred out of the PPD, in step 1 the voltage on SG1 is reset to the reset drain (RD) potential by 
transferred out of the PPD, in step 1 the voltage on SG1 is reset to the reset drain (RD) potential by
turning both transistors M3 and M4 on. In step 2, the transfer gate (TG) is pulsed high and the charge 
turning both transistors M3 and M4 on. In step 2, the transfer gate (TG) is pulsed high and the charge
stored under the PPD is transferred under SG1, followed by turning off the TG in step 3. In step 4, 
stored under the PPD is transferred under SG1, followed by turning off the TG in step 3. In step 4, the
the  storage 
storage gategate 
SG2SG2  is  reset 
is reset and insulating
and the the  insulating  gate  (IG1) 
gate (IG1) is  biased 
is biased in  preparation 
in preparation for the for 
charge the  transfer
charge 
transfer from SG1 to SG2 in step 5. SG1 is then lowered to substrate potential by applying a pulse to 
from SG1 to SG2 in step 5. SG1 is then lowered to substrate potential by applying a pulse to the CG of
the CG of M5 while M3 and M4 are turned off, which makes the charge move under SG2. 
M5 while M3 and M4 are turned off, which makes the charge move under SG2.  
Once the charge has been transferred, as shown in step 6, SG1 is reset by turning on M3 and M4, 
Once the charge has been transferred, as shown in step 6, SG1 is reset by turning on M3 and M4,
with M5 turned off (step 7). After this, the transistors M3 and M4 are turned off and the reset level 
with M5 turned off (step 7). After this, the transistors M3 and M4 are turned off and the reset level
on SG1 is read out via the source follower M1 as required to implement correlated double sampling 
on SG1 is read out via the source follower M1 as required to implement correlated double sampling
(CDS). Next, the potential on SG2 is lowered so that the charge can be transferred back under SG1 
(CDS). Next, the potential on SG2 is lowered so that the charge can be transferred back under SG1 (step
(step 8). After the transfer is complete, the amount of charge under SG1 is measured by differencing 
8). After the transfer is complete, the amount of charge under SG1 is measured by differencing the
the  voltage 
voltage levellevel  on  SG1 
on SG1 and theand  the  previously 
previously taken 
taken reset reset  sample. 
sample. By  repeating 
By repeating steps 4 tosteps 
10, it4 isto  10,  it  is 
possible to
possible to measure the signal charge under SG1 multiple times non‐destructively. 
measure the signal charge under SG1 multiple times non-destructively.  
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Figure 1 shows SG1 as the floating gate used for the measurement; however, SG1 and SG2 are
Figure 1 shows SG1 as the floating gate used for the measurement; however, SG1 and SG2 are 
interchangeable and either can be used if they connect to M1. Furthermore, SG1 and SG2 can be
interchangeable  and 
connected to their owneither  can  be readout
separate used  if  circuits,
they  connect  to  M1. 
consisting ofFurthermore,  SG1  and 
a source follower, rowSG2  can and
select be 
connected to their own separate readout circuits, consisting of a source follower, row select and reset 
reset transistors. Figure 2 shows that the reset and the signal time periods on SG1 and SG2 are in
transistors. Figure 2 shows that the reset and the signal time periods on SG1 and SG2 are in anti‐
anti-phase, so that the reset level on SG1 can be measured simultaneously with the signal level on
phase, so that the reset level on SG1 can be measured simultaneously with the signal level on SG2 
SG2 and vice versa, as in steps 7 and 10, respectively. This makes it possible to use both SG1 and SG2
and vice versa, as in steps 7 and 10, respectively. This makes it possible to use both SG1 and SG2 for 
for multiple-signal sampling, thus reaching the required number of samples in half the time. The
multiple‐signal 
downsides to thissampling, 
approachthus  reaching 
are the the number
increased required 
of number  of  which
transistors, samples  in  half 
occupy the  time. 
a larger area, The 
and
downsides to this approach are the increased number of transistors, which occupy a larger area, and 
the need to have two outputs per pixel, since the signals from SG1 and SG2 appear concurrently. In
the need to have two outputs per pixel, since the signals from SG1 and SG2 appear concurrently. In 
addition, the gain difference between the two non-destructive readout paths would make the signal
addition, the gain difference between the two non‐destructive readout paths would make the signal 
processing more challenging. In this work we have considered sampling only for SG1, as shown in
proce 
Figure 1.

Figure 2. Timing diagram of the charge transfer in the proposed pixel. 
Figure 2. Timing diagram of the charge transfer in the proposed pixel.

After enough measurements have been made, the charge can be transferred out of the BC. This
After enough measurements have been made, the charge can be transferred out of the BC. This 
can be done by pulsing IG2 after the sense node has been reset in advance by the transistor M3 while
can be done by pulsing IG2 after the sense node has been reset in advance by the transistor M3 while 
M4 is turned on. This allows a conventional readout of the signal with CDS, after which the charge is
M4 is turned on. This allows a conventional readout of the signal with CDS, after which the charge is 
destroyed. Alternatively, the charge can simply be dumped to the sense node without reading it. In
destroyed. Alternatively, the charge can simply be dumped to the sense node without reading it. In 
any case, the charge in the BC must be cleared before the next charge is transferred from the PPD.  
any case, the charge in the BC must be cleared before the next charge is transferred from the PPD. 
The pixel architecture relies on efficient multiple charge transfers in a BC CCD with low channel
The pixel architecture relies on efficient multiple charge transfers in a BC CCD with low channel 
potential
potential VVch0 . Typically, the PPD pinning voltage is in the range between 1.0 and 1.5 V, which implies
ch0. Typically, the PPD pinning voltage is in the range between 1.0 and 1.5 V, which implies 
that the CCD channel potential must be of a similar value. We performed TCAD simulations based on
that the CCD channel potential must be of a similar value. We performed TCAD simulations based 
a 180-nm
on  CIS process
a  180‐nm  usingusing 
CIS  process  a customized BC implant
a  customized  to achieve
BC  implant  to  V ch0 = 2 V.
achieve  The
Vch0   =  simulations modeled a
2  V.  The  simulations 
PPD and a BC with four gates, as shown in Figure 2, using Athena (for process and device generation)
modeled a PPD and a BC with four gates, as shown in Figure 2, using Athena (for process and device 
and Atlas (for device simulation) commercial software from Silvaco Inc. Using simulated light, a
generation) and Atlas (for device simulation) commercial software from Silvaco Inc. Using simulated 
charge was generated in the PPD and collected, then transferred out to the BC by pulsing the TG. This
light, a charge was generated in the PPD and collected, then transferred out to the BC by pulsing the 
was not different from normal PPD operation.
TG. This was not different from normal PPD operation.   
Figure 3a–c 
Figure  3a–c shows 
shows the 
the potential 
potential in 
in the 
the BC 
BC and 
and the 
the size 
size of 
of the 
the stored 
stored charge 
charge during 
during transfer, 
transfer,
demonstrating that the charge was stored away from the Si–SiO22 interface, which is needed for a good 
demonstrating that the charge was stored away from the Si–SiO interface, which is needed for a good
CTI. Figure 3d shows the potential along the middle of the buried channel when IG1 is biased to 0.5 V
CTI. Figure 3d shows the potential along the middle of the buried channel when IG1 is biased to 0.5 
and acts as a potential barrier between SG1 and SG2, both biased at 2 V. During the charge transfer
V and acts as a potential barrier between SG1 and SG2, both biased at 2 V. During the charge transfer 
between SG1
between  SG1 and and SG2, IG1
SG2,  is held
IG1  at anat intermediate
is  held  constant
an  intermediate  voltagevoltage 
constant  in orderin  to order 
reduceto 
thereduce 
capacitive
the 
capacitive  coupling  to  SG1  from  the  clock  voltage  on  SG2.  Simulations  indicate  that  the  charge 
transfer between SG1 and SG2 completes within 0.2 ns for signals of less than 100 electrons, which is 
Sensors 2020, 20, 2031 5 of 12

coupling to SG1 from the clock voltage on SG2. Simulations indicate that the charge transfer between
Sensors 2020, 20, x FOR PEER REVIEW    5  of  12 
SG1 and SG2 completes within 0.2 ns for signals of less than 100 electrons, which is to be expected
considering the short gate length. Because of this, the charge transfer time is likely to be negligible
to be expected considering the short gate length. Because of this, the charge transfer time is likely to 
comparedbe negligible compared to the signal sample time, which is in the range of few hundred nanoseconds. 
to the signal sample time, which is in the range of few hundred nanoseconds.

 
Figure 3. Simulated potential profile in the buried channel and electron density plots for the charge
Figure 3. Simulated potential profile in the buried channel and electron density plots for the charge 
stored under SG1 (a), during transfer from SG1 to SG2 (b) and for the charge stored under SG2 (c). Plot
stored under SG1 (a), during transfer from SG1 to SG2 (b) and for the charge stored under SG2 (c). 
(d) shows Plot (d) shows the potential along the dashed lines in (a), (b) and (c). 
the potential along the dashed lines in (a–c).

3. Expected Performance 
3. Expected Performance
3.1. Readout Noise 
3.1. Readout Noise
We  can  calculate  the  expected  noise  performance  of  a  CIS  using  the  described  multiple  non‐
We can calculate the expected noise performance of a CIS using the described multiple
destructive signal sampling. The following considerations assume that a whole pixel row is read out 
non-destructive signal sampling. The following considerations assume that a whole
simultaneously using column‐parallel circuitry, as is the norm in most CMOS image sensors.    pixel row
is read out simultaneously using
The  voltage  noise  column-parallel
density  of  the  source  follower  𝑒 as
circuitry,   (in isunits  of  V⁄√Hz
the norm in most
)  as  a CMOS
function image
of  the  sensors.
√
The voltage 𝑓  can be expressed as 
frequency noise density of the  source follower en (in units of V/ Hz) as a function of the
frequency f can be expressed as 𝑒 𝑒 p 1 𝑓 ⁄𝑓   (1) 
where  𝑒   is  the  white  noise  density  = enw
en and  + f1nc⁄/
𝑓   is 1the  𝑓   fnoise  corner  frequency,  defined  as  the  (1)
frequency where the white and the  1⁄𝑓  noise have the same power. The signal readout is assumed 
where enw to use dual slope integrator (DSI) circuitry, which has a nearly ideal signal‐to‐noise ratio (SNR) for 
is the white noise density and fnc is the 1/ f noise corner frequency, defined as the frequency
white and the 1/ f noise have the same power.
where thesignals dominated by white noise and with negligible  The signal readout is assumed to use
1⁄𝑓  noise. The noise performance of the DSI 
dual slopecan be approximated by digital multi‐sampling [18], which is widely used in modern low‐noise CISs. 
integrator (DSI) circuitry, which has a nearly ideal signal-to-noise ratio (SNR) for signals
dominated by white noise and with negligible 1/ f noise. The noise performance of𝑉the
With the in‐pixel source follower being the dominant noise source, the RMS noise voltage    at the 
DSI can be
output of a DSI circuit is given by [19] 
approximated by digital multi-sampling [18], which is widely used in modern low-noise CISs. With
the in-pixel source follower being the dominant 𝑉 𝑒 noise 4𝑓 ln2  the RMS noise voltage Vn at(2) 
2𝑓 source, the output
of a DSI circuit
where is𝑓  given by [19]frequency.  The  time pperiod  of  one  signal  measurement  is  𝑇 1⁄𝑓   and 
is  the  readout 
comprises the reset and the signal samples. To convert to input‐referred ENC we divide Equation (2) 
Vn = enw 2 fr + 4 fnc ln 2 (2)

where fr is the readout frequency. The time period of one signal measurement is Tr = 1/ fr and
comprises the reset and the signal samples. To convert to input-referred ENC we divide Equation (2)
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by the charge-to-voltage conversion gain SV = q/Cn , where q is the elementary charge and Cn is the
total capacitance of the sense node. The ENC of one signal measurement becomes
enw p
Qn_1 = 2 fr + 4 fnc ln 2 . (3)
SV

After performing
√ N independent signal measurements the ENC of the average decreases to
Qn_N = Qn_1 / N. Therefore, to reach the ENC threshold for single-electron detection Qn_sp , taken as
Qn_sp = 0.15 e- RMS [5], the number of measurements Nsp must be
Sensors 2020, 20, x FOR PEER REVIEW    6  of  12 
 2
Nsp =
by the charge‐to‐voltage conversion gain  𝑆 Q𝑞n_1
⁄𝐶 /Q n_sp 𝑞  is the elementary charge and  𝐶   is the 
, where  (4)
total capacitance of the sense node. The ENC of one signal measurement becomes 
Substituting Equation (3) into (4) gives the𝑒 number of required signal measurements:
𝑄 _ 2𝑓 4𝑓 ln2 .  (3) 
𝑆
!2
After  performing  𝑁  independent  signal 
enw measurements  the  ENC  of  the  average  decreases  to 
𝑄 Nsp = (2 fr + 4 fnc ln 2)
𝑄 _ /√𝑁. Therefore, to reach the ENC threshold for single‐electron detection  𝑄 _ , taken as  (5)
_ SV Qn_sp
𝑄 _   0.15 e‐ RMS [5], the number of measurements  𝑁   must be 
The time to read one pixel, which is equal
𝑁 to 𝑄
the   time of one image row trow ,(4) 
readout
_ ⁄𝑄 _
becomes
Substituting Equation (3) into (4) gives the number of required signal measurements: 
!2 !
enw 4 fnc ln 2
trow = Nsp Tr = 𝑒 2+ (6)
𝑁 SV Qn_sp2𝑓 4𝑓 ln2   fr (5) 
𝑆 𝑄 _

Whether an imager using multiple-signal averaging can find a practical application

The time to read one pixel, which is equal to the readout time of one image row  𝑡 , becomes 
depends
  on
the number of samples Nsp needed to reach single-photon 𝑒 sensitivity.
4𝑓 ln2 From Equation (5) we can see
𝑡 𝑁 𝑇 2
that to reduce Nsp it is very important to reduce enw and
𝑆 𝑄 _ maximize 𝑓 SV
 
due to the quadratic (6)  dependence.
At readout frequencies well above the noise corner frequency, which are likely to
Whether an imager using multiple‐signal averaging can find a practical application depends on be used in order to
reduce the the number of samples 
readout time, the second term in Equation (6) levels off to two.
𝑁   needed to reach single‐photon sensitivity. From Equation (5) we can see 
that  to  reduce  𝑁of  the
After optimization it  is source
very  important 
follower’sto  reduce  𝑒  length
channel and  maximize  𝑆   due 
and width, itsto noise
the  quadratic 
performance is
dependence. At readout frequencies well above the noise corner frequency, which are likely to be 
determined mainly by the foundry process, leaving the conversion gain SV as the most important
used in order to reduce the readout time, the second term in Equation (6) levels off to two.   
parameter in Equation (6) to address. Using typical transistor noise parameters for 180 nm CMOS
After optimization of the source follower’s channel length and width, its noise performance is 
image sensor process, we can calculate the number of samples and the row
determined mainly by the foundry process, leaving the conversion gain  readout time as a function
𝑆   as the most important 
parameter in Equation (6) to address. Using typical transistor noise parameters for 180 nm CMOS 
of SV . As a representative example, Figure 4 shows the number of samples Nsp required to achieve
image sensor process, we can calculate the number of samples and the row readout time as a function  √
single-photon sensitivity (Qn_sp = 0.15 e- RMS), calculated from Equation (5) for enw = 30 nV/ Hz
of  𝑆 . As a representative example, Figure 4 shows the number of samples  𝑁   required to achieve 
and fnc = 330 kHz. These parameters  are
single‐photon sensitivity (𝑄 typical and were not taken for a specific
0.15 e‐ RMS), calculated from Equation (5) for  𝑒 foundry;
30 nV/√Hz however,
_
we expect to see
and  𝑓 gradual improvements in the future from advances in the processing technology for
330 kHz. These parameters are typical and were not taken for a specific foundry; however, 
we expect to see gradual improvements in the future from advances in the processing technology for 
low-noise transistors.
low‐noise transistors. 

 
Figure  4. of
Figure 4. Number Number  of  averaged 
averaged samplessamples 
for 0.15for e-0.15 
RMS e‐  RMS 
ENCENC  for  different 
for different conversion gains
conversion gains  as 
as a 
a function
function of the time required for a single sample for  𝑒 √30 nV/√Hz  and  𝑓 330 kHz. 
of the time required for a single sample for enw = 30 nV/ Hz and fnc = 330 kHz.
Sensors 2020, 20, 2031 7 of 12
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Figure 4 shows that the required number of samples falls as 
Figure 4 shows that the required number of samples falls as 1/T 1⁄𝑇r  and
and levels off at long sample 
levels off at long sample
times due to the increasing fraction of 1/f noise in the total. We are interested in assessing a large 
times due to the increasing fraction of 1/f noise in the total. We are interested in assessing a large
number of
number of samples
samples in in aa short
short amount
amount ofof time,
time, therefore
therefore itit isis important
important that
that the 1⁄f𝑓 noise
the 1/ noise corner
corner 
frequency is well below the readout frequency. 
frequency is well below the readout frequency.  
Figure 5 shows the number of image sensor rows that can be read out per second, which is equal 
Figure 5 shows the number of image sensor rows that can be read out per second, which is equal
to  1/𝑡   calculated from Equation (6) for the same conditions as in Figure 4. For the highest used 
to 1/trow calculated from Equation (6) for the same conditions as in Figure 4. For the highest used
gain (SV  == 100 μV/e‐) we can see that a megapixel‐scale sensor with 1000 rows and >1000 
conversion gain (𝑆
conversion 100 µV/e-) we can see that a megapixel-scale sensor with 1000 rows and >1000
columns can achieve a readout rate exceeding 100 fps when the time for one sample is shorter than 
columns can achieve a readout rate exceeding 100 fps when the time for one sample is shorter than
about 300
about 300 
ns.ns.  This 
This is  within 
is within the  capabilities 
the capabilities of  existing 
of existing CIS  technology, 
CIS technology, and  indicates 
and indicates that  this 
that this approach
be practical. Even for SV = 10 µV/e-,
approach can be practical. Even for 
can 𝑆   = 10 μV/e‐, which should be easier to achieve with a floating 
which should be easier to achieve with a floating gate, a
gate, a megapixel‐scale sensor should be able to reach one frame per second. 
megapixel-scale sensor should be able to reach one frame per second.  

 
Figure Line
Figure 5.5.  rate
Line  forfor 
rate  0.150.15 
e- RMS ENCENC 
e‐  RMS  for different conversion
for  different  gains asgains 
conversion  a function of the time
as  a  function  of required
the  time 
for a single sample.
required for a single sample. 

The readout rates calculated above depend very much on the noise characteristics of the used CIS
The readout rates calculated above depend very much on the noise characteristics of the used 
process and whether the required conversion gain can be achieved. Further on, we investigate pixel
CIS process and whether the required conversion gain can be achieved. Further on, we investigate 
layouts based on the TCAD simulations shown in Figure 3 and on the design rules of a 180-nm process
pixel layouts based on the TCAD simulations shown in Figure 3 and on the design rules of a 180‐nm 
from a leading CIS foundry.
process from a leading CIS foundry.   
3.2. Linearity and Full Well Capacity
3.2. Linearity and Full Well Capacity 
It is important that the method of capacitive charge measurement is linear (i.e., the signal depends
It  is  important  that  the  method  of  capacitive  charge  measurement  is  linear  (i.e.,  the  signal 
linearly on the amount of charge under SG1). A simulation of the voltage on SG1 was performed at
depends  linearly  on  the  amount  of  charge  under  SG1).  A  simulation  of  the  voltage  on  SG1  was 
increasing signal sizes for the model shown in Figure 3, with the results shown in Figure 6. The signal
performed at increasing signal sizes for the model shown in Figure 3, with the results shown in Figure 
response had linearity, defined as the deviation of the data from the line of best fit, of better than 1%.
6. The signal response had linearity, defined as the deviation of the data from the line of best fit, of 
The slope of the straight-line fit provided a conversion gain of 83.4 µV/e- for a SG1 gate with length of
better than 1%. The slope of the straight‐line fit provided a conversion gain of 83.4 μV/e‐ for a SG1 
1 µm. The effective gate capacitance of SG1 in this model did not include contributions from the source
gate  with  length  of  1  μm.  The  effective  gate  capacitance  of  SG1  in  this  model  did  not  include 
follower and the reset transistor in Figure 1, but took into account the gate capacitance to the BC and
contributions from the source follower and the reset transistor in Figure 1, but took into account the 
the gate-to-gate edge capacitances.
gate capacitance to the BC and the gate‐to‐gate edge capacitances.   
The depth of the 2D model is 1 µm, which corresponds to a BC width of the same size. In the
The depth of the 2D model is 1 μm, which corresponds to a BC width of the same size. In the 
simulation, the charge stored under SG1 began to fill up the potential well and come into contact with
simulation, the charge stored under SG1 began to fill up the potential well and come into contact with 
the Si–SiO2 interface above 2000 e-, which severely degraded the CTI. This corresponded to a full well
the Si–SiO2 interface above 2000 e‐, which severely degraded the CTI. This corresponded to a full well 
capacity (FWC) of 2 ke- per µm of channel width. If needed, the signal capacity can be increased by
capacity (FWC) of 2 ke‐ per μm of channel width. If needed, the signal capacity can be increased by 
widening the BC at the expense of reducing the conversion gain, since SG1 is widened as well.
widening the BC at the expense of reducing the conversion gain, since SG1 is widened as well.   
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The FWC of the proposed sensor is dominated by the BC CCD due to its small size, and the 
Sensors 2020, 20, x FOR PEER REVIEW    8  of  12 
area taken up by the PPD is also smaller than in a typical PPD pixel. This 
The FWC of the proposed sensor is dominated by the BC CCD due to its   small size, and the area
The FWC of the proposed sensor is dominated by the BC CCD due to its small size, and the 
taken up by the PPD is also smaller than in a typical PPD pixel. This would not be a major limitation if
area taken up by the PPD is also smaller than in a typical PPD pixel. This    additional noise.
a high readout rate were used, due to the ability to stack the images without

Figure 6. Simulated voltage on SG1 as a function of the amount of charge under SG1. The simulation 
is in 2D with a 1‐μm depth in the third dimension corresponding to the BC width. 
Figure 6. Simulated voltage on SG1 as a function of the amount of charge under SG1. The simulation is
Figure 6. Simulated voltage on SG1 as a function of the amount of charge under SG1. The simulation 
4. Design
in 2D with a 1-µm depth in the third dimension corresponding to the BC width.
is in 2D with a 1‐μm depth in the third dimension corresponding to the BC width. 
4. Design
4.4.1. Pixel Design 
Design  
Based 
4.1. Pixel on  a  reference  10‐μm  pitch  PPD  pixel,  we  created  several  designs  suitable  for 
Design
4.1. Pixel Design   
implementation in a prototype image sensor. Figure 7 shows the bottom part of the PPD, the buried 
Based on a reference 10-µm pitch PPD pixel, we created several designs suitable for implementation
channel and the readout transistors of an example pixel layout. The PPD occupies approximately 40% 
in a Based  on  image
prototype a  reference 
sensor. 10‐μm 
Figure 7pitch 
showsPPD  pixel,  we 
the bottom part created  several 
of the PPD, designs 
the buried suitable 
channel and for 
the
of the pixel area, and the BC extends from the TG in a straight line towards the edge of the pixel. 
implementation in a prototype image sensor. Figure 7 shows the bottom part of the PPD, the buried 
readout transistors of an example pixel layout. The PPD occupies approximately 40% of the pixel area,
More compact layouts with higher fill factors are possible if the BC is bent by 90 degrees under the 
channel and the readout transistors of an example pixel layout. The PPD occupies approximately 40% 
and the BC extends from the TG in a straight line towards the edge of the pixel. More compact layouts
PPD.   
of the pixel area, and the BC extends from the TG in a straight line towards the edge of the pixel. 
with higher fill factors are possible if the BC is bent by 90 degrees under the PPD.
More compact layouts with higher fill factors are possible if the BC is bent by 90 degrees under the 
PPD.   

Figure 7. Example pixel layout using a 180-nm CIS process showing the BC elements and the readout
circuitry. Only the bottom part of the PPD is displayed.
Figure 7. Example pixel layout using a 180‐nm CIS process showing the BC elements and the readout 
circuitry. Only the bottom part of the PPD is displayed. 
Figure 7. Example pixel layout using a 180‐nm CIS process showing the BC elements and the readout 
circuitry. Only the bottom part of the PPD is displayed. 
Sensors 2020, 20, 2031 9 of 12

In this layout, the total capacitance of SG1 has been estimated by capacitance extraction from the
Cadence Virtuoso CAD software, giving 2.63 fF and SV = 61 µV/e-. This conversion gain is lower than
the one derived from the TCAD simulation in Section 3.2 due to the inclusion of the source follower and
all other parasitic capacitances, but is still high enough to allow sensors with single-photon sensitivity
to be built. Using a 1-MHz readout frequency, Equation (3) gives ENC = 0.88 e- RMS for a single
measurement and a line rate of nearly 30,000 rows/s with averaging of 34 samples to finally achieve
ENC = 0.15 e- RMS. This would translate to 30 fps from a 1-Mpixel sensor. In comparison, an EMCCD
with the same format (e.g., CCD201-20 from Teledyne e2v) achieves 14 fps with sub-electron noise at a
15-MHz serial pixel rate.

4.2. Performance Limitations

The suitability of the proposed sensor for its target applications depends on many factors. The
first and perhaps the most important is the noise for a single-charge measurement, which we addressed
in Section 3. The other factors we need to consider are the image lag in the PPD, the CTI in the buried
channel and the dark current in the device.
The PPD can suffer from incomplete charge transfer, called image lag [16], due to the slow electron
transport and potential barriers and pockets along the transport path. Various methods involving
potential gradients inside or outside the PPD have been developed to reduce the image lag. The most
widely used one creates a potential gradient under the transfer gate using an implant, achieving an
image lag below 0.1% [20]. At this low level the lag is unlikely to be a limiting factor.
Tens or even hundreds of charge transfers have to be made during the multiple-signal measurement,
and the charge can spend long time in the BC, during which it can be captured by traps. If the trap
emission time constant is short, some of the charge can be re-emitted into its own signal packet;
otherwise, it will merge with the next one and be lost. We can expect the trap concentration in modern
CIS processes to be low, and its impact on the CTI can be estimated from the available literature data.
The worst-case CTI is seen when every trap in the volume swept by the charge packet is empty
and able to trap an electron, a process characterized by a capture time constant [21]. If subsequent
re-emission into the same packet does not occur, the CTI is simply
nt
CTI = (7)
ns

where nt is the trap density and ns is the signal charge density. To our knowledge, the best CTI achieved
in a BC CCD-in-CMOS device is 10−5 for a 5-µm pixel [17]. The usual signal size for a CTI measurement
is 1620 electrons, generated by X-rays from a 55 Fe source. From Equation (7) we can calculate that
a CTI of 10−5 corresponds to 0.0162 active traps in a pixel area of 5 × 5 µm, since the traps and the
signal occupy the same volume. The channel area used for charge transfer in the layout in Figure 7
is approximately 2 × 3 µm; this translates to 3.9 × 10−3 traps/pixel, or one in 257 pixels containing
a trap. Fortunately, the capture time constant for small charges is large [21], because it is inversely
proportional to the signal density. Therefore, we can expect the effects of charge trapping to be much
less than the worst case described above, which assumes that every trap captures an electron.
The buried channel operates in non-inverted mode and therefore its dark current density is likely
to be in the region of several nA/cm2 [17] at room temperature. If we take the optimistic value of
1 nA/cm2 , counting on future technology improvements, the dark current in the BC with an area of
6 µm2 is 375 e-/s. During a typical row readout time of 30 µs (corresponding to 30 samples at 1 µs each)
this would generate 0.011 dark current electrons on average. Using a metal shield over the buried
channel in front-side illuminated sensors may be necessary to block out parasitic light and prevent
spurious signals. In back-side illuminated sensors, a buried p-well under the BC can be used instead.
The dark current density from the PPD is much lower due to the pinning implant and is usually
below 1 pA/cm2 ; however, the PPD collects the charge from the whole pixel area. If we take the dark
current density in the PPD as 1 pA/cm2 and the pixel area as 10 × 10 µm, the number of dark current
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electrons per pixel at 100 fps will be 0.0625. Longer integration times can increase this figure to a level 
electrons per pixel at 100 fps will be 0.0625. Longer integration times can increase this figure to a level
where single‐photon detection becomes compromised.   
where single-photon detection becomes compromised.
Dark current shot noise from the BC and PPD add in quadrature with the electronic noise and 
Dark current shot noise from the BC and PPD add in quadrature with the electronic noise and is a
is a fundamental limitation to single‐photon imaging. Short exposure times and cooling can be used 
fundamental limitation to single-photon imaging. Short exposure times and cooling can be used to
to reduce the dark current. For long exposures, the operating temperature of the sensor has to be 
reduce the dark current. For long exposures, the operating temperature of the sensor has to be reduced
reduced significantly, and can be as low as ‐100 C, as it typical for astronomical CCDs.   
significantly, and can be as low as −100 ◦ C, as it typical for astronomical CCDs.
4.3. Sensor Architecture 
4.3. Sensor Architecture
Figure 8 shows the block diagram of the proposed SP image sensor. Similar to a mainstream CIS, 
Figure 8 shows the block diagram of the proposed SP image sensor. Similar to a mainstream CIS,
the sensor includes a row address decoder, row clock drivers, CDS circuitry and an ADC for each 
the sensor includes a row address decoder, row clock drivers, CDS circuitry and an ADC for each
pixel column. The raw data rate from the ADC array is likely to be very high due to the multiple 
pixel column. The raw data rate from the ADC array is likely to be very high due to the multiple
signal  samples;  therefore  it  would  be  much  more  convenient  and  power‐efficient  to  perform  the 
signal samples; therefore it would be much more convenient and power-efficient to perform the signal
signal averaging on‐chip. Taking data from the ADCs, a dedicated circuitry in each column is added 
averaging on-chip. Taking data from the ADCs, a dedicated circuitry in each column is added to
to perform the digital accumulation of the multiple samples, which is then scaled to obtain the signal 
perform the digital accumulation of the multiple samples, which is then scaled to obtain the signal
average. A dual slope ADC that integrates the reset and signal levels with opposite signs could also 
average. A dual slope ADC that integrates the reset and signal levels with opposite signs could also
perform the role of an averager when operating on each sample consecutively. Following the digital 
perform the role of an averager when operating on each sample consecutively. Following the digital
averager, the data are multiplexed and read out serially on one or several sensor outputs. In the block 
averager, the data are multiplexed and read out serially on one or several sensor outputs. In the block
diagram in Figure 8, the row and the column addresses and the pixel control signals are provided 
diagram in Figure 8, the row and the column addresses and the pixel control signals are provided
externally to the image sensor; however, they can be generated on‐chip by a state machine residing 
externally to the image sensor; however, they can be generated on-chip by a state machine residing in
in the control block.   
the control block.
 

 
Figure 8. Block diagram of the proposed image sensor.
Figure 8. Block diagram of the proposed image sensor. 

The increase of peripheral circuitry compared to a traditional CIS is modest because accumulation
The  increase  of  peripheral  circuitry  compared  to  a  traditional  CIS  is  modest  because 
and scaling are relatively simple operations that can be implemented efficiently in digital logic. In a
accumulation  and  scaling  are  relatively  simple  operations  that  can  be  implemented  efficiently  in 
more advanced design using 3D integration [22], the peripheral circuitry (including averaging) can be
digital logic. In a more advanced design using 3D integration [22], the peripheral circuitry (including 
placed on a separate digital tier.
averaging) can be placed on a separate digital tier. 
The expected performance of the proposed image sensor can be compared with existing devices
The expected performance of the proposed image sensor can be compared with existing devices 
such as skipper CCDs, EMCCDs, high-conversion-gain CISs and SPADs. A major advantage of the
such as skipper CCDs, EMCCDs, high‐conversion‐gain CISs and SPADs. A major advantage of the 
proposed implementation in CMOS technology over the skipper CCD [13] is the greatly increased 
Sensors 2020, 20, 2031 11 of 12

proposed implementation in CMOS technology over the skipper CCD [13] is the greatly increased
frame rate, which could be three orders of magnitude higher. This is due to the massive parallel readout
possible in CISs, while offering the same or better noise performance. This sensor could have similar
characteristics to an EMCCD operated in a photon counting mode [4], but without the drawbacks
of using high voltages such as gain ageing and clock-induced charge generation, which reduce the
photon detection probability [23]. CISs with high conversion gains do not offer true single-photon
sensitivity yet [7]. Our proposed design has adjustable noise characteristics depending on the number
of samples, and could be better than a high-conversion-gain CIS, but it is slower due to the multiple
sampling. Our design is also much slower than SPADs [3], but does not suffer from a high dark count
rate due to the absence of avalanche gain. This skipper CMOS design therefore provides several
advantages over existing technologies, combining single-photon detection at high frame rates with
CMOS compatible-voltages and no spurious signal.

5. Conclusions and Outlook

We have presented a concept for a single-photon image sensor using multiple non-destructive
signal sampling in CMOS image sensor technology. By averaging multiple signal samples that are
statistically independent, the readout electronic noise can be reduced by the square root of the number
of samples. This allows the noise level to be reduced to ENC < 0.15 e- RMS, a level widely considered
necessary for single electrons to be reliably distinguished. This will allow imaging to be limited only
by the shot noise of the registered photons, and to be free from electronic noise.
The proposed pixel design uses a pinned photodiode as a photosensitive element, and a buried
channel CCD per pixel for multiple charge transfer and non-destructive signal readouts via capacitive
coupling between a sense gate and the signal charge. A pixel design using this method was simulated
in TCAD, and several layouts were generated for a 180-nm CMOS image sensor process. Significant
increases in the readout speed over the equivalent “skipper CCD” technique are possible due to the
massive parallel readout in CMOS image sensors. Using simulations, the noise performance of the
pixel was determined as a function of the number of samples, sense node capacitance, sampling rate
and transistor characteristics.
The presented results show that single-photon imaging using multiple non-destructive signal
sampling in CIS technology is viable. Our designs and simulations indicate that a megapixel-scale
sensor operating at ~100 fps is feasible using present-day technology. Such a sensor could find numerous
applications in science and technology in fields such as astronomy, adaptive optics, biological imaging,
quantum technologies and autonomous systems.
Future work will involve the manufacturing of a prototype CIS using several variants of the
described pixel design. Following that, a full-scale imager with digital signal averaging implemented
on chip will be the next objective of our work.

Author Contributions: Conceptualization, K.D.S.; Investigation, K.D.S., M.J.P., M.D., E.G. and N.B.; Formal
analysis and TCAD simulations, K.D.S. and M.J.P.; Schematic designs and layout, M.J.P.; Writing – original draft,
K.D.S. and E.G.; Writing – review & editing, M.D., E.G. and N.B.; Supervision, A.D.H.; Funding acquisition, K.D.S.
and M.D. All authors have read and agreed to the published version of the manuscript.
Funding: This project has received funding from the ATTRACT project funded by the EC under Grant
Agreement 777222.
Conflicts of Interest: The authors declare no conflict of interest.

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