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Vlsi 1

This document discusses VLSI design techniques. It covers: 1. Combinational and sequential logic circuits using CMOS technology. Common gates include AND, OR, inverters. 2. Static CMOS design uses complementary MOS transistors for low power consumption and improved noise margins. 3. Design techniques to reduce propagation delay such as ratioed logic, cascode voltage switch logic. Skew in gates is also addressed.

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Dinesh Kumar
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0% found this document useful (0 votes)
37 views

Vlsi 1

This document discusses VLSI design techniques. It covers: 1. Combinational and sequential logic circuits using CMOS technology. Common gates include AND, OR, inverters. 2. Static CMOS design uses complementary MOS transistors for low power consumption and improved noise margins. 3. Design techniques to reduce propagation delay such as ratioed logic, cascode voltage switch logic. Skew in gates is also addressed.

Uploaded by

Dinesh Kumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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VLSI DESIN

Cùraits
Cembinati onql As
Many inpt oulput
Cunent inpute
opat de prodr
and Exanples -
Combina
Adder
H'aal Vout aaitplcxer
conveie
3. Pail Geneoat 4. cock
Vn

(O Staho cMOS nthoris. -Prid


and
NMOs
Prnos
CPnos
stahe CMoS Uses
Vop 4 Vcs.
op conrecled o
Erxogy Effeient
fast b dsign
Adr fan in.
(3) Sage
a) Copleentay CMoS Gatercorret olp
PuN Vss
VDo 2. PDN connect olp
Shahe Cmos , Low
3.
1h2 PuN PUN ig G-LouU -nmos
nmos - ON -DFF
inN
A. Gale - high
Hth- Pm- ojf G-lao, Pras- oN
in2 PoN 5. Gate -
.OM0S
Vss
seieS- Ano Porallel - oR
Parallkl- AND,
Sehes - pull doun
-
q. pavallel Coonecho of Tran sisho pall p,
b.
of compleenary mos Gater:

perallel- o
o.
Ptnos
A
Oe-teganle Theoem
The
C.
Prggatioo dlay
VoD Vpp
Cmos

Each Trqos'sko
Gole -

A (
Series cei

ídeal Soitch.
A
A

d
Design Toehiniquer
gcduce Suttehg
Reshuckrg:- chang te topolgr f ge ohs
02

02
chain shuche shchue

2) Tpat oderuy i
Z
A

Glirch Reduchon . tmtrmatch of pats Tog.


|2

a) Bubble pushig

Ntrd Inverld OR NoR

F: Aß+ Co NANo and OR Gates


A Ano gatt cse bubble at
OR at Vp
A Gale : (
Ard- OR - CnVelr fupckn
Vop

A
.B4C.p A-d

A 42 P123
Parasthc delo
C Inpat Ore GND
AC -Doun 2+ 2Jj

Take

Reset = B,
d Galer Decocare th
Value
A
B = Resc -
VDp

Y
A

Rasct
e Shecved ales -
InVcrler
= unSEeued

conskewed InVerteri -
Hi Skew
Low-Skw:

Pr CMo Invcole!
L0-S5eco

A
W,p ihv : 2
Wp inN 2
th Lo Ske o
Cn beucd,

High shcw R'3uy


R
3

o5
2
(nSBcvCd - COS NANo

Jlo
Np NaND 2

NANO: Np > n
H-sbco ip Nn
Np, NND 2 B
NnAND
NpNAND2

ConSbeed - ChnoS NOR


as

Inveiter
Nn,inv =|
2x pin
2X224
Lo.shU CMOS NoR: -

D
Hi-sew NDR: ) Wp <
wp NDR 4 Wp, NDR > 1/2 2
A WnNDR>

P Rabos: -
Raio of plnos to nmoS.
giate ttan omos

8 tulkpk
theot Volles malhbplk Vt.
Ceph haate
(2) Ratioed chts
sze pesistole
Depthndi on Of deic
oxeckan Oahon.
PpN - oFf, Op- I
R PpN- ON OJp - o

Reduce no. of Tranti.


PoN is Dcplacect by
Siogle rcndial
deice always o
nMoS Rahoed qates.
i) seadlo- nmos
VDD
os Logie VDD

Pos Is ab DN.
A

GND B4L
Tnveater
NAND 2

B Series
A nmor

OFF

Geresc O fF ON
Gorged CMoS ON

ON ON
Also called NoR
VDD

A A Pi

A B NI Pi Y
OFF ON Off oN I

OFF ON OF
ON
oN ofF OFF
OFF ofF
Cascode Noltaqe Svitch Lgte / D'f le senhal
Voitage Scoñch Logic : (cvsL // DC.Dc VSL) -
Cascodc anssto Scics
ot PDN - DFF
Any p -0.CPrnos)
I4 PDN - bN - MaBc
oN fre ohr
These olp tun
Y
Pnos.
VDD
T
T-oN

GNP

combinahn of YA.B.
True and conplerentay
B =0
A B AND NANp A 4C ={

NANO.
ANO
cvsL ANo/NANO GAE.

Disad
Adv: Raho cht delay
Reduce

Uscel Deal sail DopO (8)

VDp

y =D

JED
Auhosatcally
oh -of, OFF Foot
At
Omar Herc
oN
VOD
rduee does
no
-ON Nmor | A
. Ls =mr-
ON +oClk
nverter
- yanio Fooled
B off NMOS
:EValuakn. cihHC 0
L A
|n3.
PeN
N P-4 AB+c uy=lRraare
VDD PrOs-ON
Eg.
VoD
Y
Reehasge oN Mn
off Mp
Rcharge MpoN
Evaea
te
PDN. Locu
odue (6)Valuahon
igh p- ofe Pmar- prcciage O
pnos clock
ode tuo :-opesle CsB
TnVester. DybamiC
olr
Vdd
A
CS
VoD bycht
tansith. pull.
p cocsecd tfe
ciiruit ynamie
dracubaCs
of tte sishs Tean Pmos
rahoed In
Dyraie
Foted :
NAND 2
NOR 2 Cntoted
VDA VDD
VDD
T
ABC
A

B
H

DisadV s
Appli
AdV cardul ). MuX.
2. ide NOR
e cap 2. MoIC DoiSC fune.
2. NO contenton dung code Convertr.

B.a. Donioo CK
ad n vere.
Combinahön of aynama ON
y ,X0.
VDD OFF
X I.
MP

NOR!-
PDN
VDP
VDp
Mn

ab
VDp
in NMOS Ntmo
GNO
Vor
VT. Vo
-!Uhit -Reje
trantist Pas
Vaut
bigh -wite
- h
. GY
tec Oeno
. and h e kach code En
cwireo.
IhValíd
Precharged
meabig h
GalCo Nomin0 Degl.
ba
AND Ano/ Inverter)
GND
yh
AB
VpD
VDD
merttig
on and all
pgte KoninD RailDlal Bb
-
B
A

B
B

AB
AND Galc

B
AB Y Val

1 A:Vbp
B =0.
OR Gale
vin

peeudo- no Domino
VDp
VDP

5.
Tsansmission Gales
Reger unit
lao
A b.
witt Chyor Tran. Galr

VoD

A M2

MI

Malkplexer (MOSTG)
Transmosion Gate

'=Aigh A =B-l

-0,

B
B
GNP
Tsans. Gate xOR

CooTG VbD
B

A NI

NI
N2

A4C
Tristate InVeoter
VDD ENB Prnos-DN
NMor-Ff
A
F
Y
EN EB =0

EN Y= A
Nor-ON

F D
Teiltat
Zrydoa.
A EN A ENG

Hi

Hi-.

5.a. conpkroay
Ofsenbial Pai AB Y
Tranri ter Iegie.
Ans pa
A
A F =At8

E
A

B -FA8
OR/NOR
AND NAND XOR NOR
F:AB

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