CMOS Logic Design

Dinesh Sharma
EE Department, IIT Bombay

September 2, 2021
Contents

1 Static CMOS Logic Design 3

1.1 Static CMOS Design style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 CMOS Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2.1 Static Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2.2 Noise margins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.2.3 Dynamic Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.2.4 Trade off between power, speed and robustness . . . . . . . . . . . . . 15
1.2.5 CMOS Inverter Design Flow . . . . . . . . . . . . . . . . . . . . . . . . 15
1.3 Conversion of CMOS Inverters to other logic . . . . . . . . . . . . . . . . . . . 15

1
List of Figures

1.1 The basic CMOS inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2 nMOS and pMOS drain currents for different input voltages . . . . . . . . . . 4
1.3 Output voltage for nMOS in saturation, pMOS in linear regime . . . . . . . . 5
1.4 Output voltage when both transistors are saturated . . . . . . . . . . . . . . . 7
1.5 Transfer Curve of a CMOS inverter . . . . . . . . . . . . . . . . . . . . . . . . 7
1.6 Output voltage when nMOS is in linear regime while pMOS is saturated. . . . 8
1.7 CMOS inverter with the nMOS ‘off’ . . . . . . . . . . . . . . . . . . . . . . . . 12
1.8 CMOS inverter with the pMOS ‘off’ . . . . . . . . . . . . . . . . . . . . . . . . 14
1.9 CMOS implementation of 2 input NAND and NOR gates . . . . . . . . . . . . 16
1.10 CMOS implementation of A.B + C.(D + E) . . . . . . . . . . . . . . . . . . . 17

2
Chapter 1

Static CMOS Logic Design

Static logic circuits are those which can hold their output logic levels for indefinite periods as
long as the inputs are unchanged. Circuits which depend on charge storage on capacitors are
called dynamic circuits and will be discussed in a later chapter.

1.1 Static CMOS Design style

The most common design style in modern VLSI design is the Static CMOS logic style. In this,
each logic stage contains pull up and pull down networks which are controlled by input signals.
The pull up network contains p channel transistors, whereas the pull down network is made of
n channel transistors. The networks are so designed that the pull up and pull down networks
are never ‘on’ simultaneously. This ensures that there is no static power consumption.

1.2 CMOS Inverter

VDD

In Out

Figure 1.1: The basic CMOS inverter

3
 The simplest of such logic structures is the CMOS inverter. In fact, for any CMOS logic
design, the CMOS inverter is the basic gate which is first analyzed and designed in detail.
Thumb rules are then used to convert this design to other more complex logic. The basic
CMOS inverter is shown in fig. 1.1. We shall develop the characteristics of CMOS logic
through the inverter structure, and later discuss ways of converting this basic structure more
complex logic gates.

1.2.1 Static Characteristics

The range of input voltages can be divided into several regions.

• nMOS ‘off’, pMOS ‘on’

• nMOS saturated, pMOS linear

• nMOS saturated, pMOS saturated

• nMOS linear, pMOS saturated

• nMOS ‘on’, pMOS ‘off’

Let us compute the output voltage for a series of input voltages from 0V to VDD . We have
plotted the individual drain currents of the n and p channel transistors as functions of the
output voltage for different input voltages Vin .
The gate voltage for the nMOS transistor = Vin and the drain voltage = Vout while the
0.4
Vin = 3.0 0.4
0.35 Vin = 0.0
0.35
0.3 0.3
0.25
pMOS Id (mA)

Vin = 2.5 0.25

nMOS Id (mA)

Vin = 0.5
0.2 0.2
0.15 0.15
Vin = 2.0 Vin = 1.0
0.1 0.1
0.05 Vin = 1.5 0.05
Vin = 1.0 Vin = 1.5
Vin = 2.0
0 0
0 0.5 1 1.5 2 2.5 3 0 0.5 1 1.5 2 2.5 3
Vout (V) Vout (V)

Figure 1.2: nMOS and pMOS drain currents for different input voltages

absolute gate voltage for pMOS is VDD − Vin and the absolute drain voltage is VDD − Vout .

The Output voltage of the inverter will be the value where the two currents are equal for
any given Vin .

4
nMOS ‘off’, pMOS ‘on’
For 0 < Vi < VT n the n channel transistor is ‘off’, the p channel transistor is ‘on’ and the
output voltage = VDD . This is the normal digital operation range with input = ‘0’ and output
= ‘1’.

nMOS saturated, pMOS linear

In this regime, both transistors are ‘on’. The input voltage Vi is > VT n , but is small enough
so that the n channel transistor is in saturation, and the p channel transistor is in the linear
regime. In static condition, the output voltage will adjust itself such that the currents through
the n and p channel transistors are equal.
The absolute value of gate-source voltage on the p channel transistor is VDD - Vi , and therefore
0.14 Inverter Transfer Curve
VDD Idp: Vin = 1.0V
0.12 3.0
VoH
2.5
0.1

Output Voltage
2.0
In Out 0.08 nMOS saturated pMOS linear
1.5 V +V
Id (mA)

0.06 Tn Tp

1.0
0.04
Idn = Idp
0.5
0.02 Idn: Vin = 1.0V
VoL
0.0
0 0.0 0.5 1.0 1.5 2.0 2.5 3.0
0 0.5 1 1.5 2 2.5 3 ViL ViH
Vout (V) Input Voltage

Figure 1.3: Output voltage for nMOS in saturation, pMOS in linear regime

the “over voltage” on its gate is VDD - Vi - VT p . The drain source voltage of the pMOS has an
absolute value VDD -Vo .
Therefore,
1 Kn
 
Id = Kp (VDD − Vi − VT p )(VDD − Vo ) − (VDD − Vo )2 = (Vi − VT n )2 (1.1)
2 2
Where symbols have their usual meanings.

We define β ≡ Kn /Kp . We make the substitution Vdp ≡ VDD − Vo , where Vdp is the absolute
value of the drain-source voltage for the p channel transistor. Then,
1 2 β
(VDD − Vi − VT p )Vdp − Vdp = (Vi − VT n )2 (1.2)
2 2
Which gives the quadratic
1 2 β
Vdp − Vdp (VDD − Vi − VT p ) + (Vi − VT n )2 = 0 (1.3)
2 2
5
Solutions to the quadratic are:
q
Vdp = (VDD − Vi − VT p ) ± (VDD − Vi − VT p )2 − β(Vi − VT n )2 (1.4)

These equations are valid only when the pMOS is in its linear regime. This requires that

Vdp ≡ VDD − Vo ≤ VDD − Vi − VT p

Therefore, we must choose the negative sign. Thus

q
VDD − Vo = (VDD − Vi − VT p ) − VDD − Vi − VT p )2 − β(Vi − VT n )2 (1.5)

Therefore, q
Vo = Vi + VT p + (VDD − Vi − VT p )2 − β(Vi − VT n )2 (1.6)
Since Vo must be ≥ Vi + VT p , the limit of applicability of the above result is given by

(VDD − Vi − VT p )2 = β(Vi − VT n )2

That is, the solution for Vo is valid for

√
VDD + βVT n − VT p
Vi ≤ √ (1.7)
1+ β
In the case where we size the n and p channel transistors such that

Kn = Kp ; so β = 1

we have q
Vo = (Vi + VT p ) + (VDD − VT n − VT p )(VDD − 2Vi + VT n − VT p ) (1.8)
with
VDD + VT n − VT p
Vi ≤
2

nMOS saturated, pMOS saturated

At the limit of applicability of eq. 1.7, when the input voltage is exactly at
√
VDD + βVT n − VT p
Vi = √ (1.9)
1+ β
both transistors are saturated. Since the currents of both transistors are independent of their
drain voltages in this condition, we do not get a unique solution for Vo by equating drain
currents.
The currents will be equal for all values of Vo in the range

6
 0.14 Inverter Transfer Curve
VDD
0.12 3.0
VoH
0.1 nMOS saturated, pMOS saturated 2.5

Output Voltage
2.0
In Out 0.08
1.5 V +V
0.06 Idp: Vin = 1.5V Idn: Vin = 1,5V Tn Tp
Id (mA)

1.0
0.04 Range of Vout with Idn = Idp

0.5
0.02
Idn: Vin = 1,5V Idp: Vin = 1.5V VoL
0.0
0 0.0 0.5 1.0 1.5 2.0 2.5 3.0
0 0.5 1 1.5 2 2.5 3 ViL ViH
Vout (V) Input Voltage

Figure 1.4: Output voltage when both transistors are saturated

Inverter Transfer Curve

3.0
VoH
2.5
Output Voltage

2.0

1.5 V +V
Tn Tp

1.0

0.5
VoL
0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0
ViL ViH
Input Voltage

Figure 1.5: Transfer Curve of a CMOS inverter

Vi − VT n ≤ Vo ≤ Vi + VT p

Thus the transfer curve of an inverter shows a drop of VT n + VT p at a voltage near VDD /2. This
is actually an artifact of the simple transistor model chosen for this analysis, which assumes
perfect saturation of drain current. In a real case, the drain current does depend on the drain
voltage (albeit weakly) in the saturation region. If the model incorporates an Early Voltage
like effect, the drop near the middle of the characteristic is more gradual.

7
nMOS linear, pMOS saturated
At the gate voltage given by eq. 1.9, both transistors are saturated. As we increase Vi beyond
this value, such that √
VDD + βVT n − VT p
√ < Vi < VDD − VT p
1+ β
both transistors are still ‘on’, but nMOS enters the linear regime while pMOS gets saturated.
Equating currents in this condition,
0.14 Inverter Transfer Curve
VDD Idn: Vin = 2.0V
0.12 3.0
VoH
2.5
0.1

Output Voltage
2.0
In Out 0.08 nMOS linear pMOS saturated
1.5 V +V
Tn Tp
Id (mA)

0.06

1.0
0.04
Idn = Idp
0.5
0.02 Idp: Vin = 2.0V
VoL
0.0
0 0.0 0.5 1.0 1.5 2.0 2.5 3.0
0 0.5 1 1.5 2 2.5 3 ViL ViH
Vout (V) Input Voltage

Figure 1.6: Output voltage when nMOS is in linear regime while pMOS is saturated.

Kp 1
 
Id = (VDD − Vi − VT p )2 = Kn (Vi − VT n )Vo − Vo2 (1.10)
2 2
From this, we get the quadratic equation
1 2 (VDD − Vi − VT p )2
Vo − (Vi − VT n )Vo + =0 (1.11)
2 2β
This has solutions
s
(VDD − Vi − VT p )2
Vo = (Vi − VT n ) ± (Vi − VT n )2 − (1.12)
β
Since the equations are valid only when the n channel transistor is in the linear regime
(Vo < Vi − VT n ), we choose the negative sign. This gives,
s
(VDD − Vi − VT p )2
Vo = (Vi − VT n ) − (Vi − VT n )2 − (1.13)
β
Again, in the special case where β = 1, we have
q
Vo = (Vi − VT n ) − (VDD − VT n − VT p )(2Vi − VDD − VT n + VT p ) (1.14)

8
nMOS ‘on’, pMOS ‘off’
As we increase the input voltage beyond VDD - VT p , the p channel transistor turns ‘off’, while
the n channel conducts strongly. As a result, the output voltage falls to zero. This is the
normal digital operation range with input = ‘1’ and output = ‘0’.

The figure below shows the transfer curve of an inverter with VDD = 3V, VT n = 0.6V and
VT p = 0.5V, and β = 1.
3.5

2.5
Output Voltage

1.5

0.5

0
0 0.5 1 1.5 2 2.5 3
Input Voltage

The plot produced by SPICE for this circuit with realistic models is quite similar.

1.2.2 Noise margins

The requirement from a digital circuit is that it should distinguish logic levels, but be in-
sensitive to the exact analog voltage at the input. This implies that the flat portions of the
transfer curve (where ∂V o
∂Vi
is small) are suitable for digital logic. We select two points on the
transfer curve where the slope ( ∂V o
∂Vi
) is -1.0. The coordinates of these two points define the
values of (ViL ,VoH ) and (ViH ,VoL ). Robust digital design requires that the output high level
be higher than what is acceptable as a high level at the input (VoH > ViH ). The difference
between these two levels is the ‘high’ noise margin. This is the amount of noise that can ride
on the worst case ‘high’ output and still be accepted as a ‘high’ at the input of the next gate.
Similarly, we require VoL < ViL . The difference, ViL −VoL is the ‘low’ noise margin. Obviously,
it is of interest to evaluate the values of these noise margins. For the discussion which follows,
we shall use the expressions derived earlier for β = 1 to keep the algebra simple.

Calculation of ViL and VoH

from eq. (1.8)
q
Vo = (Vi + VT p ) + (VDD − VT n − VT p )(VDD + VT n − VT p − 2Vi )

9
 ∂Vo
From this, we can evaluate ∂Vi
and set it = -1.
s
∂Vo VDD − VT n − VT p
= −1 = 1 − (1.15)
∂Vi VDD + VT n − VT p − 2Vi

This gives
3VDD + 5VT n − 3VT p
ViL = (1.16)
8
Substituting this in eq.(1.8), we get

3VDD + 5VT n − 3VT p

VoH = + VT p +
s 8
3VDD + 5VT n − 3VT p
 
(VDD − VT n − VT p ) VDD + VT n − VT p −
4
s
3VDD + 5VT n + 5VT p VDD − VT n − VT p
 
= + (VDD − VT n − VT p )
8 4
3VDD + 5VT n + 5VT p VDD − VT n − VT p
= +
8 2
7VDD + VT n + VT p
=
8
So
7VDD + VT n + VT p VDD − VT n − VT p
VoH = = VDD − (1.17)
8 8

Calculation of ViH and VoL

When the input is ‘high’, we should use eq.(1.14).
q
Vo = (Vi − VT n ) − (VDD − VT n − VT p )(2Vi − VDD − VT n + VT p )

Differentiating with respect to Vi gives

s
∂Vo VDD − VT n − VT p
= −1 = 1 − (1.18)
∂Vi 2Vi − VDD − VT n + VT p

VDD − VT n − VT p
So =4
2Vin − VDD − VT n + VT p
Therefore VDD − VT n − VT p = 8Vin − 4VDD − 4VT n + 4VT p
From where, we get
5VDD + 3VT n − 5VT p
ViH = (1.19)
8

10
Substituting the value of ViH for Vin in eq.1.14), we get

5VDD + 3VT n − 5VT p

VoL = − VT n −
s 8
5VDD + 3VT n − 5VT p
 
(VDD − VT n − VT p ) − VDD − VT n + VT p
4
s
5VDD − 5VT n − 5VT p VDD − VT n − VT p
 
= − (VDD − VT n − VT p )
8 4
5VDD − 5VT n − 5VT p VDD − VT n − VT p VDD − VT n − VT p
= − =
8 2 8
So
VDD − VT n − VT p
VoL = (1.20)
8

Calculation of Noise Margins

The high noise margin is given by
VDD − VT n + 3VT p
VoH − ViH = (1.21)
4
Similarly, the Low noise margin is
VDD + 3VT n − VT p
ViL − VoL = (1.22)
4
The two noise margins can be made equal by choosing equal values for VT n and VT p .

1.2.3 Dynamic Considerations

In this section, we analyze the dynamic behaviour of the inverter. For the calculation of rise
and fall times, we shall assume that only one of the two transistors in the inverter is ‘on’.
(Notice that this is more conservative than the input high and low conditions determined by
slope considerations in eq.1.19 and 1.16). We shall continue to use the simple model described
at the beginning of this booklet.

Rise time
When the input is low, the n channel transistor is ‘off’, while the p channel transistor is ‘on’.
The equivalent circuit in this condition is shown in fig. 1.7. From Kirchoff’s current law at
the output node,
dVo
Idp = C
dt

11
 VDD

ViL

VoH

CL

Figure 1.7: CMOS inverter with the nMOS ‘off’

so,
dt dVo
=
C Idp
This separates the variables, with the LHS independent of operating voltages and the RHS
independent of time. Integrating both sides, we get
τrise VoH dVo
Z
=
C 0 Idp
Till the output rises to ViL + VT p , the p channel transistor is in saturation. Since the current
is constant, the integration is trivial. If VoH > ViL + VT p (which is normally the case), the
integration range can be broken into saturation and linear regimes. Thus
τrise ViL +VT p dVo
Z
= Kp
C 0
2
(VDD − ViL − VT p )2
VoH dVo
Z
+ h i
ViL +VT p Kp (VDD − ViL − VT p )(VDD − Vo ) − 21 (VDD − Vo )2

We define V1 ≡ VDD − Vo and V2 ≡ VDD − ViL − VT p , so dVo = −dV1 .

We get
Kp τrise ViL + VT p dV1
Z VDD −VoH
= 2
−
2C V2 V2 2V1 V2 − V12
The integral can be evaluated as
VDD −VoHdV1
Z
I ≡ −
V2 2V1 V2 − V12
1 Z V2 1 1
 
= + dV1
2V2 VDD −VoH V1 2V2 − V1

12
 V2
1 V1
 
= ln
2V2 2V2 − V1 VDD −VoH
1 2V2 − VDD + VoH
= ln
2V2 VDD − VoH
Therefore,
Kp τrise ViL + VT p 1 2V2 − VDD + VoH
= 2
+ ln
2C V2 2V2 VDD − VoH
or
Kp τrise ViL + VT p 1 2V2 − VDD + VoH
= + ln
2C (VDD − ViL − VT p ) 2 2(VDD − ViL − VT p ) VDD − VoH
Thus,

C(ViL + VT p )
τrise = Kp
2
(VDD
− ViL − VT p )2
C VDD + VoH − 2ViL − 2VT p
+ ln (1.23)
Kp (VDD − ViL − VT p ) VDD − VoH

The first term is just the constant current charging of the load capacitor. The second term
represents the charging by the pMOS in its linear range. This can be compared with resistive
charging, which would have taken a charge time of
VDD − ViL − VT p
τ = RC ln
VDD − VoH
to charge from ViL + VT p to VoH .

Fall time
When the input is high, the n channel transistor is ‘on’ and the p channel transistor is ‘off’. If
the output was initially ‘high’, it will be discharged to ground through the nMOS. To analysis
the fall time, we apply Kirchoff’s current law to the output node. This gives
dVo
Idn = −C
dt
Again, separating variables and integrating from the initial voltage (= VDD ) to some terminal
voltage VoL gives
τf all Z voL
dVo
=−
C VDD Idn

The n channel transistor will be in saturation till the output voltage falls to Vi - VT n . Below
this voltage, the transistor will be in its linear regime. Thus, we can divide the integration

13
 VDD

VoL
ViH

Figure 1.8: CMOS inverter with the pMOS ‘off’

range in two parts.

τf all dVo
Vi −VT n VoL dVo
Z Z
= − −
C VDD Idn Vi −VT n Idn
dVo
Z VDD
= Kn
Vi −VT n
2
(Vi − VT n )2
dVo
Z Vi −VT n
+ h i
VoL Kn (Vi − VT n )Vo − 12 Vo2

Therefore
Kn τf all VDD − Vi + VT n Z Vi −VT n dVo
= +
2C (Vi − VT n ) 2 VoL 2Vo (Vi − VT n ) − Vo2
!
VDD − Vi + VT n 1 1 1
Z Vi −VT n
= + dVo +
(Vi − VT n )2 2(Vi − VT n ) VoL Vo 2(Vi − VT n ) − Vo
Which gives
" #Vi −VT n
Kn τf all VDD − Vi + VT n 1 Vo
= + ln
2C (Vi − VT n ) 2 2(Vi − VT n ) 2(Vi − VT n ) − Vo VoL
VDD − Vi + VT n 1 2(Vi − VT n ) − VoL
= + ln
(Vi − VT n ) 2 2(Vi − VT n ) VoL
and therefore
C(VDD − Vi + VT n ) C 2(Vi − VT n ) − VoL
τf all = Kn + ln (1.24)
2
(Vi − VT n ) 2 Kn (Vi − VT n ) VoL
Again, the first term represents the time taken to discharge at constant current in the satu-
ration regime, whereas the second term is the quasi-resistive discharge in the linear regime.

14
1.2.4 Trade off between power, speed and robustness
As we scale technologies, we improve speed and power consumption. However, as we can see
from the expression for noise margins, (eq 1.21 and eq 1.22) the noise margin becomes worse.
We can improve noise margins by choosing relatively higher threshold voltages. However, this
will reduce speeds. We could also increase VDD - but that would increase power dissipation.
Thus we have a trade off between power, speed and noise margins.
This choice is made much more complicated by process variations, because we have to
design for the worst case.

1.2.5 CMOS Inverter Design Flow

The CMOS inverter forms the basis of most static CMOS logic design. More complex logic
can be designed from it by simple thumb rules. A common (though not universal) design
requirement is symmetric charge and discharge behaviour and equal noise margins for high
and low logic values. This requires matched values of Kn and Kp and equal values of VT n and
VT p . For a constant load capacitance, rise and fall times depend linearly on Kn and Kp . Thus
it is a straightforward calculation to determine transistor geometries if speed requirements
and technological parameters are given. However, as transistor geometries are made larger,
self loading can become significant. We now have to model the load capacitance as

CLoad = Cext + αKn

where we have assumed that β = Kn /Kp is kept constant. α is a technological constant. We

use the expressions for Kτ /C which depend only on voltages. Once these values are calcu-
lated, the geometry can be determined.

In the extreme case, when self capacitance dominates the load capacitance, K/C becomes
constant and τ becomes geometry independent. There is no advantage in using wider tran-
sistors in this regime to increase the speed. It is better to use multi-stage logic with tapered
buffers in this regime. This will be discussed in the module on Logical Effort.

1.3 Conversion of CMOS Inverters to other logic

Once the basic CMOS inverter is designed, other logic gates can be derived from it. All
logic gates will have a pull up circuit consisting of pMOS transistors and pull down circuits
consisting of nMOS transistors. The more complex logic gates derived from the inverter design
should continue to provide the following essential characteristics of CMOS sytle of logic:
1. The logic gate should not consume current when the input is not changing. This implies
that at no time should the pull up and pull down circuits be simulataneously ’ON’,
providing a path from VDD to ground.

15
 VDD VDD

MPA MPB MPA

Out
A B
A B MPB
MNB Out

MNA MNA MNB

Figure 1.9: CMOS implementation of 2 input NAND and NOR gates

2. The logic gate output should be continuously driven to a ‘1’ or a ‘0’. This means that
one of the pull up and pull down networks must be ’ON’ for any input combination.
This ensures that if due to noise or leakage, the output voltage level changes, it will
restored to VDD or ground by the pull up or pull down circuit which is ’ON’.

Apart from these essential properties, we would like to have the desirable property that the
rise and fall times of the output are equal.

These conditions require that any input combination which produces a ’0’ at the output
should turn the pull down network ‘ON’, and simultaneously ensure that the pull up network
is ‘OFF’. Similarly, for all input combinations for which the output is ‘1’, the pull up circuit
should be ‘ON’ and the pull down circuit should be OFF. Since the logic gate is derived from
an inverter, the output should be expressed in a canonical form which has a bar (inversion)
on top. Also, each input should drive an nMOS transistor in the pull down network and a
pMOS transistor in the pull up network, to ensure that the essential requirements of CMOS
logic are met.

Now consider a NAND gate. The output should be ‘0’ only when both inputs are at ‘1’.
Since a ‘1’ at the input turns the nMOS transistors ‘ON’ and the pMOS transistors ’OFF’,
the nMOS transistors must be in series. Then the pull down circuit as a whole will be ‘ON’
only when both inputs are at ‘1’. Both inputs being at ‘1’ ensures that both pMOS transistors
are ‘OFF’, so the pull up circuit is off as required.

If either or both inputs are ‘0’, the output should be ‘1’. To ensure this, the pull up
circuit should be ‘ON’ while the pull down circuit should be ‘OFF’. Either input being ‘0’ will
turn the corresponding nMOS transistor ‘OFF’. The series connection of nMOS transistors is
therefore suitable for this. To make sure that even if one input is at ‘0’, the pull up circuit is

16
‘ON’, the pMOS transistors should be in parallel.

Similarly, for NOR logic, we can see that the nMOS transistors should be in parallel, while
the pMOS transistors must be connected in series. Fig.1.9 shows the implementation of two
input NAND and NOR gates.

For more complex logic, the logic expression shouldh be put in a cannonical form with a
bar on top to indicate inversion and the expression should be a sum of products.

For every ‘.’ in the expression, we put the corresponding n channel transistors in series
and the corresponding p channel transistors in parallel. For every ‘+’, we put the n channel
transistors in parallel and the p channel transistors in series. This rule is known as the series-
parallel rule.

Fig.1.10 shows the implementation of A.B + C.(D + E) in CMOS logic design style.
VDD

A B

D
C
E

Out
A C

B D E

Figure 1.10: CMOS implementation of A.B + C.(D + E)

Apart from the series-parallel connection, we have to decide how to determine the geom-
etry of the transistors which are so connected. This is done by using what is known as the
series-parallel rule. We scale the transistor widths up by the number of devices (n or p) put
in series. The geometries are left untouched for devices put in parallel. One can justify this
rule by analogy with on resistance of transistors. Two transistors in series will have the same
on resistance as the single transistor in the inverter if each of the series transistors has half
the on resistance of the inverter transistor. This can be done by making each of the series
transistors twice as wide.

While at first sight it might appear that in case of parallel transistors, we can make do
with half the width of the corresponding transistor in the inverter, it is not so. This is because

17
parallel transistors must be ‘on’ whenever either of the transistors is ‘on’. Thus in the worst
case, only one of the parallel transistors may be ‘on’ and this transistor must provide the same
on resistance as the corresponding transistor in the inverter. Hence, for parallel transistors,
we leave the geometry unchanged.

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