19 Modern FET [Mostly Read Oniy] Structures ‘To achieve higher operating speeds and increased packing densities, FET device structures have been subjected to greater and greater miniaturization. The decrease in FETT device dimensions, in itself, can lead to major modifications in the observed device characteristics, ‘Small dimension effects, aso referred to as short-channel effects or small geometry effects, include, for example, shifts in the threshold voltage and an increase in the subthreshold current. The cited modifications in device behavior are of major importance in practical applications. Notably, an accurate prediction of the threshold voltage is needed to deter- mine logic levels, noise margins, speed, and node voltages, while the subthreshold current affects the off-state power dissipation, dynamic logic clock speeds, and memory refresh times. A large portion of this chapter is devoted to the description and discussion of small dimension effects. It should be understood from the outset that small dimension effects are generally undesirable and are minimized or avoided in commercial structures through the Proper scaling of device dimensions or modifications in device design. Relative to modifi- cations in device design, the chapter concludes with a brief survey of select implemented and developmental FET structures. 19.1 SMALL DIMENSION EFFECTS 19.1.1 Introduction In 1965 the smallest MOSFETs had an L ~ | mil = 25 um. By 1990 industry-standard versions of MOS device structures had attained submicron dimensions. The steady pro- gression toward smaller and smaller FETs is pictured schematically in Fig. 19.1. Projec- tions into the near future are summarized in Table 19.1 1970 1980 1990 2000 Year Figure 19.1 The “shrinking” MOSFET. The relative scaling of the MOSFET channel length in the figure roughly depicts the decrease in minimum feature size of production-line MOS DRAMSs. 691692 © FIELDEFFECTOEVICES Table 19.1 Silicon IC Projections!*l, (DRAM is an acronym for dynamic random access memory. 1/0 is an abbreviation for input/output, Wiring levels refer to the number cof metallization levels that interconnect devices on an IC.) YEAR of first DRAM shipment 1995 | 1998 | 2001 2007 | 2010 0.35 0.10 | 0.07 7 ena 250 | 620 Chip size (mm?) — -——-{ 190 | 1400 Bits/chip in DRAMs 64M | 64G 200 400 r-chip logicy | 45 78 Wiring levels (maximum in on-chip logic) 0 pads per chip (high performance) 900 1350 | 2000 | 2600 | 3600 | 4800 © Desktop 33 | 25 1s | 12 | 09 Power supply voltage (V) ~ ——_- —— : © Portable 25 [18-25 o9 | 09 | 09 | | Chip frequency (MHz) |sonehip 300 | 450 | 600 | 800 | 1000 | 1100 high performance Chip-to-board | 150 | 200 | 250 | 300 | 375_| 475 The departure from long-channel behavior, which can accompany the noted decrease in device dimensions, is nicely illustrated using observed J~Vp characteristics. The onset of short-channel effects is heralded by a significant upward slant in the post-pinch-off por- tions of the [p~Vp curves. Severe short-channel effects lead to characteristics of the form reproduced in Fig. 19.2, Not only do the /)~Vj, characteristics fail to saturate, but /y ® Vp? curves are observed for gate voltages below threshold. (The Fig. 19.2 device should be “off” for Vg > 0 V!) Another clear manifestation of short-channel effects is provided by the subthreshold transfer characteristics. A sample long-channel subthreshold characteris- tic was presented in Fig. 17.11. In long-channel MOSFETs the subthreshold drain current varies exponentially with Vg and is independent of Vy provided Vp > few KT/q volts. In short-channel devices, on the other hand, the subthreshold drain current is found to increase systematically and significantly with increasing Vz. Shifts in the observed threshold volt- age constitute the third widely quoted indication of small-dimension effects. As is readily confirmed by referring to the Vz relationship in Subsection 18.3.1, the threshold voltage in a long-channel MOSFET is independent of the gate length and width. In short-channel devices, Vz becomes a function of the gate dimensions and the applied biases (see Fig. 19.3).MODERN FETSTRUCTURES 693, 40 3.0 -0 CIS 208 Vo (volts) Figure 19.2 1,-Vj, characteristics of a MOSFET exhibiting severe short-channel effects. (Re- printed from Bateman et al.2"!, © 1974, with kind permission of Elsevier Science Ltd.) 06 Vy = 0.125 V Vy (volts) L (um) Figure 19.3 Observed threshold-voltage variation with channel length and applied drain bias in short-channel MOSFETS. Ny = 8 X 10!/cm?, x, = 0.028 jum, and r, = 1 jum. (Adapted from Fichiner and Potz1 1)FIELD EFFECT DEVICES ‘The majority of small-dimension effects in MOSFET’ are associated with the reduc- tion in the channel length L. Itis therefore reasonable to introduce and specify a minimum channel length, Lgie, below Which significant short-channel effects are expected to occur. Crudely speaking, L.,jq must be greater than the sum of the depletion widths associated with the source and drain junctions. Values in the 0.1 am to 1 jam range are indicated. As suggested by computer simulations and confirmed by experimental observations, a more precise estimate of L pig i given by the empirical relationship") Legin = OAL X(Ws + Wp)?! yin A Lagins Mo 9.1) Ws, Wp in wm 1 is the source/drain junction depth, 1, the oxide thickness, W, the depletion width at the source junction, and W, the depletion width at the drain junction, Note from Eq. (19.1) that L pip can be made smaller by reducing the depth of the source/drain islands, by reduc ing the oxide thickness, and/or by increasing the substrate doping, which in turn causes a dectease in W, and Wp. All of the above have in fact been employed to help assure long- channel operation of MOSFETs with increasingly scaled-down dimensions. ‘The causes underlying departures from long-channel behavior fall into one of three ‘general categories. For one, differences between experiment and Iong-channel theory may simply arise from a breakdown of assumptions used in the long-channel analysis. Second, a reduction in device dimensions automatically leads to an enhancement of certain effects that are known to occur but are negligible in long-channel devices. Lastly, some departures from Iong-channel behavior arise from totally new phenomena, All three categories are represented in the following consideration of specific-case effects 19.1.2 Threshold Voltage Modification Short Channel In enhancement-mode short-channel devices | V;| is found to monotonically decrease with decreasing channel length L. Qualitatively, the decrease in threshold voltage can be ex- plained as follows: Before an inversion layer or channel forms beneath the gate, the subgate region must first be depleted (W —> W,). In a short-channel device the source and drain assist in depleting the region under the gate; that is, a significant portion of the subgate deletion-region charge is balanced by the charge on the other side of the source and drain pn junctions. Thus less gate charge is required to reach the start of inversion and |V;| decreases. The smaller L, the greater the percentage of charge balanced by the source/drain pn junctions, and the greater the reduction in |. AA first-order quantitative expression for the AV, associated with short-channel effects can be established using straightforward geometric arguments. Although highly simplified, the derivation to be presented is very informative in that it illustrates the general method of analysis. The derivation also indicates how parameters such as the source/drain junction depth enter into the specification of short-channel effects.MODERN FET STRUCTURES As previously established, for an ideal device K Vo = bs + Kees (19.2) Let Qs be the total charge/cm? inside the semiconductor. Applying Gauss’ law, itis readily established that, Qs = ~ Kee (19.3) Combining Eqs. (19.2) and (19.3), we can therefore write — 2095 _ 4 _ Qs os Kot bs C, (19.4) When Vo = Vz, 5 = 2bp and Qs = Qn, where Qy is the bulk or depletion-region charge per unit area of the gate. Specialized to the threshold point, Eq. (19.4) thus becomes (19.5) Next introducing AV, = V;(short channel) — V,(long channel) (19.6) taking Oy, and Qps to be the long-channel and short-channel depletion-region charges/ cm?, respectively, and making use of Eq. (19.5), we obtain (19.7) ‘To complete the derivation, it is necessary to develop expressions for Qg, and Ops in terms of the device parameters. Working toward this end, consider the short n-channel MOSFET pictured in Fig. 19.4. To simplify the analysis, Vj, is taken to be small or zero $0 that W = Wr at all points beneath the central portion of the gate. The shaded areas in the figure identify those portions of the subgate region that are assumed to be controlled by the source and drain pn junctions. In a long-channel device, charge in the entire rectangular region of side-length L is balanced by charges on the gate and _aNg(ZLW,) = -qN, 198) a aN,W, (19.8) On = 695696 FIELD EFFECT DEVICES / Nie 7 ? /> S Depletion boundary Figure 19.4 Cross section of a MOSFET identifying parameters that enter into the short-channel analysis. The shaded portions of the subgate area are assumed to be controlled by the source and drain pn junctions. It is also assumed that Vp = ZLW, is the depletion-region volume and ZZ the area of the gate. In a short-channel device, the depletion-region charge controlled by the gate is confined to the trapezoidal region of side lengths L and 1’. Thus 2 L+L = ow te 9 Ors a ON We 9.) ‘Substituting the Op, and Qp« expressions into Eq. (19.7) then gives L+L AV, = -8sth(, - ast) (19.10) Next, looking at the source region in Fig. 19.4 and assuming Ws geometrical considerations W,, one deduces from Or + We? 9.11) which can be solved to obtain =L = 2r, ji? (19.12) ly Finally, eliminating L’ in Eq. (19.10) using Eq. (19.12), we concludeMODERN FET STRUCTURES AV; (short channel) = GN Wr i 2Wr aN We 1 coe 19. aly! F | (19.13) eee ee eee Although a first-order result, the AV; given by Eq. (19.13) does exhibit the same parametric dependencies initially noted in the Lpi, discussion. Examining AV,,/V;(long- channel), which is the relevant quantity in gauging the importance of short-channel effects, one again finds the effects are minimized by reducing x,, reducing r,, and increasing Ny. Narrow Width ‘The threshold voltage is also affected when the lateral width Z of a MOSFET becomes comparable to the channel depletion-width W/,. In enhancement-mode narrow-width de- vices, |V;| is found to monotonically increase with decreasing channel width Z, Note that the Z-dependence of the threshold voltage shift is opposite to the L-dependence. The narrow-width effect, however, is explained in much the same manner as the short-channe! effect, Referring to the side view of a MOSFET in Fig. 19.5, note that the gate-controlled depletion region extends to the side, lying in part outside the Z-width of the gate. In wide- width devices, the gate-controlled charge in the lateral region is totally negligible. In narrow-width devices, on the other hand, the lateral charge becomes comparable to the charge directly beneath the Z-width of the gate; that is, there is an increase in the effective ccharge/cm? being balanced by the gate charge. Thus, added gate charge is required to reach the start of inversion and | V| increases. Paralleting the short-channel derivation, a quantitative expression for AV; associated with the narrow-width effect is readily established. Ifthe lateral regions are assumed to be quarter-cylinders of radius Wp, the lateral volume controlled by the gate is (ar/2)W3 and an,( zt, + im) Qy(narrow width) = -———— = anans(1 1 3 tr) (19.14) Gate oxide Wr Figure 19.5 Side view of a MOSFET used to explain and analyze the narrow-width effect. 697698 FIELD EFFECT DEVICES Replacing Qgs in Eq. (19.7) with the narrow-width Qj, one rapidly concludes V, W; AV;(narrow width) = atte a 9.15) This result confirms our initial assertion that the narrow-width effect becomes important when Zis comparable to W>. As a concluding point it should be noted that a combined-effect AV, must be estab- lished for MOSFETs that have both a short channel and a narrow width. The short-channel and narrow-width A V;'s are not simply additive. The combined-effect AV; and more ex- acting AV, expressions for the individual effects can be found in the device literature.°°1 19.1.3 Parasitic BUT Action Containing an oppositely doped region between the source and the drain, the MOSFET bears a striking physical resemblance to a lateral bipolar junction transistor (BJT). Thus, with the distance between the source and drain in a modern MOSFET reduced to a value ‘comparable to the base width in a bipolar transistor, it is not surprising that phenomena have been observed that are normally associated with the operation of BJTs. ‘One such phenomenon is source to drain punch-through. When the source and drain are separated by a few microns or less it becomes possible for the pn junction depletion regions around the source and drain to touch or punch-through as pictured in Fig. 19.6 When punch-through occurs, a significant change takes place in the operation of the MOSFET. Notably, the gate loses control of the subgate region except for a small portion of the region immediately adjacent to the Si-SiO, interface. The source-to-drain current is then no longer constrained to the surface channel, but begins to flow beneath the surface through the touching depletion regions. Analogous to the punch-through current in BJTs, this subsurface “space-charge” current varies as the square of the voltage applied between Depletion-region boundaries Figure 19.6 Punch-through and space-charge current ina short-channel MOSFET.MODERN FET STRUCTURES the source and drain. The Vg > 0 characteristics presented in Fig, 19.2 are examples of the Jy V3, current that results from source to drain punch-through. As a practical matter, punch-through in small-dimension MOSFETS is routinely sup- pressed by increasing the doping of the subgate region and thereby decreasing the source/ drain depletion widths. This can be accomplished by increasing the substrate doping. How- ever, increasing the substrate doping has the adverse effect of increasing parasitic capaci- tances. Consequently, it is common practice to perform a deep-ion implantation to selec- tively increase the doping of the subgate region. Parasitic BIT action involving carrier multiplication and regenerative feedback leads to a second potentially significant perturbation of the MOSFET characteristics. There is a certain amount of carrier multiplication in the high-field depletion region near the drain in all MOSFETs. In long-channel devices the multiplication is negligible. In short-channel devices, however, carrier multiplication coupled with regenerative feedback can dramati- cally increase the drain current and place a reduced limit on the maximum operating Vp. Catastrophic failure may even occur under extreme conditions. ‘The multiplication and feedback mechanism operating in small-dimension MOSFETs is very similar to that which lowers Vepayceo int a BIT relative to Viggycpo (see Subsection 11.2.4), The basic mechanism is best described and explained with the aid of Fig. 19.7. ‘The process is initiated by channel current entering the high-field region in the vicinity of the drain, Upon acceleration in the high-field region, a small percentage of the channel carriers gain a sufficient amount of energy to produce electron-hole pairs through impact ionization, For an n-channel device the added electrons drift into the drain, while the added holes are swept into the quasineutral bulk. Because the semiconductor bulk has a finite resistance, the current flow associated with the impact-generated holes gives rise to a po- tential drop between the depletion region edge and the back contact. This potential drop is electron injection and carrier flow Hoes into drain swept into bulk 438 [5] potent drop caused by hole curtent Back-to-source forward biased Figure 19.7 Visualization of carrier multiplication and regenerative feedback that can give rise to current enhancement in short-channel MOSFETs.FIELD EFFECT DEVICES of such a polarity as to foward bias the source pn junction. Forward biasing of the source pn junction in turn leads to electron injection from the source pn junction into the quasi- neutral bulk, an additional electron flow into the drain, increased carrier multiplication, and so forth. The process is stable as long as the fractional increase in the drain current or the multiplication factor is less than 1/ar, where a is the common-base gain of the parasitic BIT. At high enhanced currents there is the potential for excessive current flow through the device and device failure. 19.1.4 Hot-Carrier Effects Oxide Charging ‘Oxide charging, or charge injection and trapping in the oxide, is a phenomenon that occurs in all MOSFETs. In the vicinity of the drain under ‘operational conditions, channel carriers, and carriers entering the drain depletion region from the substrate, periodically gain a suf- ficient amount of energy to surmount the Si-SiO, surface barrier and enter the oxide, Neu- tral centers in the oxide trap a portion of the injected charge and thereby cause a charge buildup within the oxide, In long-channel devices, oxide charging is the well-known cause of “walk-out” —a progressive increase in the drain breakdown voltage of MOSFETs op- erated at large Vp, biases, Unfortunately, the effects of oxide charging in short-channel MOSFETs are decidedly more serious. This is true because a larger percentage of the gated region is affected in the smaller devices. Specifically, significant changes in V, and g,, can result from the oxide-charging phenomenon. Moreover, because oxide charging is cumu- lative over time, the phenomenon tends to limit the useful “life” of a device and must be minimized. A popular approach for minimizing hot-carvier effects, the formation of a lightly doped drain (LDD), is described in Subsection 19.2.1 Velocity Saturation In the conventional analysis of the long-channel MOSFET, there is no theoretical limitation on the velocity that the carriers can attain in the surface channel. It is implicitly assumed the carrier velocities increase as needed to support the computed current. In reality, the carrier drift velocities inside silicon at T = 300 K approach a maximum value of 2, 10” cm/sec when the accelerating electric field exceeds ~3 X 10 V/cm for electrons and ~10° Vicm for holes (see Fig. 3.4 in Part 1). If, for example, Vi) = 2 V and L = 0.5 um, there will obviously be points in the MOSFET surface channel where the accelerating elec- tric field is greater than or equal to.4 X 104 V/cm, Limitation of the channel current due to velocity saturation is clearly a possibility in short-channel devices. Velocity saturation has two main effects on the observed characteristics. First, Ip is significantly reduced. The modified Ip,x is approximately described by Tose = ZCKVe ~ Vr Woue (19.16) ‘Second, as can be inferred from Eq. (19.16) and as illustrated in Fig. 19.8, the saturation current exhibits an almost linear dependence on Vq-V;. as opposed to the conventional square-law dependence.MODERN FET STRUCTURES Ye =5V av s 3 rersv é = 3 3 avg My z 3 av é tse E 6 6 2v au TV iva Lv Drain voltage (1 V/div) Drain voltage (1 Viiv) Drain voltage (1 Viiv) @ o © Figure 19.8 Illustration ofthe effects of velocity saturation on the MOSFET J,—V, characteristics. (a) Experimental characteristics derived from a short-channel MOSFET with L = 2.7 um, x, = 0.05 jum, r, = 04 um, and N, (substrate) = 10!*/cm?, Comparative theoretical characteristics com- puted (b) including velocity saturation and (c) ignoring velocity saturation. (From Yamaguchil>!!, © 1979 IEEE.) Velocity Overshoot / Ballistic Transport In the Chapter 17 modeling of carrier drift in the MOSFET surface channel, we implicitly assumed that carriers experienced numerous scattering events in traveling between the source and the drain. This is equivalent to assuming the channel length (L) is much greater than the average distance (/) between scattering events. Clearly, if the MOSFET channel length is reduced to a value comparable to /, fundamental revisions will be required in the analytical formalism. More importantly, however, if even smaller-dimension structures could be built with 1 < J, a large percentage of the carriers would then travel from the source to the drain without experiencing a single scattering event. The envisioned projectile- like motion of the carriers is referred to as ballistic transport. Observable ballistic effects are theoretically possible in GaAs structures where L = 0.3 um. Somewhat shorter lengths are required in Si devices. Experimentally, both Si and GaAs FETs with channel lengths ~0.1 jum have been fabricated in research laboratories, ‘Thus, FET structures with L = / are attainable with present-day technology. Moreover, referring to Table 19.1, such structures are expected to become commonplace in the near future. Practically speaking, ballistic ransport is of interest because it could lead to super-fast devices. With reduced scattering, the average velocity of carriers transversing the channel can exceed v,.. This is referred to as velocity overshoot. Average velocities up to 35% larger than the saturation velocity have been observed in an L = 0.12 ym MOSFET"), 701702 FIELD EFFECT DEVICES Admittedly there are other considerations, such as the operation of the carrier injecting source, that can limit ballistic device performance. Nonetheless, ballistic effects have been observed and are likely to play a role in the operation of future FETS. 19.2 SELECT STRUCTURE SURVEY In discussing the essentials of MOSFET operation, we made use of the basic enhancement mode structure, Use of the basic structure allows one to focus on the development of con- cepts and the understanding of phenomena. Naturally, given the maturity of MOSFET tech- nology, there exists a significant number of distinct device variations. Modifications to the basic structure have been implemented to solve specific problems or to enhance a specific device characteristic, It is also true that closely related FET devices fabricated in GaAs and other compound semiconductors invariably take a somewhat different form than those fab- ricated in Si. A brief survey of select MOSFET and MOSFET-like structures has been included in this section to provide some feel for the variety that exists and the nature of major modifications. It should be emphasized that the surveyed device structures constitute only a sampling, with a bias toward structures likely to be encountered in the recent FET literature. 19.2.1 MOSFET Structures LDD Transistors As described in the preceding section, reduced dimension devices are more susceptible to hot-carrier effects. The field-aided injection and subsequent trapping of carriers in the gate oxide near the drain can lead to serious device degradation, The degradation effects are further worsened by the common practice of using bias voltages that have not been scaled down in proportion to the device dimensions. The lightly doped drain (LDD) structure shown in Fig. 19.9 helps to minimize hot-carrier effects. The feature of note is the lightly doped drain region between the end of the channel and the drain proper (the n™ region in Fig. 19.9). The reduced doping gradient in going from the channel to the drain proper lowers the €-field in the vicinity of the drain and shifts the position of the peak €-field toward the end of the channel. Carrier injection into the oxide is thereby reduced and oxide charging correspondingly minimized. Sidewalt ‘oxide SRE Gate oxide source psi drain Lightly doped drain Figure 19.9 Cross section of a lightly doped drain (LDD) structure.MODERN FET STRUCTURES Diffusion mask edge O) Figure 19.10 (2) Cross section of a DMOS structure. (b) Magnified cross section of the channel region and lateral doping profile. (From Pocha et al.""), © 1974 IEEE.) DMos A double-diffused MOSFET (DMOS) structure is pictured in Fig. 19.10. The structure is distinctive in that the channel region is formed, and the channel length specified, by the difference in the lateral extent of two impurity profiles. A p-type dopant (e.g., boron) and an n-type dopant (¢.g., phosphorus) are admitted and diffused into the Si through the same oxide mask opening. The p-type dopant, which is introduced first, diffuses slightly deeper and farther to the side than the n-type dopant. The result is the simultaneous formation of the source and channel regions as clearly shown in the magnified cross section of Fig. 19.10(b). The most important physical characteristic of DMOS is a short channel Jength (~1 zm) that can be established without using small-dimension lithographic masks. ‘The DMOS structure thus boasts high-frequency operation, which is combined with a high drain breakdown voltage. It has been used in high-frequency analog applications and high- Voltage/high-power circuits. Although first introduced in the carly 1970s, variations of the DMOS structure, notably power-DMOS structures, continue to be developed. 703704 FIELD EFFECT DEVICES Oxite ‘Substrate G Np Nn eB [pay *s ow Dv \a | Ma Np I q, @ (b) (Channel region b+ g z Figure 19.11 (a) Cross section of a buried-channel MOSFET. (b) Approximate subgate doping profile. (Adapted from Van der Tol and Chamberlain", © 1989 IEEE.) Buried-Channel MOSFET Figure 19.11 shows the cross section of a buried-channel MOSFET and the approximate subgate-doping profile inside the transistor. The unique structural feature, a surface layer beneath the gate with the same doping as the source and drain islands, is typically formed by ion implantation. With a pn junction bottom gate and an MOS top gate, the buried- channel MOSFET is physically and functionally a hybrid J-FET/MOSFET structure. It can be designed to function as a depletion-mode or enhancement-mode device depending on the thickness and doping of the surface layer. The buried-channel MOSFET gets its name from the fact that channel conduction can be made to take place away from the oxide- semiconductor interface. This leads to inherently higher carrier mobilities, a reduced inter- facial trap interaction, and a decreased sensitivity to hot-carrier effects, SiGe Devices With the development of the ultrahigh-vacuum chemical-vapor-deposition (UHV/CVD) process!, it has become possible to deposit high-quality Si, _,Ge, alloy films on a production-line basis. The process permits atomic-level control of the film thickness, pre- cise control of the film composition, and minimization of background contamination. Films covering the entire range from 0 to 100% Ge content are readily deposited. Reflecting the fact that the Ge lattice constant is a = 5.65 A compared to the smaller a = 5.43 A of silicon, SiGe alloys preferably exhibit a lattice constant larger than Si. However, if sufficiently thin (typically = 1000 A), SiGe alloy films deposited on a Si sub- strate are pseudomorphic in nature; that is, they conform atom-by-atom to the lattice patternMODERN FET STRUCTURES 15m | 5% —> 30% Ge h a Figure 19.12 SiGe enhanced-mobility MOSFET. The n-channel MOSFET incorporates a strained- ‘Si surface channel. (From Welser et al.'"), © 1994 IEEE.) of the underlying Si substrate, Si heterojunction bipolar transistors (HBTs) fabricated with a pseudomorphic SiGe base layer have achieved the highest operating frequency of any Si bipolar device. Because of the constrained lattice spacing, pseudomorphic films are subject to a con- siderable amount of internal stress. Growing a SiGe alloy film beyond a critical thickness causes defects to nucleate spontaneously. The defect generation relieves the stress and al- lows the film to relax to its preferred lattice constant. Relaxed SiGe films are of particular interest in the present context because they have been used in fabricating “enhanced mo- bility” MOSFETS as illustrated in Fig. 19.12. In fabricating the Fig. 19.12 device a compositionally graded SiGe buffer layer, a re~ laxed Sig,Geo 5 layer, and a thin pseudomorphic Si film are sequentially grown on a Si substrate. With strain-telief defects primarily confined to the buffer layer, the relaxed Sig Geo, layer effectively functions as a quality substrate for the pseudomorphic layer. Conforming to the larger lattice constant of Sig Ge, , places the pseudomorphic Si film under tension, The strain in the Si layer in turn gives rise to reduced carrier scattering and a lower electron effective mass parallel to the Si~SiO, interface. These combine to enhance the carrier mobility in the Si surface channel. The pictured device, for example, exhibited a factor of ~ 2 enhancement in the observed low-field mobility over a standard MOSFET, The enhanced mobility, translating into increased current drive at higher fields, has the potential to extend the performance limits of existing MOS technology. SOI Structures ‘The term silicon-on-insulator (SOI) is used to describe structures where devices are fabri- cated in single-crystal Si layers formed over an insulating film or substrate. The first real- ization of SOI structures involved crystalline films of Si deposited on properly oriented sapphire substrates (SOS). Subsequently, laser annealing techniques were used to crystal- lize amorphous Si films deposited on insulators such as SiO, and SisN,. In both of these approaches the Si film quality has impeded their widespread utilization. A more recent approach, epitaxial layer overgrowth (ELO), has solved the film quality problem. In ELO 705706 FIELDEFFECT DEVICES Oxygen UID =n I : Implant oxygen Silicon ‘Anneal to form SiO Silicon - i = Grow CVD epi to SOy required Si thickness Siticon Figure 19.13 Basic steps in the production of a SIMOX wafer. (From Hostack et al.°"} Reprinted with permission.) a hole is opened in the insulator to expose a small section of the underlying crystalline-Si substrate. With the exposed substrate acting as a seed, epitaxial Si is then grown up through the hole and sideways over the insulator. Unfortunately, ELO is not considered to be a production-line technology. Among all the SOI technologies only SIMOX and BESOI are currently considered production-line technologies that are capable of yielding Si films of acceptable quality. Both SIMOX and BESOI wafers are available commercially. In BESOI (BondEd SOI) a SiO, layer, which is to become the insulating layer, is thermally grown on one Si wafer. A second Si wafer is next bonded to the top of the first wafer and annealed. Finally, the top wafer is ground, polished, and chemically etched until the desired surface-layer thickness is attained. In SIMOX (Separation by /Mplantation of (OXygen) the SOI structure is formed by creating an SiO, layer just beneath the surface of a bulk-Si wafer as illustrated in Fig. 19.13. The SIMOX process begins with the ion- implantation of oxygen beneath the Si surface. The O, implant is normally performed em- ploying an accelerating energy of 150-200 keV and involves a total dose of 1-2 x 10!8 atoms/cm, Annealing the structure at an elevated temperature (typically 1300°C for roughly 6 hours) next allows the implanted O, to react with the Si to form a buried oxide (BOX) layer. The anneal also minimizes defects in the surface Si layer. Additional Si is sometimes deposited by standard epitaxial techniques to increase the final thickness of the Si surface layer. Required thicknesses range from 500 A to 2000 A for CMOS applications and from 0.3 zm to 10 jum for thick-film bipolar applications. ‘The numerous projected advantages of SOI-based ICs, particularly MOS ICs, help to ‘explain the extensive research effort expended to develop a viable SOI technology. The dielectric isolation of individual circuit elements possible with SOI reduces parasitic capac-MODERN FET STRUCTURES itances, thereby giving rise to higher operating speeds, and totally eliminates latch-upt, ‘SOI-based MOSFETs are also projected to consume less power, operate at higher tem- peratures, provide improved radiation hardness, and exhibit reduced short-channel effects. From a design standpoint, SOI permits higher packing densities and easier scaling to smaller linewidths. From a fabrication standpoint SOI leads to simpler processing because it permits a reduction in the number of masking (lithographic) steps. Perhaps most impor- tantly, the wafers derived from SIMOX and BESOI are totally compatible with production- line equipment and procedures. The most extensive use of SOI to date is in the production of radiation-hardened SRAMs for military applications. Expanded use is anticipated in the areas of very high speed very large scale CMOS ICs, low-power supply-voltage devices, and DRAMS,"8 19.2.2 MODFET (HEMT) The last member of the FET family to be surveyed is the modulation doped field effect transistor (MODFET). Although MODFET appears to be the preferred acronym for the device structure, itis often alternatively identified as the high electron mobility transistor (HEMT). When first introduced, the structure was sometimes called the selectively doped heterostructure transistor (SDHT) or the two-dimensional electron-gas field effect transistor (TEGFET). A perspective view of an AlGaAs/GaAs MODFET was presented in Fig. 15.7 as part of the general introduction to field-effect devices; a simplified cross sec- tion of the structure is shown in Fig. 19.14(a). The structural similarities of the MODFET and MOSFET are obvious from Fig 19.14(a) if one thinks of the AlGaAs layer as an insulator. The MODFET does differ from the MOSFET in that the “insulating” layer, the AlGaAs, is doped. Moreover, the GaAs epilayer is nominally undoped. The term “modulation doping” arises from the modulation of the dopant source to selectively dope only the AlGaAs layer during the sequential depo- sition of the GaAs and AlGaAs layers. Doping of the AlGaAs helps induce a surface chan- nel adjacent to the AIGaAs/GaAs interface. Because the current-carrying GaAs layer is nominally undoped, there is only minimal scattering from residual (unintentional) dopant impurities in the GaAs surface channel. Very high electron mobilities are observed at room temperature, and an even greater mobility enhancement relative to doped-channel devices like the MESFET is obtained at liquid nitrogen temperatures. This is why the structure is alternatively identified as the “high electron mobility” transistor Greater detail of the gated region and the electrostatic situation inside the MODFET are pictured in Fig. 19.14(b). AlGaAs has a wider band gap than GaAs and, as previously illustrated in Fig. 11.19(a), energy band offsets arise at the AlGaAs/GaAs interface. In the * Latch-up isthe term for a major problem in digital CMOS circuits where the circuitry gets stuck in a specific logic state. Simply stated, ltch-up is caused by an internal feedback mechanism associated with parasitic PNPN- like ection # Although the HEMT acronym continues o be employed, its now recognized thatthe low-field mobility is not ‘the key parameter in determining the characteristics of the device under normal operating conditions. Rather, analogous to MESFET operation described in Section 15.3, its the high-field velocity that becomes the critical parameter when large electric fields exist along the FET channel 707708 FIELD EFFECT DEVICES 5 Schottky n*-Gaas contact’ cap layer mnt TH WITT eatGeas IHU NiGGnoy TOGTGaG Gahs (nominally undoped) Alloyed # Semiinslating ohmic Gas contact, @ Schottky Canned contact conduction eo { pratGaas! fh p-caas LIN N*7 Undoped inversion layer bya] two-dimensional ' electron gas) 1 i t ' | | : 1 i ! i \ i I ! ' i © Figure 19.14 The basic MODFET or HEMT structure. (a) Simplified cross section, (b) Section through the transistor beneath the gate and the associated energy band diagram. [Part (b) from Pierret and Lundstrom'*, © 1984 IBEE.]MODERN FET STRUCTURES MODFET the conduction band offset (AE.) becomes an electron containment barrier, As already noted, the AlGaAs is doped to induce an inversion or accumulation layer of elec- trons at the GaAs surface. (The conducting electron layer is usually referred to as a two- dimensional electron gas in the MODFET literature.) The AlGaAs layer is also made suf- ficiently thin so that it is totally depleted under equilibrium conditions by the built-in potential associated with the Schottky gate contact. The resulting uncompensated dopant ions in the AlGaAs give rise to an energy band diagram very similar to that of a MOSFET with sodium ions distributed throughout the oxide (compare Figs. 19.14b and P18.7). We should note that, because AIGaAs/GaAs is a lattice-matched system, the interface between the two materials is essentially free of fixed charges and interfacial traps, a prerequisite of proper device operation Although exhibiting acceptable electrical characteristics similar to those of other FETs at low current levels, a material-related property of the AIGaAs/GaAs MODFET leads to a degradation of device performance at moderate and high current levels. Specifically, above a certain carrier density, the relatively small conduction band discontinuity at the AlGaAs/GaAs interface permits channel charge to spill over into the AlGaAs. Conse- quently, the carrier density in the channel tends to saturate as a function of the gate poten- tial. Device performance is thereby degraded. Seeking a solution to the problem has led to the development of two second-generation MODFET structures, In one structure a pseu- domorphic In, Ga,,, As layer is positioned between the AlGaAs and GaAs. The addition of In to GaAs reduces the semiconductor band gap and increases the AE, containment barrier. ‘The larger AZ, in turn permits higher carrier densities to be induced in the InGaAs surface channel. The cross section of a pseudomorphic MODFET or PHEMT sold commercially by Hewlett-Packard is reproduced in Fig. 19.15. The other second-generation MODFET features an alternative lattice-matched system—namely, the Aly 43] 57 As/Itp 53 Gap «7 AS/ InP system, where InP is the substrate material. The AZ, at the AllnAs/InGaAs interface is approximately two times the conduction band discontinuity of the AlGaAs/GaAs system, Even though the AllnAs/InGaAs MODFET technology is relatively immature, it already Au nt-GaAs n-AIGaAs Ohmic contact InGaAs Undoped GaAs ‘Semi-insulating GaAs substrate Figure 19.15 Cross section of a commercially available pseudomorphic MODFET or PHEMT. (From the 1993 Hewlett-Packard catalogue of communication components. ©! Reproduced courtesy of Hewlett Packard Co., Components Group.) 709710 FIELD EFFECT DEVICES boasts the highest current-gain cutoff frequency (>250 GHz) yet reported for a three- terminal device. Relative to high-frequency operation, note the mushroom or “T” shape of the gate in Fig, 19.15. Atthe routinely submicron gate-lengths found in MODFETs, the effect of para- sitic resistances often masks intrinsic device performance. While maintaining a small “footprint,” the T shape of the gate metallization increases its current-carrying cross- sectional area and thus reduces its resistance. At present, the MODFET is gradually replacing GaAs MESFETs in many advanced commercial and military systems that demand ultra-high performance. It is an ideal candi- date for applications involving low-noise amplification at microwave and millimeter wave frequencies. Although originally conceived as a ultra-high-speed digital logic device, the compound-semiconductor MODFET is now considered unlikely to replace Si devices in ‘the near future. PROBLEMS, CHAPTER 19 PROBLEM INFORMATION TABLE Complete | Difficulty! Suggested ‘Short Problem |“ ster | Level Point Weighting Description 191 | 19.22 1 [15 (each part) | Quick quiz 19.2.2 | 1 | 5(1/2each answer) | Acronyms and abbreviations | 19.3} 912 | 2-3 | 12@5,65,62) | Ly, AV; calculations 194 | 1921 | 1 | 10@eachpart) | Identify unique features tos | 1922 | 2-3 [30(Scach part) | Summarize journal articles 19.1 Quick Quiz Answer the following questions as concisely as possible. (a) Small-dimension effects are generally undesirable and are minimized or avoided in commercial MOSFET structures through the proper scaling of device dimensions or ‘modifications in device design. True or false? (b) Name the three most commonly cited indications of short-channel effects. (©) Relative to threshold-voltage modification, how do the short-channel and narrow-width effects differ? In what ways are they alike? (@) For a fixed channel Jength and channel width, name two other MOSFET parameters that can be adjusted to minimize small-dimension effects. Also indicate how the pa- rameters must be adjusted to reduce small-dimension effects. (©) Name (wo BJT-like phenomena that have been observed in short-channel MOSFETs. (f) Describe what happens inside a MOSFET affected by the hot-carrier phenomenon known as oxide charging.MODERNFETSTRUCTURES © 711 (g) Why is oxide charging associated with hot-carrier effects more important in short- channel devices? (b) How can you tell whether velocity saturation is affecting the Jy~V,, characteristics of a MOSFET? (i) Indicate what is meant by ballistic transport. (i) Indicate what is meant by velocity overshoot. (k) Describe a popular approach for minimizing the oxide charging problem. (). What exactly is a pseudomorphic film? (m) Cite two examples of pseudomorphic films in device structures. (a) Briefly summarize the SIMOX process. (©) Whatiis the difference between a MODFET and a HEMT? 19.2 Acronyms and Abbreviations Indicate what the following acronyms and abbreviations stand for: LDD, DMOS, SOI, ‘SOS, ELO, SIMOX, BESOI, BOX, MODFET, and PHEMT. 19.3 (a) Making use of the parameters supplied in the figure caption, compute the expected Lyin for the Fig. 19.3 device when Vp = 0.125 V. Assume n*-p drain and source step junctions and that the source and back are grounded. Comment on your computational resull. (b) Utilizing Eq. (19.13), what is the AV; expected for the Fig. 19.3 device when L=1 mand Vp = 0.125 V? (©) Can Eq. (19.13) be applied to compute an expected AV; for comparison with the Vp = 4 V data? Explain. 19.4 Briefly indicate the unique physical feature of the following transistor structures: (@) LDD transistors (b) DMOS (©) Buried-channel MOSFET (@) Enhanced-mobility (strained-Si) MOSFET (©) SOI structures 19.5 Read the following journal artictes and prepare a one- to two-page summary of each article, (a) J.J. Sanchez, K. K. Hsueh, and T. A. DeMassa, “Drain-Engineered Hot-Electron Re- sistant Device Structures: A Review,” IEEE Trans. on Electron Devices, 36, 1125 Gune 1989). (b) M.J. Van der Tol and S. G. Chamberlain, “Potential and Electron Distribution Model for the Buried-Channel MOSFET,” IEEE Trans. on Electron Devices, 36,670 (April 1989).712 FIELD EFFECT DEVICES (©) B.S. Meyerson, “UHV/CVD Growth of Si and Si:Ge Alloys: Chemistry, Physics, and Device Applications,” Proc. IEEE, 80, 1592 (Oct. 1992). (d) B.S. Meyerson, “Ultrahigh- Vacuum CVD Process Makes SiGe Devices,” Solid State ‘Technology, 37, 53 (Feb. 1994), (e) L. Peters, “SOI Takes Over Where Silicon Leaves Off,” Semiconductor International, 16, 48 (March 1993). (©) L. D. Nguyen, L. E. Larson, and U, K. Mishra, “Ultra-High-Speed Modulation-Doped Field-Effect Transistors: A Tutorial Review,” Proc. IEEE, 80, 494 (April 1992).