10/18/2019

ENGINEERING DESIGN THINKING

DIGITAL ELECTRONICS SPEAKER YVONNE LIN
SYSTEM DESIGN  Yvonne Lin (AB ENGN ‘00)
 Founder, 4B Collective and the Femme Den
 Thursday, Oct. 17, 12-1pm
FALL 2019  B&H 190
PROF. IRIS BAHAR  Title: Design Engineering: Making Actual Stuff.
Taking a product idea from inception to fruition
OCTOBER 16, 2019
 Yvonne will speak about her path from Brown to the design
LECTURE 12: CMOS TRANSIENT BEHAVIOR (CONTINUED) world and what it took to get there
 How design works: from idea to real life
 What is design engineering? How is it different from
traditional engineering
 Putting together a design portfolio (to land a great job)

CMOS INVERTER: DYNAMIC

HOMEWORK PROBLEMS BEHAVIOR
VDD
 Transient, or dynamic,
 To give you practice on some of the concepts covered in response determines the
class (and the labs), Jiwon has prepared a practice maximum speed at which a
homework set Rp
device can be operated.
 You can find it on the course webpage
 Look under Handouts and “Exam related materials from 2019”
Vout = 0
 I am also including homework sets from past years prepared tpHL = f(Rn, CL)
CL
by Prof. Patterson. Rn

Vin = V DD

1
 10/18/2019

INPUT PATTERN EFFECTS ON DELAY TRANSISTOR SIZING

 How should NMOS and PMOS devices be sized relative to an
 Delay is dependent on the pattern of inputs inverter with equal rise/fall times?
Rp Rp  1st order approximation of delay:  Size for the worst case series path
A B tp ≈ 0.69 Reff CL
1 = 2Wmin Rp Rp 1 = 2Wmin 2 = 4Wmin Rp
Rn CL A B B
 Reff depends on the input pattern
A
2 = 4Wmin R
Rn 2 Rn CL p Cint
Cint  To get (more equal) rise/fall delays, we need A A
B to size transistors not just to compensate
for differences in mobility, but also for 2 R Rn Rn
n Cint CL
differences in the topology. 1 1
B A B

WIRE DELAY MODELS WIRE DELAY MODELS, CON’T

 Lumped RC model
 Lumped C model  total resistance and capacitance are lumped into a single R, C respectively
 good for short wires; pessimistic and inaccurate for long wires
 when only a single parasitic component (C, R, or L) is dominant the different
fractions are lumped into a single circuit element  Distributed RC model
 circuit parasitics are distributed along the length, L, of the wire
 c and r are the capacitance and resistance per unit length

rL rL rL rL rL (r,c,L)

Driver Vin VN Vin VN
RDriver
Vout Vout cL cL cL cL cL

cwire Clumped
 Delay is determined using the Elmore delay equation:
N
capacitance per unit length Di =  ckrik
k=1
 good for short wires; pessimistic and inaccurate for long wires

2
 10/18/2019

CHAIN NETWORK ELMORE DELAY CHAIN NETWORK ELMORE DELAY

r1 r2 ri-1 ri rN D1=c1r1 D2=c1r1 + c2(r1+r2)
1 2 i-1 i N
Vin VN r1 r2 ri-1 ri rN
1 2 i-1 i N
c1 c2 ci-1 ci cN Vin VN
c1 c2 ci-1 ci cN

 A typical wire is a chain network with (simplified) Elmore

Di=c1r1+ c2(r1+r2)+…+ci(r1+r2+…+ri)
delay of N i
DN =  cirij =  ci  rj
N i
i
Elmore delay equation DN =  cirii =  ci  rj
 Where  rj = r1 + r2 + … + ri
If all resistors are equal size,
Di=c1req+ 2c2req+ 3c3req+…+ icireq

FANIN CONSIDERATIONS TP AS A FUNCTION OF FANIN

1250
quadratic
1000 function of
fanin
A B C D
750 tpHL
Distributed RC model
A (Elmore delay) tp (psec) tp
CL 500

B C3
tpHL = 0.69 Reqn(C1+2C2+3C3+4CL) 250 tpLH
C C2 (assuming all NMOS equally sized) linear function
0 of fanin
D C1 2 4 6 8 10 12 14 16
Propagation delay deteriorates rapidly
fanin of NAND gate
as a function of fanin: quadratically in
the worst case.  Gates with a fan-in greater than 4 should be avoided.

3
 10/18/2019

D LATCH
Clk D R S Q Q’
1 1 0 1 1 0
1 0 1 0 0 1
0 X 0 0 Qprev Q’prev

SEQUENTIAL LOGIC D
R (reset) Q
D Q

Q’ Clk Q’
S (set)
Clk

 Circuit guarantees R=S=1 will never occur

FLIP-FLOP FLIP-FLOP MADE FROM D-LATCHES

D D Q D Q Q
 Flip-flop: Samples input on triggering edge of clock
 Rising edge  positive edge-triggered flip-flop Q’ Q’
Clk Clk
 Falling edge  negative edge-triggered flip-flop
Clk

D Clk Q
 D flip-flop: Two D latches back-to-back
0 0
 Copies D to Q
D Q
1 1 on the rising edge
Q’ X 0 Qprev of the clock

Clk X 1 Qprev

4
 10/18/2019

D FLIP-FLOP VS. D LATCH D FLIP-FLOP VS. D LATCH

CLK CLK
D Q D Q D Q D Q
Q Q Q Q

CLK CLK

D D

Q (latch) Q (latch)

Q (flop) Q (flop)

FLIP-FLOPS VS. LATCHES TIMING METRICS

clock
clock tsu = setup time for
data before
 Why use a flip flop when it just takes twice as much logic? clock edge
tsu thold time
 When would you want to use a flip-flop instead of a latch? thold = time data
In data must remain
stable valid after
clock edge
tc-q time
output output tc-q = max FF delay
Out from clock
stable stable
edge to output Q
time

5
 10/18/2019

SYSTEM TIMING CONSTRAINTS LATCH RACE PROBLEM

tplogic = worst case delay
Sequential Circuit B
through combinational B B’
logic
inputs Combinational outputs tcdlogic = min. delay through
Logic combinational logic
Prev. Next tcdreg = min. delay through
State register logic clk
State
State

clk T (clock period) clk Which value of B is stored?

Two-sided clock constraint
T  tc-q + tplogic + tsu
T  tc-q + tplogic + tsu tcdreg + tcdlogic  thold Thigh  tc-q + tcdlogic

NMOS TRANSISTORS IN
SERIES/PARALLEL
 So far we have assumed that primary inputs are only allowed to
drive gate terminals of MOS transistors.
 Now assume primary inputs can drive both gate and source/drain
terminals
 NMOS switch closes when the gate input is high
A B

PASS TRANSISTOR LOGIC X Y

X = Y if A and B

B X = Y if A or B
X Y

 Remember - NMOS transistors pass a strong 0 but a weak 1

6
 10/18/2019

PASS TRANSISTOR (PT) LOGIC VTC OF PASS TRANSISTOR AND GATE

B
B B
A A 2
F =A  B B B=VDD, A=0VDD
B
0 F =A  B

Vout,V
0 A 1

B A=VDD, B=0VDD
 Gate is static – a low-impedance path exists to both F = AB
A=B=0VDD
supply rails under all circumstances 0 0
0 1 2

 N transistors instead of 2N
 Pure PT logic is not regenerative: signal gradually
 No static power consumption degrades after passing through a number of PTs
 Bidirectional (versus non-directional)  fix with static CMOS inverter insertion

NMOS ONLY PT DRIVING AN

INVERTER
3
In
In = VDD
2
Vx = M2 x = 1.8V
VGS
A = VDD VDD-VTn
Voltage, V

D S
1
B M1
Out
0
0 0.5 1 1.5 2
Time, ns

 Vx does not pull up to VDD , but VDD – VTn

 Threshold voltage drop causes static power dissipation (M2
may be weakly conducting forming a path from VDD to GND)