Basic Electronic Devices and Circuits

EEE 2201

Md. Sahabuddin
Assistant Professor
Dept. of Biomedical Engineering (BME)
Jashore University of Science and Technology (JUST)
References:
 Electronic Devices and Circuit Theory
Robert L. Boylestad
Louis Nashelsky
 Principles of Electronics
V.K. Mehta
Rohit Mehta
 A Text Book of Electrical Technology Volume IV
B.L Theraja
A.K Theraja
 Microelectronic Circuts
Sedra and Smith
 Op – Amps and Linear Integrated Circuits
Ramakant A. Gayakward
The field-effect transistor (FET)
 The field-effect transistor (FET) is a three-terminal device used for a variety of applications that match, to a large
extent, those of the BJT transistor.
 It is a three-terminal unipolar solid-state device in which current is controlled by an electric field.

 BJT transistor is a current-controlled device while the JFET transistor is

a voltage-controlled device.
 There are npn and pnp bipolar transistors, there are n-channel and p-
channel field-effect transistors.
 BJT transistor is a bipolar device—the prefix bi- revealing that the
conduction level is a function of two charge carriers, electrons and holes.
The FET is a unipolar device depending solely on either electron (n-
channel) or hole (p-channel) conduction.
 One of the most important characteristics of the FET is its high input
impedance.
The FET family tree is shown below
Junction FET (JFET)
Basic Construction
As shown in figure it can be fabricated with either an N-channel or P-channel though N channel is generally preferred.
For fabricating an N-channel JFET, first a narrow bar of N-type semiconductor material is taken and then two P-type
junctions are diffused on opposite sides of its middle part. These junctions form two P-N diodes or gates and the area
between these gates is called channel. The two P-regions are internally connected and a single lead is brought out
which is called gate terminal. Ohmic contacts (direct electrical connections) are made at the two ends of the bar-one
lead is called source terminal S and the other drain terminal D. When potential difference is established between
drain and source, current flows along the length of the ‘bar’ through the channel located between the two P-regions.
The current consists of only majority carriers.

 P-channel JFET is similar in construction except that it uses

P-type bar and two N-type junctions.
 Source. It is the terminal through which majority carriers enter
the bar. Since carriers come from it, it is called the source.
 Drain. It is the terminal through which majority carriers leave
the bar i.e. they are drained out from this terminal. The drain-to
source voltage V DS drives the drain current ID.
 Gate. These are two internally-connected heavily-doped
impurity regions which form two P-N junctions. The gate-source
voltage VGS reverse biases the gates.
 Channel. It is the space between two gates through which
majority carriers pass from source-to-drain when VDS is applied.
 Gates are always reversed-biased. Hence, gate current IG is
practically zero.
 The source terminal is always connected to that end of the
drain supply which provides the necessary charge carriers. In
an N-channel JFET, source terminal S is connected to the
negative end of the drain voltage supply (for obtaining
electrons). In a P-channel JFET, S is connected to the positive
end of the drain voltage supply for getting holes which flow
through the channel.
Theory of Operation
When VGS = 0 and VDS = 0
In this case, drain current ID = 0, because VDS = 0. The depletion regions around the P-N
junctions are of equal thickness and symmetrical.
When VGS 0 V, VDS Some Positive Value
 A positive voltage VDS has been applied across the channel and the gate has been
connected directly to the source to establish the condition VGS =0 V. The result is a
gate and source terminal at the same potential and a depletion region in the low end
of each p-material similar to the distribution of the no-bias conditions.

 As the voltage VDS is increased from 0 to a few volts, the

current will increase as determined by Ohm’s law and
the plot of ID versus VDS will appear as shown in figure.

 As VDS increases and approaches a level referred to as

VP in figure, the depletion regions will widen, causing
a noticeable reduction in the channel width.
 The reduced path of conduction causes the resistance to increase and the curve in the graph occurs. The more
horizontal the curve, the higher the resistance, suggesting that the resistance is approaching “infinite” ohms in
the horizontal region.

 If VDS is increased to a level where it appears that the two depletion regions would “touch”, a condition referred
to as pinch-off will result. The level of VDS that establishes this condition is referred to as the pinch-off voltage
and is denoted by VP .
When VGS <0 V

The voltage from gate to source, denoted VGS, is the controlling voltage of the JFET. For the n-channel device the
controlling voltage VGS is made more and more negative from its VGS = 0 V level. In other words, the gate terminal
will be set at lower and lower potential levels as compared to the source.
TRANSFER CHARACTERISTICS
The metal-oxide-semiconductor-field-effect transistor(MOSFET)

 MOSFETs are further broken down into depletion type and enhancement type

Basic Construction
A slab of p-type material is formed from a silicon base and is referred to as the
substrate. It is the foundation upon which the device will be constructed. In some
cases the substrate is internally connected to the source terminal. However, many
discrete devices provide an additional terminal labeled SS, resulting in a four-
terminal device. The source and drain terminals are connected through metallic
contacts to n-doped regions linked by an n-channel as shown in the figure. The gate
is also connected to a metal contact surface but remains insulated from the n-
channel by a very thin silicon dioxide (SiO2) layer.

 There is no direct electrical connection between the gate terminal and the channel of a MOSFET.
Basic Operation and Characteristics

Figure : Drain and transfer characteristics for an n-channel depletion-type

Figure : n-Channel depletion-type MOSFET with VGS =0 V and MOSFET.
an applied voltage VDD.
ENHANCEMENT-TYPE MOSFET
Basic Construction
A slab of p-type material is formed from a silicon base and is again referred to as the substrate. As with the depletion-
type MOSFET, the substrate is sometimes internally connected to the source terminal, while in other cases a fourth lead
is made available for external control of its potential level. The source and drain terminals are again connected through
metallic contacts to n-doped regions, but note the absence of a channel between the two n-doped regions. This is the
primary difference between the construction of depletion-type and enhancement-type MOSFETs—the absence of a
channel as a constructed component of the device. The SiO2 layer is still present to isolate the gate metallic platform
from the region between the drain and source, but now it is simply separated from a section of the p-type material. In
summary, therefore, the construction of an enhancement-type MOSFET is quite similar to that of the depletion-type
MOSFET, except for the absence of a channel between the drain and source terminals.
VMOS and CMOS
DC Load Line
FIXED-BIAS CONFIGURATION
Applying Kirchhoff’s voltage law in the clockwise direction of
the indicated loop of Fig. 6.2 will result in