Static Digital Pre-Distortion Method for High-Speed

Current-Steering Digital-to-Analog Converters

Patrick Valet David Schwingshackl Ulrich Gaier Andrea M. Tonello
Connected Home Division Connected Home Division Connected Home Division Networked & Embedded Systems
2021 Austrochip Workshop on Microelectronics (Austrochip) | 978-1-6654-3661-8/21/$31.00 ©2021 IEEE | DOI: 10.1109/Austrochip53290.2021.9576860

MaxLinear Austria GmbH MaxLinear Austria GmbH MaxLinear Austria GmbH Klagenfurt University
Villach, Austria Villach, Austria Villach, Austria Klagenfurt, Austria
[email protected] [email protected] [email protected] [email protected]

Abstract—This paper presents a static digital pre-distortion DAC (CALDAC) which adds the mismatch current to
(DPD) method for a current-steering digital-to-analog converter the converter output [4]–[6].
(CS-DAC). The proposed model utilizes the knowledge of the • Current source calibration: a common analog calibra-
current cell array architecture to calculate the static mismatch
currents of the cells. The mismatch values of all cells are stored in tion method for CS-DACs is to calibrate the current
memory and added to the original input code to generate the new sources [7].
pre-distorted input word. The converter corrects the static error • Black Box approach: this class of methods use polyno-
with its own current cells without incorporating an additional mial functions with memory such as the Volterra series,
calibration DAC (CALDAC) or programmable current sources. Wiener model or generalized memory polynomial, which
This results in a reduction in area, power and simulation run
times because of the simpler circuit design. The proposed method estimate the inverse transfer function of the non-linear
is able to use an information signal for the calibration phase, thus system [8].
it is possible to be implemented as a background calibration. • Look-up-table (LUT) approach: these methods estimate
The evaluation of the proposed DPD is done via simulations in a mismatch factor for every possible code of the DAC and
MATLAB with a 14-bit static CS-DAC model. The results show store those in a LUT. The LUT is searched through for
a performance gain of the signal-to-noise-plus-distortion ratio
(SNDR) of up to 16 dB. every new input code [9]–[11].
Index Terms—Digital pre-distortion, calibration, DAC, When closer investigating the above listed methods, the
current-steering, digital-analog conversion, MATLAB, signal following disadvantages can be determined:
processing
• Change of switching sequence: only applicable for
unary coded DAC segments and faster performance de-
I. I NTRODUCTION crease for higher standard deviation of static mismatch
currents, compared to other methods.
M ODERN communication systems require high-speed
digital-to-analog converters (DAC). The current-
steering architecture is almost exclusively used for those ap-
• CALDAC methods: additional current sources for the
CALDAC cost area, power and can also have a nega-
plications due to its high switching frequencies. The static ran- tive influence on the dynamic linearity of the converter
dom mismatch between the current cells introduces distortions because more cells are switching.
in the output spectrum of the converter due to imperfections • Current source calibration: current sources need to be
in the manufacturing process. Dynamic non-linearities arise designed to be adjustable. Often only applied for the
from clock network timing errors, clock jitter and charge MSB segment. Lower segments might not get calibrated.
feedthrough [1]. Additionally, these effects introduce signal Increased complexity of the circuitry and simulation
dependent harmonics in the output spectrum. These spectral times.
impurities are the main factor in limiting the spurious free • Black Box approach: no insight into the schematic of
dynamic range (SFDR) and the signal to distortion ratio the chip. It does not consider the physical behavior and
(SDR). Various calibration and linearization techniques have reasons for the non-linearities of the system.
been proposed to counteract these non-idealities: • Look-up-table approach: Size of LUT grows exponen-
tially with the number of bits (NLU T = 2Nbits ) of the
• Change of switching sequence: source currents are mea- DAC. Crucial factor when implementing the DPD method
sured for each individual cell and the switching sequence in hardware in terms of area.
is rearranged post-fabrication [2], [3].
• CALDAC methods: static mismatch currents are mea- The proposed static digital pre-distortion (DPD) method
sured per cell and compensated for with a calibration averts those disadvantages. The main idea is to estimate the
static mismatch of each individual current cell and to add that
mismatch value to the original input of the DAC to attenuate
978-1-6654-3661-8/21/$31.00 ©2021 IEEE the distortions. The reduction of the static non-linearity results
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 in a better lineartiy performance of the converter. In addition
the DAC current cell array can be designed smaller, thus
reducing area cost. The proposed DPD does not implement
a CALDAC or programmable current cells but instead can
correct the static mismatch itself using the original current
array. This further results in a reduction in area and power.
Furthermore, it reduces the simulation run-times of a cir-
cuit simulator, e.g., Spectre, since the number of nodes in
the schematic is reduced. The shown model-based approach
(MBA) can be implemented in hardware or as a software
solution into already existing designs and lab/measurement
equipment (e.g., arbitrary wave generator (AWG)) which in-
clude a current cell DAC architecture to enhance the static
performance. Fig. 1: DAC transfer curve
An important part of the MBA is the accuracy of the
estimation algorithm for the mismatch factors of the individual FS

current sources. When looking at the equations for the output dinDPD[n]
din[n] bin2thermo DEM DPD DAC y(t)
current of a unary current steering DAC it can be seen that
those factors can be estimated with the least-squares algorithm. F S/ L
ΔILSB
Mathematical model for the ideal output current: Estimation
y[n]
ADC
Algorithm
N!
CS −1

IOU T [n] = Din !k" [n] ∗ Ik (1) Fig. 2: Block diagram of MBA architecture
k=0

Real output current:

The rest of the paper is organized as follows. Section II
N!
CS −1 focuses on the proposed digital pre-distortion method itself. It
IOU T [n] = Din !k" [n] ∗ Ik ∗ αk,CS (2) describes the most important building blocks such as how the
k=0 mismatch codes are calculated and the selection of the cells is
Where IOU T is the DAC output current, Din !0 : N − 1" is accomplished and shows how it differentiates itself from prior-
the N-bit unary coded digital input word, NCS is the number art. Section III compares the performance of the MBA with
of current cells of the converter, Ik is the unit current of the other DAC calibration methods found in the literature through
k-th current cell and αk,CS stands for the mismatch factor MATLAB simulations. Section IV concludes this paper.
of the current cells. The ideal output current is the sum of all
current sources that are switched to the output. Due to process II. M ODEL BASED A PPROACH (MBA)
variations during the manufacturing, Ik is not equal for all
current sources. The current mismatch is defined as mismatch The model based approach (MBA) uses the knowledge of
per current cell. The estimation is done by comparing the real the circuit architecture of the DAC to compensate for the static
current cell values at the DAC output to the ideal values also current cell mismatch. Fig. 2 depicts the block diagram of the
known as a direct learning architecture as shown in [12]. overall system.
The impact of the current cell mismatch can be visualized The original digital input word din[n] is a binary input
with the transfer curve of the DAC. An example of such a vector that feeds into the binary-to-thermometer converter
transfer characteristic of a 3-bit converter is shown in Fig. 1. and the ”Estimation Algorithm” block. The second input of
The solid line is the ideal curve and the dashed line depicts this block is the digitized DAC output y[n]. The DPD block
the non-ideal case. It can be seen that due to the static is programmed with the ∆ILSB vector. It contains all the
mismatch the DAC output voltage deviates from the straight mismatch values of the current cells normalized to one LSB
line. This is called the integral non-linearity (INL). The plot current. Those values pre-distort the input and result in the
also shows that the non-ideal output voltage of input code signal dinDP D [n] which feeds into the converter input. The
101 has a similar value as the ideal Vout of code 100. This analog output must be converted back to the digital domain.
means to get a output voltage level which is closer to the The analog-to-digital converter (ADC) has to be built linear
ideal value, the input code has to change from 100 to 101. enough so that the least-squares algorithm can deliver accurate
Within this lies the basic working principle of the MBA. The results. Usually those ADCs work with a factor L lower
knowledge of the current mismatches is used to self-correct update frequency than the DAC. In addition to the digital pre-
the DAC output with its own cells, thus negating the need distortion, a DEM algorithm is also used to further spread
for additional compensation cells. This also results in a static the remaining distortions across the spectrum and increase the
accuracy of ±0.5 LSB. performance of the DAC.
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 Thermo- TCAout[n] Overflow Cell din,DPD[n]
DEMOUT[n]
Code-Adder Selection

ΔILSB0 ΔICode ΔILsbCode

+ X
0

ΔILSB1
+
0
.
din[n]
. 1/ILSB
.
.
ΔILSBN-2
+
0

ΔILSBN-1
0

Fig. 3: Block diagram of DPD Block

A. DPD Block
The DPD Block shown in Fig. 3 generates the pre-distorted
digital input word for the DAC. The output of the DEM block Fig. 4: Comparison of INL curves with and without OCS
controls N switches. Depending on the value of DEMOU T [n]
the mismatch values ∆ILSBk of the respective current cells are
added up. This results in a scalar mismatch value ∆ICode for value of the MSB cell should be the total current of the ISB
every k-th DEM output vector. The result then is normalized segment plus one additional ISB current source.
by the LSB current and the digital code is added to the !
original input and sent to the DAC. The mismatch values IM SB = IISB,i + IISB (3)
i
are determined in the ”Estimation Algorithm” block in Fig.
2. It implements the least-squares algorithm to estimate the The OCS method searches through the MSB segment to find
mismatch factors for the current cells. At the summation point the best matching cell according to the equation above. Due to
a so called “Thermo-Code-Adder (TCA)” is used. The function the static mismatch not one ISB unit current source is added,
of the TCA is to add the calculated mismatch code of the DPD but the mean current value of the whole segment. This changes
block to the original output of the DEM block in a way, so that the equation for the reference value to:
the rules of the used DEM method are uphold, i.e., the start and 2N 2N
!
ISB −1
1 !
ISB −1
end indices of the input code stay the same regardless of the IM SB,ref = IISB,i + IISB,i (4)
value of the mismatch code. If the current value of ∆ILsbCode i=1
2N
ISB − 1 i=1
is positive, the TCA selects from those current cells to switch
With NISB being the number of bits in the unary coded ISB
on that are currently in their switched off state.
segment. The OCS chooses the cell closest to IM SB,ref .
B. Overflow-Cell-Selection (OCS) Cellswitch = mini=1···2M −1 (IM SB,i − IM SB,ref ) (5)
A problem arises, if during the addition of the mismatch
code to the original digital input word, one DAC array over- With M being the number of bits in the unary coded MSB
flows and a cell from the next higher segment must switch. segment. The cell numbers are then stored in memory. The
This is especially critical if a cell in the MSB segment is impact when using OCS can be clearly seen in the INL plot.
affected. This leads to big spikes in the INL. This problem Fig. 4 show simulation results of the INL of a 14 bit DAC
is counteracted by the so called “Overflow-Cell-Selection”- with a relative standard deviation σM SB of 0.5 % for the
Method (OCS). It chooses the best cell to switch to minimize static current cell mismatch. The solid curve shows the INL
the mismatch when an overflow occurs. An example for such without using the proposed pre-distortion method, the dashed
an overflow is shown below. line depicts the INL of our model-based approach without
This example uses a 14-bit segmented DAC. The segmen- OCS and the dotted line with the OCS activated. While the
tation scheme is 7-3-4 with a 7-bit unary-coded MSB array MBA without OCS is already displaying a great improvement
followed by a 3-bit unary-coded ISB array then a 4-bit binary- in static linearity, there are still significant spikes at codes
coded LSB array. where overflows of the ISB segment occur, that can be further
improved on. When using the OCS method, most of the spikes
din = 742310 ⇒ 0111001 | 111 | 11112 are no longer visible, thus showing that it further improves the
static performance of the DAC.
The calculated mismatch value for this input word is taken as
1 LSB and gets added to din . III. S IMULATIONS
dinDP D = 742410 ⇒ 0111010 | 000 | 00002 The performance of the above described DAC pre-distortion
method is evaluated using simulations. The simulations use a
The example above shows that the ISB segment overflows and static non-linearity model of a 14-bit segmented DAC which
one MSB cell is switching. In a first step the OCS searches incorporates the random mismatch between current cells. The
for all the codes where such an overflow happens. Ideally, the modelled converter is suitable for high speed applications. For
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 cells to compensate for the static current mismatch.
IV. C ONCLUSION
This paper presents a digital pre-distortion (DPD) method,
herein referred to as model-based approach (MBA), that uses
the DACs own cells to correct for the static mismatch without
introducing any additional analog circuitry. The overflow-cell-
selection (OCS) gives an innovative solution to enhance the
static linearity of the converter. When adding the mismatch
code the best cell in terms of difference to the ideal transfer
function is selected to switch. Simulations show an improve-
ment of the signal-to-noise-plus-distortion ratio (SDNR) of
up to 16 dB. The comparison to other state-of-the-art CS-
DAC static calibration methods also shows competitive results.
Fig. 5: Comparison of MBA with prior-art based on SNDR Further research needs to be done to gain knowledge on the
effectiveness of the MBA with measurements on real silicon.
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