Hello, and welcome to this presentation of the embedded

Flash memory which is included in all products of the

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The STM32G4 microcontrollers embed up to 512
Kilobyte of Flash memory with dual-bank architecture.
The Flash memory interface manages all memory
access (read, programming and erasing) as well as
memory protection, security and option bytes.
Applications using this Flash memory interface benefit
from its high performance together with low-power
access. It supports read-while-write, has a small erase
granularity, a short programming time and allows dual-
bank booting.
It provides various security and protection mechanisms
for code and data, read and write access.

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This slide highlights the differences regarding the flash
memory implementation between STM32G43X/4X,
called category 2 microcontrollers, and STM32G47X/8X,
called category 3 microcontrollers:
Flash memory size is 128 Kbytes for category 2, 512
Kbytes for category 3
Number of banks is 1 for category 2, 1 or 2 for
category3, depending on the DBANK option bit. Note
that read-while-write capability (or RWW) is only
supported when the dual-bank architecture is active. This
enables programming or erasing one bank while
executing code from the other bank.
The page size which provides the minimum erase
granularity is 2 KB for category 2, 4 KB for category 3
with single bank and 2 KB for category 3 with dual bank.
The number of pages is 64 for category 2 and 128 for
category 3.

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Regarding protection features, the category 2
microcontrollers have 1 Write Protect area, 1 PCROP
and 1 securable memory area while category 3
microcontrollers have 2 write protect areas, 2 PCROPs
and two securable memory areas.

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The Flash memory supports page erase, bank erase and
mass erase.
A page, bank or mass erase operation requires only 22
ms, and the programming time is only 82 µs for a double-
word.
Fast programming mode writes 64 double-words in a row
and reduces the page programming time eliminating the
need for verifying the Flash locations for each double-
word access and in addition avoiding the rising and
falling time of the high voltage for each double-word
writing.
An 8-bit ECC code is appended to the double-word to
program. It is checked on read to detect and correct
single-bit errors and detect double-bit errors.
In case of an uncorrectable error, the Flash memory
controller asserts the Non-Maskable Interrupt (NMI) to
the Cortex®-M4.

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The adaptive real-time memory accelerator, with an
instruction cache, a data cache and a prefetch buffer,
allows a linear performance in relation to the frequency.
It also contributes to decrease the power consumption,
as it belongs to the Vcore power domain.
The following protection mechanisms are supported.
• Write protection areas, used to protect against
unwanted write operation.
• Proprietary code read protection areas (or PCROP): a
part of the flash memory can be protected against
access from third parties.
• The protected area is execute-only: it can only be
reached by the STM32 CPU, as an instruction code
area, while all other accesses (DMA, debug and CPU
data read, write and erase) are strictly prohibited.
• The securable memory area defines an area of code
which can be executed only once at boot, and never

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again, unless a new reset occurs.

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The main memory contains 64 or 128 pages depending
on the category of the microcontroller.
For Category 3 with a single-bank architecture, page size
is 4 KB, each page consists of 8 rows of 512 bytes.
For Category 3 with dual-bank architecture and Category
2, page size is 2 KB, each page consists of 8 rows of
256 bytes.
In addition to main Flash memory, the STM32G4
supports:
• A System memory of 28 Kbytes containing the ST
bootloader
• A 1-Kbyte OTP memory that can be used to store
user data that must not be erased or modified. If one
bit is ‘0’, the entire double-word can no longer be
written, even with the value ‘0’.
• Options bytes containing default settings to configure
IPs in the system-on-chip. They are automatically

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loaded after a power-up reset.

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The first table details the memory organization based on
a Main Flash memory area and an information block for
Category 3 microcontrollers with dual-bank architecture.
The second table details the granularity of the Flash
memory operations:
• Programming is done on 8-byte double words
• Fast programming is done on a row of 512 bytes
• Erase is done either globally (mass erase) or with
bank or page granularity.
• The securable memory is aligned on pages.
• Write protection is done per page
• Read protection is global
• Proprietary Code Readout Protection is based on
programmable start and end addresses aligned on
either quad-words or double-words.
The DUALBANK (DBANK) option is used to select either
a single bank or a dual bank for the category 3 devices.
The Flash memory can be configured to support two
banks, with read-while-write and dual-bank boot
capability, able to boot from either Bank 1 or Bank 2.
The BFB2 option in the user option bytes is used to
select the dual-bank boot mode. When the BFB2 option
is set, the device boots either from Bank 2 or Bank 1
depending on the valid bank. When the BFB2 option is
cleared, the device always boots from Bank 1.

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In order to read the Flash memory, it is required to
configure the number of wait states to be inserted in a
read access, depending on the clock frequency. The
number of wait states also depends on the voltage
scaling range. In Range 1, the Flash memory can be
accessed up to 170 MHz with 7 wait states. It can be
accessed with 0 wait states up to 20 MHz. For Range 2,
it is up to 26 MHz, with 2 wait states. Thanks to the
adaptive real-time accelerator, the ART accelerator, the
program can be executed with 0 wait states independent
of the clock frequency. This provides an almost linear
performance in relation to the frequency with a
benchmark result of 213 Dhrystone MIPS at 170 MHz.

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Data in Flash memory words are 72-bits wide: eight bits
are added per each double word (64 bits). The ECC
mechanism supports:
• One error detection and correction
• Two errors detection
When one error is detected and corrected, the ECCC
flag (ECC correction) is set in the Flash ECC register
(FLASH_ECCR). An interrupt can be generated.
When two errors are detected, the ECCD flag (ECC
detection) is set in the Flash ECC register
(FLASH_ECCR). In this case, an NMI is generated

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Fast programming enables the programming of a row of
256 bytes while normal programming has a granularity of
8 bytes.
The main purpose of Fast Programming is to reduce the
page programming time. It is achieved by eliminating the
need for verifying the Flash memory locations before
they are programmed, thus saving the time of high-
voltage ramping and falling for each double-word.

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Fast programming is one third faster than standard mode
programming.
Mass erase time, meaning a 512-Kbyte erase operation,
approximately takes the same time as a page erase.

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Fast programming vs standard programming:
• 512 consecutive bytes are programmed instead of 8-
byte double-words located anywhere in the main
Flash memory
• 8-byte programming is more reliable due to the
verification step.
Note that the maximum time between two consecutive
double words is around 50 µs. If a second double word
arrives after this delay, fast programming is aborted and
an error flag is set. Consequently interrupts should be
disabled to make sure that this delay is not exceeded.

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This table summarizes the differences between standard
and fast programming.

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Each program / erase operation can degrade the Flash
memory cell.
After an accumulation of program / erase cycles,
memory cells can become non-functional, causing
memory errors.
Endurance is the maximum number of
erase/programming sequences that the Flash memory
can support without affecting its reliability.
Data retention is defined as retaining a given data
pattern for a given amount of time.
The retention depends on the number of program/erase
cycles and also on the temperature.

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The ART accelerator brings outstanding performance
and reduces dynamic power consumption.
It consists of a 1-KByte instruction cache, 256 bytes of
data cache and a prefetch buffer.
The instruction cache contains 32 lines of 4 double-
words and the data cache has 8 lines of 4 double-words.
Once all the instruction cache memory lines have been
filled, the LRU (least recently used) policy is used to
determine the line to replace in the instruction memory
cache.
This feature is particularly useful when code contains
loops.
This architecture is chosen to provide the best tradeoff
between cache size, power consumption and
performance.
After each miss, the cache is updated with only the
requested double-word in order to limit the Flash access

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for power-saving. In a line, the 4 double-words may not
all be valid.
In case of a miss, the Cortex M4 code takes the
instruction directly from the Flash memory.
In parallel, the 64-bit line is copied into the current buffer
enabled and I-Cache if enabled.
So the next sequential access is taken directly from the
current buffer.
If prefetch is enabled, another 64-bit Flash access is
performed to fill the Prefetch buffer with sequential data.
When the data is present in the current buffer, the CPU
reads the current buffer.
The next sequential read is performed in the Prefetch
buffer, which is copied into the current buffer, so that it is
free to be filled with the next sequential data.
If the data is not present in the current buffer, it is read
from the Prefetch buffer if it is present.
If not, it is read from the instruction cache if there is a
cache hit.
Otherwise, a Flash access is performed.

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The Instruction Cache behaves differently depending on
if the prefetch buffer is enabled or not.
If the prefetch buffer is enabled, the ART instruction
cache behaves like a branch cache.
The cache is modified each time a branch or a jump
occurs in the execution flow.
Sequential accesses are issued by the current instruction
buffer and the prefetch buffer; each time the prefetch
buffer responds hit, its contents are transferred to the
current instruction buffer and a new Flash access to fill
the prefetch buffer is performed. In this case, the cache
content is not altered.
If the prefetch buffer is disabled, the ART instruction
cache behaves like a normal cache.
Since no prefetch buffer is available, even a sequential
access will modify the cache content.
The power and performance tradeoff must be evaluated

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for each application to know whether is it is better to
enable or disable the prefetch buffer.
For most of applications, enabling the prefetch buffer
allows to increase slightly the performance but with a
higher consumption.
Generally, the best energy efficiency is provided with
caches enabled and prefetch buffer disabled, as it often
reduces the number of Flash accesses.

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This slide shows the number of cycles needed to
execute sequential 16-bit instructions without prefetch,
when 3 wait states are needed to access the Flash
memory. Every Flash access provides 64 bits or 4
instructions; 3 wait states are therefore inserted every 4
instructions, at every Flash access.

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This slide shows the number of cycles needed to
execute sequential 16-bit instructions with prefetch
enabled, when 3 wait states are needed to access the
Flash memory.
After each Flash access, another Flash access is
performed to fill the prefetch buffer.
So after all instructions are fetched from the current
buffer, the next sequential instruction is read from the
prefetch buffer and no wait state is inserted as long as
the instruction flow is sequential.

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Several Flash memory protection options can be
configured using the option bytes.
Readout protection aims to protect the contents of the
Flash memory, option bytes, internal CCM SRAM and
backup registers against reads requested by debuggers
or software reads caused by programs executed after a
boot from SRAM or bootloader.
Only a boot from Flash memory is permitted to read the
contents of these memories.
The Proprietary Code Protection is a way to mark parts
of the Flash memory as execute only. Note that this kind
of access permissions is not supported by the Memory
Protection Unit present in the Cortex®-M4 core.
PCROP areas are useful to protect only a part of the
Flash memory against third party reads.
Write protection prevents part of the Flash memory from
being erased and reprogrammed.

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The main purpose of the securable memory area is to
protect a specific part of Flash memory against
undesired access. This allows implementing software
security services such as secure key storage or secure
boot, in charge of image authentication.
Once the processor has exited the securable memory,
this part of the Flash memory is no longer accessible.
The securable area can only be unsecured by a reset of
the device.
The size of the securable memory area is aligned on
pages.
In addition, the code executed from the securable
memory can temporarily disable debug accesses.

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Option Bytes are used to early configure the system-on-
chip before starting the Cortex®-M4. They represent 48
Bytes.
They are automatically loaded after a power reset or on
request by setting the OBL_LAUNCH bit in the
FLASH_CR register. This capability is required to apply a
new setting without resetting the device.
This slide and the two next ones describe the various
fields in the Option Bytes.

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Bootlock forces the system to boot from the Main Flash
memory regardless of the other boot options.

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The readout protection level enables the readout
protection for the entire Flash memory:
• Level 0: no protection
• Level 1: read protection
• Level 2: no debug.
The following transitions are supported: Level 0 to Level
1, Level 1 to Level 0 which implies a partial or mass
erase, Level 0 to Level 2 and Level 1 to Level 2.
• PCROPA_STRT and PCROPA_END define the
proprietary code readout protection address range A.
• PCROPB_STRT and PCROPB_END define the
proprietary code readout protection address range B.
• PCROP_RDP allows to select if the PCROP area is
erased or not when the RDP protection is changed
from Level 1 to Level 0.

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The Flash memory controller supports many interrupt
sources, listed in this slide and the next one.
An interrupt can be asserted upon successful end of
operation.
An interrupt can also be asserted when an error occurs
during a program / erase operation.
Protection violations can also cause interrupts.
A Size error occurs when the data to be programmed is
not word-aligned.
Programming sequential error occurs when a program
operation is attempted without having previously erased
the location in Flash memory.
A programming alignment error occurs when a complete
double word is not provided before initiating a standard
program operation or when a complete row is not written
before initiating a fast programming operation.
A Data miss programming error occurs when data is not
written in time during a fast programming sequence.
When a single-bit ECC error is detected and fixed, an
interrupt can be asserted.
When a double-bit ECC error is detected, the NMI is
asserted.
The Flash memory’s consumption can be reduced when
the code is not executed from Flash.
The Flash clock can be gated off in Run and low-power run
modes. It can also be configured to be gated off in Sleep
and low-power sleep modes. The Flash clock is configured
in the Reset and Clock controller. It is enabled by default.
The Flash memory can be configured in Power-down mode
during the Sleep and low-power sleep modes.
It can also be configured in power-down mode during Run
and low-power run modes, when the code is executed from
SRAM.
Gating the clock and putting the Flash memory in Power-
down mode significantly reduces power consumption.
The Flash memory module supports the following low
power capabilities:
• Clock gating
• Flash memory power-down mode
• Power gating of the entire module: Flash memory and
controller.
In Run, Sleep, Low Power Run and Low Power Sleep
modes, clock gating and power-down is supported. It can
be used when code is executed from SRAM.
In Stop0 and Stop1, the clocks are gated and Flash
memory can enter Power-down mode.
In Shutdown mode, the power of the Flash memory
module is gated, for both the Flash memory and
controller.
Gating the clock and putting the Flash memory in Power-
down mode significantly reduces power consumption.
Here we compare code execution performance at 150
MHz while running the EEMBC CoreMark benchmark.
The maximum performance is reached when the code is
executed in CCM SRAM with data located in SRAM1.
When executing from Flash memory at 150 MHz, the
maximum CoreMark performance is reached when the
ART accelerator is enabled, and there is almost no loss
of performance due to the Flash access time requiring 7
wait states at 150 MHz. Enabling the prefetch buffer
yields a slightly higher score: 3.36 CoreMark / MHz in
case of Single bank mode.
The Flash memory module has relationships with the
following other modules:
• System configuration controller (SYSCFG)
• Reset and clock controller (RCC)
• Power controller (PWR)
• Interrupts (NVIC)
• Memory protections.

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For more details, please refer to application note AN2606
about the STM32 microcontroller system memory boot
mode.

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