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State Diagram

This document describes the design of a finite state machine string recognizer with the following properties: 1) It checks for the sequence "010" and asserts the output if seen, as long as "100" is not detected. 2) It includes a state diagram and state table specifying the states and transitions. 3) VHDL code is provided for the design including a test bench.

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SHYAM
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79 views

State Diagram

This document describes the design of a finite state machine string recognizer with the following properties: 1) It checks for the sequence "010" and asserts the output if seen, as long as "100" is not detected. 2) It includes a state diagram and state table specifying the states and transitions. 3) VHDL code is provided for the design including a test bench.

Uploaded by

SHYAM
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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3.

DESIGN OF A STRING RECOGNIZER


DATE: 31-12-2022

AIM:
To design a finite string recognizer which has an output z. the output is asserted whenever the
sequence …010…is recorded , as long as …100..is not seen.

DESIGN:
A sequence recognizer checks for a particular sequence and gives an output accordingly.
This design checks for z sequences and the program terminates once ‘100’ is detected. The
state diagram and state table are drawn. code is written in vhdl module.

STATE DIAGRAM:

SSSSS
So/
sssSS
0
0 SSS 1

SSSSS
S1/ SSSSS
S4/
sssSS
0 sssSS 1
0
SSS SSS
1
0

1
SSSSS
S2/ SSSSS
S5/
sssSS
0 sssSS
0
SSS SSS

SSSSS
S3/ SSSSS
S6/
sssSS
1 sssSS
0 1/0
SSS SSS
STATE TABLE:
PRESENTSTATE NEXTSTATE OUTPUT
A B C
X=0 A BX=1 C A X=0 B C X=1
0 0 0 0 0 0 1 0 0 0 0
0 0 1 0 0 1 0 1 0 0 0
0 1 0 0 1 1 1 0 0 0 1
0 1 1 1 1 0 0 1 0 0 0
1 0 0 1 1 0 1 0 0 0 0
1 0 1 1 1 0 0 1 0 0 0
1 1 0 1 1 0 1 1 0 0 0
1 1 1 d d d d d d d d

VHDL CODE AND TEST BENCH CODE:


VHDL CODE:

library IEEE;
use IEEE.std_logic_1164.all;

entity string_detector is
    Port ( x,clk : in STD_LOGIC;
           y : out  STD_LOGIC);
end string_detector;

architecture Behavioral of string_detector is

begin

process(x,clk)
variable a: std_logic_vector (2 downto 0) :="000";
variable b: std_logic:='1';
variable c: std_logic:='0';
begin
c:='0';

if (clk'event and clk='1') then


a(2):=a(1);
a(1):=a(0);
a(0):=x;
end if;

if a="010" then
c:='1';
end if;
if a="100" then
b:='0';
end if;

y<=b and c;

end process;

end Behavioral;

TEST BENCH CODE:

library IEEE;
use IEEE.std_logic_1164.all;
--use std.env.finish;
 
entity testbench is
end entity testbench;

architecture tb of testbench is

component string_detector is
port(
  x,clk: in std_logic;
  y: out std_logic);
end component;

signal a_in,clk, q_out: std_logic;

begin

  DUT: string_detector port map(a_in,clk,q_out);

  process
  begin
 
    clk<='1';
  a_in <='0'; wait for 10ns;
--assert (q_out='0') report to_string(q_out) severity note;
    clk<='0'; wait for 1ns;
  
    clk<='1';
    a_in <='1' ; wait for 10ns;
   -- assert (q_out='0') report to_string(q_out) severity note;
    clk<='0'; wait for 1ns;
  
    clk<='1';
    a_in <= '0' ; wait for 10ns;
  --  assert (q_out='1') report to_string(q_out) severity note;
    clk<='0'; wait for 1ns;
  
    clk<='1';
    a_in <= '1' ; wait for 10ns;
  --  assert (q_out='1') report to_string(q_out) severity note;
    clk<='0'; wait for 1ns;
  
    clk<='1';
    a_in <= '1' ; wait for 10ns;
   -- assert (q_out='1') report to_string(q_out) severity note;
    clk<='0'; wait for 1ns;
  
    clk<='1';
    a_in <= '0' ; wait for 10ns;
   -- assert (q_out='1') report to_string(q_out) severity note;
    clk<='0'; wait for 1ns;
  
    clk<='1';
    a_in <= '1' ; wait for 10ns;
    --assert (q_out='1') report to_string(q_out) severity note;
    clk<='0'; wait for 1ns;
  
    clk<='1';
    a_in <= '0' ; wait for 10ns;
   -- assert (q_out='0') report to_string(q_out) severity note;
    clk<='0'; wait for 1ns;
  
    clk<='1';
    a_in <= '0' ; wait for 10ns;
   -- assert (q_out='0') report to_string(q_out) severity note;
    clk<='0'; wait for 1ns;

    clk<='1';
  --  assert (false) report "Test done." severity note;
    wait for 10ns ;
  
    --finish;
  end process;
end tb;
OUTPUT:

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