316 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 50, NO.

1, JANUARY 2002

Distributed Active Transformer—A

New Power-Combining and
Impedance-Transformation
Technique
Ichiro Aoki, Student Member, IEEE, Scott D. Kee, David B. Rutledge, Fellow, IEEE, and Ali Hajimiri, Member, IEEE

Invited Paper

Abstract—In this paper, we compare the performance of the off-chip transmission lines, off-chip capacitors, and/or external
newly introduced distributed active transformer (DAT) structure baluns to achieve watt level output power.
to that of conventional on-chip impedance-transformations Several other works have been reported using alternative
methods. Their fundamental power-efficiency limitations in the
design of high-power fully integrated amplifiers in standard silicon process technologies with higher transistor breakdown volt-
process technologies are analyzed. The DAT is demonstrated to ages and/or insulating substrates to achieve watt-level output
be an efficient impedance-transformation and power-combining power, such as GaAs monolithic microwave integrated circuits
method, which combines several low-voltage push–pull amplifiers (MMICs) [7]–[9] or silicon-on-insulator (SOI) LDMOS with
in series by magnetic coupling. To demonstrate the validity of the 20-V breakdown voltage [10].
new concept, a 2.4-GHz 1.9-W 2-V fully integrated power-ampli-
fier achieving a power-added efficiency of 41% with 50- input
These results [1]–[6] demonstrate that while silicon transis-
and output matching has been fabricated using 0.35- m CMOS tors are capable of producing watt-level output power in the gi-
transistors. gahertz-frequency range with reasonable efficiency, the on-chip
Index Terms—Circular geometry, CMOS analog integrated cir- passive devices are the major limiting factor in the performance
cuit, distributed active transformer, double differential, harmonic- of the amplifier and, therefore, deserve special attention. These
control, impedance transformation, low voltage, power amplifier, passive devices are unavoidable due to the impedance transfor-
power combining. mation required to achieve high power with low-breakdown sil-
icon transistors.
I. INTRODUCTION Two major problems associated with the design of on-chip
power amplifiers using submicrometer CMOS processes are low

A MONG THE several building blocks necessary to con-

struct today’s holy grail in wireless communication, the
“single-chip radio,” power amplifiers have been one of the most
transistor breakdown voltage [11] and the high loss of on-chip
impedance transformation [12]. The latter is caused by the highly
conductive substrate, as well as thin metal and dielectric layers.
significant challenges. Several results have been published in These problems become more serious as the minimum feature
this field, but none have reported a watt-level fully integrated sizes are scaled down in each new process generation [13].
power amplifier using silicon technology. Today’s submicrometer transistors necessary for gigahertz
Until now, the highest output powers achieved by fully inte- operation have breakdown voltages in the range of 4–6 V [14].
grated power amplifiers in standard silicon processes are 85 mW This low breakdown voltage limits the drain (collector) ac
[1] delivered to a differential 50- load with a power-added ef- voltage swing to around 2 V. Without any impedance trans-
ficiency (PAE) of 30% and 100 mW with a drain efficiency of formation, the power delivered to a 50- load for a sinusoidal
16% [2], both implemented in CMOS technology. Other works voltage waveform is only 40 mW. The necessary impedance
using CMOS [3], [4] or Si bipolar [5], [6] processes rely on the transformation to achieve higher output power might be accom-
use of external passive components such as bond wire inductors, plished by an on-chip transformer or inductor–capacitor
(LC) resonant matching network. Unfortunately, these on-chip
Manuscript received May 27, 2001. This work was supported by the Intel components using CMOS processes are very lossy due to the
Corporation, the Army Research Office, the Jet Propulsion Laboratory, Infinion, low substrate resistivity and high metal ohmic loss [12], [15]
and the National Science Foundation.
I. Aoki is with the California Institute of Technology, M/C 136-93, Pasadena, and, therefore, they significantly degrade the output power and
CA 91125 (e-mail: [email protected]). efficiency of the amplifier.
S. D. Kee, D. B. Rutledge, and A. Hajimiri are with the Department of Elec- The distributed active transformer (DAT) is presented as an
trical Engineering, California Institute of Technology, Pasadena, CA 91125-
9300. alternative method to achieve simultaneous impedance trans-
Publisher Item Identifier S 0018-9480(02)00841-4. formation and power combining that can be used to overcome
0018–9480/02$17.00 © 2002 IEEE
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 AOKI et al.: DISTRIBUTED ACTIVE TRANSFORMER 317

the abovementioned problems [16]. This new method relies

on extensive use of symmetric push–pull amplifiers, ac virtual
grounds, and magnetic coupling for series power combining.
This paper presents a study of the most common passive
impedance-transformation networks for watt-level fully inte-
grated power amplifiers and compares their efficiencies to that
of the DAT structure. This comparison demonstrates the advan-
tages of the DAT approach to the existing ones. Details of the
active device issues and different classes of operation will be
presented in a companion paper [17]. Section II presents simple Fig. 1. Ideal resonant LC impedance-transformation network.
models of common transformation networks, issues related to
their design, and their corresponding lowest achievable power and hence lowers the associated loss of the inductor. The dual
losses. Section III explains how the DAT structure alleviates network, however, results in better harmonic suppression due to
the loss in the passive components. In Section IV, the design its low-pass nature.
process and measurement results of a 2.4-GHz DAT-based The impedance-transformation ratio is defined as
fully integrated power amplifier will be shown using a standard
0.35- m CMOS transistors. (1)
It should be noted that while this paper addresses silicon-
based power amplifiers, it may also be possible to apply these where and are the load and its transformed impedance
techniques to other technologies such as GaAs or SOI to provide at port-1, and is the loaded quality factor of the network at the
further improvements in efficiency, output power, and/or higher angular frequency, , assuming lossless passive components,
power density compared to conventional power amplifiers. i.e.,

II. IMPEDANCE-TRANSFORMATION NETWORKS (2)

A low loss impedance transformation with a large ratio is es-
sential to deliver a large ac power efficiently into a 50- load The voltage swing limitations of the active device in combi-
using low-breakdown submicrometer high-frequency integrated nation with desired output power determine . A given
transistors. For instance, to deliver 2 W to a 50- load using a and will set and in (1). Then (2) can be used to cal-
drain voltage swing of 2 V, a minimum impedance-transfor- culate the value of the inductor, . Knowing , the capacitor
mation ratio of 1 : 50 is necessary. value can be selected using the following resonant condition:
In this section, we will present an analytical study of the
power efficiency of some common impedance-transformation (3)
networks as a function of their inductor unloaded quality factor
and their transformation ratio. As the quality factors of the
on-chip capacitors are significantly higher than that of the in- While complete models for on-chip inductors have been de-
ductors, their losses are not considered here. vised [22], the loss of a one-port inductor at a single fre-
In this paper, we will not consider conventional quarter wave- quency can always be modeled using a single parallel resistor
length transmission-line transformers or power-combining tech- or by using its unloaded quality factor defined as
niques, such as Wilkinson combiners [18], because the very high
loss of the on-chip silicon transmission lines [19] makes them (4)
impractical for use in power amplifiers.
at the frequency of interest. Fig. 2 shows the resonant
A. Resonant Impedance Transformation impedance-transformation network with the simplified
LC resonant matching [18], [20], [21] is one of the most narrow-band inductor model. The passive power transfer
straightforward means of impedance transformation. A single efficiency of this network, calculated as the ratio between the
LC section, as shown in Fig. 1, may be used to perform input RF power and the RF power delivered to the load can be
impedance matching. In some cases, it may be desirable to computed as a function of , and as follows:
cascade several such sections to enhance the efficiency. We
will analyze the single section and extend the analysis to the
general multisection case.
Using the single section network in Fig. 1, an impedance-
transformation ratio is achieved with a parallel inductor and a
series capacitor. The dual network with a parallel capacitor and
a series inductor may also be used. However, a series capacitor
has the added advantage of blocking the dc current from flowing
(5)
through the load, and a parallel inductor with a terminal con-
nected to ground lowers the energy coupling into the substrate
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 318 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 50, NO. 1, JANUARY 2002

Fig. 2. Resonant LC impedance-transformation network with loss.

The efficiency is the ratio between the load conductance,

, and total conductance, . The Fig. 3. Required inductor reactance versus PER and inductor Q for a resonant
impedance-transformation network.
impedance-transformation ratio in the presence of loss can be
easily calculated using (1) as a function of , , unloaded
inductor , and total loaded quality factor , namely,

(6)

where the total loaded quality factor is defined as

(7)

Equations (4) and (6) can be solved for in terms of the de-
sired transformation ratio , load resistance , and inductor Fig. 4. Efficiency versus PER and inductor Q for a single section resonant
impedance-transformation network.
quality factor , i.e.,

Using the definition in (10) together with (4)–(6), we can

(8) find a closed-form solution to calculate the passive network ef-
ficiency for a necessary and available inductor , as fol-
which can be used to calculate the value of in the design lows:
process. In practice, and are both functions of and,
therefore, several iterations may be necessary to obtain the exact (11)
value of .
The efficiency of the transformation network can also be Furthermore, can be calculated from and as fol-
calculated as a function of and from (5) and (8) lows:

(9) (12)

Appendix A contains the derivations leading to (11) and (12).

For any matching network, we can define the power enhance- Fig. 3 shows plots of versus for several different
ment ratio (PER) as the ratio of the RF power delivered to the values of and a 50- load resistor for a single LC
load with a transformation network in place to the power section. As can be seen from these graphs, for a PER of 50, a
delivered to the load for the same sinusoidal input voltage source reactance of is necessary if an inductor with of ten
when it drives the load directly , i.e., is to be used.
Fig. 4 shows plots of versus for several different
for a single section network. For instance, with a PER of 50 and
(10) an inductor of ten, the matching network alone will have
a maximum passive power efficiency of around 30%. This does
Unlike , PER accounts for the loss in the passive impedance- not include any loss in the active device, the driving network,
transformation ratio and is thus particularly important for lossy or the external connections. We can also see in the Fig. 4 that,
on-chip passive components in silicon technology. for a given inductor quality factor , there is an upper bound
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 AOKI et al.: DISTRIBUTED ACTIVE TRANSFORMER 319

Fig. 5. Multisection resonant LC impedance-transformation network with loss.

on the maximum achievable PER , where the efficiency be-

comes zero. This maximum achievable PER can be cal-
culated from (11) to be

(13)

Equation (13) provides an upper bound on the value of

in a single inductor–capacitor section. However, it should be
noted that the efficiency would drop to zero as we approach this
, making this bound unachievable.
A similar analysis can be performed for the more general case
of multisection transformation with segments, as shown in
Fig. 5. Assuming the same load enhancement ratio for
each individual section to have an overall PER , the derivations
in Appendix A leads to the following expression for passive
efficiency: Fig. 6. Efficiency versus PER and inductor Q for a multisection resonant
network. Vertical gray lines separate regions using different number of sections.
n
The best number of sections from 1–4 is chosen for the highest efficiency for
(14) different PERs and inductor .Q
section decreases rapidly as the desired PER is increased as
The inductance value for the th parallel inductor in the seen in Fig. 3. More importantly, the transformation efficiency
chain can be calculated as follows: also decreases quickly with higher PER , as can be seen
in Fig. 4. In a multisection approach, the loss is improved
significantly compared to the single-section network, but still
increases with higher PER , as can be seen from Fig. 6. This
analysis provides the theory for what PA designers have long
(15) understood by intuition and experience. The low passives
currently available on chip fundamentally limit achievable
power efficiencies at the 1-W level. No amount of complexity
in an LC transformation network can overcome this.
In principle, the multisection transformation network has a
lower loss for high PER compared to a single section. However, B. Magnetically Coupled Transformer Impedance
it requires a more complex layout and some of its inductors will Transformation
have very large or very small reactance compared to a single
section. This results in a lower overall quality factors for the By magnetically coupling two inductors, we can create a cou-
network. Fig. 6 shows plots of versus for several different pled-inductor transformer. In a coupled-inductor transformer,
values of for a multisection network. This figure only the magnetic field created by the port-1 current through the
shows the efficiencies for the number of sections leading to the primary inductor generates a voltage in the secondary in-
minimum loss, so it can also be used to find the optimum number ductor . At the same time, the current through the secondary
of sections. For example, we can see that with a PER of 50 and will magnetically induce a voltage in the primary circuit. The
an inductor quality factor of ten, the best matching network port voltages of the loosely coupled lossy transformer and
will have three LC sections and will have a maximum passive in Fig. 7(a) are related to its port currents through
efficiency of around 60%. Again, this figure does not include any
loss in the active device, the dc feeds, or the external connections. (16)
Equations (11) and (12) have important implications re-
garding the necessary reactance, transformation efficiency, and
the PER. In particular, (12) suggests that the inductor reactance
necessary for this type of matching network with a single
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 320 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 50, NO. 1, JANUARY 2002

The transformer efficiency is the ratio of power delivered

to the load to the total power delivered into port-1 of the
network , which is calculated in Appendix B to be

(a)
(18)

This is obtained assuming and using the op-

timum value of given by

(19)
(b)
Equation (18) can be differentiated to obtain the optimum
Fig. 7. (a) Transformer model. (b) Transformer equivalent T-model.
value of resulting in the highest possible , which is

where is the mutual inductance, is the coupling factor, is

(20)
the transformation ratio, and is the turn ratio between primary
and secondary coils. Fig. 7(b) shows the equivalent model for
the transformer of Fig. 7(a), where the lossy inductors of the
transformer are modeled by the equivalent series resistors
where
and and net inductances and for a single frequency
[23]. The quality factors and , of the primary and the
secondary inductors can be calculated in terms of and , (21)
respectively, i.e.,

(17)
Using this optimum , the maximum efficiency will be
The quality factors of the coupled inductors are slightly dif- given by
ferent from those of the individual inductors due to the current
redistribution that occurs on both inductors when they are cou-
(22)
pled. This effect is shown in the current density graph of Fig. 8,
which shows the current densities in stand alone primary and
secondary loops as well as the redistributed current densities due
to their magnetic coupling. These graphs were obtained using
The above equation shows that passive efficiency can be max-
the Sonnet electromagnetic simulator [24].
imized using a as close as possible to unity. This is because the
The leakage inductances and can have
smaller the , the larger fraction of the primary inductor current
a significant effect on the primary and secondary reactance if
will go through the magnetizing inductor and, hence, a
the coupling factor is small. The factor is low for on-chip
lower power will be delivered to the load resistor. More impor-
spiral transformers because of the low permeability of the core
tantly, unlike resonant matching, the transformer efficiency is
material (e.g., SiO ) and the planar geometry that results in large
not affected by the transformation ratio, as seen in (22).1 Fig. 10
magnetic field leakage.
shows how the transformer efficiency is reduced when the reac-
If the transformer is used to achieve output matching in a
tance of the inductor is above or below the optimum value de-
power amplifier, it will be necessary to resonate some of the
termined by (20). Several plots of versus are shown for
transformer’s inductance to minimize the loss. This effect is dis-
a 50- load and a peak PER of 50. For each plot, a fixed is
cussed in more detail in Appendix B. A capacitor is also nec-
used in order to have PER 50 for peak . In these plots,
essary on the primary side of the transformer to adjust its input
and are assumed to be equal to facilitate visualization.
reactance to the desired value for the driving transistor. This can
The equivalent input admittance of the transformer for the
be done using a parallel capacitor on the primary and another ca-
optimum values of and given by (19) and (20) can be
pacitor in series with the secondary, as shown in Fig. 9(a), and
calculated to be
its expanded form using the equivalent T-model in Fig. 9(b).
Now, we can use the equivalent model of Fig. 9(b) to cal-
culate the transformer efficiency , the best value of the series (23)
matching capacitor , and the best inductor values and
for the lowest loss as a function of the load resistance and
other transformer characteristics. 1Except to the degree that L , L , k , Q , and Q , change with r .
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 AOKI et al.: DISTRIBUTED ACTIVE TRANSFORMER 321

Fig. 8. Current densities in planar one turn inductors and a planar transformer.

Fig. 11 shows plots of versus and for 0.4, 0.6, 0.8,

and 1 using (22). As an example, to obtain a transformation ratio of
50withprimaryandsecondaryinductorqualityfactorsoftenanda
of0.6,thetransformerprimarycircuitshouldhaveanimpedance
of approximately at the frequency of operation to achieve the
highest efficiency. In this case, should be approximately eight
and the best achievable passive efficiency is 70%.
Although a single series capacitor with the load can provide the
necessary negative reactance to resonate the inductive output of
(a) the transformer, an additional capacitor parallel to the load
(Fig.12)canbeusedtoadjusttherealpartoftheimpedanceseenby
thesecondaryofthetransformertoloweritsloss.Thisextradegree
of freedom can be used to obtain a lower turn ratio and a lower
primary inductance for a given load resistance and PER .
Equations (22), (24), and (25) determine the optimum value of
and the resultant and for . We can recalculate these
parametersfortheotherlimitingcase, when islarge ,
using (10), (16), (19), (20), and (24). The new PER is

(26)
(b)
Fig. 9. (a) Transformer model with load and tuning capacitors.
(b) Transformer equivalent T-model with load and tuning capacitors.
which is obtained for a and an given by

We now calculate the transformer turn ratio for a desired

PER using (10) and (23) using the assumption
(27)
(24)
The new input admittance is

(28)
(25)

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 322 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 50, NO. 1, JANUARY 2002

Fig. 10. Efficiency versus primary inductor reactance normalized to load resistance, inductor Q, and coupling factor k for a transformer with loss.

(a) (b)

(c) (d)
Fig. 11. Efficiency versus primary inductor Q , secondary inductor Q , and coupling factor k for a transformer with loss.

Fig. 12. Transformer equivalent T-model for analysis with load, tuning capacitors, and extra tuning capacitor in parallel to the load.

The new turn ratio in this case will be terms of quality factors. The maximum PER is achieved when
is very large. This maximum PER given by (26) is
times larger than (24).2
In the design process, we start from a given transistor and a
(29) given power level that has to be delivered to the load. These two
conditions determine the desired value of the PER . Once this
The efficiency of this new setup is still given by (22). Note 2In practice, there is no need for C as the transformer dc isolation between
that plots of Fig. 11 are still valid since they are calculated in the input and output ports allows us to short circuit C .
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 AOKI et al.: DISTRIBUTED ACTIVE TRANSFORMER 323

is achieved, there is no point in increasing it beyond the re- an of 50 into a 50- load is approximately 80 pH at 2 GHz.
quired value, and we should maximize the efficiency instead. Inter-winding these short primary metal lines with the multi-
As can be seen from (29), the addition of the parallel capacitor turn secondary forces them to be very narrow. Unfortunately,
makes it possible to use smaller turn ratio for a desired this reduces the of both primary and secondary circuits,
. Typically, a lower results in a higher quality factor in mag- significantly. Noting the limitations of these two conventional
netically coupled transformers, which translates to a higher ef- impedance-transformation methods, we introduce an alterna-
ficiency, as can be seen from (22). tive solution, which does not suffer from these shortcomings.
A capacitor parallel to the transformer input completes
this circuit. It tunes the reactive part of the transformer input III. DAT
impedance to the desired value appropriate to provide the re-
quired drain or collector impedance for the chosen class of the The analysis in these last two sections show that if we could
amplifier.3 increase the transformer turn ratio while maintaining a con-
Using the above analysis, we can compare the performance stant , we could achieve a high efficiency for large PER, as
of a magnetically coupled transformer with an LC-based res- suggested by (22) and (24). Unfortunately, the quality factor
onant impedance transformation discussed in Section II. Un- suffers if a large turn ratio is to be used for the reasons that will
like the resonant LC matching circuit, in a magnetically cou- be discussed in Appendix C. Also (20) shows that the required
pled transformer the efficiency does not depend on the PER impedance level at the input can become impractically small for
and, hence, does not drop for larger output power level, as large turn ratios because it is inversely proportional to . These
can be seen from (11) and (22). The implicit assumption is that observations leave us no choice but to use lower turn ratios. In
the quality factors do not change with larger , which may not practice, the lowest loss can be achieved for a 1 : 1 ratio, which
be correct as mentioned earlier. These equations shown graph- is also very appealing since high- coupled slab inductors dis-
ically in Figs. 6 and 10 also show that for a PER above 15, the cussed in Appendix C can be used to realize it.
magnetically coupled transformer provides a higher efficiency While 1 : 1 transformers are desirable for the above reasons, it
than the resonant matching for a given . is obvious that we need more than one 1 : 1 transformer to obtain
This difference in behavior arises from a fundamental any impedance transformation. A high PER, can be achieved
difference between the LC resonant and magnetically coupled using independent 1 : 1 transformers by connecting the sec-
transformer matching, which can be understood using a simple ondary circuits in series, as shown in Fig. 13(a) and (b). In
model. In both approaches, in order to achieve a high PER, this arrangement, the ac voltages on the secondaries add, while
the input ac current has to be larger than the output ac the primaries can be driven at a low voltage by separate active
current and the output ac voltage has to be larger devices. It should be noted that this configuration still has an
than the input ac voltage , both approximately by .4 In impedance-transformation ratio . Additionally, as there are
a resonant matching network, the loss is proportional to the devices being power combined, the PER of such a (lossless)
product of and , which are both large. On the other structure is .
hand, while in a magnetically coupled transformer, there are Unlike loop or spiral inductors, the two terminals of a slab
two loss components, namely, and , each inductor are not in close proximity of each other. This inherent
one is smaller than the single loss component in the case of a property adds extra constraints to how they can be used. For ex-
resonant matching by . Therefore, loosely speaking, the loss ample, if one is to make a parallel LC tank using a slab inductor,
of the resonant matching circuit is larger by a factor of . the parallel capacitor cannot be connected using regular wires,
In a properly designed impedance-transformation network as the inductance and resistance of this wire will be compa-
using magnetically coupled transformers, the reactance of the rable to that of the slab inductor. The absence of low-loss ground
primary inductor is approximately the load resistance that planes in silicon technologies exacerbates the situation and de-
should be seen by the active device, as seen in (20). Similarly, grades the quality factor of a slab inductors, if they are config-
the reactance of output inductor , will be approximately ured in such a way that the return current conducts through the
the load resistance. Additionally, a negative reactance in series substrate.
with the load is necessary to achieve the highest possible A double differential drive can solve this problem in a power
efficiency. This negative reactance can be generated by a amplifier. A virtual ac ground is created in the middle of the slab
combination of a series and a parallel capacitor, as shown in inductor if differential push–pull transistors drive it. This virtual
Fig. 12. These observations are particularly important for the ac ground can be used as a dc feed for the power supply, making
DAT structure introduced in the following section. the impedance of the dc biasing networking inconsequential as
The disadvantage of a magnetically coupled transformer is far as the differential signal is concerned. The differential drive
the low primary inductance necessary to achieve the highest solves only half of the problem as the ground connection for
efficiency. If spiral transformers on a silicon substrate were to the driving transistors are not going to be in close proximity
be used, the small primary inductance results in extremely short with each other. It is necessary to form an ac ground by con-
metal lines. For instance, the necessary inductance to achieve necting the two transistor grounds to stop the ac current from
flowing through the lossy ground line and, thus, induce extra
3Although the tuning capacitor could be placed in series, biasing issues usu-
loss. Again, a wire cannot be used to form this ac ground, as
ally favor the parallel setting. However, the series arrangement has the advantage its inductance will be comparable to that of the slab inductor it-
of resulting in yet smaller n.
4In a transformer,
p  r n. self. This problem can be solved by a double-differential drive

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 324 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 50, NO. 1, JANUARY 2002

inductors [see Fig. 15(b)] has exactly the same effect since the
voltage across the capacitor will be identical to that of a ca-
pacitor in parallel with the slab. The output matching capacitor
can be simply placed in parallel to the load, as illustrated
in Fig. 15(b). A representative drawing of this structure with
eight NMOS transistors and four slab transformers is shown in
Fig. 16.
(a) A modified version of the transformer analysis described in
Section II can be used to analyze the DAT. The new required
primary inductance and the effective input admittance are given
by

(30)

(31)
(b)
Fig. 13. (a) Fundamental building block of DAT. N independent power
sources combined in series through N transformers with turn ratio 1 : 1. where is the number of combined transistors. The new ex-
(b) Same diagram using coupled slab inductors as the transformer. pressions for and in the presence of and can be
derived using a similar derivation to that of Section II.
shown in Fig. 14, where each driving transistor has an opposite The definition of PER can be generalized to the case of a
phase to companion adjacent to it. In this case, the ac current matching/transformation network with multiple input ports. In
flows through the adjacent transistors and hence an ac ground is this scenario, it is natural to define the PER as the ratio of
created at their ground connections. Finally, to provide the same the RF power delivered to the load with the network in place
virtual ground for the two active devices at the ends of this com- to the power delivered to load for one of the sinusoidal
bined structure, it can be wound to form a DAT, as depicted in input voltage sources driving the load directly . Based on
Fig. 15(a) for slabs. Although this winding will reduce the this definition, the PER for the DAT can be calculated to be
of the inductors, due to the negative magnetic coupling between
opposite sides of the polygon, this effect is significantly lower
(32)
than winding each transformer individually as the dimension of
the total structure is much larger. The schematic of Fig. 15(a)
shows the central concept behind the DAT structure. In this con-
figuration, the impedance-transformation and power-combining Finally, the efficiency will be the same as the efficiency of a
functions are achieved concurrently. Also all the dc currents standard transformer matching circuit given by (22).
are provided to the amplifier through virtual ac grounds, which Several very important observations can be made about the
makes the amplifier insensitive to the means used to supply the DAT, when compared to conventional impedance-transforma-
dc voltages (e.g., length of bonding wires). tion networks.
The DAT combines the relatively high primary inductance of 1) The PER of the DAT is proportional to the square of the
the LC matching networks, the PER-independent efficiency of number of transistors , as shown by (32). This is com-
a magnetically coupled transformer, and the high quality factor parable to the PER of a standard transformer matching
of slab inductors, while providing an effective means of power circuit with a turn ratio given by (26).
combining. In the DAT structure the loss is reduced because the 2) Comparing (27) and (30), it can be seen that the primary
voltages add on the secondary to combine power. Thus, the total inductance will be times larger in the DAT than
ac current through the secondary inductor of the DAT is smaller the standard magnetically coupled transformers. This will
than the current through the LC matching inductor by a factor allow the DAT to use values that are more practical for
of . Since the impedance of the DAT secondary is larger than at the input ports.
the LC matching inductor by the same factor, the loss of the 3) In the DAT, transistors generate the power and, there-
DAT is smaller than that of the LC match by approximately a fore, each active device needs to deliver a smaller power
factor of . Additionally, while large currents do flow through to the passive structure. This difference manifests itself in
the magnetizing inductors of the primary circuits in a DAT, the (28) and (31), where the input conductance of each port
low-loss slab inductors minimize the associated loss due to their in the DAT is times smaller than the input of a standard
higher . magnetically coupled transformer.
As discussed earlier and shown in Fig. 9(a), the transformer’s 4) Unlike LC-resonant matching networks, the loss mecha-
input shunt capacitor is necessary for the transformer to nism of the DAT structure is independent of the PER to
present the proper impedance to the active device. As mentioned the first order. It is noteworthy that standard magnetically
earlier, cannot be placed in parallel with the slab inductors coupled transformers benefit from the same advantage.
because of the physical distance between its terminals. How- 5) The geometry of the DAT makes it possible to use 1 : 1
ever, placing capacitors between two adjacent ends of two slab slab transformers. In the DAT, we can make the primary
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 AOKI et al.: DISTRIBUTED ACTIVE TRANSFORMER 325

Fig. 14. N independent power sources combined in series through N=2 transformers in double-differential configuration with grounds shared between adjacent
power sources, except for the first and last sources in the chain.

Fig. 16. Representative drawing of a complete DAT with 8 NMOS transistors.

(a) a factor of due to the more even distribution of the

active device area across the chip.
8) The current in the secondary of the DAT is approximately
times smaller than in LC-resonant circuits, which al-
lows narrower metal lines to be used on the secondary.
Table I summarizes the performances of each one of the dis-
cussed power-combining, impedance-transformation and har-
monic tuning techniques.

IV. A DESIGN EXAMPLE

In this section, we will demonstrate the design process of a
2-W power amplifier using 0.35- m CMOS transistors with a
drain breakdown voltage around 6 V. The passive parameters of
this process are summarized in Table II.
For reliability, we should leave some margin for the max-
(b) imum drain voltage to avoid junction breakdown. For this reason
we limit the power supply to 2 V. To achieve 2 W output power
Fig. 15. (a) N independent power sources combined in series through N=2
transformers in double-differential configuration with grounds shared between into a 50- load with a 2-V power supply, we need a PER higher
every adjacent power sources using the circular geometry. (b) Same diagram than 50. For this design example, we have chosen a center fre-
with cross-connected drain tuning capacitors and output capacitor. quency of 2.45 GHz.
Now, let us compare the performance of the three different
slab inductors wide to lower their series resistance. This methods of power enhancement discussed in Sections II and III.
reduction of loss in the primary is particularly important To obtain a PER of 50 using resonant impedance transforma-
because large magnetizing currents flow in the primary tion (Section II-A), we need to use a three-stage network, as
circuits. determined by Fig. 6. For this frequency and power level, the
6) The two terminals of the slab inductors are not in close three inductors can be calculated using (15) to be 1.6, 0.35, and
proximity of each other. The DAT uses a double-differen- 0.075 nH. To obtain an estimate of the efficiency of the passive
tial drive to be able to incorporate slab inductors into the network, we can use ASITIC [22] to optimize these inductors,
design. resulting in quality factors of 14, 10, and 3, respectively. The
7) The distributed nature of the DAT can improve the geometric mean of these quality factors can be used to approx-
thermal dissipation capability of the active devices up to imate the efficiency of the passive network using Fig. 6. With a
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 326 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 50, NO. 1, JANUARY 2002

TABLE I
COMPARISON OF CHARACTERISTICS OF SEVERAL LUMPED IMPEDANCE MATCHING AND POWER-COMBINING TECHNIQUES

TABLE II ondary inductor with approximately (3.3 nH at 2.4 GHz)

PROCESS CHARACTERISTICS and seven turns without reducing the quality factors. Due to
the physical layout constraints, these standard transformers will
have a very narrow metal width and/or a reactance significantly
higher than . Due to these limitations, passive efficiency of
these impedance-transformation networks will be much lower
than the theoretically predicted upper limit of 68%.
Now, we can compare the LC-matching and coupled-inductor
transformers with the DAT structure. Since the primary of the
DAT consists of a slab inductor, it achieves a of more than
30 in this process technology. The secondary loop of the DAT
structure has a of ten and coupling coefficient of 0.6. The
secondary parameters are comparable to a standard spiral trans-
former. Using (22), we predict a theoretical passive efficiency
around 82%, for the DAT structure. As can be seen, The DAT
achieves a higher passive efficiency than the resonant and stan-
dard transformer networks. Also, the double-differential drive
mean of 7.5 the efficiency of the passive resonant matching of Fig. 15(b) generating multiple virtual grounds makes it pos-
network will be less than 50%. Even using a single LC section sible to implement a DAT on a lossy silicon substrate without a
with an optimum5 inductor of 15, Fig. 4 indicates that passive significant reduction in this theoretically predicted passive effi-
efficiency cannot exceed 52%. Note that this is the efficiency ciency due to biasing and ground connections.
of the passive network alone assuming that ideal ac grounds To verify the feasibility of the DAT, the structure of Fig. 16
can be provided and layout issues and parasitic components do was simulated using Sonnet [24]. The primary slab inductors
not limit the performance. In practice, a resonator based passive have a of 30, while the of the secondary loop is around
network will have an even lower efficiency, for such high PER. eight. The electromagnetic simulations show a PER of 65. This
The second alternative is a standard coupled-inductor trans- translates to a maximum achievable output power of 2.5 W with
former. If we assume a typical inductor of eight and a cou- a 2-V power supply. The simulated DAT passive efficiency was
pling factor of 0.6, we can obtain an efficiency of up to 68%, 70.5%. This in combination with the active device efficiency
based on Fig. 10. Although this is higher than that of resonant of 67.5% (operating in fully saturated class mode [25])
network, it is extremely difficult (if not impossible) to layout a and a compressed gain of 10 dB, result in a PAE of 43%. The
moderate- short and wide (70 pH at 2.4 GHz) inductor6 predicted drain efficiency is around 48%.
for the primary circuit and simultaneously inter-wind a sec- This truly fully integrated CMOS power amplifier was
5This is the best value that could be obtained using Sonnet [24] EM simulator
fabricated using 0.35- m CMOS transistors. The measurement
for a spiral inductors in this process. shows a PAE of 41% with a maximum output power of
6The ASITIC optimized Q of this spiral inductor without the secondary is of 1.9 W on a 2-V power supply, as shown in Fig. 17. The
around three. amplifier has a small signal gain of 14 dB and a compressed
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 AOKI et al.: DISTRIBUTED ACTIVE TRANSFORMER 327

TABLE III
SUMMARY OF MEASURED AND SIMULATED AMPLIFIER PERFORMANCE

Fig. 17. Measured gain and PAE versus P of the DAT power amplifier
when driving a differential load.
amplifiers distributed across the chip without using additional
components. This new concept combines in series several
push–pull amplifiers efficiently by extensive use of virtual ac
grounds and magnetic couplings.

APPENDIX A
RESONANT NETWORK EFFICIENCY COMPUTATION
To calculate the LC matching network efficiency as a func-
tion of and , we eliminate the terms and from the
definition (10) using (5) and (6) and isolate the term
as follows:

Fig. 18. Microphotograph of the measured DAT power amplifier.

(A.1)
gain of 8.7 dB at 1.9-W output power. Its drain efficiency is
48%. The input and output are both matched to 50 , with an
input reflection coefficient of 9 dB. The 3-dB bandwidth is
510 MHz centered at 2.44 GHz. All harmonics up to 20 GHz
were more than 64 dBc below the fundamental. An on-chip This isolated term is by (5)
balun allows for a single ended 50- input. The same amplifier
also provides a PAE of 31% with an output power of 2.2 W for (A.2)
an unbalanced 50- load. The die size was 1.3 2.0 mm and
its microphotograph can be seen in Fig. 18.
Judging by the measured efficiency, we believe that every Equation (A.2) stands as is approximately square of
eight transistors are receiving fairly in-phase signals when the and is .
power amplifier is driving a symmetric differential load. On the Substituting in the definition (4) using (A.1), we can find
other hand, the lower efficiency measured with unbalanced load a solution for , as shown by (12).
is likely due to a phasing problem caused by an undesirable For the multisection case, we have
asymmetric feedback from the output.
A summary of these results can be seen in the Table III.

V. CONCLUSION
A fundamental analysis of the loss mechanisms of the
conventional on-chip impedance-transformation networks
and their limitations are performed. We conclude the study (A.3)
with a description of the characteristics of the DAT. DAT
is a new impedance-transformation and series power-com- If we assume that each individual ’s are equal, we have
bining architecture, which offers the advantages of LC and
coupled-inductor matching simultaneously. Furthermore, it (A.4)
presents the advantage of power combining in series several (A.5)
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 328 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 50, NO. 1, JANUARY 2002

and from the above, we obtain To maximize in the above expression, should resonate
at the frequency of interest, i.e.,
(A.6)
(B.3)
The total efficiency of the network is the product of the effi-
ciency of each stage. Simultaneously, if the total PER is , the This condition minimizes the current through and its
PER of each stage will be . Analyzing the Fig. 5, we can dissipated power by resonating the inductors and
calculate the inductor value for each stage in a similar way as in with the capacitor .
a single section network Assuming and using (17) and (B.3), we can
further simplify (B.1) to
(A.7)
(B.4)

(A.8)
which is obtained by dividing the equivalent load resistance
From (1), (A.1), and (A.2) we have by the sum of three equivalent resistances, which are
, , and reduced by the ratio .

(A.9) APPENDIX C
DESIGN OF A LOW IMPEDANCE INDUCTOR
From (A.7), (A.8) and (A.9) we have Inductors are essential blocks to design various forms of
impedance-transformation networks and their properties can
significantly affect the performance of such networks, as
discussed earlier.
Spiral inductors [12], [15], [22] have been widely used in
radio frequency integrated circuits. They can be single-turn or
(A.10) multiturn, as shown in Fig. 19. For a spiral inductor the negative
magnetic coupling between the opposite sides of the polygon
lowers its total equivalent inductance. However, this inductance
reduction by negative mutual coupling does not occur when the
APPENDIX B distance between the opposite sides of the spiral is significantly
TRANSFORMER EFFICIENCY COMPUTATION larger than the mirror current penetration depth of the transmis-
sion line in the substrate.
The transformer efficiency is the ratio of power dissi-
In a single turn inductor with larger spacing between its op-
pated in the load resistance and total power dissipated
posite sides, the substrate (back plane) mirror current limits the
in , , and , shown in (B.1) at the bottom of this page,
inductance per metal length. Therefore, it behaves similarly to a
where
microstrip transmission line of the same length. Also, the prox-
imity of the opposite terminals of the inductor provides an al-
(B.2)
ternative current path through the shunt-capacitors and the sub-
strate that increases the loss.

(B.1)

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 AOKI et al.: DISTRIBUTED ACTIVE TRANSFORMER 329

Fig. 19. One-turn planar spiral inductor and multiturn planar spiral inductor.

Fig. 21. Inductance of a transmission-line inductor versus metal width for

constant metal length (1500 m).

Fig. 20. Short transmission-line inductor with one terminal grounded on a

dielectric substrate with backside ground plane.

If we use more than one turn to form a spiral inductor, the

positive magnetic couplings between the conductors in the same
side of the polygon enhance the total equivalent inductance.7
We can also build an inductor using a short transmission line
with one of its terminals short-circuited to the ground, as in
Fig. 20. Standard transmission-line analysis can be used to cal-
culate the inductance and the of this inductor [18] as follows:
Fig. 22. Q of a transmission-line inductor versus metal length and metal width.
(C.1)
where and are transmission line’s characteristic impedance silicon process using a planar E/M simulator [24]. Fig. 22
and complex propagation constant given by shows plots of versus for different values of . The
process characteristics used in the simulation can be seen in the
Table III. Fig. 22 shows that series metal resistance, , is the
dominant loss factor for a narrow line (small ) and, hence,
is approximately constant as a function of . This is because
(C.2) both the series resistance and the inductance are proportional
In which and , are the series impedance to , thus their ratio remains constant, i.e.,
and shunt admittance per unit length, respectively. Equation
(C.1) shows that the inductance is proportional to the trans- (C.3)
mission-line characteristic impedance and its length. If the
substrate has a low resistivity (e.g., in silicon), the loss terms in On the other hand, the shunt elements is the dominant loss
(C.2) will be large, which results in a relatively small inductor factor for a wide line (large ). In this case, decreases almost
quality factor. In practice, it is very difficult to obtain analytical quadratically with increasing because both the series induc-
expressions for these loss components due to the nonuniformity tance and shunt-conductance scale with , i.e.,
of the conductor and substrate mirror current components, and
one should resort to simulation methods [26]. (C.4)
For small lengths, the inductance of the microstrip trans-
mission-line inductor is proportional to its length , as shown Fig. 22 shows this behavior, where for m is
in (C.1). Also, smaller line width increases and, hence, almost constant with , while it drops with rapidly for
raise the inductance . However, the dependence is weaker m. Consequently, we can conclude that microstrip in-
than linear due to the mutual coupling between parallel current ductor increases with increasing when it is short and
components on the line. This behavior is shown in Fig. 21 degrades with increasing when the line is long, as illustrated
where is plotted versus . This plot was obtained for a in Fig. 22.
7The multiturn spiral inductor also suffers from a larger parasitic capacitance Based on this argument, we can find the and that maxi-
between adjacent turns that lowers its self-resonant frequency. mize the for a desired inductance. This optimum is plotted
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 330 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 50, NO. 1, JANUARY 2002

Fig. 23. Q of a transmission-line inductor versus metal length or metal width and inductance. In the first plot, for each metal length, the width, which provides
the selected inductance, is chosen. In the second plot, for each metal width, the length, which provides the selected inductance, is chosen.

as functions of and in Fig. 23. The lower the inductance, the [2] Y. J. E. Chen, M. Hamai, D. Heo, A. Sutono, S. Yoo, and J. Lascar,
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[4] C. Yoo and Q. Huang, “A common-gate switched, 0.9W class-E power
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transformer coupled 5-W silicon power amplifier with 59% PAE
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[18] D. M. Pozar, Microwave Engineering, 2nd ed. New York: Wiley, 1998. David B. Rutledge (S’77–M’77–SM’89–F’93)
[19] H. Wu and A. Hajimiri, “Silicon-based distributed voltage-controlled received the B.A. degree in mathematics from
oscillators,” IEEE J. Solid-State Circuits, vol. 36, pp. 493–502, Mar. Williams College, Williamstown, MA, in 1973, the
2001. M.A. degree in electrical sciences from Cambridge
[20] K. K. Clarke and D. T. Hess, Communication Circuits: Analysis and University, Cambridge, U.K., in 1975, and the Ph.D.
Design, 1st ed. Reading, MA: Addison-Wesley, 1971. degree in electrical engineering from the University
[21] D. B. Rutledge, The Electronics of Radio, 1st ed. Cambridge, U.K.: of California at Berkeley, in 1980.
Cambridge Univ. Press, 1999. He currently holds the Kiyo and Eiko Tomiyasu
[22] A. M. Niknejad and R. G. Meyer, “Analysis, design and optimization of Chair of Electrical Engineering at the California
spiral inductors and transformers for Si RF IC’s,” IEEE J. Solid-State Institute of Technology (Caltech), Pasadena. He is
Circuits, vol. 33, pp. 1470–1481, Oct. 1998. Executive Officer for Electrical Engineering and
[23] W. K. Chen, The Circuits and Filters Handbook. Boca Raton, FL: CRC Director of Caltech’s Lee Center for Advanced Networking. His research has
Press, 1995. focused on integrated-circuit antennas, active quasi-optics, computer-aided
[24] Sonnet Suite User’s Manual, Release 6.0, vol. 1, Sonnet Software, Liv- design, and high-efficiency power amplifiers. He authored the electronics
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[25] S. D. Kee, I. Aoki, and D. B. Rutledge, “7-MHz, 1.1-kW demonstration Press,1999) and co-authoed the microwave computer-aided-design software
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[26] H. Hasegawa, M. Furukawa, and H. Yanai, “Properties of microstrip line MICROWAVE THEORY AND TECHNIQUES. Six of his former students have won
on Si–SiO system,” IEEE Trans. Microwave Theory Tech., vol. 19, pp. Presidential Investigator Awards from the National Science Foundation. He
869–881, Nov. 1971. was the recipient of the Microwave Prize, the Distinguished Educator Award
of the IEEE Microwave Theory and Techniques Society (IEEE MTT-S), the
Teaching Award of the Associated Students of Caltech, the Doug DeMaw
award of the ARRL, and the Third Millennium Award of the IEEE.
Ichiro Aoki (S’98) was born in Kyoto, Japan, in
1965. He received the B.S.E.E. degree from the
Universidade Estadual de Campinas, Campinas SP,
Brazil, in 1987, the M.S.E.E. degree from California
Institute of Technology (Caltech), Pasadena, in Ali Hajimiri (S’94–M’99) received the B.S. degree
1999, and is currently working toward the Ph.D. in electronics engineering from the Sharif University
degree at Caltech. of Technology, Tehran, Iran, and the M.S. and Ph.D.
He founded and managed the PST Indústria degrees in electrical engineering from Stanford Uni-
Eletrônica da Amazônia Ltda, SP, Brazil, a car versity, Stanford, CA, in 1996 and 1998, respectively.
electronic components manufacturing company with From 1993 to 1994, he was a Design Engineer
300 employees in 1998 from 1988 to 1998. His with Philips Semiconductors, where he was involved
current research interests include high-frequency silicon RF analog integrated with a BiCMOS chipset for GSM cellular units.
circuits for wireless communications with emphasis on power amplifiers. In 1995, he was with Sun Microsystems, where
Mr. Aoki was the recipient of the Schlumberger Fellowship (1998–1999) and he was involved with the UltraSPARC micropro-
the 2000 Walker von Brimer Foundation Award presented by Caltech. cessor’s cache RAM design methodology. During
the summer of 1997, he was with Lucent Technologies (Bell Laboratories),
Holmdel, NJ, where he investigated low phase-noise integrated oscillators. In
1998, he joined the Faculty of the California Institute of Technology, Pasadena,
as an Assistant Professor of electrical engineering. His research interests are
Scott D. Kee was born in Albany, OR, in 1976. He high-speed and RF ICs. He co-authored The Design of Low Noise Oscillators
received the B.E.E. degree in electrical engineering (Norwell, MA: Kluwer, 1999). He holds several U.S. and European patents.
from the University of Delaware, Newark, in 1998, Dr. Hajimiri is a member of the Technical Program Committees of the In-
and is currently working toward the Ph.D. degree at ternational Conference on Computer-Aided Design (ICCAD). He has served
the California Institute of Technology, Pasadena. as a guest editor of the IEEE TRANSACTIONS ON MICROWAVE THEORY AND
His research interests include high-efficiency TECHNIQUES. He was the recipient of the Gold Medal of the National Physics
power amplifiers, switching amplifiers, RF and Competition, the Bronze Medal of the 21st International Physics Olympiad,
microwave design, analog integrated circuits, and Groningen, The Netherlands, and the IBM Faculty Partnership Award. He was a
electronics for practicing musicians. corecipient of the International Solid-State Circuits Conference 1998 Jack Kilby
Outstanding Paper Award.

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