This article has been accepted for publication in a future issue of this journal, but has not been

fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2018.2863181, IEEE
Transactions on Industrial Electronics
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Model Predictive Current Control of Modular

Multilevel Converters with Phase-Shifted
Pulse-Width Modulation
Dehong Zhou, Member, IEEE, Shunfeng Yang, Student Member, IEEE, Yi Tang, Senior Member, IEEE

Abstract—Model predictive current control (MPCC) is Their modularity facilitates future maintenance and allows for
a promising candidate for modular multilevel converters future adjustments to the voltage rating through increasing or
(MMCs) control due to its advantages of direct modeling decreasing the number of submodules (SMs) [10]. Moreover,
and fast dynamic response. The conventional MPCC, which
obtains the optimal control input by evaluating a cost MMCs can operate even with faulty SMs through the utiliza-
function for all the possible switching states, may make tion of fault-tolerant techniques, which improves the reliability
the MPCC impractical due to the exponentially increasing of MMCs [11], [12].
computation burden with the increasing number of sub- Despite these advantages, controlling MMCs is more chal-
modules (SMs). On the other hand, MPCC experiences high lenging than that of other multilevel converters, mainly be-
load current and circulating current tracking errors since
only one switching state is selected and applied during cause efforts have to be devoted to SMs capacitor voltage
one control period. To address these issues, this paper balancing [13] and circulating currents suppression [14] simul-
proposes an MPCC with phase-shifted pulse-width mod- taneously in addition to output power or current control [15].
ulation (PS-PWM) for improving the steady-state control Linear system theory-based proportional-integral (PI) [16] or
performance. The arm voltages are considered as a whole proportional-resonant (PR) [17] controllers with phase-shifted
to implement the proposed MPCC. The optimal duty cycle is
obtained based on the load and circulating current tracking pulse-width modulation (PS-PWM) are usually developed for
error minimization and applied using the PS-PWM. As a the MMC system control. However, the MMC system is
result, the computation burden is unrelated to the num- highly nonlinear with a wide range of operational points.
ber of SMs by avoiding the exhaustive evaluation process Its transient performance with the PI or PR controllers is
for all the possible switching states. A better steady-state not satisfactory. Model predictive current control (MPCC)
performance with smaller tracking errors is achieved with
the similar switching frequency and the tedious tuning provides a promising alternative for the control of complex and
process of weighting factor is eliminated. Experimental multi-objective power converter systems. It has a fast dynamic
results are presented to demonstrate the effectiveness of response, straightforward realizations, and easy inclusion of
the proposed MPCC. nonlinearities and constraints of the system [18]. Because of
Index Terms—Modular multilevel converter (MMC), these advantages of MPCC over traditional control schemes,
model predictive current control (MPCC), phase-shifted it is becoming popular for MMC control [19]–[23].
modulation (PS-PWM) However, the conventional MPCC for MMC suffers from
problems such as overload computation burden and limited
I. I NTRODUCTION steady-state performance. In conventional MPCC, all the
switching states should be evaluated to obtain the optimal
M ODULAR multilevel converters (MMCs) have emerged
as one of the most attractive topologies for high volt-
age applications [1]–[4], such as high-voltage direct-current
control switching state in every control period [21], and the
computation burden increases exponentially with the increas-
(HVDC) transmission systems [5], flexible alternating current ing number of SMs. When the number of SMs is large, the
transmission systems [6], medium voltage motor drives [7], real-time implementation becomes impractical with the state-
[8] and energy storage systems [9] thanks to their advanced of-art microprocessor. Extensive research efforts have been
benefits of modularity, flexible expandability, transformer- devoted to reducing the computation burden of MPCC [23]–
less configuration, ease of assembling, scalability, and so on. [27]. An indirect MPCC that decouples the control of the
SM capacitor voltages from the cost function by an external
Manuscript received January 13, 2018; revised April 20, 2018, June voltage sorting algorithm was proposed in [24]. This scheme
13, 2018; accepted July 20, 2018. The work presented in this paper
is part of the research programme of Maritime Research Between increased the complexity and reduced the control option to
Singapore (SMI) & Norway (RCN) with project number SMI-2015-MA- 2N + 1 voltage levels. Several works on the MMC with N + 1
15, which is funded by the Singapore Maritime Institute. (Corresponding output voltage levels for further reducing the computational
author: Yi Tang)
D. Zhou is with Maritime Institute@NTU (email: [email protected]). complexity of MPC methods [22], [23], [28]. Nevertheless,
S. Yang is with the Rolls-Royce@NTU Corporate Lab, Nanyang Tech- the MMC with N + 1 output voltage levels has inferior THD
nological University, Singapore (e-mail: [email protected]). performance with respect to the ac-side currents compared to
Y. Tang is with the School of Electrical and Electronic Engineering,
Nanyang Technological University, 50 Nanyang Avenue, 639798 Singa- that of the MMC with 2N +1 output voltage levels. Moreover,
pore (E-mail: [email protected]). the complexity of these methods increases with extra loop and

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on, the capacitor voltage is inserted and the capacitor voltage

idc SMu,1
appears at the terminal, and when Sx0 is on, the capacitor
uu
U dc SMu,N voltage is bypassed and the terminal voltage is zero. Ra is
Cdc Su ,1
2
iu Ra the equivalent resistance of the arm inductor. uu , iu , and ul , il
C usm,u ,1
La represent the voltages and currents of the upper arm and the
Ll Rl uo Su¢ ,1
U dc ic lower arm, respectively. uo is the output voltage and io is the
io
La output current. ic is the circulating current. Ll , Rl are the load
il inductor and resistance. Udc is the dc source voltage. usm,u,i
Cdc
U dc Ra
2 SMl,1
and usm,l,i are the ith SM capacitor voltages of the upper arm
ul and the lower arm, respectively. N is the number of SMs.
SMl,N
Using the Kirchhoff’s circuit laws, the following mathemat-
ical equations can be obtained
Fig. 1: Structure of a single-phase MMC based inverter.
N
X N
X
uu = usm,u,i , ul = usm,l,i , (1)
i=1 i=1
the very limited number of control options cannot ensure the
correct controllability of the circulating currents. On the other diu 1 dio
hand, only one switching state is selected and applied during Ra iu + La = Udc − uu − Rl io − Ll , (2)
dt 2 dt
one control period in the conventional MPCC, the sampling
frequency should be high enough to achieve a satisfactory con- dil 1 dio
trol performance. Additionally, weighting factors are utilized Ra il + La = Udc − ul + Rl io + Ll , (3)
dt 2 dt
in the cost function of the conventional MPCC, which are
sometimes challenging to fine-tune [29]. The MPCC with a 1 1
iu = ic + io , il = ic − io . (4)
modulator can retain all the advantages of conventional MPCC 2 2
and address the associated problem with conventional MPCC The dynamic equations of MMCs can be described as
such as weighting factor tuning, poor steady-state performance
[30], [31]. Compared with other modulation schemes, PS- dio Ra + 2Rl −uu + ul
PWM has a better harmonic characteristic at a low switching = − io + . (5)
dt La + 2Ll La + 2Ll
frequency. Combined with the PS-PWM, MPC of MMC can dic Ra Udc − uu − ul
achieve smaller tracking errors and lower total harmonic = − ic + (6)
dt La 2La
distortions (THD).
Although extensive research efforts have been devoted to the The predictive model of MMCs can be estimated by the
implementation of the MPCC with two-level converters [32], first-order Euler approximation of (5) and (6).
[33] to achieve fixed switching frequency model predictive
 
Ra + 2Rl −uu + ul
control. To our best knowledge, little effort has been made to io (k + 1) = io (k) + − io + Ts , (7)
La + 2Ll La + 2Ll
develop MPCC with PS-PWM because the fixed switching fre-  
quency model predictive control for two-level converters is not Ra Udc − uu − ul
ic (k + 1) = ic (k) + − ic + Ts , (8)
portable to multilevel converters because of the computation La 2La
burden and the characteristics of PS-PWM where the update where io (k) and ic (k) are the measured load current and
frequency of each SM is 1/N of the sampling frequency. In circulating current at time instant k, respectively. io (k + 1)
this paper, the arm voltages are considered as a whole and the and ic (k + 1) are the predicted load current and circulating
four virtual voltage vectors are adopted to integrate PS-PWM current at time instant k + 1, respectively. Ts is the sampling
to the MPC. The optimal duty cycle is obtained based on period.
the load and circulating current tracking error minimization
and applied using a PS-PWM. As a result, the proposed III. MPCC WITH PS-PWM
MPCC scheme can reduce current harmonic components and
In the conventional MPCC, only one switching state is
THD, obtain a constant switching frequency, and remain the
selected and applied during one control period. With a lower
advantage of fast dynamic response in conventional MPCC.
switching frequency in high power applications, the total
The procedure of exhaustive cost function evaluation for all
harmonic distortion (THD) of the output current is high. To
the possible switching states is avoided, and the computation
improve the steady-state performance of the MMC, PS-PWM
burden is unrelated to the number of SMs.
is integrated into MPCC for MMC control. In this method,
the arm voltages are considered as a whole to calculate the
II. S YSTEM D ESCRIPTION optimal duty cycles. The proposed MPCC with PS-PWM is
The circuit configuration of a single-phase MMC is shown carried out in five steps: 1) arm voltage combination selection,
in Fig. 1, which consists of two arms. Each arm is equipped 2) current tracking error minimization, 3) individual SM
with an arm inductor La to limit the arm currents. Each SM capacitor voltage balancing, 4) duty cycle application by PS-
contains a dc storage capacitor C and two complementary PWM, 5) delay compensation. Each step is discussed in detail
IGBT modules (i.e., Sx and Sx0 ). For each SM, when Sx is in the following section.

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TABLE I: Arm Voltage Combination in the MMC where i∗o is the reference of load current. The switching
voltage uo for voltage uc for combination with a smaller cost function value, denoted as vo1
state symbol
load current control circulating current control uc and its corresponding voltage for circulating current control
10 −uu Udc − uu v1 denoted as vc1 , will be selected. v3 and v4 are also selected
01 ul Udc − ul v2
11 −uu + ul Udc − uu − ul v3 to minimize the load and circulating current tracking errors
00 0 Udc v4 simultaneously, denoted as vo2 /vc2 and vo3 /vc3 .

B. Current Tracking Error Minimization

A. Arm Voltage Combination Selection After the determination of three voltage combinations, the
In order to integrate the PS-PWM into MPC and eliminate duration of each voltage combination should be calculated.
the procedure of exhaustive cost function evaluation for all The optimal duty cycle is obtained based on the tracking error
the possible switching states, the arm voltages are considered minimization. The derivatives of load and circulating currents
as a whole to calculate the duty cycle for each arm. For can be represented using uo and uc as follows:
simplification, the voltage drop on the resistor in (5) and (6) 
dio  Ra + 2Rl uo
is ignored and the arm voltage combination of the MMC can σoi = =− io + , (12)
dt uo =voi
 La + 2Ll La + 2Ll
be categorized in Table I. 
dic  Ra uc
1) state ”10” denotes that all SMs in the upper arm are inserted σci = = − ic + , (13)
and the ones in the lower arm are bypassed. In this state, dt uo =vci
 La 2La
−uu is applied to load current control and (Udc − uu ) is where i ∈ {1, 2, 3}.
applied to circulating current control, denoted as v1 . The predicted circulating and load currents at the end of the
2) state ”01” denotes that all SMs in the upper arm are control period can be expressed by
bypassed and the ones in the lower arm are inserted. In this
state, ul is applied to load current control and (Udc − ul ) io (k + 1) = io (k) + σo1 t1 + σo2 t2 + σo3 (Ts − t1 − t2 ), (14)
is applied to circulating current control, denoted as v2 . ic (k + 1) = ic (k) + σc1 t1 + σc2 t2 + σc3 (Ts − t1 − t2 ), (15)
3) state ”11” represents that all the SMs in the upper arm and
lower arm are inserted. In this state, (−uu + ul ) is applied where σo1 , σo2 , and σo3 are the load current derivatives
to load current control and (Udc − ul − uu ) is applied to when applying arm voltage combinations vo1 , vo2 , and vo3 ,
circulating current control, denoted as v3 . respectively. σc1 , σc2 , and σc3 are the circulating current
4) state ”00” represents that all the SMs in the upper arm derivatives when applying arm voltage combinations vc1 , vc2 ,
and lower arm are bypassed. In this state, arm voltage 0 and vc3 , respectively. t1 is the duration time of vo1 /vc1 and t2
is applied to load current control and Udc is applied to is the duration time of vo2 /vc2 . (Ts − t1 − t2 ) is the duration
circulating current control, denoted as v4 . time of vo3 /vc3 .
It should be noted that the four virtual states are utilized to The cost function for simultaneous circulating and load
calculate the total amount of duty cycles for each arm based current control is defined as follows
on the voltage-second balance rule. They are not directly used J = (i∗o − io (k + 1))2 + λ(i∗c − ic (k + 1))2 , (16)
to control the MMC. By considering the arm voltages as a
whole, the predictive model of MMCs can be rewritten as where i∗c is the reference of circulating current. λ is the
  weighting factor which can be utilized to set the priority of
Ra + 2Rl uo the current control. Substituting (14) and (15) into (16), the
io (k + 1) = io (k) + − io + Ts , (9)
La + 2Ll La + 2Ll optimization of cost function J is to select proper t1 and t2
  to minimize the cost function.
Ra uc To obtain the minimized load and circulating current track-
ic (k + 1) = ic (k) + − ic + Ts , (10)
La 2La ing errors, the optimal values of t1 and t2 should satisfy the
minimum value conditions
where uo and uc are the arm voltage combinations listed in (
∂J(t1 ,t2 )
Table I. ∂t1 = 0,
∂J(t1 ,t2 ) (17)
In the steady state, the arm voltages are balanced, and = 0.
∂t2
the value of (−uu + ul ) is insignificant and can be ignored.
Therefore, v3 and v4 have a same effect on load current control The solution of (17) is given by
and their derivatives approximate to zero. According to (5), t1 = tnum1

tden ,
the load current derivative of v1 is negative and that of v2 tnum2 (18)
t2 = tden .
is positive by neglecting the voltage drop on the resistor.
Therefore, only one voltage combination out of v1 and v2 where tnum1 , tnum2 and tden are denoted in (19) (20) (21),
should be selected for current control in each control period. respectively. As shown in the expressions of tnum1 , tnum2 and
Then, the first step is to select a proper state between ”10” tden . λ is eliminated, which means that this control scheme is
and ”01” using a cost function defined as follows free from weighting factor tuning. The values of t1 and t2 are
saturated to zero if they are negative, or Ts if t1 and t2 are
Js = (i∗o − io (k + 1))2 , (11) larger than Ts due to the physical limitation.

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tnum1 = (σc2 − σc3 )(i∗o − io (k)) + (σo3 − σo2 )(i∗c − ic (k)) + (σc3 σo2 − σc2 σo3 )Ts , (19)
tnum2 = (σc3 − σc1 )(i∗o − io (k)) + (σo1 − σo3 )(i∗c − ic (k)) + (−σc3 σo1 + σc1 σc3 )Ts , (20)
tden = σc3 σo2 − σc1 σo2 − σc2 σo3 + σc1 σo3 − σc3 σo1 + σc2 σo1 . (21)

Proposed MPCC PS-PWM 2 NTs tu 1 d u1

SMu,1
k+N N ( st1 + t2 )
2 NTs
tbu1 2Ts
Nusm tu / l usm tsm ,u / l = Ntu / l k tu 2 du2
N ( st1 + t2 ) SMu,2
output
tu / l Î [0, Ts ] tsm ,u / l Î [0, NTs ] tuk1 tuk1+ N tuk1+ 2 N tuk1+ 3 N tbu 2 2Ts
(a) tuN d uN
k+N N ( st1 + t2 ) SMu,N
Arm voltage Duty cycle SM voltage Duty cycle
k tbuN
Fig. 2: Diagram of the duty cycle calculation and implemen- PS-PWM
tuk1 tuk1+ N
Upper arm t
l1 d l1
tation equivalence in each sampling period. N ( (1 - s )t1 + t2 ) SMl,1

k+N-1 tbl1
tl 2
dl 2
tuk2+ N -1 N ( (1 - s )t1 + t2 ) SMl,2
C. Individual SM Capacitor Voltage Balancing tbl 2
k+1 tlN
d lN
Although it is assumed that the SM capacitor voltages N ( (1 - s )t1 + t2 ) SMl,N

are balanced in MMC normal operation, an individual SM tblN

output
k +1
tuN Lower arm
capacitor voltage balancing scheme is still needed, where (b) (c)
tbui/bli refer to the duty cycle for voltage balancing of the ith Fig. 3: Diagram of the duty cycle calculation for each SMs and
SM in the upper and lower arms. Note that tbui/bli is normally operation process of PS-PWM (a) duty cycle updates in SMu,1
negligible compared to t1 and t2 . The duty cycle for individual (b) duty cycles update sequence in the upper arm (c) phase
SM capacitor voltage balancing is generated according to dispatch of the PWM and the calculated intervals connected
∗
iu/l uc,u/l,i − uc,u/l,i (k) to the modulator.
tbui/bli = kc  Ts , (22)
u∗c,u/l,i

iu/l 
where u∗c,u/l,i refer to the voltage balancing reference of the each peak and valley point. Therefore, the duty cycle update
ith (i ∈ {1, 2, ..., N }) SM in the upper and lower arms and kc frequency for each SM is N1Ts . At each sampling point,
is a proportional parameter that regulates the balancing speed only one SM’s duty cycle will be updated. Based on the
of individual SM capacitor voltage. voltage-second balance rule, the duty cycle for the SM at each
sampling point can be updated as follows
D. Duty Cycle implementation by PS-PWM uu tu N usm tu
tsm,u = = = N tu , (25)
After the arm voltage combination and their optimal dura- usm usm
ul tl N usm tl
tion time determination, the duty cycles for each SM should tsm,l = = = N tl , (26)
be calculated and applied to the MMC by PS-PWM. In the usm usm
proposed MPCC, the arm voltage is considered as a whole where tu/l ∈ [0, Ts ] and tsm,u/l ∈ [0, N Ts ]. The equivalence
to calculate the total duty cycle for each arm based on the of the duty cycle calculation and implementation is presented
voltage-second balance rule. The switching state of each SM in Fig. 2. As shown in Fig. 3, the duty cycles update follow
is managed by the PS-PWM. Therefore, the proposed MPCC the sequence SMN -SMN−1 -...-SM1 -SMN -SMN−1 -...
consists of two independent parts, i.e., MPCC calculates the Taking the individual SM capacitor voltage balancing into
duration time of the arm voltages, and PS-PWM generates consideration, the duty cycle for each SM at each sampling
interleaving gating signals for SMs according to the output of point in the lower and upper arm is represented as
the MPCC.
The duty cycle for the lower and upper arm is represented tui = N (st1 + t2 ) + tbui , (27)
as tli = N ((1 − s)t1 + t2 ) + tbli , (28)

tu = st1 + t2 , (23) where tui and tli refer to the duty cycles applied to ith
tl = (1 − s)t1 + t2 , (24) SM of the upper and lower arms. The detailed duty cycle
calculation for each SM is presented in Fig.3. Within each
where s is a binary variable, and s is equal to 1 when v1 is SM, the duty cycle is updated at the peak and valley point of
selected and s1 is equal to 0 when v2 is selected. triangular carriers and the update frequency is N1Ts , as shown
For simplicity, the capacitor voltages usm of each SM are in Fig.3 (a). The duty cycle update sequence within each arm
assumed to be balanced and equal to UNdc . The arm voltages is presented Fig.3 (b). The phase displacement of triangular
uu /ul = N usm are considered as a whole to calculate the duty carriers for SMs in one arm is 2π
N , and no phase displacement
cycle for each arm. In the PS-PWM, the carrier frequency is is required between the upper and lower arms, as shown in
set to 2N1Ts and the duty cycle for each SM is updated at Fig.3 (c). In this way, the output voltage level is 2N + 1 and

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Proposed MPCC
Duration calculation for load
v ,v
o1 o 2 Start
Duration and circulating current tracking
io Arm
vo 3 , vc1 Calculation t , t errors minimization
Delay Current Voltage 1 2
ic Compensation Prediction Combination by Tracking Voltage and current
Selection vc2 , vc3 Errors sampling Individual SM capacitor voltage
Minimization balancing
Outer loop Delay compensation
io* PS- tui , tli Duty cycles calculation
Output Current MMC
PWM
Reference Generation for each SM
* Load current and circulating
ic _ dc Capacitor Balancing current reference calculation
(uc ,u + uc ,l ) / 2
*  ic*_ va  ic* Pulse generation by
PS-PWM
uc NF1 PI
Individual SM tbui , tbli
Arm voltage combination
selection
0 Capacitor Voltage
uo *
(uc ,u - uc ,l )
 NF2 PI
ic*_ vd Balancing end

Fig. 5: Flowchart of the proposed MPCC with PS-PWM.

Fig. 4: Control diagram of the proposed MPCC with PS-PWM.

where Uo and Io are root mean square (RMS) output voltage

the equivalent switching frequency is 2N fsw , where fsw is and output current, respectively, ϕo is phase difference of the
the carrier frequency. output voltage and current.
Besides the load current tracking and circulating current
E. Delay Compensation suppression, the SM capacitor voltage is also controlled for
stable operation of MMC. The averaging and differential
There is a well-known one-step delay between the command capacitor voltage control are achieved by the voltage con-
voltage and the applied voltage in the digital implementation trollers given in Fig. 4.The output of proportional-integral (PI)
of MPCC [34]. Therefore, the voltage vector at (k + 2) instant controller for averaging capacitor voltage control is denoted as
rather than the voltage vector at (k + 1) instant should be i∗d va and the output of PI controller for differential capacitor
applied to the converter to eliminate the adverse influence voltage control multiplied with the normalized output voltage
caused by the one-step delay. A model-based prediction is u∗o is represented as i∗d vd . As derived in [35], there exist
applied to obtain all the variables values at (k + 1) instant, second-order ripples in (uc,u + uc,l ) and fundamental ripples
which serves as the initial state for duty cycle calculation. in (uc,u − uc,l ). Therefore, the voltage ripples are removed
Based on the voltage-second equilibrium, the optimal voltage with the help of notch filters (NFs), whose transfer functions
calculated at k instant is are expressed as
vo1 t1 + vo2 t2 + vo3 (Ts − t1 − t2 ) s2 + (2ω0 )2
uo (k) = , (29) N F1 = (32)
Ts s2 + 2ω0 s/Q + (2ω0 )2
vc1 t1 + vc2 t2 + vc3 (Ts − t1 − t2 )
uc (k) = . (30) s2 + ω02
Ts N F2 = (33)
s2 + ω0 s/Q + ω02
These two voltage values are substituted into (9) and (10)
where ω0 is the fundamental angular velocity and Q is the
to get load and circulating current io (k + 1) and ic (k + 1).
quality factor of the notch filter. ω0 is set to 100π and Q is
These current values serve as the initial state for voltage
set to 0.707. The individual SM capacitor voltage balancing
combination selection and current tracking error minimization
is regulated by injecting duty cycle to each SM as discussed
to compensate the one-step delay. More details regarding the
in Section III-C. Finally, the flowchart of the proposed MPCC
computational delay compensation can be found in [34].
with PS-PWM is given in Fig. 5.

IV. OVERALL C ONTROL S CHEME D ESIGN FOR T HE V. T HEORETICAL C OMPARISON OF THE P ROPOSED
MMC M ETHOD WITH THE C ONVENTIONAL MPCC
The control diagram of proposed MPCC with PS-PWM is For MMCs with conventional MPCC, the predictive values
illustrated in Fig. 4, which mainly consists of the following of all the control variables are calculated. All the possible
parts, i.e., outer loop reference calculation, load and circulating switching states are evaluated using a single cost function to
current reference tracking by the proposed MPCC, individual obtain the optimal control of load current, circulating current,
capacitor voltage balancing, PS-PWM. The outer loop refer- and capacitor voltage simultaneously [20].
ence calculation is discussed in this section. The predictive model for the load and circulating current is
The load current reference i∗o is obtained according to the the same as in (7) (8). The predictive model for the capacitor
output power reference. The circulating current reference is voltage can be written as follows
obtained from SM capacitor voltage balancing and active 1
power balancing. The dc component of the circulating current uc,u/l,i (k + 1) = uc,u/l,i (k) + Ts iu/l (k)Sui/li (34)
C
reference is set for active power balancing as follows
where uc,u/l,i (k) and uc,u/l,i (k + 1) refer to the capacitor
i∗d dc = Uo Io cos(ϕo )/2Udc (31) voltages of the ith SM in the upper and lower arms at time

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instant k and k + 1, respectively. Sui/li is the switching state 

of the ith SM in the upper and lower arms. iu/l (k) refers to 
the upper and lower arm current at time instant k. 
The cost function of MMCs can be written as 


J= λ1 (i∗c
− ic (k + 1)) + 2
λ2 (i∗o
− io (k + 1)) (35) 2

N
X XN 
+ (u∗c − uc,u,i (k + 1))2 + (u∗c − uc,l,i (k + 1))2 ,
i=1 i=1

where λ1 and λ2 are weighting factors that determine the Fig. 6: Experimental setup of the single phase MMC (1)
importance of different objectives when selecting the optimal control desk (2) DSPACE MicroLabBox (3) DC source (4)
switching combination. u∗c is the capacitor voltage reference converter (5) load resistance (6) arm inductor (7) load inductor.
for each SM. The switching state with the lowest cost function
value is applied to the MMC.
Although the duty cycle calculation process and structure 5
Conventional MPCC
of the proposed scheme are more complicated than that of
4 Proposed MPCC
the conventional MPCC, the proposed MPCC presents the

sw[kHz]
following advantages. 3

1) In the proposed MPCC, the optimal duration time is

f
2
selected in every control cycle with the objective of ob-
taining the minimum load and circulating current tracking 1

errors. However, in conventional MPCC, the duration

0
time in every control period is constant. Consequently, the 20% 40% 60% 80% 100%
current ripples in the proposed method are significantly
Load (p.u.)
lower than that of the conventional MPCC.
2) The load current and the circulating current reach their Fig. 7: Switching frequency of one SM with the two MPCCs
reference values at the end of the control cycle in the at different load conditions
proposed MPCC. The response to the references of load
and circulating current is straightforward and the dynamic TABLE II: System Parameters
performance of the proposed method is intact compared
Parameters Values Parameters Values
to that of the conventional MPCC.
DC bus voltage: UDC 240 V Load inductance: Ll 2 mH
3) In the proposed MPCC, the arm voltage is considered DC bus capacitance:CDC 3.9 mF Arm inductance: La 5 mH
as a whole to obtain the optimal control of load and Rated output frequency: 50 Hz Load resistance: Rl 11 Ω
circulating current simultaneously. Therefore, the compu- No. of SM in each arm: N 3 SM capacitance: CSM 940 µF
Arm resistance: Ra 0.2 Ω
tation burden of the proposed MPCC is unrelated to the
number of SMs. However, in the conventional MPCC,
all the switching combinations are evaluated to obtain
A. Experimental Rig
the optimal control and the computation burden increases
exponentially with the increasing number of SMs. The single-phase MMC inverter shown in Fig. 1, whose
4) In the proposed MPCC, the load current and circu- detailed parameters are listed in TABLE II, was built in the
lating current are optimized by selecting the optimal laboratory. The experimental setup is illustrated in Fig. 6. A
arm voltage combination and optimal duration time. The dSPACE MicroLabBox DS1202 was adopted to implement
individual capacitor voltages are regulated by injecting the digital control and a slave Xilinx was applied to generate
duty cycle directly. The weighting factor and its tedious the gate signals for individual SMs. The voltage and current
tuning procedure are eliminated. However, in the conven- quantities required by the proposed control strategy were
tional MPCC, at least two weighting factors are adopted sampled every Ts to calculate the switching signals for each
and their values are always determined in an empirical SM in the dSPACE module. To carry out a fair comparison,
try-and-error way. The implementation of the proposed the average switching frequency fsw of the two MPCC should
MPCC is easier than that of the conventional MPCC. be approximately the same. However, the switching frequency
of the conventional MPCC varies with the load. When the
load is very heavy or at full load, almost all the SMs will be
VI. E XPERIMENTAL R ESULTS inserted and the switching state will remain unchanged in sev-
In this section, the effectiveness of the proposed MPCC and eral consecutive sampling periods. Therefore, the number of
its performance comparison with the conventional MPCC [20] switchings used to maintain the internal dynamic will reduce
are evaluated with experimental results. All the experimental at full load. In this paper, the similar switching frequency at
results are obtained at 10 kHz sampling rate except the data for full load is chosen for the test. The sampling frequency of the
Fast Fourier Transformation (FFT) which is obtained directly conventional MPCC is set to 10 kHz and the average switching
by the oscilloscope with a sampling rate of 1 MHz. frequency of the conventional MPCC at full load is 1.811

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2018.2863181, IEEE
Transactions on Industrial Electronics
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

i i
u i u i
l l

[A]

[A]
10 10

5 5
l

l
i ,i

i ,i
u

u
0 0

-5 -5

10 10
[A]

[A]
0 0
o

o
i

i
-10 -10

4 4
[A]

[A]
2 2
c

c
i

i
0 0
& [V]

& [V]
100 100
u ~ uc,u,3 u u ~ uc,l,3
~ uc,l,3 u ~ uc,u,3
c,l

c,l
c,u,1 c,l,1 c,u,1 c,l,1
u

u
80 80
c,u

c,u
60 60
u

u
100 100
o[V]

o[V]
50 50
0 0
-50 -50
u

u
-100 -100

0.0 0.1 0.2 0.0 0.1 0.2

t[s] t[s]

(a) Proposed MPCC (b) Conventional MPCC

Fig. 8: Steady performance of MPCC. From top to bottom, waveforms are arm currents, output current, circulating current,
SM capacitor voltages, Output voltage.

kHz, as shown in Fig.7. Therefore, the carrier frequency of the the output voltage. In the conventional MPCC, all the control
PS-PWM should be set to 1.811 kHz for a fair comparison. objectives are controlled by selecting the switching states.
In the PS-PWM, the sampling frequency should be set to Therefore, a certain number of switching times are required
2N fsw = 10.8 kHz. For simplicity, the sampling frequency of to guarantee internal dynamics, such as the SM capacitor
the proposed MPCC is set to 10 kHz and the carrier frequency voltage balancing. However, in the proposed method, no extra
of the PS-PWM is set to 1.667kHz. The weighting factors switching is required to guarantee internal dynamics. The
of the conventional MPCC are selected by the trial-and-error internal dynamic is guaranteed by adjusting the applied duty
method. In this paper, the weighting factors are set as λ1 = 16 cycles in (22). In view of this, it is understandable that the
and λ2 = 24. output current performance of the conventional MPCC with
The execution time of the two MPCC with 3 SMs was a higher switching frequency is even worse than that of the
tested to evaluate their computation burden using the dSpace proposed MPCC.
profiler. Even though dSpace MicroLabBox is a very powerful Fig. 9 (a) (b) presents the circulating current and output
controller with a dual-core 2 GHz real-time processor, the current tracking errors of the MMC regulated by the proposed
execution time of the proposed MPCC is 6.2 µs while that of MPCC with PS-PWM and conventional MPCC, respectively.
the conventional MPCC is 9.1 µs. The execution time of the The peak-to-peak circulating current tracking error of the
proposed method is only 68.1% of the conventional MPCC. proposed MPCC is less than 0.4 A, whereas that of the
conventional MPCC is over 2 A. The peak-to-peak load current
B. Steady-State Performance tracking error of the proposed MPCC is around 0.6 A, whereas
The steady-state performance of the MMC regulated by the that of the conventional MPCC is over 2 A. Therefore, it
proposed MPCC is investigated in this set of experiments. The is evident that the proposed MPCC can track the current
amplitude of the output current is set to 8 A. The steady-state references more accurately than the conventional MPCC.
performance of the MMC regulated by the proposed MPCC In order to further validate the advantage of the proposed
with PS-PWM is illustrated in Fig. 8 (a). It can be seen that the MPCC, the harmonic spectra are presented in Fig. 10. The data
load current and circulating current are well regulated with the were acquired from an oscilloscope at 1 MHz sampling rate
help of the proposed MPCC and the MMC operates stably with and analyzed in MATLAB. With the same sampling frequency,
balanced SM capacitor voltages. For comparison, the voltage the load current THD of conventional MPCC is 6.13%, which
and current waveforms of the MMC with conventional MPCC is much higher than that of the proposed MPCC which is
are shown in Fig. 8 (b). According to the experimental results, 2.68%, proving the dramatic performance improvement in
the proposed MPCC with PS-PWM presents fewer ripples in output current quality. It should be noted that for conventional
the control variables (load current and circulating current) and MPCC, only one switching state is used in one control

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2018.2863181, IEEE
Transactions on Industrial Electronics
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2 2
2.2 (peak-to-peak)
ic_error [A]

ic_error [A]
0.4 (peak-to-peak)

0 0

-2 -2

2 2
0.6 (peak-to-peak) 2.1 (peak-to-peak)
io_error [A]

io_error [A]
0 0

-2 -2
0.0 0.1 0.2 0.0 0.1 0.2

t[s] t[s]

(a) Proposed MPCC (b) Conventional MPCC

Fig. 9: Tracking errors of MPCC. From top to bottom, waveforms are circulating current tracking error and load current
tracking error.

10 10
io [A]

0 io [A]
0

-10 -10
0 0.01 0.02 0.03 0.04 0 0.01 0.02 0.03 0.04
Fundamental (50Hz) = 8.02 , THD= 2.68% Fundamental (50Hz) = 7.931 , THD= 6.13%
1 1
H1 H n [%]

H1 H n [%]

0.5 0.5

0 0
0 100 200 300 400 500 0 100 200 300 400 500
Harmonic order Harmonic order
(a) Proposed MPCC (b) Conventional MPCC

Fig. 10: Current FFT results of MPCC. From top to bottom, waveforms are the load current and its spectrum.

period, and the harmonic contents are distributed broadly, the output current is 0.25 p.u.. The capacitor voltages of each
which are not easy to filter. On the contrary, by using the SM are balanced indicating the effectiveness of the proposed
proposed MPCC with PS-PWM, the switching frequency can scheme at a low operation point. The slow response of ic is
be constant. The current harmonics concentrate on the 100th-, introduced by the delayed updating of i∗c dc which is calculated
200th-, 300th-order harmonics, which are in accordance with for active power balancing according to the output voltage and
the switching frequency. This brings some benefits for the output current measurements.
design of filters. To verify the dynamic performance of the proposed MPCC,
a more critical step change is tested. The load current reference
C. Dynamic Response phase 180◦ step change is presented in Fig. 12. As shown,
The dynamic response of the MMC with the proposed the load current and the circulating current can track their
MPCC is evaluated in the following set of experiments. The references and the capacitor voltages of the upper and lower
amplitude of the output current reference is changed from arms are balanced after a short transient process. It can be seen
2 A to 8 A at 0.1 s. The voltage and current waveforms that the MMC system is stable during load current reference
of the MMC with the proposed MPCC and the conventional phase 180◦ steps change. The load current reaches its reference
MPCC during i∗o step changes are presented in Fig. 11 (a) (b), in a very short time.
respectively. It can be seen that the MMC system is stable As shown in Fig. 11 and Fig. 12, the transient response
during large operation point step changes in both cases. It can of the proposed MPCC is very fast and same as that of
be noticed that the load current and circulating current can the conventional MPCC, indicating that the advantage of
track their references at a low range of operation point where fast dynamic response in conventional MPCC is intact by

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2018.2863181, IEEE
Transactions on Industrial Electronics
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

i i
u l
[A]

[A]
10 10
i i
u l
5 5
l

l
i ,i

i ,i
u

u
0 0

-5 -5

10 10
[A]

[A]
0 0
o

o
i

i
-10 -10

4 4
[A]

[A]
2 2
c

c
i

i
0 0
& [V]

& [V]
100 100 u
u ~ uc,u,3
u ~ uc,l,3 c,u,1 ~ uc,u,3 u ~ uc,l,3
c,l

c,l
c,u,1 c,l,1 c,l,1
u

u
80 80
c,u

c,u
60 60
u

u
100 100
o[V]

o[V]
50 50
0 0
-50 -50
u

u
-100 -100

0.0 0.1 0.2 0.0 0.1 0.2

t[s] t[s]

(a) Proposed MPCC (b) Conventional MPCC

Fig. 11: Dynamic performance of the load current reference magnitude steps change. From top to bottom, waveforms are arm
currents, output current, circulating current, SM capacitor voltages, output voltage.

i i
u
l i i
u l
[A]

[A]

10 10

5 5
l

l
i ,i

i ,i
u

0 0

-5 -5

10 10
[A]

[A]

0 0
o

o
i

-10 -10

4 4
[A]

[A]

2 2
c

c
i

0 0
& [V]

& [V]

100 100
u u ~ uc,l,3 u
~ uc,u,3 ~ uc,u,3 u ~ uc,l,3
c,l

c,l

c,u,1 c,l,1 c,u,1 c,l,1

u

80 80
c,u

c,u

60 60
u

100 100
o[V]

o[V]

50 50
0 0
-50 -50
u

-100 -100

0.0 0.1 0.2 0.0 0.1 0.2

t[s] t[s]

(a) Proposed MPCC (b) Conventional MPCC

Fig. 12: Dynamic performance of the load current reference phase steps change. From top to bottom, waveforms are arm
currents, output current, circulating current, SM capacitor voltages, output voltage.

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Transactions on Industrial Electronics
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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2018.2863181, IEEE
Transactions on Industrial Electronics
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[32] D. Zhou, P. Tu, and Y. Tang, “Multivector model predictive power Yi Tang (S’10-M’14-SM’18) received the B.Eng.
control of three-phase rectifiers with reduced power ripples under degree in electrical engineering from Wuhan
nonideal grid conditions,” IEEE Trans. Ind. Electron., vol. 65, no. 9, University, Wuhan, China, in 2007 and the
pp. 6850–6859, 2018. M.Sc. and Ph.D. degrees in power engineering
[33] Z. Zhang, H. Fang, F. Gao, J. Rodriguez, and R. Kennel, “Multiple- from the School of Electrical and Electronic
vector model predictive power control for grid-tied wind turbine system Engineering, Nanyang Technological University,
with enhanced steady-state control performance,” IEEE Trans. Ind. Singapore, in 2008 and 2011, respectively.
Electron., vol. 64, no. 8, pp. 6287–6298, 2017. From 2011 to 2013, he was a Senior
[34] P. Cortes, J. Rodriguez, C. Silva, and A. Flores, “Delay compensation in Application Engineer with Infineon Technologies
model predictive current control of a three-phase inverter,” IEEE Trans. Asia Pacific, Singapore. From 2013 to 2015,
Ind. Electron., vol. 59, no. 2, pp. 1323–1325, 2012. he was a Postdoctoral Research Fellow with
[35] M. Hagiwara, K. Nishimura, and H. Akagi, “A medium-voltage motor Aalborg University, Aalborg, Denmark. Since March 2015, he has been
drive with a modular multilevel pwm inverter,” IEEE Trans. Power with Nanyang Technological University, Singapore as an Assistant
Electron., vol. 25, no. 7, pp. 1786–1799, 2010. Professor. He is the Cluster Director of the advanced power electronics
research program at the Energy Research Institute @ NTU (ERI@N).
Dr. Tang received the Infineon Top Inventor Award in 2012, the Early
Career Teaching Excellence Award in 2017, and four IEEE Prize Paper
Dehong Zhou (S’14-M’17) was born in Sichuan Awards. He serves as an Associate Editor of the IEEE Journal of
Province, China, in 1989. He received the B.S. Emerging and Selected Topics in Power Electronics (JESTPE).
and Ph.D. degrees from the Department of
Control Science and Engineering, Huazhong
University of Science and Technology, Wuhan,
China, in 2012 and 2016. He is currently a
Research Fellow with Nanyang Technological
University, Singapore.
His research interests include power
electronics, energy storage system, high
performance ac motor drives, predictive control
and fault tolerant control.

Shunfeng Yang (S’15) received the B.Eng. and

M.Sc. degrees in Electrical Engineering from
Southwest Jiaotong University, Chengdu, China,
in 2007 and 2010, respectively. Since 2014,
he has been with the School of Electrical and
Electronic Engineering, Nanyang Technological
University, Singapore, working towards the
Ph.D. degree in power engineering.
His research interests include power
electronics, multi-level converters and converter
control techniques.

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