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CG2027 Assign3

This document contains two problems from an assignment on transistor-level digital circuits: 1) The first problem asks about analyzing a static CMOS logic gate circuit, including determining the Boolean expression and transistor sizing, output resistances for different input patterns, and propagation delays. 2) The second problem examines a pass transistor logic circuit and level restoration circuit. It involves determining the logic function, explaining static power dissipation, designing a fix using one transistor to eliminate static power, and replacing the pass transistor network to perform a new logic function.

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clement hung
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75 views

CG2027 Assign3

This document contains two problems from an assignment on transistor-level digital circuits: 1) The first problem asks about analyzing a static CMOS logic gate circuit, including determining the Boolean expression and transistor sizing, output resistances for different input patterns, and propagation delays. 2) The second problem examines a pass transistor logic circuit and level restoration circuit. It involves determining the logic function, explaining static power dissipation, designing a fix using one transistor to eliminate static power, and replacing the pass transistor network to perform a new logic function.

Uploaded by

clement hung
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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National University of Singapore

Electrical and Computer Engineering

CG2027 (Transistor-Level Digital Circuits)


Assignment #3
AY23/24 Semester 2
Issued: Aug. 28, 2023 Due: Sep. 4, 2023 (12:00pm noon)

Problem 1: CMOS Logic

Consider the following CMOS logic circuits:

VDD

A C D 4

B E
OUT

A B

E
D

Figure 1: A static CMOS gate.

a) Provide the Boolean expression for the circuit.

b) What is the appropriate transistor sizing for the logic circuit to have similar to 1X inverter delay? Fill
in the empty boxes. Assume PMOS D has width of 4(as shown above), and INV1X has
WPMOS:WNMOS of 2:1.

c) Assume the transistors have been sized to give a worst-case output resistance of 12kohm in both pull-
up and pull-down networks for the worst-case input patterns. What input patterns (A-E) give the
lowest output resistance when the output is low? What is the value of that resistance?

d) What input patterns (A-E) give the lowest output resistance when the output is high? What is the
value of that resistance?

e) Neglecting parasitics and assuming a load capacitance of 100fF, calculate the best case t pLH and tpHL.
Problem 2: Pass Transistor Logic and Level Restoration

Consider the circuits of Figure 2. Assume the inverter of M1 and M2 switches ideally at VDD/2, neglect body
effect, channel length modulation and all parasitic capacitances throughout this problem.

Pass Transistor
VDD
Network
B
M1
A x
Mn1 OUT

B M2

Mn2

Figure 2: Level restoring circuit.

a) What is the logic function performed by this circuit?

b) Explain why this circuit has non-zero static power dissipation?

c) Using only just 1 transistor, design a fix so that there will not be any static power dissipation. Explain
how you chose the size of the transistor.

d) Replace the pass-transistor network in Figure 2 with a pass transistor network that computes the
following function: x=ABC at the node x. Assume you have the true and complementary versions of
the three inputs A, B and C.

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