module lab12 (

input wire clk,

input wire reset,
input wire data_in,
output reg sequence_detected
);

// State definitions
parameter S0 = 2'b00;
parameter S1 = 2'b01;
parameter S2 = 2'b10;
parameter S3 = 2'b11;

reg [1:0] state;

always @(posedge clk or posedge reset) begin

if (reset)
state <= S0;
else begin
case (state)
S0: begin
if (data_in)
state <= S1;
else
state <= S0;
end

S1: begin
if (data_in)
state <= S2;
else
state <= S0;
end

S2: begin
if (data_in)
state <= S3;
else
state <= S0;
end

S3: begin
if (data_in)
state <= S3;
else
state <= S0;
end
endcase
end
end

always @(state) begin

sequence_detected <= (state == S3);
end

endmodule

module USR (
input wire clk,
 input wire reset,
input wire shift,
input wire [3:0] I,
output reg [3:0] O,
input wire [1:0] s,
input wire SINR,
input wire SINL
);

wire [3:0] w;
reg [2:0] shift_count;
wire data_out;

always @(posedge clk or posedge reset) begin

if (reset)
shift_count <= 3'b0;
else if (shift)
shift_count <= shift_count + 1;
end

UniversalShiftRegister u1 (
.clk(clk),
.reset(reset),
.shift(shift),
.data_in(I[0]),
.data_out(data_out)
);

Mux m1 (
.sel1(s[1]),
.sel0(s[0]),
.input0(I[0]),
.input1(SINL),
.output1(O[0]),
.output0(O[1])
);

Mux m2 (
.sel1(s[1]),
.sel0(s[0]),
.input0(O[0]),
.input1(O[1]),
.output1(O[2]),
.output0(O[1])
);

Mux m3 (
.sel1(s[1]),
.sel0(s[0]),
.input0(O[1]),
.input1(O[2]),
.output1(O[3]),
.output0(O[2])
);

Mux m4 (
.sel1(s[1]),
.sel0(s[0]),
.input0(O[2]),
 .input1(SINR),
.output1(SINR),
.output0(O[3])
);

dflipflop d1 (
.D(O[0]),
.CLK(clk),
.RST(reset),
.Q(w[0])
);

dflipflop d2 (
.D(O[1]),
.CLK(clk),
.RST(reset),
.Q(w[1])
);

dflipflop d3 (
.D(O[2]),
.CLK(clk),
.RST(reset),
.Q(w[2])
);

dflipflop d4 (
.D(O[3]),
.CLK(clk),
.RST(reset),
.Q(w[3])
);

assign O = w;

endmodule

module clkdividor (
input wire clk_1hz,
input wire clk,
input wire rst
);

parameter n = 25;
parameter N = 2500;

reg [n-1:0] count;

reg clk_1s_reg;

always @(posedge clk_1hz or posedge rst) begin

if (rst)
count <= 0;
else if (count == N - 1) begin
clk_1s_reg <= ~clk_1s_reg;
count <= 0;
end else
count <= count + 1;
end
 assign clk_1hz = clk_1s_reg;

endmodule

module Mux (
input wire sel1,
input wire sel0,
input wire input0,
input wire input1,
output reg output1,
output reg output0
);

always @(sel1 or sel0 or input0 or input1) begin

case ({sel1, sel0})
2'b00: begin
output1 <= 1'b0;
output0 <= input0;
end
2'b01: begin
output1 <= 1'b0;
output0 <= input1;
end
2'b10: begin
output1 <= input0;
output0 <= input1;
end
2'b11: begin
output1 <= input1;
output0 <= 1'b0;
end
endcase
end

endmodule

module dflipflop (
input wire D,
input wire CLK,
input wire RST,
output reg Q
);

always @(posedge CLK or posedge RST) begin

if (RST)
Q <= 1'b0;
else
Q <= D;
end

endmodule
//////////////////////////////
*****************************************//////////////////
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:46:16 06/07/2023
// Design Name:
// Module Name: lab12
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module lab12 (
input wire clk,
input wire reset,
input wire data_in,
output reg sequence_detected
);

// State definitions
parameter S0 = 2'b00;
parameter S1 = 2'b01;
parameter S2 = 2'b10;
parameter S3 = 2'b11;

reg [1:0] state;

always @(posedge clk or posedge reset) begin

if (reset)
state <= S0;
else begin
case (state)
S0: begin
if (data_in)
state <= S1;
else
state <= S0;
end

S1: begin
if (data_in)
state <= S2;
else
state <= S0;
end

S2: begin
if (data_in)
state <= S3;
else
state <= S0;
end

S3: begin
if (data_in)
state <= S3;
else
 state <= S0;
end
endcase
end
end

always @(state) begin

sequence_detected <= (state == S3);
end

endmodule

module UniversalShiftRegister (
input wire clk,
input wire reset,
input wire shift,
input wire data_in,
output wire data_out
);

reg [7:0] shift_reg;

reg [2:0] shift_count;

always @(posedge clk or posedge reset) begin

if (reset)
shift_reg <= 8'b0;
else begin
if (shift)
shift_reg <= {shift_reg[6:0], data_in};
end
end

always @(posedge clk) begin

if (reset)
shift_count <= 3'b0;
else begin
if (shift)
shift_count <= shift_count + 1;
end
end

always @(*) begin

data_out = shift_reg[shift_count];
end

endmodule

module clk_dvr (
input wire clk_1s,
input wire clk,
input wire rst
);

parameter n = 25;
parameter N = 2500;

reg [n-1:0] count;

reg clk_1s_reg;
 always @(posedge clk_1s or posedge rst) begin
if (rst)
count <= 0;
else if (count == N - 1) begin
clk_1s_reg <= ~clk_1s_reg;
count <= 0;
end else
count <= count + 1;
end

assign clk_1s = clk_1s_reg;

endmodule
*********************************************///
**************************************************
In control systems, we study the principles, analysis, design, and implementation
of systems that govern the behavior of dynamic systems. Control systems are used to
manage and regulate the behavior of various devices, processes, and machines to
achieve desired outputs or performance.

Here are some of the key concepts and topics that are typically studied in control
systems:

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mathematical equations. Models can be in the form of differential equations,
transfer functions, state-space representations, or block diagrams.

System Response: Understanding how a system reacts to different inputs and

disturbances. This involves studying transient response (how a system responds to
sudden changes), steady-state response (how it behaves over time), and frequency
response (how it reacts to different frequencies of input signals).

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behavior. These include:

Open-loop control: A control system where the output does not influence the control
action. The control action is predetermined based on the input.
Closed-loop control (Feedback control): The output is compared to the desired
reference signal, and the control action is adjusted accordingly. This allows the
system to correct errors and maintain stability.
Proportional (P) control: The control action is proportional to the difference
between the desired setpoint and the actual output.
Integral (I) control: The control action is proportional to the accumulation of
past errors. It helps to eliminate steady-state errors.
Derivative (D) control: The control action is proportional to the rate of change of
the error. It helps to improve transient response.
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Nyquist plots are used for this purpose.

State-Space Analysis: Representing a control system in terms of state variables and

studying its behavior in the state-space domain.

Digital Control Systems: Studying control systems implemented using digital devices
like microcontrollers or digital signal processors.

Optimal Control: Techniques to optimize control signals to achieve the best

performance while considering constraints and objectives.

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Control systems find applications in various fields, including engineering,

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specific performance criteria and ensure stability and safety.