HDI

D ESIGN GUIDE
Blind, Buried, and
HIGH-DENSITY
INTERCONNECT

Microvias
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FOREWORD
Written by Happy Holden

Sierra Circuits has once again led the industry by introducing a

comprehensive HDI Design Guide. This is characteristic of their support
for printed circuit designers and electrical engineers. Like their excellent
PCB Stackup Designer tool that is available on the Internet (an Industry
FIRST), this design guide thoroughly explains the benefits of using high
density interconnects, in this case, microvias.

I have never read in one place such a thoroughly researched design

guide. There may be more complicated or more detailed HDI information
available (like my HDI HANDBOOK-at 681 pages), but not in such an easy
to read and understandable volume as this is. I hope you will use the
advice presented here to successfully implement HDI in your boards and
encourage others to download the design guide and use it also.

The “e-Book” format of this guide is also an important step towards

making this book useful, not just for the present, but, also, into the future.
HDI is a fast-moving technology, and in some respects combines the
elements of both “revolutionary” and “evolutionary” technology changes.
This format will allow the Editor, to update material as appropriate,
keeping it fresh and pertinent at the leading edge of the technology.

Integrated circuit technology will continue to drive those devices into ever
smaller and denser packages with increasing interconnection points. This
will continue to make HDI technologies more and more “main stream,”
or standard printed circuit design, fabrication and assembly elements.
Success in dealing with these issues will be critical to the success in the
market place for electronic products. This e-Book will help the reader get
the most out of HDI and make it work for you.

Copyright Sierra Circuits Inc., 2023

T able of Contents
1. OVERVIEW
1.1 What is HDI? ............................................................................................5
1.2 What is driving the increase preference for HDI PCBs?........................9
1.3 The cost of HDI......................................................................................10
1.4 What can go wrong?..............................................................................12

2. THE KEY TO HDI PCB DESIGN SUCCESS

2.1 The benefits of a planned approach......................................................13
2.2 Choose the right PCB material...............................................................14
2.3 Have a plan for your PCB stack-up and microvia structure .................18
2.3.1 HDI stack-up classes.....................................................................19
2.3.2 Stacked vs staggered vias............................................................23
2.4 Key considerations in your HDI PCB design strategy
- a checklist.............................................................................................25

3. SIGNAL INTEGRITY FOR HDI

3.1 Signal quality of one net.........................................................................28
3.2 Crosstalk noise.......................................................................................29
3.3 The constraints of controlled impedance.............................................32

4. MANUFACTURING FOR HDI

4.1 Layers and laminations..........................................................................34
4.2 Mechanical vs laser drill.........................................................................35
4.2.1 Laser drilled microvias..................................................................36
4.3 Hole fill process......................................................................................36
4.4 Drill-to-copper..........................................................................................37
4.5 Landless via technology.........................................................................38
4.6 Surface finishes......................................................................................40

5. BGA BREAKOUT STRATEGY

5.1 Example of how to breakout a .4mm BGA...........................................42
5.2 Example of how to breakout a .5mm BGA...........................................45

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6. MANUFACTURING TOLERANCE
6.1 Drilling tolerance.....................................................................................47
6.2 Annular ring tolerance.............................................................................48
6.3 Copper trace width and spacing tolerances..........................................48
6.4 Controlled impedance tolerances..........................................................49
6.5 Board-related tolerances........................................................................50
6.6 Copper thickness tolerances............................................................................51
6.7 Solder mask feature tolerances.......................................................................52

7. Sierra Circuits’ capabilities

7.1 Materials available at Sierra Circuits.....................................................54
7.2 Sierra Circuits’ PCB Stackup Designer online tool...............................54
7.3 PCB Stackup Designer tutorial...............................................................55
7.4 About Sierra Circuits...............................................................................57

Copyright Sierra Circuits Inc., 2023

 1
1. Overview

1.1 What is HDI?

High-Density Interconnect

• HDI is characterized by its high density of components and routing intercon-

nections.
• HDI uses microvias, blind and buried via/microvia techniques, as well as
built-up PCB laminations.
• Microvias have an aspect ratio of less than 1:1.
• HDI design reduces the overall cost by decreasing the number of layers and
size as compared to a standard technology PCB design.
• HDI offers a better electrical performance.

HDI stands for High-Density Interconnect. As the name suggests, an HDI PCB is characterized by
its high density of components and routing interconnections that use the latest PCB technologies.
An HDI design is by its very nature a high-performance design.

HDI design uses the latest advances in the PCB interconnection technology. Keeping in mind the
latest state of the art PCB technology, we can define the HDI PCBs as those printed circuit boards
that use some or all of these features: microvias, blind and buried via/microvia techniques, built-
up PCB laminations and high-signal performance considerations.

Copyright Sierra Circuits Inc., 2023

What is ‘high-density’?

Happen Holden told us, “The definition may vary, but experienced designers usually consider 120-
160 average pins per square inch to be ‘high-density’. The amount of density (or complexity) of a
printed circuit, Wd, as measured by the average length of traces per square inch of that board,
including all signal layers. The metric is inches per square inch. The PWB density was derived by
assuming an average of three electrical nodes per net and that the component lead was a node of
a net. The result was an equation that says the PWB density is β times the square root of the parts
per square inch times the average leads per part. β is 2.5 for the high analog/discreet region, 3.0
for the analog/digital region and 3.5 for the digital/ASIC region:

PWB Density (Wd) =β √([Cd] )×(Cc)

=β √([(parts per sq.in.)] )×(ave.leads per part)
Where:
Cd = component density = ave. parts per sq. inch for a design
Cc = component complexity = ave. leads per part
PWB Density (Wd) = β x Cc x (Cd)^.5

© Happy Holden

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 1 The table below shows the advantage of using HDI staggered microvias over
through-holes in terms of cost and pin density:

HDI became a thing in the 1990s as the consumer market started to ask for electronic products
capable of supporting new features and capabilities – which means additional components and
circuitry – while displaying smaller footprints and lower power consumption (typically measured in
terms of battery life). HDI improved the way components were mounted and connected using the
microvia technique. Until the late 1980s, most PCB manufacturers could only build through-holes
that pass all the way through the board and have an aspect ratio (the ratio of the board thickness
to the diameter of the drilled hole) from 6:1 to 20:1. Microvias have an aspect ratio of less than 1:1
and therefore perform with many times the thermal cycle life of the through-hole vias.

Aspect ratio of laser drilled microvias

- Ratio of laser microvia = C/B:1

- Most productive and cost-effective A/R is .75:1 or less

Where, A= Laser drill capture pad (top pad)

B= Drill diameter of laser microvia
C= Thickness of dielectric layer
D= Laser drill target pad (bottom pad)

Copyright Sierra Circuits Inc., 2023

 The chart below gives some aspect ratio guidelines:

Microvia A
Hole Maximum Dielectric Layer Thickness (mils)
Diameter

A/R =0.5 A/R =0.75 A/R =0.9 A/R =1

6.00 3.0 4.50 5.40 6.00

5.00 2.5 3.75 4.50 5.00

4.00 2.0 3.00 3.60 4.00

3.00 1.5 2.25 2.70 3.00

2.00 1.0 1.50 1.80 2.00

Microvias connect embedded capacitors and resistors within the layers of an HDI PCB. Reducing
the distance and the mass of the conductive material improves electrical performance in compact,
complex devices.

One of the key driving factors is to achieve more connections per area of the printed circuit board.
This results in a more compact, dense, and lower layer count PCBs.

Not only does it make the PCBs smaller, lighter, and thinner; but HDI PCBs provide a much
superior electrical performance, including:

• Better electrical performance and signal integrity

• Lower noise and crosstalk, and lower EMI/RFI
• Smaller size and weight
• Cost optimization: HDI design reduces the overall cost by decreasing the number
of layers and size as compared to a standard technology PCB design for the same
level of complexity.
• Reduced design time: HDI technology allows for more real estate on the board
which results in faster signal routing during the layout design stage.
• More reliable designs: Studies conducted by IPC and other industry organizations
have talked about superior reliability of small-blind vias over through-hole vias.
This is due to the fact that the via aspect ratio is less than 1:1 compared to through-
hole which has an aspect ratio greater than 6:1 that goes as high as 20:1.
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 1 1.2 What is driving the increase
preference for HDI PCBs?

HDI provides a smar ter solution.

• HDI offers high-pin count and high-density device packages.

• HDI means smaller PCB sizes and a reduced number of PCB layers.

HDI allows for dense component placement and more versatile routing in a PCB. The main benefit
of HDI is that it reduces drill-to-copper. Using blind and buried vias allows designers to avoid
denser areas of the board, which in turn means the denser circuitry is routed cleaner.

Compared with traditional PCBs, HDI PCBs have thinner trace widths and superior wiring density.
They achieve these advantages through the use of technologies such as buried vias, blind vias,
stacked, and staggered laser-drilled microvias.

Another note on microvias: Their extremely small pad size helps to boost channel routing width.
Layer reduction is possible since through-holes may be replaced with microvias, allowing signal
layers along with their corresponding reference planes to be eliminated. It’s the PCB version of
hitting two birds with one stone.

Sometimes, high-density can be a better option than a microelectronic board. Building a 6-layer
HDI board requires less time and money compared to a 4-layer microelectronic board.

PCB designers also cite the following reasons for the increased adoption of HDI:

• Complex and dense devices: High-pin count and high-density device packages such as ball grid
arrays (BGA), chip-scale packaging (CSP), wire-bond and flip chip BGAs, chip-on-board (COB), and
system-in-package (SiP) are leading factors. When a complex and dense device has a large pin
count and a very low pitch, it is almost impossible to design a PCB with a reasonable number of
layers and/or thickness using standard PCB technology. The solution? HDI!
• Compact PCBs: As everything gets smaller, faster and cheaper at an ever increasing rate, the
designers are faced with increasingly smaller PCB sizes and a reduced number of PCB layers. If
one were to use conventional non-HDI designs, many would require a large number of PCB layers.
HDI provides a smarter solution.
• Integrating several PCBs into a single PCB: With HDI, several existing PCBs can be integrated
into a single high-density PCB in a more efficient manner.

Copyright Sierra Circuits Inc., 2023

• Signal integrity discipline: As PCBs have incorporated circuits that require higher speed signal
transitions, faster rise/fall times, and higher clock rates, it requires even higher signal integrity
levels and electrical performance. These require a high degree of signal integrity discipline to
be implemented during the PCB design and manufacturing, which HDI provides. HDI inherently
provides a better signal integrity performance than non-HDI because all the stray capacitances and
inductances get reduced when using small vias. And because there are no stubs, the impedance
of microvias is nearer to the traces impedance. The stray capacitance of a normal via is much
higher, which causes greater discontinuity in impedance than a microvia does.

Making HDI work for you – The first step!

A good rule of thumb is to ask yourself, “Will HDI PCB technology solve a real problem and serve
a real purpose in my design?” You should know exactly why you need HDI PCB technology in your
PCB at the very beginning of the design process. We have provided some examples of when you
should consider HDI PCB technology. Whatever your reasons, it is imperative that you are very
clear about what these are from the very start!

1.3 The cost of HDI

What is the cost of a risky design?

• More laminations equal more cost.

• Yield is the paramount cost consideration.
• Your manufacturer might not get it right the first time.

It is true that more laminations equal more cost. However, when designing your
board, you should keep in mind that adding layer after layer and making holes
smaller and smaller as your circuit designs become more complex does not make
any sense and will eventually cost you more. Over the years, Sierra Circuits has seen
many PCB designers gambling on high via aspect ratios and tight hole-to-copper
clearance instead of turning to a blind-and-buried via architecture, which would
have been more effective. Why not choose to design your boards in an HDI manner,
achieve 8-mil hole-to-copper clearances, instead of 4 mils, with through-hole aspect
ratios that are 8:1, instead of 20:1, and use fewer layers?

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 1

The benefit of HDI: The green PCB on the left is a conventional 12-layer through-hole controlled imped-
ance design. The black PCB shows the benchmarked 8-layer HDI redesign, which saved 40% in surface
area and 33% in layer depth with the same function. © Copyright 2001 Westwood Associates.

HDI can make you save money when it comes to manufacturing. Once a job is quoted and accepted
by a PCB shop, the fabricator has to deliver the number of boards requested, even if they push the
edge of process tolerances. Let’s say you ordered 10 twelve-layer boards with 3-mil drill-to-copper
clearance. The manufacturer would probably have to produce 20 boards in order to just yield 10
that are acceptable. Perhaps the job would have to be run twice. And perhaps the temperature
cycling would cause 8 out of these 10 good boards to short during use. The PCB shop would
have to absorb the waste on this order but if you need another batch, you will be billed more to
compensate for the loss on the previous batch. You could think of going to another PCB shop, but
you know that it is unlikely that you would have time to start all over again. Inevitably, yield is the
paramount cost consideration in PCBs.

Do not make the mistake to believe that you can keep adding layers, making everything smaller,
and think that the manufacturer will find a way to produce your boards and get it right the first
time. This is when you are supposed to think strategically and concentrate on yield from the
beginning. If you focus on the lowest installed cost, at some level of circuit complexity, you will
have to carefully assess the cost of HDI construction versus not using HDI.

Happy Holden revealed, “The thing we like to tell people is that an optimized HDI board can cost
less than a through-hole board, and offer more reliability and higher electrical performance. But
it does not happen by accident. It takes a lot of skill and experience. We hear, ‘I don’t use HDI
because it costs too much.’ It only costs too much because the designer has to learn how to take
advantage of HDI. It can cost less or be the same, but it depends on the designer’s education.”

Rick Hartley, Principal Engineer at RHartley Enterprises:

The only disadvantage of HDI is a cost increase in the bare board. However that only
happens when layer count is not reduced. With proper planning, cost of an HDI board
can be the same or less than an all through-via board.

Copyright Sierra Circuits Inc., 2023

1.4 What can go wrong?

Before designing begins, figure out if you

require HDI, and how it will benefit you.
• Why do I need HDI?
• What materials should I use?
• Think about the testability of your board.

HDI as a forethought reduces your cost and gives you better electrical performance. HDI as an
afterthought increases your cost.

HDI designs require upfront planning. We often see designs where laser drills and blind vias have
been added at the last step. This is typical, because people do not necessarily want to design HDI.
They are designing a finer chip or they are putting more parts together, and they get the board
80% - 90% completed and they are via starved. They have run out of places for vias. The only way
to finish the design is to add hundreds of laser-drilled blind vias. That will certainly work, but that
is the worst-case-scenario in terms of cost. You are paying for HDI but you are not fully benefiting
from any of HDI’s advantages. HDI really requires that you plan for HDI design far before you start
to turn on the CAD system. In other words, what are my design rules? What are my materials? Do
I require HDI? What are the reasons why I require HDI? Is it for higher wiring density? Better signal
integrity and electrical performance? Smaller size?

Steve Watt, Manager of PCB Engineering at Zuken:

Understand the rules of your manufacturer and how that correlates to the intent of
your PCB design. Ensure that the DRCs that control your design tool are properly
aligned with the above to create the most producible design possible and cut down
on getting into a change loop with the manufacturer.

HDI testability: How to ensure success on your first HDI design

As a designer, the testability of your board should always be taken into consideration.
When you use blind and buried vias and you begin eliminating through-holes,
testability is even more crucial. So have test pads for your critical nets.

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Happy Holden advices that the first HDI board you should ever design should
be a test vehicle, where you test the functionality and guarantee testability,
reliability, signal integrity and power integrity.
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 2 2. The Key to HDI PCB Design Success
As a designer, the first step in the HDI design workflow is to determine whether or not you
need HDI. You should have an idea by looking at your schematic and your target board.

Once you determine that you require HDI, you need to look at the stack-up. Don’t use more
than three sequential layers unless there is absolutely no other solution. We recommend
that you use a good fanout strategy for complex ICs, like BGAs and QFNs – this will help you
reduce the number of sequential laminations if you plan your fanout strategy properly.
See section 5.

One of the PCB designers asked us, “can you guys give us suggestions for the stack-ups of
4-layer and 6-layer boards?”

Our design experts answered saying, “ there are three categories of PCBs - standard, advanced,
and microelectronics. When using a 3 mil trace, the board will fall into the advanced category.
While implementing a blind via, ensure that the aspect ratio of the laser via is met. If the board has
a 0.4 mm BGA component, you cannot use more than 5 mil laser via on pads. Hence, if you use 5 mil vias,
the dielectric between 1-2 should be 3.5 mil or less.”

Check whether or not you need controlled impedance. If the line length: (where is the rise-
time of the highest frequency component in the signal), you have a shortline and it is not necessary to
consider its transmission line effects, nor to design it as a controlled impedance line. But if the line length
, it then becomes necessary to consider the transmission line effects and to design such lines as
controlled impedance lines.

In this case, it is important that you understand the built-up layers copper characteristics to model the
controlled impedance traces on these layers. The Transmission Line Reflection Calculator illustrates the
reflected signals (ringing) at both source and load of a transmission line.

Built-up layers are like outer layers – they start with foil and get plated up. It is also possible
to have the built-up layer only on one side of the board if needed. Stacked vias have outer
plating step. Talk to your manufacturer to learn more.

2.1 The benefits of a planned approach

Plan ahead and avoid having to redesign
from scratch.
• A planned approach will result in a design that performs as
expected and is on budget.
• Planning ahead will speed up the design process.

There are no shortcuts when it comes to HDI design. High-density interconnect PCBs are more complex than
standard PCBs. It is, therefore, very important that you plan out your HDI design process and other
considerations well in advance. Warning: It is very difficult in HDI designs to implement major changes in
the PCB structure as an afterthought!

Copyright Sierra Circuits Inc., 2023

At Sierra Circuits, we have often seen how designers new to HDI design end up redesigning from
scratch after spending weeks on the first attempt. Often, their design becomes very expensive for
fabrication.

A well thought out approach, on the other hand, results in a design that not only performs as
expected, but is also on budget. Here are some key benefits to planning your HDI designs:

• Avoid costly design iterations: Once design strategies are made with a proper understanding
of budget and manufacturing cycle time, you will be able to avoid costly design iterations. Your
design will likely be more optimal in terms of electrical performance and you will have better
control over the manufacturing.

• Optimal Design: With a planned approach, even if you have had to add or reduce the number
of signal layers, it will not leave you with a stack-up structure so constrained that the design
never finishes, becomes suboptimal, or is difficult to manufacture. You will also have realistic
expectations and avoid unpleasant surprises for all the important design determinants, such as
the number of layers, lamination cycles, trace and space sizes, and via and pad sizes.
• Faster: Using a planned approach speeds up the design process significantly while also staying
in budget. It is our hope that our planned approach will give you insight into whether using HDI
design guidelines will reduce your layer count significantly, or if using HDI design is absolutely
necessary. It will also allow you to compare your options right at the beginning.

Sierra Circuits has a team of stack-up designers who are available for you to discuss your trade-
offs. We provide support to all our customers during the design stage. If you request a custom
stack-up, we offer the preliminary stack-up, which is 90% correct until the end of manufacturing
the board. Slight variations may occur due to impedance requirements.

2.2 Choose the right PCB material

Will your material meet your temperature
and electrical requirements?
• Is your high-speed material suitable for sequential laminations?
• Materials will affect the electrical performance of the signal traces.
• The dielectric loss plays a vital role in material selection.

Material selection is, of course, important for all PCB designs. It is especially
important for HDI PCB manufacturing because there are additional manufacturing
constraints that play a role. The goal is always to select the right material for
manufacturability that, at the same time, meets your temperature, and your
electrical requirements. Also, make sure that your high-speed material is also
suitable for your HDI design. They are many other factors that come into play
when selecting the proper materials for your design. 14
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 2 Proper material selection is important for the layout design since materials will affect
the electrical performance of the signal traces. The physical thickness of the material
is important when considering the aspect ratio of the microvia to be plated. The current
standard aspect ratio for a microvia is 0.75:1. (The microvia diameter should be larger
than the height of the material it is penetrating to the next adjacent layer.)

Minimum aspect ratio for microvias

For laser drilled holes, the maximum aspect ratio is 0.75:1, and for
mechanically drilled holes, it is 10:1. This depends on the drilled hole
thickness. If hole thickness is less than 100 mil, it is 10:1, and If it exceeds
200 mil, it will vary.

c/b=.75
c=press out thickness.

The PCB manufacturer makes sure your materials come in required thickness to achieve .75 aspect ratio.

Other material considerations are the maximum withstanding temperature, maximum frequency
of signals and coefficients of thermal expansion (CTE). The maximum temperature here refers to
that temperature which the PCB is required to withstand without affecting its mechanical integrity.
It is usually expressed in degrees Celsius. The maximum frequency refers to the highest frequency
that the electrical signals realized on the PCB are operating at. This is usually expressed in MHz or
GHz. Our engineering staff will ask you the fastest rise/fall time during the circuit operation and
help narrow down the selection of materials that would meet your requirements.

Along with these items, the dielectric constant of the material and the dielectric loss, or dissipation
factor, will also play vital roles in material selection.

Copyright Sierra Circuits Inc., 2023

If you choose a high-speed material, make sure it is suitable for sequential laminations.
When using high-speed materials like Rogers 3000, it is difficult to go through more
than one lamination, it is very hard to predict the material movement and make the
material really bond well. The material Sierra Circuits recommends for high-speed
HDI is Megtron, Isola I-speed, etc.

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 2 When you are designing your stack-up for HDI, know where your cores are
and know which ones are your prepreg layers so when you are doing your
controlled impedance structure you have an idea of what the possible variation
could be in the layer thickness – the distance of the dielectric from the signal layer
to the reference plane. There is no harm in using sequential laminations as long
as you understand the variations that could happen. If you pick the right
material with less glass weave and more resin, you can have more predictability
during press-out, which means better predictability in your impedance.

Our Material Selector tool will help you select the best material suitable for your
PCB design.

Atar Mittal, General Manager at Sierra Circuits

Don’t try to pick the materials that have been used for a long time because new
materials are coming out that address any previous issues taht the material may have
had.
There is no necessity to go for very expensive materials because your application may
not require it. There is a safety factor to take into account but not beyond a certain
point. You have to be pragmatic about this.

Dielectric thickness of glass styles:

Dielectric thicknesses are dependent on prepreg glass styles and their press-out.

Press Out Thicknesses vary from material to

Glass Styles
material

Nanya NP175 Isola 370HR Nelco 4013

106 1.7 2 2

1080 2.8 3.1 3.1

2113 3.8 3.7 3.7

2216 4.1 4.9 4.8

7628 7.1 -- --

Copyright Sierra Circuits Inc., 2023

2.3 Have a plan for your PCB stack-up
and microvia structure
The microvia structure affects the number of
lamination cycles and therefore impacts the
manufacturing process and cost.
• The best practice for a balanced structure is to have an even number of plane
and signal layers.
• Know the process steps associated with the stack-up so you can control cost
and yield.
• Should you use stacked or staggered microvias?

The total number of layers of your final HDI PCB is determined by BGA
(or the highest pin count device), signals break-out, the number of signal TIP:
layers, as well as the number of power and ground layers. The number Answer the following
of power and ground layers can be determined by taking into account the questions before you
number of grounds, the number of different major voltages in the circuit, start working on your
as well as signal integrity/controlled impedance requirements. next project: Are you
meeting the design
The sequence in which the layers are put together (signal, power, guidelines for microvia
ground, etc.) is another factor that affects signal performance and aspect ratio? Are you
allows for a balanced PCB structure. It is always good practice to order stacking or staggering
your microvias?
the layers in a balanced manner.
You should have the number of plane and signal layers both odd or both even (both
even is the best for a balanced structure). They should also be symmetrically placed.

For instance, a designer had a query asymmetrical stack ups - “ For a PCB
with built up area on one side, should I still have a 3 mil thick dielectric on
the other side, or can that be ignored?

Our expert advised- “No, you should have a 3 mil thick dielectric to prevent it
from warping. Even though there is no drill on those layers, the stackup
should be symmetrical.”
Manufacturability of HDI design primarily has to do with via structures.

Microvia structures can have a big impact on the manufacturing process since they
directly affect the number of lamination cycles. The more variations you have of
layers where microvias start and stop at, the more number of sequential laminations
are needed for the PCB manufacturing. Any layer on which a microvia starts or stops at
requires a sub-construction, and each sub-construction will require an extra
lamination cycle. (The lamination process is defined as pressing a set of copper layers
with uncured dielectrics in between two adjacent copper layers under heat and pressure

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to form a multilayer PCB laminate).

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 2 HDI stack-up planning block diagram:

Our stackup designer tool was created with this in mind.

Stack-up architecture:

In conventional multilayer boards, your design choices depend on the number of signal layers you
require. HDI offers a larger variety of design choices. Choose from blind and buried, sequential
build-up, or stacked and staggered, as well as many other design choices. Of course, HDI does
not require complex architectures. One of the most common mistakes designers make is creating
architectures that are unnecessarily complex.

2.3.1 HDI stack-up classes

0-N-0 STACK-UP
There are different stack-up classes for HDI
boards. The first option is a single lamination
built using laser drills. This stack-up class is a
no-brainer in terms of utilizing microvias in the
least expensive way possible: Using only one
lamination. When you use a laser drill, you ben-
efit from a smaller pad and via size. This can
help ease some of the design restrictions and
reduce your design time.
The laser via is connected to the through-hole.

Copyright Sierra Circuits Inc., 2023

Going over the possible structures, it is important to know the process steps associated with the
stack-up. Additional process steps mean more cost and more yield loss.
N represents the number of layers in the first or base lamination (or core lamination) and 0 tells
that there is no sequential lamination steps and no extra dielectric and copper layers are added.

In this 1-N-1 type of stack-up, the ‘1’ represents one sequential lamination on either side of the
core. One sequential lamination adds two copper layers for a total of N+2 layers. This stack-up
does not feature stacked vias. There is one extra lamination and no stacking of the vias. The bur-
ied via has been mechanically-drilled. There is no need to use a conductive fill for the via. It will
naturally fill with the dielectric material. The second lamination adds the top and bottom layers.
Then, we finish up with a final mechanical drill. The pcb manufacturer plans the right amount of
prepreg between layer one and two so the resin flows into the buried via.

TIP:
1-N-1 WITH LASER MICROVIAS AND Consider whether you need a fi-
MECANICAL BURIED CORE VIA nal mechanical drill. You can get
the same connections with the
Step 8 laser drill and the buried me-
Step 7 Step 6
chanical. This saves an extra drill
Step 4 cycle and saves the manufactur-
er from dealing with the registra-
tion of the mechanical drill and
the laser drill.
Step 1 Step 5

Step 3

Step 2

Building this next stack-up takes an additional two laminations for a total of
three laminations:

2-N-2 WITH STAGGERED MICROVIAS AND BURIED CORE VIA

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 2 The manufacturing steps are as follows:

1-N-1 2-N-2
1. The core is laminated. (The core can be 1. The core is laminated. (The core can be only
only two layers, so no lamination.) two layers, so no lamination.)
2. The core is mechanically drilled. 2. The core is mechanically drilled.
3. The laser drilled vias are formed. 3. The laser drilled vias are formed.
4. The mechanical drill is plated. 4. The mechanical drill is plated.
5. Layer two is imaged/etched. 5. Layer two is imaged/etched.
6. The sequential lamination adds two ad- 6. The sequential lamination adds two addi-
ditional layers. tional layers. (The mechanical drill is now a
7. (The mechanical drill is now a buried buried via.)
via.) 7. The laser drilled vias are formed.
8. The laser drilled vias are formed. 8. Lamination of another 2 layers.
9. The final through-hole via is formed. 9. Laser drill.
10. The laser drill and the through-holes 10. Plating the laser drill.
are plated. 11. Image and etch.
12. Back to lamination.

The manufacturer will be going back to the laser drill and plating process twice for the laser drills,
once for the buried mechanical drill, and then a second time for the through-hole mechanical
drills. Each lamination cycle can be done in one day. So with three laminations, this can only be
done in three days. Plus an additional day for outer layer processing. Four days in total.

Here are some additional types of stack-ups:

• 0-N-0 with laser microvias

In this stack-up, the manufacturing steps are as follows:

1. The core is laminated.
2. The core is mechanically drilled.
3. The laser drilled vias are formed.

• 1-N-1 with microvia stacked on top of buried and filled core via

This stack-up is similar to the one above, except in this case there are also laser microvias stacked
on top of buried core vias. This requires that the buried core vias should be filled and plated be-
fore adding the additional two layers. And the microvias need to be plated with copper and pla-
narized flat.

• 2-N-2 with stacked microvias and buried core via

In a 2-N-2 stack-up, the ‘2’ represents two sequential laminations.

As stated above, one sequential lamination adds two copper layers, so two sequential laminations
add four copper layers for a total of N+4 layers. Again, there are no stacked vias.

Copyright Sierra Circuits Inc., 2023

A more complicated structure is called a 3-N-3. At this point, material selection becomes critical.
Is your material robust enough to handle four lamination cycles, plus a reflow cycle in assembly,
plus a possible rework that you might have afterwards?

Let’s now talk about the cost.

On the left of this chart, you have HDI stack-up classes, and on the right, you have the associated
cost. The more sequential laminations, the higher the cost. The most expensive stack-up class is
three sequential laminations. This includes microvias stacked on top of each other, which is nec-
essary when you are breaking out of a tight pitch BGA, like .3 mm. Second in the stack-up class in
terms of cost are using a non-conductive hole through process.

Getting design help from the PCB manufacturer: Too much of a good thing?

Leaning on your PCB fabricator too much has its pros and cons.
Most PCB fabricators have fleshed out their engineering support to be able to
provide basic feedback on your HDI PCB layout. This is great information, but
only up to a certain level. A PCB fabricator will seldom take into account your de-
cision-making criteria when looking at your circuit schematics or
BOM. If you want a strict review of your layout, there is no need to waste your
time waiting for a response from the PCB fabricator’s engineer. There are on-
line web tools available that will provide this service quickly and with great detail.
(Freedfm.com and BetterDFM.com)

Try our Better DFM tool to check for the manufacturability of your PCB design.

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 2 When you are placing your vias, you need to know where they are going –
what layer are they starting from and what layer are they stopping at? Know-
ing where your drilled holes are is the key to keeping your cost down. Think
about the number of times the board has to go through mechanical and laser
drill versus just going to laser drill. Most designers think they need mechani-
cal drilling for the power of the pins of the BGA but this is not necessarily true.
You do not want an HDI design where right at the center of the BGA there is
a through-hole. A through-hole has to align with the laser drilled vias, which
makes it harder to manufacture, you might have a lower yield, and you are
just adding an extra through-hole process, which you probably did not need
at first. The manufacturer has to align mechanical versus laser drilled holes.

Rick Hartley, Principal Engineer at RHartley Enter-

prises:
TIP: When part of the power delivery system, they [vias] help create very low
power bus impedance. Vias are one of the largest inductance features in
The manufacturere power delivery, causing large Ldi/dt switching noise. HDI vias, especially
should have a vision when placed properly, have much lower inductance.
drill system for this
HDI vias create much less of the ‘Swiss Cheese’ effect in the planes,
to work.
also helping to lower plane inductance. This also lowers switching noise
in the power bus.
When placed on signal lines, they eliminate via stubs. Via stubs, at GHz
frequencies, cause signal integrity issues.”

2.3.2 Stacked vs staggered vias

Staggered vias essentially mean less process steps. The manufacturer does not have to fill the
laser-drilled vias with copper because the second laser drill does not land on the first laser drill.
Filling or plating a microvia shut usually happens in a special plating tank designed with chemistry
that plates the laser-drilled microvia from the bottom of the via to the top of the via, until the
hole is completely filled. Plating a laser-drilled microvia shut adds time and cost to the process
and is only needed when you are stacking on an inner layer or if you have a via-in-pad on the
outer layer. If the second laser-drilled via is staggered or offset, there is no need to copper plate
shut. If you are staggering your laser-drilled microvias, it is important to know what spacing your
manufacturer requires between the laser drills.

One of the design engineers questioned us- “Can microvias be stacked for via-in-pad?”

We suggested saying- “Yes! Via-in-pad can be stacked. We fill those stacked vias. The vias will be
filled with copper if you are stacking on a laser drill. However, if it is on a mechanical drill, vias will
be filled with non-conductive material”.

Copyright Sierra Circuits Inc., 2023

 Randy Clemmons, PCB Designer CID+ at San Diego PCB:
A board with staggered vias is more difficult and time consuming to design. It is easier
and faster to design a board using stacked vias. Good CAD tools have hot spot snap
features, which simplify precise positioning stacked vias during the design process.

STAGGERED VS. STACKED MICROVIAS

STAGGERED STACKED
-NO COPPER FILL REQUIRED -HOLE FILL REQUIRED
-NO EXTRA IMAGING STEP -PLANARIZATION REQUIRED
-EXTRA IMAGING STEP

What is the laser drill accuracy? It is very safe to assume it is +/- 1 mil accuracy. Usually, in a stag-
gered microvia formation, the diameters of both operate and lower microvias are the same. The
key parameter that decides whether the staggering is possible or not, without the lower microvia
needing to be filled, is the dimension E, the vertical separation between the central access of the
two microvias. For staggering to be viable, the value of E must be greater than the microvia diam-
eter.

Sometimes, the space restrictions are so tight that your only option is a stacked via. Here are some
precautions for stacked vias: Stacking on a buried mechanical drill is known to be a bad structure
where failure can occur. We have seen cracks at this connection. We have not seen cracks on
stacked laser-drilled microvias.

The final point is: If you have a buried via, it is better to offset your laser drills from the buried
mechanical drills and then stack from that point onwards. This gives you the most
reliable con-nection.

Randy Clemmons, PCB Designer CID+ at San Diego

PCB:
When choosing between staggered and stacked vias, there are
fabrication processes and design costs, as well as reliability and
signal integrity issues to consider. If the board is a low volume test
board, like an IC test board which will be used to test millions of ICs,
then signal integrity and reliability will be a priority. If the board is a
consumable commercial product, then lower fabrication cost will be
given a higher priority than design cost. 24
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 3 2.4 Key considerations in your HDI PCB
design strategy – a checklist
Via diameter, pad diameter, trace width and
space, and aspect ratio.

• Think about the assembly process when deciding your BGA pad size.
• The trace width and via sizes will determine an optimum number of
signal layers.
• Have your aspect ratios right for the plating process.

Take into account a complete view of the design before deciding the via and pad sizes you are
implementing, so you don’t paint yourself into a corner. The primary consideration at this point
in the planning stage is routing density. Routing density is determined by the high-pin count fine
pitch device on the board, for example, a BGA. BGA pin count and BGA pitch are both important
parameters that affect routing density.

When you are deciding your BGA pad size, do take into account the assembly process and the PCB
design rules that you are following. For example, pad to pad spacing and soldermask web are two
critical design parameters. If you are choosing a via-in-pad approach, your BGA pad size needs to
account for the size of the laser and mechanically drilled microvias while keeping the correct pad
size required by the BGA assembly process.

The BGA pad size and the microvia size should be determined along with the trace width and spac-
ing. Depending on the pitch of your BGA (say for example, 0.8 mm), the trace width and the via siz-
es will determine an optimum number of signal layers. At Sierra Circuits, we have created an HDI
Design Planning Tool (with requisite algorithms) that assists our engineering staff in specifying an
optimum via size, pad size, and trace width depending upon the desired number of signal layers.

You can see what an important role via sizes, pad sizes, and trace width and space play in the
overall stack-up structure.

For example, if you want to use a BGA of 0.4 mm pitch with a via-in-pad.
• A 9 mil pad is recommended with a minimum finished hole size of 4 mil for laser.
• Dielectric thickness should be less than 3 mils between layers 1 and 2, or 3 and 4. (3.5 mil is
suggested by IPC)
• If you don’t have any impedance requirement, then you can reduce the dielectric thickness
between the start layer and the end layer to less than 3 mil.

When you design an HDI board, make sure that you have your aspect ratios right for the plating
process. To achieve acceptable copper plating, the plating solutions have to properly fill the hole.
If the hole sizes are too small compared with the thickness of the PCB, you might get unsatisfac-
tory plating.

Copyright Sierra Circuits Inc., 2023

3. Signal Integrity for HDI
Eric Bogatin, Signal Integrity Evangelist at Teledyne Lecroy:
In HDI boards, signal integrity issues are just as important to deal with as in traditional
through-hole boards.

By reducing the size and offering the opportunity for smaller current loops on critical nets, HDI
improves signal integrity. HDI can indeed provide improvements and alternatives to issues like noise,
crosstalk, and electro-magnetic interference (EMI). Because they are smaller, shorter, and have almost
ten times less electrical parasitics than through-holes, microvias offer a decreased inductance and
capacitance, which results in helping reducing switching and circuit noise, signal reflections, and
crosstalk.

You can use the Via Impedance Calculator to calculate the via capacitance, inductance, and imped-ance.

Carefully select your materials for HDI as they have an impact on the signal integrity performance.

In a paper entitled HDI’s Beneficial Influence On High-Frequency Signal Integrity, Happy Holden
explained that due to the physical structure of microvias, there is a reduction in switching noise. This is
attributable to the decreased inductance and capacitance of the via as its physical size becomes
smaller and shorter. A microvia will have nearly one-tenth the electrical parasitics of a through-hole.
Another advantage of using microvia technology for creating interconnects is a re-duction in signal
reflections and crosstalk between traces. The corresponding increase in routabil-ity area also allows
designers to place traces further apart to reduce crosstalk.

Four categories of noise describe the various effects:

1. Signal quality of one net and its return path (ringing due to reflections)
2. Crosstalk between two or more nets (noise pulses due to switching on neighboring lines)

Signal Switching
HDI Features Cross Talk EMI
Quality Noise
Short interconnect lengths x x

Low dielectric constant x x

Small vias and small features x x

Vias in pads x

Fine lines and thin dielectric x x x

Support for fine-pitch components x x 26

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 3 Each of the four categories named above has specific causes. By identifying the
cause in each family of problems, design- and technology-based solutions can be
identified and implemented.

Signal quality of one net: reflectioins and

distortions from impedance discontinuites in
the signal or return path

Cross talk between multiple nets: with ideal

return paths, and without (SSO)

Rail collapse in the power and ground distribution

network

EMI from a component or the system

Noise can come from many sources in the board layout, such as:
• Changes in trace width
• Plane splits
• Cutouts in Power/Ground planes
• Via antipads
• Insufficient plane capabilities
• Excessive stubs, branched or bifurcated traces
• Component lead frames
• Improper impedance matching and termination networks
• Coupling between signals
• Varying loads and logic families

Copyright Sierra Circuits Inc., 2023

3.1 Signal quality of one net

A smaller substrate and improved signal integrity.

• Shorter interconnect lengths, smaller vias, and thinner dielectrics of

lower dielectric constant materials improve signal integrity.
• The signal return path is just as important as the signal path.

HDI is a fabrication technology of miniaturization that has two main benefits: A smaller substrate
and improved signal integrity. The smaller substrate is due to the shorter interconnect length,
smaller vias, and thinner dielectrics of lower dielectric constant materials. These things also im-
prove the signal integrity.

With HDI, devices can be brought so close together (both from a surface point of view and using
the secondary or backside of the interconnect) that the signal may not need to use transmission
lines. Interconnects with a time delay shorter than about 20 percent of the rise time of the signal
may not need to use transmission lines. The interconnect length is given by:

LENGTH < 20% of (rt X C) / Dk^.5

Where:
rt = signal rise time in nsec
c = the speed of light in air~11.8 inches per nsec
Dk = dielectric constant of the material

The signal return path is just as important as the signal path, and exists whether you
provided for it or not. The signal return path contributes to the inductance, capaci-
tance, and resistance experienced by the signal. The signal return current will seek
the path of minimum energy, which has the least impedance. For low frequencies, this
path will have the least resistance; for high frequencies, the path will minimize the cur-
rent loop. At higher frequencies, inductance dominates over resistance, so the return
path follows the signal path even though it meets higher resistance.
The low dielectric constant results from the use of many new HDI materials. Many
of these materials are not glass-reinforced and thus have lower dielectric constants
than glass-reinforced laminates. Many of the dielectrics are liquid such as the high-
Tg epoxy or polyimide, or the photodielectric resins (PDR). Some materials are thin,
vacuum-laminated dielectrics with high thermo-plastics contents. However, all ma-
terials are uniformly thin — this contributes to reductions in wiring delays and
reduction in noise. Several of these new materials and their electrical charac-
teristics are shown in the table below. 28
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 3 Typical HDI
Materials
Dielectic
Cosntant
Dissipation
Factor
ISOLA 370HR 3.92 0.015 - 0.025

Isola I-speed 3.63 0.0071

Isola I -Tera MT40 3.45 0.0031

Nelco N4800-20 3.76 0.0075

Nelco - 4000-13 (low 3.9 - 3.7 0.009

Dk and loss)
NanYa CCL FR-4 4.3 0.01 - .016
NP170
Rogers R040003 3.4 0.0027
(low Dk and loss)
Rogers R04350 3.5 0.004
(low Dk and loss)

3.2 Crosstalk noise

Crosstalk in HDI substrates is reduced by the

shor ter coupled lengths and by the lower dielectric
constant by as much as 50 percent.

• Reduce crosstalk in HDI substrates by using lower Dk materials.

• The lower dielectric constant of the HDI material system may allow a board to
shrink up to 28 percent.
• The thinner the distance to the reference plane, the lower the near-end cross-
talk will be.

Copyright Sierra Circuits Inc., 2023

HDI miniaturization provides shorter interconnect lengths, and if the lower dielectric constant
material is used, then crosstalk in HDI substrates is reduced. Eric Bogatin provides the following
example: “A typical line-width in HDI technology is 3 mils (75 microns). The figure below shows the
characteristic impedances of 3-mil-wide traces for various dielectric thicknesses.

The dielectric thickness will be less

for a lower dielectric constant. This
means a lower dielectric constant ma-
terial system will either result in less
crosstalk for the same spacing, or the
traces can be moved closer together
and have the same amount of cross-
talk.”

Bogatin continues, “The variation in

the near-end crosstalk coefficient with
separation for two 50-ohm microstrip
traces is shown [below].”

“In the two cases studied, the line-width was 3 mils, and the dielectric thickness
was adjusted so that for the two different dielectric constants, the line imped-
ance was the same. From these curves, it can be seen that if the routing pitch
is crosstalk constrained, just the lower dielectric constant of the HDI material
system may allow a board to shrink up to 28 percent.

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 3
For coupled lengths less than the saturation length, the magnitude of the
near-end voltage noise will scale with length. The saturation length will de-
pend on the rise time. For a rise time of 1 nanosecond, the saturation length
with an effective dielectric constant of 2.5 is about 7.6 inches, which would
include many of the traces in a small card application. The relative coupled
near-end noise would be given by:”

Crosstalk in HDI substrates is reduced by the shorter coupled lengths and by the low-
er dielectric constant by as much as 50 percent. Shorter trace lengths will radiate less,
and traces with thinner dielectric will radiate less. The example below shows that the
shorter the coupled length, the less the mutual inductance (Lm), and the thinner the
traces, the less the mutual capacitance (Cm).

Moreover, the thinner the distance to the reference plane, the lower the near-end crosstalk will
be, or the same crosstalk for a longer coupled length. With length reductions of 2x and dielectric
thickness reductions of 2x over conventional boards, the radiated field from HDI signal loops
might be reduced by as much as 4x, which is 12 dB.

Copyright Sierra Circuits Inc., 2023

 Eric Bogatin, Signal Integrity Evangelist at Teledyne Lecroy:
If the entire board is HDI, rather than just a few outer layer, controlling the return path can be a
bigger challenge than in through-hole boards.
You have to pay attention to the same issues in HDI substrates:
1. Providing a continuous return path
2. Engineering controlled impedance interconnects
3. Routing in a linear, daisy chain path with minimal stub lengths
4. Managing reflection noise with terminations
5. Controlling via to via crosstalk by return path control
6. Using low inductance capacitors connected to the IC pins
In conjunction with a through-hole core, HDI interconnects can be incredibly valuable.

3.3 The constraints of controlled impedance

Know where to put your impedances.

• Make sure your manufacturer knows how to control the tolerance

of a 3.5 or 3-mil trace.
• Use the correct thicknesses for the dielectrics between the
signal layers and the reference planes.

Controlled impedance for HDI has some additional issues. HDI has thinner dielec-
trics than traditional boards, so if you are looking for a traditional 50-ohm sin-
gle-ended or 100-ohm differential pair, the thinner dielectrics will require less wide
traces. That is why it is possible to have a higher density of interconnections in an
HDI board. You can design with 5-mil trace and space, but it is a lot better if you are
using 3.5-mil trace and space, as that matches the 3 or 4-mil dielectrics on the build-
up. As such, it is important that the fabricator knows how to control the tolerance of
a 3.5 or 3-mil trace, in order to meet that characteristic impedance.

Also, spacing is more critical than the trace width. Even if you cannot have a trace
width of 3.5 mil, try to keep a 3.5 mil spacing between the conductors. The spacing
between the traces on the inner layer depends on the thickness of the copper.

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 4 In order to get a higher impedance, you must have:
- Thinner traces
- Thicker dielectrics
- Less copper
- Lower dielectric constant (Dk)
- More space in between differential pairs

In order to get a lower impedance, you must have:

- Thicker traces
- Less dielectrics
- More copper
- Higher dielectric constant (Dk)
- Less space in between differential pairs

When you are trying to design appropriated trace widths for controlled impedance lines, it is im-
portant that you use the correct thicknesses for the dielectrics between the signal layers and the
reference planes. The dielectric thickness to be taken is what is called the press-out thickness.

Another challenge in HDI technology is that you have to use the correct thickness of the copper
layers in the built-up layers resulting from sequential lamination. Pay attention or things could go
wrong.

The base thickness of the material is found on the material data sheets or is available from the
laminate manufacturers. PCB manufacturers calculate the final press-out thicknesses that they
expect from the prepreg, which depends on the amount of resin in the prepreg, the amount of the
copper area percentage, and the thickness of the adjoining copper layers. PCB manufacturers cal-
culate the copper area percentage from the CAD files that you sent. Therefore, they do not follow
the generic thickness specified on the data sheets, they use the calculated press-out thicknesses
for impedance modeling, which will change from design to design. This will require small adjust-
ments in the trace widths and spacing of the controlled impedance traces. If they cannot meet the
impedance requirement that you are looking for with the dielectric thicknesses or material types
you have selected, they will suggest an alternative dielectric thickness or PCB material.

Randy Clemmons, PCB Designer CID+ at San Diego PCB:

Maintaining a controlled impedance path from the signal source to the load destination is
easier using stacked vias. Staggered vias create additional discontinuities and therefore may
be less desirable to use in ultra high-speed designs, like 10 Gbit or higher.

Copyright Sierra Circuits Inc., 2023

4. Manufacturing for HDI

4.1 Layer and laminations

Think smar t and reduce your cost.

• Have you planned your layer sequencing for reduced EMI?

• What is the total number of sequential laminations?
• And have you minimized your laminations?

When you are designing an HDI circuit board, there are many things to consider. The first thing
you need to consider regarding the manufacturing process is the cost. What will make your HDI
Board more expensive by accident? You want to avoid inadvertently increasing the cost of your
HDI design by using a set of rules that are the easiest to manufacture. The first thing to
understand is the number of laminations that your design requires because it will add
to your cycle time and therefore cost. Understand how many sequential laminations
you are designing for and then optimize. Try to get the least as possible.

In a traditional through-hole design, a lot of designers surround their signal layers

with power and ground planes, but then they end up with a lot of layers. In HDI,
this is a bad practice. Use mixed planes instead if there are signals that you need to
protect with power and ground planes. In this manner, you are also shortening your
signal path which inherently increases signal integrity and reduces crosstalk.

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 4 4.2 Mechanical vs laser drill

Drilling is the huge cost driver.

• The use of laser-drilled vias will decrease cost and cycle time.
• Define your laser drill size in proportion to the finished press-out
thickness.

It is important to know what the pros and cons of mechanical versus laser drilling are. Let’s start
with the mechanical drilling. This chart shows the reasons why:

DRILLING COST DRIVERS

-HOLE SIZE
-DRILL COST
-STACK HEIGHT
-FEED and SPEED
-PECKING
-EQUIPMENT SPEED REQUIRED
-YIELDS
-NUMBER OF DRILL FILES

To name a few, there is the cost of the drill bit, the time it takes to drill mechanical holes, and the
quality of the drill. On the right side is the cost index. A 6-mil drill is much more expensive when
compared to a 10-mil drill. What can make this process even more complex is the use of hybrid
materials. For hybrid materials, each material requires a different drill cycle and plasma cycle.
Bottom line, if you have the opportunity to reduce or eliminate mechanically-drilled vias and use
laser-drilled microvias instead, you could save a tremendous direct cost for yield.

Strangely enough, designers typically seem to want to add more vias to protect their critical traces.
However, to decrease cost and cycle time, instead of through-hole vias, use laser-drilled vias in
your modeling. Laser-drilled vias do not add much cost. One laser drill costs the same as 10,000
laser drills.

Copyright Sierra Circuits Inc., 2023

4.2.1 Laser drilled microvias
Here is the basic make-up of a laser-drilled microvia. The critical dimensions are the pad size, the
laser drill size, and the press-out thickness of the dielectric. You must define your laser drill size
in proportion to the finished press-out thickness in order to properly plate the via. Laser drill di-
mensions can get very small. But remember, they are only going from one layer to the next. Many
fabricators can laser a 2-mil hole but plating the 2-mil hole becomes problematic because of the
aspect ratio of the thickness due to the drill diameter of the hole.

LASER-DRILLED MICROVIAS
A
A = LASER DRILL CAPTURE PAD (TOP PAD)
B
B = DRILL DIAMETER OF LASER MICROVIA
C = THICKNESS OF DIELECTRIC LAYER
D = LASER DRILL TARGET PAD (BOTTOM PAD)
C

4.3 Hole fill process

Conductive or non-conductive hole fill process?

• A hole fill is to help assembly form a good solder joint.

The next cost factor to consider is choosing between a conductive or non-conductive

hole fill process. Do you have vias underneath a surface-mount component that is
required to be filled and capped or plated over? It is costly because it requires two
plating steps and two drill steps. We drill holes that will be filled separately from the
regular through-holes on the board and any extra steps mean extra cost. In this case,
the manufacturer is going back to the process twice, which costs in terms of time and
dollars, drilling and plating.

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 4 The final objective of a hole fill is to help assembly form a good solder joint. And it
works great for that. Just be aware of the added cost and time when it comes with
this. If you have a choice between offset laser-drilled microvias and via-in-pads, I
would choose the laser-drilled microvias over the mechanical drill.

Sierra Circuits can plate the laser drills and the through-hole mechanical drills at
the same time. And not only is via-in-pad design another step in the process, it
also challenges the manufacture registration system. If the via-in-pad is imple-
mented with the through-hole mechanical drill instead of a laser drill, there is an
extra step with a non-conductive fill process. Using a non-conductive fill is more
expensive than plating the laser-drilled via shut.

Dog bone structure can be used when there is enough spacing between the pads
(when you don’t want to use any via-in-pad).

4.4 Drill-to-copper
Drill-to-copper only matters on inner layers. Drill to copper is the distance between the edge of
your drilled hole and the next copper feature on your inner layers.

The software design tools do not check for drill-to-copper. If you provide enough annular ring, it
does not mean that you cannot have any drill-to-copper issues. PCB materials move: When you
laminate a core might shift one way and another core might shift another way. If this happens, it
might hit the copper. Another possibility is that copper grows over time inside the circuit board
along the glass weave of the dielectric – it is called CAF, which stands for conductive anodic fila-
ments. The copper might grow enough to touch the hole and cause the board to be unreliable.
CAF does not usually happen with laser drilling but it does with mechanical drilling.

Copyright Sierra Circuits Inc., 2023

If you use mechanical drills along with your laser drills, the first thing your manufacturer should
check for the registration of the mechanical drills to the laser drills, which means more spacing is
needed for drill-to-copper. If you do not use mechanical drills, the yield will be higher. With laser
drills, drill-to-copper is not a problem because the manufacturer can easily laser drilled vias more
accurately than mechanically drilled vias.

Drill-to-Coppper

4.5 Landless via technology

Laser drilling makes it possible to have no

pad at all!
• More space to route your traces.
• Landless via technology helps on noise reduction
and signal integrity.
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 4
HDI is all about shrinking the design and pad sizes, which take a lot of space.
The reason why designers tend to put big pads is because they want big
annular rings to avoid breakouts. If you are allowed to breakout, you can
minimize your annular ring and therefore have more space to route your
traces.
As per IPC, a class-2 board
requires:
• A minimum annular ring of 3 mil
for laser drilled vias
• A minimum annular ring of 5 mil
for mechanical drilled vias
• A minimum annular ring of 8 mil
for through-hole components
• 10 mil drill to copper on the
inner layer
Laser drilling can reduce the annular ring because it is very accurate whether
mechanical drilling might be a little off due to less control. In fact, it is even
possible to not have any pad at all for laser drilling – this is what is called a
landless via technology.
Happy Holden’s experience:

“Landless vias are a little known se-

cret of some of the world’s largest
OEMs like IBM, Hewlett-Packard,
NEC and Fujitsu.

1. We used it a lot at Hewlett-Packard

after learning it from our Japanese
partner and testing the reliability. We
found it to be at least 10 times more
reliable that normal through-holes
and 20 times more on high-aspect
through-holes. So it is MUCH more
reliable than normal through-holes
and the same as landed microvias.
But we are talking about surface vias
(blind) not buried vias. This is shown
in the PC Handbook, 7th ED pp-1307-
Chapter on Via Reliability.

2. It provides for a much higher routing density on HDI boards 2X-4X, especially for bus routing
where the vias can be ‘invisible’ (that is, the via is the same diameter as the trace width – either 100
microns, 75 microns or 50 microns).

3. It has nearly 1/10 the inductance of a through-hole, which helps on noise reduction and signal
integrity.

4. To fabricate landless vias, no new processes or equipment are required, just changes to the art-
work in tooling.”

Copyright Sierra Circuits Inc., 2023

4.6 Surface finishes

Choosing the right surface finish is critical in HDI.

• When it comes to HDI, you should go with ENIG or ENEPIG.

• Get the typical thicknesses for immersion and soft gold.

Soft gold is used a lot for wire bonding – ENEPIG can also be a process for wire bonding. Make
sure that you can get non-contaminated surface finishes. In a HDI board where the traces might
be smaller, there is no reason to use HASL, which is very rough and not smooth enough to put on
BGAs. HASL is a very aggressive process which weakens the strength of the copper. When a trace
and space gets very tight, it is better to use ENIG or ENEPIG rather than a hard or soft gold which is
electrolytic. You need to use an electrolytic-less gold. Do not use HAL because it is choppy. When
you put the component down, it is not flat but tilting. So you cannot get a good connection.
Do not ask for more gold than what is needed. When you put more gold, you have more yield loss
on a PCB.

Standard thicknesses for surface finishes:

For immersion gold, the typical thickness is 0.05 - 0.23 µm (2 - 9 µ in) gold over 2.5 - 5.0 µm (100 –
200 µ in) electro-less nickel. This is not good for gold wire bonding and black pad.

For soft gold, the typical SMT thickness is 0.25 – 0.8 µm (10 - 30 µ in) gold over 2.5 – 8 µm (100 - 300
µ in) nickel. This is expensive but good for dual surface finish for fine pitch and wire bond surfaces,
and overhang.

ENEPIG is considered a universal surface finish. It offers better shear

strengths for SMT, high wire bond pull strengths for gold wire, and has a
lower cost than soft gold. 40
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 5 5. BGA breakout strategy
BGAs have the highest density of I/O connections
and array pins on a device, which is the most
complex par t of the layout.

• A good design practice is to do the layout part by part.

• Make sure that you will be able to fanout and connect all the pads
under the BGA.
• Another good design practice is to draw short tracks.

BGA breakout means applying a fanout solution and routing traces from those fanouts to the
perimeter of the device prior to general routing of the PCB. If it becomes difficult to maintain the
same trace thickness throughout the board, you can neck-down the traces near the BGAs (con-
gested areas) in the circuit board.

Robert Feranec’s fanout strategy:

“Be careful about drawing the connections all at once. It is a good design practice to do the layout
part by part. If you have a BGA, the first goal is to go out of the BGA. Be sure that you can go out
with all the pads and all the pins under the BGA. Do not fully route all the interfaces, but instead
just route a little bit of track, and then stop routing to place vias, or draw the tracks for different
parts just a little bit out of the BGA area. Make sure that you will be able to fanout and connect all
the pads under the BGA. You can then start connecting all the interfaces.

If you only draw short tracks, it is very easy to delete them and redo parts of the layout under the
BGA because you did not fully route the tracks. So you can just delete them and try to find a way to
fanout all the pins. This practice is much easier and will save you a lot of time since you only have
to deal with a small part of your layout. You want to avoid finding yourself in a difficult position
once you have fully routed your BGA and you need to take out only one pin, for example. If that
happened, you would have to deal with a lot of tracks just to be able to remove one signal.

There are some exceptions, like memories or high-speed interfaces. In this case, you can fully
route the connections between the BGA and the memories or the high-speed interfaces before
you finish the fanout of all the pads.”

Copyright Sierra Circuits Inc., 2023

5.1 Example of how to breakout a .4mm BGA
When planning out how to breakout (or route)
a .4mm BGA, the overall size and the pin out
of the part need to be thought through so the
most cost efficient technology can be used. It is
not just about the fact that the pads are .4mm
apart and figuring out what are the numbers of
widths and gaps that work.
When fanning out a .4mm BGA, the geometry
does not work out so that you can route a trace
between the pins. The traces and gaps are just
too small to go down enough layers to get all
the pins fanned out.
So with a .4mm BGA, blind and buried vias are figure A
required. The pins on the outside row in the
BGA are routed on Layer 1, the pins on the next In this configuration above, the problem is what
row in the BGA are routed on Layer 2 etc. The can you do with the GND pin? Drilling from Lay-
way the BGA is pinned out will determine how er 2 to Layer 3 will cost more.
to route the BGA.

Example of how to route a .4mm BGA:

This part is a standard .4mm BGA. The best way

to fan it out is to use blind and buried vias and
a multi-lamination fabrication.

Start off by adding a Layer 1 to Layer 2 blind via

on all of the GND pins of the BGA. (This is a hole
in the BGA pad that will tie that pin to the GND
plane on Layer 2.) Now all of the GND pins are done and do not need to follow the
routing described below.

The routing plan: figure B

Route the outside row or ring of pins (24 pins, row 1 and 7 and A and G) on the top
side of the board, Layer 1. You may need to route out some of the GND pins on the
outside row and not just add a 1 to 2 via in the BGA pad.

Add a Layer 1 to Layer 2 blind via to the next ring of pins (16 pins, row 2 and 6 and B
and F), route this ring out on board Layer 2 – Layer 2 is a GND plane so these Layer
2 routes can only route out a short distance and then a standard top to bottom
via is added. Do not cut off the GND plane with these short Layer 2 routes such
that the GND plane is cut up and pins are not connected.

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 5 Then, on the next ring of pins (8 pins, row 3 and 5 and C and E), add a Layer
1 to Layer 2 blind via and a Layer 2 to Layer 3 buried via and route these nets
out on board Layer 3.

The BGA pin in the very center of the chip will need to be worked out on Layer 2 or 3.

Pad and drill sizes for .4mm BGA:

There will be no traces between pads on the top layer so the pads can be 10 mils and
have a 5.7 gap between them. For the larger pad, let the manufacturer drill a 4 to
6-mil laser drill for the buried and blind vias. The distance between the board layers
will determine the best drill size so they can plate the hole shut and make a flat pad
for the BGA, etc.

Sequential lamination:

Let’s pretend that this is an 8-layer board.

Board Layers 2 through 7 will be laminated together. Then, a laser drill will be done
from Layer 2 down to Layer 3: This is your 2 to 3 buried via. Note that a Layer 7 to 6
buried via could also be used, and a Layer 2 to 7 could be used; but the 2 to 7 needs
to have bigger drill and pad.

.4 mm Pitch

Drill Size Pad Size Trace

BGA Area
4 mil Drill 6.75 mil Pad 3 mils
MicroVia

Board Layers 1 and 8 will now be laminated to the board and a laser drill will be done from Layer
1 down to Layer 2 (Layer 10 to 9 if needed).

Then, the standard through via is drilled top to bottom – here again, bigger drill and pad are
required.

In your Gerber files, you have parts placed around the .4mm BGA. The fanning out and adding
standard size vias and trace width and spacing will take up a lot of room around the BGA.

Copyright Sierra Circuits Inc., 2023

Technology level for .4:
For BGA Pitch - 0.4
TECH I TECH II
BGA area MicroVia Drill/Pad Dia in mils 6/12 4/6.75
BGA area BAse Core Via Drill/Pad Dia in mils 6/12 6/12

BGA Area Trace width and spacing Top Layer 5.00 5.00
BGA Area Trace width and spacing inner Buildup Layers 5.00 3.00
BGA Area Trace width and spacing inner Core Layers 5.00 5.00
BGA Area Trace width and spacing Bottom Layer 5.00 5.00

# of Traces bet BGA pads on : Top layer 0 0

# of Traces bet BGA vias on: Inner Buildup Layers 0 1
# of Traces bet BGA vias on : Inner Core Layers 0 0
# of Traces bet BGA vias on: Bottom Layer 0 0

Ben Jordan, Director of Community Tools and Content at Altium: Laser drilled uVia-in-pads
eliminate the need for via fill because they are small and very shallow compared to the pad.
Offsetting the vias in row patterns will provide larger routing channels to allow inner pads to be
easily escape-routed.

During one of our webinars we were asked- “In many designs, they use via-in-pads right at the
BGA pins, route the signals to the next layer, bring it outside the BGA area and route it to the top
layer. What are the advantages of this approach?

More space for additional channels for routing

Our experts’ replied- “One advantage is that you will have more space. You
don’t have to route all the signals on the same layer and it reduces the density.
But by using this approach, you may end up using a thicker trace than a thinner
one. This means that the board will become a standard board with one extra
process of via filling rather than a HDI one.”

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5 5.2 Example of how to breakout a .5mm BGA
19.685 MIL
19.683 MIL This example is from a board with
.5mm pitch at .5mm (19.685 mils) and the
319.683-6-3-3-3 = 10.685
19.685-3-3-3=10.865 Pad size minimum drill size is 6 mils. The min-
imum trace width needs to be 3 mils
and the trace to pad spacing also
needs to be 3 mils.
3
3 MIL
3 3 2.3
Take the BGA pitch minus the 3-mil
MILS trace minus the 3-mil trace to pad gap
minus another 3-mil trace to pad gap
and you have a pad diameter (or a pad
6 DRILL size) of 10.685 mils.
DRILL TO
COPPER
19.685 – 3 – 3 – 3 = 10.685
5.3425
10.685
10.683
PAD - DRILL ÷ 2 = ANULAR RING
10.685 - 6 = 4.685 ÷ 2 = 2.342

19.683
19.685MIL
MIL Now take the pad size of 10.685 mils minus
the 6-mil drill size divided by two and you have
a 2.3425-mil annular ring on the pads.
3 MIL WIDE COPPER SPOKE ON PLANE LAYERS

10.685 – 6 / 2 = 2.3425

On a plane layer:

If the via ties to the plane, it will be a solid tie

(no thermal relief). If the via does not tie to the
plane or to a signal trace on this layer, the pad on
this layer can be removed. You can set up your
10.683
10.685
10.685
10.683 design software to suppress unconnected pads
and it will remove the pads on non-functional
Drill to Drill to pins.
Copper Copper

5.3425
5.3423 5.3425
5.3423 On a .5mm BGA, the copper spoke between the
drills will be 3 mils wide. The distance from the
edge of the drill to the edge of the 3-mil copper
spoke between the drills is the drill-to-copper
spacing. With the above sizes, the drill-to-copper
will be 5.3425 mils. The drill-to-copper spacing
required to manufacture the PCB changes due
to many different factors. There is no set rule of
thumb size for all boards.

Copyright Sierra Circuits Inc., 2023

This works if the board is 62 mils or less thick and does not have more than eight layers. The board
thickness and the layer count have an increase in accumulative tolerances, which explains why
fewer layers on a thinner board helps a lot.

Set up the footprint of the part with the via-in-pad– ie. a drill in the surface mount component pad
of the BGA. The manufacturer might adjust the trace and space a little but can build the board
with these numbers.

.5 mm Pitch Drill size: 6 mils

Pads size: 10.68 mils
Drill Size Pad Size Trace Soldermask and solderpaste: 10.68 mils
Trace width in the BGA area: 3 mils
BGA Area Trace to pad spacing in the BGA: 3 mils
6 mil Drill 10 mil Pad 3 mils
MicroVia

For BGA Pitch - 0.50mm

TECH I TECH II TECH III
BGA area MicroVia Drill/Pad Dia in mils 6/12 6/10 5/9
BGA area BAse Core Via Drill/Pad Dia in mils 8/14 7/14 6/12

BGA Area Trace width and spacing Top Layer 5.00 5.00 5.00
BGA Area Trace width and spacing inner Buildup 5.00 3.00 3.50
Layers
BGA Area Trace width and spacing inner Core Layers 5.00 5.00 5.00
BGA Area Trace width and spacing Bottom Layer 5.00 5.00 3.50

# of Traces bet BGA pads on : Top layer 0 0 0

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# of Traces bet BGA vias on: Inner Buildup Layers 0 1 1
# of Traces bet BGA vias on : Inner Core Layers 0 0 0 47
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6 6. Manufacturing tolerance
Tolerance is the allowed deviation from the actual values specified in the design. This
is present at every stage of HDI board manufacturing.

6.1 Drilling tolerances

As you are aware, microvias are one of the special characteristics of HDI PCBs. Hence
it is essential to limit the drilling tolerances during the fabrication. The tolerance
values at Sierra Circuits are mentioned below.

Features Tolerance

Tolerance for PTH and NPTH ±3 mil (0.003”)

drills

Drill to copper minimum 8 mil (0.008”)

Drilled hole registration 1 mil (0.001”)

tolerance

Drill to drill clearance 6 mil (0.006”)

Drill (hole) to the board edge 6 mil (0.006”)

Laser hole registration 0.5 mil (0.0005”)

tolerances

6.2 Annular ring tolerence

It is crucial to maintain a minimum annular ring to avoid breakouts.
The minimum tolerance for both laser and mechanical drilling is
mentioned below.

Copyright Sierra Circuits Inc., 2023

 Laser drilled holes 2 mil

Mechanically drilled holes 4 mil

6.3 Copper trace width and spacing tolerances

The trace width is a crucial part of fabrication. It affects the signal integrity, controlled impedance,
and current carrying capacity. Hence, maintaining minimum deviation in trace width is essential.
Apart from this, tolerance in trace spacing is also important. Below we have mentioned the
tolerances related to trace width and spacing.
Trace width tolerance:

Start Copper Minimum copper Minimum copper

trace width on the trace width on the
outer layer (in mil) inner layer (in mil)
5 microns 2 2

9 microns 3 2.5

½ oz 4 3

1 oz 6 4
2 oz 8 6

3 oz 12 7

4 oz 14 8

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 6 Trace-to-trace spacing tolerance:

Start Copper Minimum spacing Minimum spacing

between the between the
conductors on the conductors on the
outer layer (in mil) inner layer (in mil)

5 microns 3 2

9 microns 3 2.5

½ oz 4 2.25

1 oz 6 4.25
2 oz 8 6.25

3 oz 12 8

4 oz 14 10

6.4 Controlled impedance tolerances

Any variation in trace impedance causes signal integrity issue. Trace width and dielectric material
are the two factors that influence the controlled impedance. Sierra Circuits capabilities are as
follows.

Product features Controlled impedance

tolerance

Standard fab 10%

Advanced fab 5%

Micro fab 5%

Copyright Sierra Circuits Inc., 2023

6.5 Board-related tolerances
The final manufactured board will have some tolerances with respect to board thickness. This
variation is due to factors like layer count, material, operating environment, etc.

A maximum of 50 µm tolerance is acceptable in the layer-to-layer registration.

In addition, tolerance can exist in the flatness of the board. A bow or a twist can occur due to
asymmetry in layers or imbalanced copper distribution. In the below table, we have mentioned
the board thickness, bow and twist tolerances.

Board thickness tolerance:

Thickness Standard board thickness

tolerance

Boards thickness - 31 mil ± 10%

and above

Boards thickness - lower ± 0.003”

than 31 mil

Bow and twist tolerances:

Feature Tolerance (IPC 2422-1 and

IPC 2422-2)

Maximum bow and twist 0.75%

with SMD

Maximum bow and twist 1.5%

without SMD

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6 6.6 Copper thickness tolerances
Copper thickness tolerances vary at different stages of board manufacturing.
For example, IPC- 4562 standard allows a maximum of 10% reduction in the
start copper of the base material. During the board’s fabrication, the tolerance
varies depending on the plating and etching process, which is mentioned below.

a) Inner layer processing without platted holes (print and etch):

Start Copper (in µm) Minimum finished copper

thickness as per IPC-A-600j-
class 2 (in µm)

12 9.3

18 11.4

35 24.9

70 55.7

105 86.6

Copyright Sierra Circuits Inc., 2023

 b) Outer layers / inner layers with plated holes (print, plate, and etch)

Industry-defined copper Minimum finished copper

thickness (in µm) thickness as per IPC-A-600j-
class 2 (in µm)
30 29.3

35 33.4

70 47.9

105 78.7

140 108.6

6.7 Solder mask feature tolerances

Solder mask is applied to insulate the traces and to avoid contamination of copper. But the
application of excess solder mask can create solder bridges. Hence, sufficient clearance/
solder mask webbing should be provided around surface elements like pads, footprints,
and test points.

Solder mask Tolerance in Tolerance in

covers solder mask solder mask
coverage webbing

Green 1.2 to 1.4 mil 4 mil

Blue 1.2 to 1.4 mil 5 mil
Black 1.2 to 1.4 mil 5 mil
Red 1.2 to 1.4 mil 4 mil
Others 1.2 to 1.4 mil 5 mil
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6 A deviation can also occur in solder mask alignment with other layers. The solder
mask registration tolerance is mentioned below.

Product Features Solder mask registration

tolerance

Standard fab 0.002”

Advanced fab 0.001”

Micro fab 0.001″

Copyright Sierra Circuits Inc., 2023

7. Sierra Circuits’ Capabilities
7.1 Materials available at Sierra Circuits
For standard FR-4 lead free boards: For standard ceramic boards:
- Isola 370 HR - Rogers RO4350 F
- Nan Ya NP-175F - Rogers RO4350
- VENTEC - Rogers TTM 3, 4, 6, 10, 10i
- Nan Ya NPG-170 - Taconics CER-10
- Nelco N4000-13SI
- Nelco N9000-13 RF For standard bond sheet boards:
- Hitachi 671N
For standard polyimide boards: - Rogers RO4450B, RO4450F
- Isola P95
- Nelco N7000-ZHT For standard flex boards:
- DuPont Pyralux AP
For advanced Teflon boards: - DuPont Pyralux LF
- Rogers RO3000 Series - DuPont Pyralux FR
- Rogers RT/DUROID Series
- Rogers ULTRALAM 2000 For advanced resistor boards:
- Rogers RO4003 / 4350 TICER TCR
For advanced ceramic boards:
- Rogers RO4003 For advanced thermal boards:
- Rogers RO4230 - Thermagon 88
- Taconics RF-35A2 - Laird IMPCB
- Taconics RF-60

For standard Cyanate Ester boards:

- Nelco N8000

7.2 Sierra Circuits’ PCB Stackup Designer

Get a cost effective, manufacturing-ready PCB stack-up in minutes using our free PCB
Stackup Designer tool. Sierra Circuits developed a unique online tool for electrical
engineers and PCB layout designers that gives confidence to build HDI technology
into their PCB boards. Design HDI layouts right the first time by getting a complete
HDI PCB stack-up in minutes. Highlights get a complete stack-up before the PCB
layout starts:

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 7
• Simple inputs, BIG outputs: Provide the tool with information, like fastest signal
rise/fall time of the devices used, maximum BGA pin count and minimum BGA pitch,
and the tool will return complete HDI stack-up options.
• Compare PCB stack-up options instantly: Each HDI PCB stack-up option comes
with complete information about dielectrics, copper weights, trace width and space
and key manufacturing steps required. The Stackup Planner also provides a cost in-
dex based on complexity so the electrical engineer and the PCB designer can make
informed decisions even before the layout begins.
• Manufacturing-ready: Have confidence that you are designing an HDI PCB stack-up
that is manufacturing-ready. The tool has been built from an authority in HDI Man-
ufacturing Technology and each HDI PCB stack-up has been tested for accuracy and
high yield.
• Save design iterations: Instead of ending up with a less-than-optimal HDI design
layout, the tool assists the HDI PCB designer to start in the right direction with a prov-
en stack-up, pad sizes, and trace width and space.
• Pricing and availability: The online tool will be complimentary for a limited time.
Please visit:
www.protoexpress.com/hdi

7.3 PCB Stackup Designer tutorial

Sierra Circuits PCB Stackup Designer can help you in creating an HDI stack-up that is easily
manufacturable on the very first attempt.
Here are the steps to design a board stack-up using our tool.

First, you’ll have to fill out the board information: project name, revision number, board size
(length and width), target board thickness, material, and board type. Next, select between the
options below:

1) I know the number of layers required in the design (Choose a Sierra Standard Stackup)

2) I do not know the number of layers required in the design, but I have a complex BGA

Copyright Sierra Circuits Inc., 2023

Case 1: When you know the number of layers required
Input the layer count and signal layer combinations. Click on Run Stackup De-signer. The
tool will show the recommended stack-up design with essential in-formation such as total
layer count, type of technology (HDI), board thickness, cost index, etc.

Click on the report to display the stack-up. You can change the required param-eters except
for the board name and size.

If required, use the built-in impedance calculator to design the controlled impedance traces.

Subsequently, under the section technology parameters and cost index, the tool suggests the
technology levels (drill size, pad size, and trace width parameters) and via set information.

Case 2: When you don’t know the required number of layers and have a complex BGA

Input the BGA details, and the tool will calculate the total number of pins and the
estimated number of signal pins. Modify the values if needed and click Run Stackup
Designer. The tool will display the stack-up option.

The steps involved are similar to the previous section, but now it will include BGA
fan-out recommendations section. This will contain all the required info about the
BGA.

Using this tool, you can lower the cost and avoid board respins. For more
details on how to use this tool, go to PCB Stackup Designer. 56
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7
7.4 About Sierra Circuits
At Sierra Circuits, our engineering staff has been trained on the topics discussed in this
article and can analyze the design from a holistic point of view. Their analysis starts
with determining the density of the most demanding component. Then, through a
systematic set of questions and answers using our in-house HDI assistance design
tool, we can recommend a set of stack-up recommendations that meet your cost,
performance and timeline needs.

Sierra Circuits is a U.S. based manufacturer of HDI PCBs. Our specialty is quick turn,
high technology and small to medium production of printed circuit boards. Our capa-
bilities include laser microvias, blind and buried vias, fine lines and spaces, sequen-
tial lamination, via-in-pad technology. With our in-house YAG laser machines, we can
laser drill 2-mil, or 50-micron microvias. Sierra Circuits has also pioneered fine line
capability. With our laser direct imaging systems, we can provide consistent traces
and spaces down to 35 microns in diameter. We also specialize in sequential build
applications, using typical PCB materials like FR4, Polyimide, and RCC. We can provide
up to 4 build-up layers on expedited lead times. Typical microvia structures include
stacked microvias, buried microvias, staggered or stepped microvias.

For our microelectronics PCBs and PCB substrates, we can provide build-up technol-
ogy with fine lines and spaces down to 40 microns, high-temperature materials, like
polyimide, stacked microvias, buried resistors, and multi-tiered cavity PCBs. We have
provided microelectronic PCBs with fine pitch devices down to 200 microns, using
50-micron laser drilled via-in-pad technology and thin build-up materials. Our quality
checks include surface cleanliness and wirebondability. Some examples of surface
finish include OSP, ENIG, ENEPIG, Soft Gold.

Our engineering support provides valuable suggestions with their knowledge of high-
speed designs, analog/digital, high-density PCB manufacturing design rules and de-
sign for assembly rules. Upload your data and receive a free consultation and review
of your design. Services include system level design, schematic capture, PCB layout,
and PCB/PCBA DFM.

Copyright Sierra Circuits Inc., 2023

Thank you...
...to all the great PCB exper ts who
contributed to this HDI Design Guide!

Before we even began to start writing this design guide, it was clear that we were
going to need the best PCB experts to give us their best tips. This is exactly what they
did and we personally want to thank each one of these PCB designers, engineers,
influencers, etc. who took the time to answer our questions and help us make this
HDI design guide come to life.

Randy Clemmons, San Diego PCB

Randy, ever since we’ve met you at Rick’s San Diego workshop in February, you’ve
always answered our questions whenever we needed your expertise. Thank you for
helping us out every so often. We love your blog and we’d love to partner even more
with you in the future!

Ben Jordan, Altium

Ben, we’ve done so much with you in the past few years that it almost feels like
you’re part of the Sierra family! Thanks for always being there for us!

Robert Feranec, Fedevel Academy

Rob, it’s always a pleasure to pick up your brain for designing tips. You’re
one of the greatest experts of our industry and we’re honored to feature
your advice in our design guide. Thank you!

Steve Watt, Zuken

Steve, we met you last year at PCB West for an interview at our booth and
here you are this year in our brand new HDI Design Guide. Let’s plan
something for 2019, shall we? But seriously, thank you for your
valuable HDI recommendations!
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7 Rick Hartley, RHartley Enterprises
Rick, attending your Control of Noise, EMI and Signal Integrity in High-
Speed Circuits workshop was a fantastic learning experience. From that
day, we knew we would need to feature the EMI Jedi – as people call you;
we swear we didn’t come up with that nickname! – in our design guide.
Thank you for helping us educate the designer community!

Eric Bogatin, Teledyne Lecroy

Signal integrity and Eric Bogatin go hand in hand, don’t they? Thank you
Eric for contributing to this design guide. Our signal integrity section
couldn’t have been complete without your immense knowledge!

Happy Holden, Father of HDI

And, of course, a huge thank you to you, Hap! Thanks for helping us
with the content. Thanks for answering all of our questions and provid-
ing us great documentation to work with. Thanks for reviewing this de-
sign guide of 50+ pages in just 24 hours. Thanks for your wise foreword.
Thanks for everything!

Because we couldn’t cover the whole topic of

HDI, you should download Happy’s free 600-
page HDI HANDBOOK at:
http://hdihandbook.com/ (English)
http://hdihandbook.cn/ (Simplified Chinese)

Now we only have one question: Are you ready

to contribute to our next design guide? ;)

Copyright Sierra Circuits Inc., 2023

Designer’s Best Friend

Sierra Circuits, Inc.

1108 West Evelyn Avenue
Sunnyvale, CA 94086