Computer System Hardware

Reading:
Silberschatz
chapter 2
Additional Reading:
Stallings
chapter 1, 2

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Outline
‰ Computer Hardware
‰ CPU Components
‰ Registers
‰ Instruction Execution
‰ Interrupt and Trap
‰ Memory
‰ Hierarchy
‰ Cache
‰ Dual Mode Operation
‰ Protection
‰ Hardware
‰ Memory
‰ CPU, I/O

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Computer Hardware
¾ Why study hardware?
OS exploits hardware resources to provide set of services
¾ Key Elements
„ CPU or Processor
„ Main Memory
Š typically volatile
Š also referred as real memory or primary memory
„ I/O modules
Š secondary memory devices
Š communications equipment
Š terminals
„ System bus
Š communication among processors, memory, and I/O modules

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CPU Components

Computer Components: Top-Level View

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Processor Registers
¾ User-Visible registers
„ Helps programmer to minimize main memory references
„ Typically two types of registers
1. Data registers
2. Address registers
„ Index
„ Segment pointer
„ Stack pointer

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User-Visible Registers
¾ Data registers
„ General purpose (programmers or machine)
„ May be dedicated (floating-point and integer operations)

¾ Address registers
„ Index
Š Involves adding an index to base value to get effective address
„ Segment pointer
Š When memory is divided into segments, memory is referenced
by a segment and an offset
„ Stack pointer
Š Points to top of stack

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Control and Status Registers
Mostly not visible to user, organization is machine specific
¾ Program Counter
„ Contains the address of instruction to be fetched

¾ Instruction Register
„ Contains the instruction most recently fetched

¾ Program Status Word (PSW)

„ Condition codes
„ Interrupt enable/disable
„ Supervisor/user mode

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Control and Status Registers
¾ Condition Codes or Flags
„ Bits set by the processor hardware as a result of
operations
„ Examples
Š Positive result
Š Negative result
Š Zero
Š Overflow

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Instruction Execution
¾ Instruction Cycle – processing required for single instruction
¾ Two step processing in simplest form
„ Processor reads instructions from memory one at time
Š Fetches
„ Processor executes each instruction

Basic Instruction Cycle

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Instruction Fetch and Execute
¾ The processor fetches the instruction from
memory
¾ Program counter (PC) holds address of the
instruction to be fetched next
¾ Processor increments the PC after each fetch

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Instruction Register
¾ Fetched instruction is loaded in IR
¾ Instruction categories
„ Processor-memory
Š Transfer data between processor and memory
„ Processor-I/O
Š Data transferred to or from a peripheral device
„ Data processing
Š Arithmetic or logic operation on data
„ Control
Š Alter sequence of execution

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Interrupts
¾ Common Class of Interrupts
„ Program
Š Result of instruction execution, e.g. arithmetic overflow,
division by zero or illegal memory reference
„ Timer
Š Processors timer, functions on regular basis
„ I/O
Š Generated by I/O controller, signal or error
„ Hardware Failure
Š Power failure or memory parity error

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Interrupt and Trap
Mechanisms to interrupt the normal processing of processor
¾ Trap
„ Trap is the notification of an internal event, highest priority
„ Traps are immediate and occur synchronously with the current
activity of processor (result of program execution)
¾ Interrupt
„ Interrupt is the notification of an external event
„ Occur asynchronously with the current activity of processor

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Program Flow of Control

(a) No Interrupts (b) Interrupts; short I/O wait (c) Interrupts; long I/O wait

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Interrupts

Simple Interrupt Processing

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Multiple Interrupts
¾ Disable new interrupts while an interrupt is being processed

Sequential interrupt processing

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Multiple Interrupts
¾ Disadvantages of sequential interrupt processing
„Does not account for relative priority or time critical needs
„ I/O device may fill and overflow

¾ Define priorities and serve in order

Nested interrupt processing

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Multiple Interrupts

Example: Time sequence of multiple interrupts with priorities

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Memory Hierarchy
¾ Design Constraints
„ How much?
Š Open ended, large capacity
„ How fast?
Š Mach the processor, do not wish to wait
„ How expensive?
Š Reasonable relationship to other components

¾ Tradeoff among three components

„ Faster access time, greater cost per bit
„ Greater capacity, smaller cost per bit
„ Greater capacity, slower access speed

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Memory Hierarchy

¾ As one goes down

„ Decreasing cost per bit
„ Increasing capacity
„ Increasing access time
Key to success – Decrease the frequency of access
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Caching
¾ Copying information into faster storage system;
main memory can be viewed as a fast cache for
secondary storage
¾ Use of high-speed memory to hold recently-
accessed data
¾ Requires a cache management policy

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Caching

Cache size
Replacement policy

Cache Read Operation

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Typical Memory Hierarchy

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Hardware Protection
¾ Sharing of Resources → Utilization and Problems

¾ OS must ensure that an incorrect program cannot cause

other programs to execute incorrectly

¾ Hardware Protection
ƒ Dual-Mode Operation
ƒ I/O Protection
ƒ Memory Protection
ƒ CPU Protection

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Dual-Mode Operation
¾ Provide hardware support to differentiate
between at least two modes of operations

„ User Mode → execution done on behalf of a user

„ Monitor Mode (also kernel mode or system mode) →

execution done on behalf of operating system

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Dual-Mode Operation
¾ Mode bit added to computer hardware to indicate current mode:
Monitor (0) or User (1)
¾ When an interrupt or fault occurs hardware switches to monitor
mode
Interrupt/fault

Monitor User
set user mode

ƒ Privileged instructions can be issued only in monitor mode

ƒ MSDOS (8088 architecture) – No Mode bit
ƒ Win 2000, IBM OS/2 (advanced versions of Intel CPU, Pentium)
provide dual-mode operation

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I/O Protection
¾ All I/O instructions → privileged instructions

¾ Must ensure that a user program could never

gain control of the computer in monitor mode

¾ All I/O instructions → through OS, checks if valid

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I/O Protection

Use of system call to perform I/O

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Memory Protection
¾ Memory protection → Prevent interrupt vector
and interrupt service routines from user program

¾ Range of legal addresses - two registers

„ Base register → holds the smallest legal physical
memory address
„ Limit register → contains the size of the range

¾ Memory outside the defined range is protected

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Memory Protection

Use of base and limit register

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Hardware Address Protection

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Hardware Protection
¾ The load instructions for the base and limit
registers are privileged instructions

¾ When executing in monitor mode, OS has

unrestricted access to both monitor and user’s
memory

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CPU Protection
¾ Prevent user program from struck in infinite loop
or never returning control to OS
¾ Timer – interrupts computer after specified
period to ensure OS system maintains control
„ Timer is decremented every clock tick
„ When timer reaches the value 0, an interrupt occurs

¾ Timer commonly used to implement time

sharing
¾ Load-timer is a privileged instruction

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