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This document contains Verilog code that defines an interface, driver, generator, and environment for testing a multiplexer module (fa) using a transaction-based methodology. The interface defines the inputs and output of the module. The driver connects the interface to a mailbox to drive input values and monitor the output. The generator creates random transactions and sends them to the driver via the mailbox. The environment instantiates and connects the driver and generator to perform the overall test.

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Moin Pasha
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29 views

Full Adder

This document contains Verilog code that defines an interface, driver, generator, and environment for testing a multiplexer module (fa) using a transaction-based methodology. The interface defines the inputs and output of the module. The driver connects the interface to a mailbox to drive input values and monitor the output. The generator creates random transactions and sends them to the driver via the mailbox. The environment instantiates and connects the driver and generator to perform the overall test.

Uploaded by

Moin Pasha
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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DESIGN.

SV
module fa (d0,d1,d2,d3,d4,d5,d6,d7,sel,out);
input d0,d1,d2,d3,d4,d5,d6,d7;
input [2:0] sel;
output reg out;
always@(sel)
begin
case(sel)
3'b000:out=d0;
3'b001:out=d1;
3'b010:out=d2;
3'b011:out=d3;
3'b100:out=d4;
3'b101:out=d5;
3'b110:out=d6;
3'b111:out=d7;
endcase
end
endmodule

INTERFACE.SV
//Interface

interface fa_intf;

logic d0;
logic d1;
logic d2;
logic d3;
logic d4;
logic d5;
logic d6;
logic d7;
logic [2:0] sel;
logic out;

endinterface

TRANSACTION.SV
//Interface

interface fa_intf;

logic d0;
logic d1;
logic d2;
logic d3;
logic d4;
logic d5;
logic d6;
logic d7;
logic [2:0] sel;
logic out;

endinterface
DRIVER.SV
class driver;

virtual fa_intf vif;

mailbox mbox;

transaction tr;

function new (virtual fa_intf vif,mailbox mbox);

tr=new();

this.vif=vif;

this.mbox=mbox;

endfunction

task run();

forever

begin

mbox.get(tr);

vif.d0=tr.d0;

vif.d1=tr.d1;

vif.d2=tr.d2;
vif.d3=tr.d3;
vif.d4=tr.d4;
vif.d5=tr.d5;
vif.d6=tr.d6;
vif.d7=tr.d7;
vif.sel=tr.sel;

#5

tr.out=vif.out;

//$display ("sum=%d,cout=%d",tr.sum,tr.cout);

end

endtask

endclass

GENERATOR.SV
class generator;

transaction tr;

mailbox mbox;
function new(mailbox mbox);

this.mbox=mbox;

endfunction

task run();

repeat(20)

begin

tr=new();

tr.randomize();

//tr.in1=1;

//tr.in2=1;

//tr.cin=0;

//$display("in1=%d,in2=%d,cin=%d",tr.in1,tr.in2,tr.cin);

mbox.put(tr);

end

endtask

endclass

ENVIRONMENT.SV
class generator;

transaction tr;

mailbox mbox;

function new(mailbox mbox);

this.mbox=mbox;

endfunction

task run();

repeat(20)

begin

tr=new();

tr.randomize();

//tr.in1=1;
//tr.in2=1;

//tr.cin=0;

//$display("in1=%d,in2=%d,cin=%d",tr.in1,tr.in2,tr.cin);

mbox.put(tr);

end

endtask

endclass

TEST.SV
//Program block test.sv//

`include "environment.sv"

program test(fa_intf vif);

environment env;

initial

begin

env=new(vif);

env.run;

end

endprogram

TESTBENCH.SV
// Code your testbench here
// or browse Examples

// test module

`include "interface.sv"

`include "test.sv"

module testbench;

fa_intf pif();

test tb(pif);

fa
f1(.d0(pif.d0),.d1(pif.d1),.d2(pif.d2),.d3(pif.d3),.d4(pif.d4),.d5(pif.d5),.d6(pif.
d6),.d7(pif.d7),.sel(pif.sel),.out(pif.out));
///fa f1 (.sel(pif.sel),.out(pif.out));

initial

begin

$dumpfile("dump.vcd");

$dumpvars;

end

endmodule

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