STM32F030x4 STM32F030x6

STM32F030x8
Value-line ARM-based 32-bit MCU with 16 to 64-KB Flash, timers,
ADC, communication interfaces, 2.4-3.6 V operation
Datasheet target specification

Features
 Core: ARM® 32-bit Cortex™-M0 CPU,
frequency up to 48 MHz
 Memories LQFP64 10x10 mm
TSSOP20
LQFP48 7x7 mm
– 16 to 64 Kbytes of Flash memory LQFP32 7x7 mm
– 4 to 8 Kbytes of SRAM with HW parity
checking – One 16-bit basic timer
 CRC calculation unit – Independent and system watchdog timers
 Reset and power management – SysTick timer: 24-bit downcounter
– Voltage range: 2.4 V to 3.6 V  Calendar RTC with alarm and periodic wakeup
– Power-on/Power down reset (POR/PDR) from Stop/Standby
– Low power modes: Sleep, Stop, Standby  Communication interfaces
 Clock management – Up to two I2C interfaces: one supporting
– 4 to 32 MHz crystal oscillator Fast Mode Plus (1 Mbit/s) with 20 mA
current sink
– 32 kHz oscillator for RTC with calibration
– Up to two USARTs supporting master
– Internal 8 MHz RC with x6 PLL option
synchronous SPI and modem control; one
– Internal 40 kHz RC oscillator with auto baud rate detection
 Up to 55 fast I/Os – Up to two SPIs (18 Mbit/s) with 4 to 16
– All mappable on external interrupt vectors programmable bit frame
– Up to 36 I/Os with 5 V tolerant capability  Serial wire debug (SWD)
 5-channel DMA controller
Table 1. Device summary
 1 x 12-bit, 1.0 µs ADC (up to 16 channels)
Reference Part number
– Conversion range: 0 to 3.6 V
– Separate analog supply from 2.4 up to STM32F030x4 STM32F030F4
3.6 V STM32F030x6 STM32F030C6, STM32F030K6
 Up to 10 timers STM32F030x8 STM32F030C8, STM32F030R8
– One 16-bit 7-channel advanced-control
timer for 6 channels PWM output, with
deadtime generation and emergency stop
– One 16-bit timer, with up to 4 IC/OC, usable
for IR control decoding
– One 16-bit timer, with 2 IC/OC, 1 OCN,
deadtime generation and emergency stop
– Two 16-bit timers, each with IC/OC and
OCN, deadtime generation, emergency
stop and modulator gate for IR control
– One 16-bit timer with 1 IC/OC

July 2013 DocID024849 Rev 1 1/88

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Contents STM32F030x4 STM32F030x6 STM32F030x8

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 ARM® CortexTM-M0 core with embedded Flash and SRAM . . . . . . . . . 12
3.2 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.4 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 13
3.5 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5.2 Power supply supervisors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.6 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.7 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.8 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.9 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.9.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 16
3.9.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 16
3.10 Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.10.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.10.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.11 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.11.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.11.2 General-purpose timers (TIM3, TIM14..17) . . . . . . . . . . . . . . . . . . . . . . 19
3.11.3 Basic timer TIM6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.11.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.11.5 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.11.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.12 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.13 Inter-integrated circuit interfaces (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.14 Universal synchronous/asynchronous receiver transmitters (USART) . . 22

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3.15 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.16 Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4 Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 41
6.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 41
6.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.3.6 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.3.10 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.3.16 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.3.17 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.3.18 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.3.19 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

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7 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
7.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
7.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
7.2.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
7.2.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . 83

8 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

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STM32F030x4 STM32F030x6 STM32F030x8 List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. STM32F030x device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 4. Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 5. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 6. Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 7. STM32F030x I2C implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 8. STM32F030x USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 9. STM32F030x SPI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 10. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 11. Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 12. Alternate functions selected through GPIOA_AFR registers for port A . . . . . . . . . . . . . . . 31
Table 13. Alternate functions selected through GPIOB_AFR registers for port B . . . . . . . . . . . . . . . 32
Table 14. STM32F030x peripheral register boundary addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 15. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 16. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 17. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 18. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 19. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 20. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 21. Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 22. Typical and maximum current consumption from VDD supply at VDD = 3.6 . . . . . . . . . . . 43
Table 23. Typical and maximum current consumption from the VDDA supply . . . . . . . . . . . . . . . . . . 43
Table 24. Typical and maximum VDD consumption in Stop and Standby modes. . . . . . . . . . . . . . . . 44
Table 25. Typical and maximum VDDA consumption in Stop and Standby modes. . . . . . . . . . . . . . . 44
Table 26. Typical current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 27. Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 28. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 29. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 30. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 31. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 32. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 33. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 34. HSI14 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 35. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 36. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 37. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 38. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 39. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 40. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 41. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 42. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 43. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 44. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 45. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 46. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 47. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

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List of tables STM32F030x4 STM32F030x6 STM32F030x8

Table 48. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 49. RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 50. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 51. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 52. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 53. IWDG min/max timeout period at 40 kHz (LSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 54. WWDG min-max timeout value @48 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 55. I2C characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 56. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 57. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 58. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data . . . . . . . . . . 75
Table 59. LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat package mechanical data . . . . . . . . . . . 77
Table 60. LQFP32 – 7 x 7mm 32-pin low-profile quad flat package mechanical data . . . . . . . . . . . . 79
Table 61. TSSOP20 – 20-pin thin shrink small outline package mechanical data . . . . . . . . . . . . . . . 81
Table 62. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 63. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 64. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

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List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 2. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 3. LQFP64 64-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 4. LQFP48 48-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 5. LQFP32 32-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 6. TSSOP20 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 7. STM32F030x memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 8. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 9. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 10. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 11. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 12. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 13. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 14. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 15. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 16. TC and TTa I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 17. Five volt tolerant (FT and FTf) I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 18. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 19. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 20. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 21. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 22. I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 23. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 24. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 25. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 26. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . 75
Figure 27. LQFP64 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 28. LQFP48 – 7 x 7 mm, 48 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 77
Figure 29. LQFP48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 30. LQFP32 – 7 x 7mm 32-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . 79
Figure 31. LQFP32 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 32. TSSOP20 - 20-pin thin shrink small outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 33. TSSOP20 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 34. LQFP64 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

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Introduction STM32F030x4 STM32F030x6 STM32F030x8

1 Introduction

This datasheet provides the ordering information and mechanical device characteristics of
the STM32F030x microcontrollers.
This STM32F030x4, STM32F030x6, and STM32F030x8 datasheet should be read in
conjunction with the STM32F0xxxx reference manual (RM0091). The reference manual is
available from the STMicroelectronics website www.st.com.
For information on the ARM Cortex™-M0 core, please refer to the Cortex™-M0 Technical
Reference Manual, available from the www.arm.com website at the following address:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0432c/index.html.

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2 Description

The STM32F030x microcontroller incorporates the high-performance ARM Cortex™-M0 32-

bit RISC core operating at a 48 MHz frequency, high-speed embedded memories (up to
64 Kbytes of Flash memory and up to 8 Kbytes of SRAM), and an extensive range of
enhanced peripherals and I/Os. All devices offer standard communication interfaces (up to
two I2Cs, up to two SPIs, and up to two USARTs), one 12-bit ADC, up to 6 general-purpose
16-bit timers and an advanced-control PWM timer.
The STM32F030x microcontroller operates in the -40 to +85 °C temperature range, from a
2.4 to 3.6 V power supply. A comprehensive set of power-saving modes allows the design of
low-power applications.
The STM32F030x microcontroller includes devices in four different packages ranging from
20 pins to 64 pins. Depending on the device chosen, different sets of peripherals are
included. The description below provides an overview of the complete range of
STM32F030x peripherals proposed.
These features make the STM32F030x microcontroller suitable for a wide range of
applications such as application control and user interfaces, handheld equipment, A/V
receivers and digital TV, PC peripherals, gaming platforms, e-bikes, consumer appliances,
printers, scanners, alarm systems, video intercoms, and HVACs.

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Description STM32F030x4 STM32F030x6 STM32F030x8

Table 2. STM32F030x device features and peripheral counts

Peripheral STM32F030F4 STM32F030K6 STM32F030C6/C8 STM32F030R8

Flash (Kbytes) 16 32 32 64 64
SRAM (Kbytes) 4 4 4 8 8
Advanced
1 (16-bit)
control
Timers General
4 (16-bit)(1) 4 (16-bit)(1) 4 (16-bit)(1) 5 (16-bit) 5 (16-bit)
purpose
Basic - - - 1 (16-bit) 1 (16-bit)
(2) (2) (2)
SPI 1 1 1 2 2
Comm.
I2C 1(3) 1(3) 1(3) 2 2
interfaces
(4) 1(4) 1(4)
USART 1 2 2
12-bit synchronized ADC 1 1 1 1
(number of channels) (11 channels) (12 channels) (12 channels) (18 channels)
GPIOs 15 26 39 55
Max. CPU frequency 48 MHz
Operating voltage 2.4 to 3.6 V
Operating temperature Ambient operating temperature: -40 °C to 85 °C
Packages TSSOP20 LQFP32 LQFP48 LQFP64
1. TIM15 is not present.
2. SPI2 is not present.
3. I2C2 is not present.
4. USART2 is not present.

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Figure 1. Block diagram

Serial VDD18 POWER

SWCLK Wire VOLT.REG
SWDIO VDD = 2.4 to 3.6 V
Debug

Obl
3.3 V TO 1.8 V VSS
as AF Flash

interface
up to @ VDD

Flash
64 KB,
CORTEX-M0 CPU POR SUPPLY
32 bits
fHCLK = 48 MHz Reset SUPERVISION
Int NRST

Bus matrix

controller
SRAM POR/PDR VDDA

SRAM
@ VDDA VDD
4 / 8 KB
NVIC RC HS 14 MHz
RC HS 8 MHz
@ VDDA
GP DMA
RC LS @ VDD
5 channels OSC_IN (PF0)
XTAL OSC
PLL OSC_OUT (PF1)
4-32 MHz
IWDG
Power
AHBPCLK Controller
RESET & APBPCLK
ADCCLK @ VDD
CLOCK
USARTCLK OSC32_IN (PC14)
CONTROL HCLK
XTAL32 kHz
PA[15:0] GPIO port A OSC32_OUT (PC15)
FCLK

GPIO port B RTC TAMPER-RTC

PB[15:0]
AHB decoder

(ALARM OUT)
GPIO port C RTC interface
PC[15:0] CRC

PD2 GPIO port D

PF[1:0] GPIO port F 4 channels

PF[7:4] TIMER 1 3 compl. channels
BRK, ETR input as AF
TIMER 3 4 ch., ETR as AF

AHB TIMER 14 1 channel as AF

APB 2 channels
TIMER 15 1 compl, BRK as AF

EXT. IT 1 channel
55 AF TIMER 16 1 compl, BRK as AF
WKUP
WWDG 1 channel
MOSI, TIMER 17
1 compl, BRK as AF
MISO,
SPI1 IR_OUT as AF
SCK, DBGMCU
NSS as AF
USART1 RX, TX,CTS, RTS,
MOSI/MISO, CK as AF
SPI2
SCK/NSS, USART2 RX, TX,CTS, RTS,
as AF CK as AF
SYSCFG IF

SCL, SDA, SMBA

I2C 1
(20 mA for FM+) as AF
@ VDDA
Temp. SCL, SDA
I2C2
sensor as AF
16 12-bit
AD inputs IF
ADC1
TIMER 6
VDDA
VSSA

MSv32137V1

1. TIMER6, TIMER15, SPI2, USART2 and I2C2 are available on STM32F030x8 devices only.

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Functional overview STM32F030x4 STM32F030x6 STM32F030x8

3 Functional overview

3.1 ARM® CortexTM-M0 core with embedded Flash and SRAM

The ARM Cortex™-M0 processor is the latest generation of ARM processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The ARM Cortex™-M0 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit devices.
The STM32F0xx family has an embedded ARM core and is therefore compatible with all
ARM tools and software.
Figure 1 shows the general block diagram of the device family.

3.2 Memories
The device has the following features:
 Up to 8 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0
wait states and featuring embedded parity checking with exception generation for fail-
critical applications.
 The non-volatile memory is divided into two arrays:
– 16 to 64 Kbytes of embedded Flash memory for programs and data
– Option bytes
The option bytes are used to write-protect the memory (with 4 KB granularity) and/or
readout-protect the whole memory with the following options:
– Level 0: no readout protection
– Level 1: memory readout protection, the Flash memory cannot be read from or
written to if either debug features are connected or boot in RAM is selected
– Level 2: chip readout protection, debug features (Cortex-M0 serial wire) and boot
in RAM selection disabled

3.3 Boot modes

At startup, the boot pin and boot selector option bit are used to select one of three boot
options:
 Boot from User Flash
 Boot from System Memory
 Boot from embedded SRAM
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using USART on pins PA14/PA15 or PA9/PA10.

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3.4 Cyclic redundancy check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a CRC-32 (Ethernet) polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.

3.5 Power management

3.5.1 Power supply schemes

 VDD = 2.4 to 3.6 V: external power supply for I/Os and the internal regulator. Provided
externally through VDD pins.
 VDDA = 2.4 to 3.6 V: external analog power supply for ADC, Reset blocks, RCs and
PLL. The VDDA voltage level must be always greater or equal to the VDD voltage level
and must be provided first.
For more details on how to connect power pins, refer to Figure 10: Power supply scheme.

3.5.2 Power supply supervisors

The device has integrated power-on reset (POR) and power-down reset (PDR) circuits.
They are always active, and ensure proper operation above a threshold of 2 V. The device
remains in reset mode when the monitored supply voltage is below a specified threshold,
VPOR/PDR, without the need for an external reset circuit.
 The POR monitors only the VDD supply voltage. During the startup phase it is required
that VDDA should arrive first and be greater than or equal to VDD.
 The PDR monitors both the VDD and VDDA supply voltages, however the VDDA power
supply supervisor can be disabled (by programming a dedicated Option bit) to reduce
the power consumption if the application design ensures that VDDA is higher than or
equal to VDD.

3.5.3 Voltage regulator

The regulator has three operating modes: main (MR), low power (LPR) and power down.
 MR is used in normal operating mode (Run)
 LPR can be used in Stop mode where the power demand is reduced
 Power down is used in Standby mode: the regulator output is in high impedance: the
kernel circuitry is powered down, inducing zero consumption (but the contents of the
registers and SRAM are lost)
This regulator is always enabled after reset. It is disabled in Standby mode, providing high
impedance output.

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3.5.4 Low-power modes

The STM32F030x microcontroller supports three low-power modes to achieve the best
compromise between low power consumption, short startup time and available wakeup
sources:
 Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
 Stop mode
Stop mode achieves very low power consumption while retaining the content of SRAM
and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the
HSE crystal oscillators are disabled. The voltage regulator can also be put either in
normal or in low power mode.
The device can be woken up from Stop mode by any of the EXTI lines. The EXTI line
source can be one of the 16 external lines or the RTC alarm.
 Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for the Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a
rising edge on the WKUP pins, or an RTC alarm occurs.
Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
or Standby mode.

3.6 Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example on
failure of an indirectly used external crystal, resonator or oscillator).
Several prescalers allow the application to configure the frequency of the AHB and the APB
domains. The maximum frequency of the AHB and the APB domains is 48 MHz.

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Figure 2. Clock tree

FLITFCLK
to Flash programming interface
HSI
to I2C1
SYSCLK

LSE
8 MHz HSI
/244
HSI RC
/2
HCLK to AHB bus, core,
memory and DMA
PLLSRC SW /8 to cortex System timer
PLLMUL
HSI FHCLK Cortex free running clock
PLL AHB
AHB APB
PLLCLK PCLK
x2,x3,.. prescaler prescaler to APB peripherals
x16 /1,2,..512 /1,2,4,8,16
HSE
SYSCLK
/1,2, CSS If (APB1 prescaler to TIM1,3,6,
3,..16 =1) x1 else x2 14,15,16,17

ADC
Prescaler
OSC_OUT /2,4 to ADC
4-32 MHz 14 MHz HSI14
HSE OSC 14 MHz max
OSC_IN HSI14 RC

PCLK
/32 SYSCLK to USART1
OSC32_IN RTCCLK HSI
LSE OSC LSE to RTC
LSE
32.768kHz
OSC32_OUT
RTCSEL[1:0]

LSI RC LSI
to IWDG
40kHz
/2 PLLCLK
Main clock HSI
HSI14
output HSE
MCO
SYSCLK
LSI (1)
LSE (1)
MCO
MS32138V1

1. LSI/LSE is not available on STM32F030x8 devices.

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3.7 General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions.
The I/O configuration can be locked if needed following a specific sequence in order to
avoid spurious writing to the I/Os registers.

3.8 Direct memory access controller (DMA)

The 5-channel general-purpose DMAs manage memory-to-memory, peripheral-to-memory
and memory-to-peripheral transfers.
The DMA supports circular buffer management, removing the need for user code
intervention when the controller reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with support for software
trigger on each channel. Configuration is made by software and transfer sizes between
source and destination are independent.
DMA can be used with the main peripherals: SPI, I2C, USART, all TIMx timers (except
TIM14) and ADC.

3.9 Interrupts and events

3.9.1 Nested vectored interrupt controller (NVIC)

The STM32F0xx family embeds a nested vectored interrupt controller able to handle up to
32 maskable interrupt channels (not including the 16 interrupt lines of Cortex™-M0) and 4
priority levels.
 Closely coupled NVIC gives low latency interrupt processing
 Interrupt entry vector table address passed directly to the core
 Closely coupled NVIC core interface
 Allows early processing of interrupts
 Processing of late arriving higher priority interrupts
 Support for tail-chaining
 Processor state automatically saved
 Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.

3.9.2 Extended interrupt/event controller (EXTI)

The extended interrupt/event controller consists of 24 edge detector lines used to generate
interrupt/event requests and wake-up the system. Each line can be independently
configured to select the trigger event (rising edge, falling edge, both) and can be masked
independently. A pending register maintains the status of the interrupt requests. The EXTI
can detect an external line with a pulse width shorter than the internal clock period. Up to 55
GPIOs can be connected to the 16 external interrupt lines.

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3.10 Analog to digital converter (ADC)

The 12-bit analog to digital converter has up to 16 external and 2 internal (temperature
sensor/voltage reference measurement) channels and performs conversions in single-shot
or scan modes. In scan mode, automatic conversion is performed on a selected group of
analog inputs.
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.

3.10.1 Temperature sensor

The temperature sensor (TS) generates a voltage VSENSE that varies linearly with
temperature.
The temperature sensor is internally connected to the ADC_IN16 input channel which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode.

Table 3. Temperature sensor calibration values

Calibration value name Description Memory address

TS ADC raw data acquired at

TS_CAL1 temperature of 30 °C, 0x1FFF F7B8 - 0x1FFF F7B9
VDDA= 3.3 V
TS ADC raw data acquired at
TS_CAL2 temperature of 110 °C 0x1FFF F7C2 - 0x1FFF F7C3
VDDA= 3.3 V

3.10.2 Internal voltage reference (VREFINT)

The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the
ADC. VREFINT is internally connected to the ADC_IN17 input channel. The precise voltage
of VREFINT is individually measured for each part by ST during production test and stored in
the system memory area. It is accessible in read-only mode.

Table 4. Internal voltage reference calibration values

Calibration value name Description Memory address

Raw data acquired at

VREFINT_CAL temperature of 30 °C 0x1FFF F7BA - 0x1FFF F7BB
VDDA= 3.3 V

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3.11 Timers and watchdogs

Devices of the STM32F0xx family include up to six general-purpose timers, one basic timer
and an advanced control timer.
Table 5 compares the features of the advanced-control, general-purpose and basic timers.

Table 5. Timer feature comparison

Capture/
Timer Counter Counter Prescaler DMA request Complementary
Timer compare
type resolution type factor generation outputs
channels

Up, Any integer

Advanced
TIM1 16-bit down, between 1 Yes 4 Yes
control
up/down and 65536
Up, Any integer
TIM3 16-bit down, between 1 Yes 4 No
up/down and 65536
Any integer
TIM14 16-bit Up between 1 No 1 No
General and 65536
purpose Any integer
TIM15(1) 16-bit Up between 1 Yes 2 Yes
and 65536
Any integer
TIM16,
16-bit Up between 1 Yes 1 Yes
TIM17
and 65536
Any integer
Basic TIM6(1) 16-bit Up between 1 Yes 0 No
and 65536
1. Available on STM32F030x8 devices only.

3.11.1 Advanced-control timer (TIM1)

The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6
channels. It has complementary PWM outputs with programmable inserted dead times. It
can also be seen as a complete general-purpose timer. The 4 independent channels can be
used for:
 Input capture
 Output compare
 PWM generation (edge or center-aligned modes)
 One-pulse mode output
If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If
configured as the 16-bit PWM generator, it has full modulation capability (0-100%).
The counter can be frozen in debug mode.
Many features are shared with those of the standard timers which have the same
architecture. The advanced control timer can therefore work together with the other timers
via the Timer Link feature for synchronization or event chaining.

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3.11.2 General-purpose timers (TIM3, TIM14..17)

There are five synchronizable general-purpose timers embedded in the STM32F030x
devices (see Table 5 for differences). Each general-purpose timer can be used to generate
PWM outputs, or as simple time base.

TIM3
STM32F030x devices feature a synchronizable 4-channel general-purpose timer based on
a 16-bit auto-reload up/downcounter and a 16-bit prescaler. TIM3 features 4 independent
channels for input capture/output compare, PWM or one-pulse mode output. This gives up
to 12 input captures/output compares/PWMs on the largest packages.
The TIM3 general-purpose timer can work with the TIM1 advanced-control timer via the
Timer Link feature for synchronization or event chaining.
It provides independent DMA request generation.
The TIM3 timer is capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.
Its counter can be frozen in debug mode.

TIM14
This timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM14 features one single channel for input capture/output compare, PWM or one-pulse
mode output.
Its counter can be frozen in debug mode.

TIM15, TIM16 and TIM17

These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM15 has two independent channels, whereas TIM16 and TIM17 feature one single
channel for input capture/output compare, PWM or one-pulse mode output.
The TIM15, TIM16 and TIM17 timers can work together, and TIM15 can also operate with
TIM1 via the Timer Link feature for synchronization or event chaining.
TIM15 can be synchronized with TIM16 and TIM17.
TIM15, TIM16, and TIM17 have a complementary output with dead-time generation and
independent DMA request generation.
Their counters can be frozen in debug mode.

3.11.3 Basic timer TIM6

This timer is mainly used as a generic 16-bit time base.

3.11.4 Independent watchdog (IWDG)

The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with
user-defined refresh window. It is clocked from an independent 40 kHz internal RC and as it
operates independently from the main clock, it can operate in Stop and Standby modes. It
can be used either as a watchdog to reset the device when a problem occurs, or as a free

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running timer for application timeout management. It is hardware or software configurable

through the option bytes. The counter can be frozen in debug mode.

3.11.5 System window watchdog (WWDG)

The system window watchdog is based on a 7-bit downcounter that can be set as free
running. It can be used as a watchdog to reset the device when a problem occurs. It is
clocked from the APB clock (PCLK). It has an early warning interrupt capability and the
counter can be frozen in debug mode.

3.11.6 SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:
 A 24-bit down counter
 Autoreload capability
 Maskable system interrupt generation when the counter reaches 0
 Programmable clock source (HCLK or HCLK/8)

3.12 Real-time clock (RTC)

The RTC is an independent BCD timer/counter. Its main features are the following:
 Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format
 Automatically correction for 28, 29 (leap year), 30, and 31 day of the month
 Programmable alarm with wake up from Stop and Standby mode capability
 On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
 Digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal
inaccuracy
 2 anti-tamper detection pins with programmable filter. The MCU can be woken up from
Stop and Standby modes on tamper event detection.
 Timestamp feature which can be used to save the calendar content. This function can
triggered by an event on the timestamp pin, or by a tamper event. The MCU can be
woken up from Stop and Standby modes on timestamp event detection.
 Periodic wakeup from Stop/Standby
 Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
The RTC clock sources can be:
 A 32.768 kHz external crystal
 A resonator or oscillator
 The internal low-power RC oscillator (typical frequency of 40 kHz)
 The high-speed external clock divided by 32

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STM32F030x4 STM32F030x6 STM32F030x8 Functional overview

3.13 Inter-integrated circuit interfaces (I2C)

Up to two I2C interfaces (I2C1 and I2C2) can operate in multimaster or slave modes. Both
can support Standard mode (up to 100 kbit/s) or Fast mode (up to 400 kbit/s). I2C1 also
supports Fast Mode Plus (up to 1 Mbit/s) with 20 mA output drive.
Both support 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2
addresses, 1 with configurable mask). They also include programmable analog and digital
noise filters.

Table 6. Comparison of I2C analog and digital filters

Analog filter Digital filter

Pulse width of Programmable length from 1 to 15

 50 ns
suppressed spikes I2C peripheral clocks
1. Extra filtering capability vs.
Benefits Available in Stop mode standard requirements.
2. Stable length
Wakeup from Stop on address
Variations depending on
Drawbacks match is not available when digital
temperature, voltage, process
filter is enabled.

In addition, I2C1 provides hardware support for SMBUS 2.0 and PMBUS 1.1: ARP
capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeouts
verifications and ALERT protocol management.
The I2C interfaces can be served by the DMA controller.
Refer to Table 7 for the differences between I2C1 and I2C2.

Table 7. STM32F030x I2C implementation

I2C features(1) I2C1 I2C2

7-bit addressing mode X X

10-bit addressing mode X X

Standard mode (up to 100 kbit/s) X X

Fast mode (up to 400 kbit/s) X X

Fast Mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s) X -

SMBus X -

1. X = supported.

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22
Functional overview STM32F030x4 STM32F030x6 STM32F030x8

3.14 Universal synchronous/asynchronous receiver transmitters

(USART)
The device embeds up to two universal synchronous/asynchronous receiver transmitters
(USART1 and USART2), which communicate at speeds of up to 6 Mbit/s.
They provide hardware management of the CTS and RTS signals, multiprocessor
communication mode, master synchronous communication and single-wire half-duplex
communication mode. The USART1 supports also auto baud rate feature.
The USART interfaces can be served by the DMA controller.
Refer to Table 8 for the differences between USART1 and USART2.

Table 8. STM32F030x USART implementation

USART modes/features(1) USART1 USART2

Hardware flow control for modem X X

Continuous communication using DMA X X
Multiprocessor communication X X
Synchronous mode X X
Single-wire half-duplex communication X X
Receiver timeout interrupt X -
Auto baud rate detection X -
1. X = supported.

3.15 Serial peripheral interface (SPI)

Up to two SPIs are able to communicate up to 18 Mbits/s in slave and master modes in full-
duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame size is configurable from 4 bits to 16 bits.
Refer to Table 9 for the differences between SPI1 and SPI2.

Table 9. STM32F030x SPI implementation

SPI features(1) SPI1 SPI2

Hardware CRC calculation X X

Rx/Tx FIFO X X
NSS pulse mode X X
TI mode X X
1. X = supported.

3.16 Serial wire debug port (SW-DP)

An ARM SW-DP interface is provided to allow a serial wire debugging tool to be connected
to the MCU.

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STM32F030x4 STM32F030x6 STM32F030x8 Pinouts and pin descriptions

4 Pinouts and pin descriptions

Figure 3. LQFP64 64-pin package pinout

BOOT0

PC12

PC10
PC11

PA15
PA14
VDD
VSS

PD2
PB9
PB8

PB7
PB6
PB5
PB4
PB3
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VDD 1 48 PF7
PC13 2 47 PF6
PC14/OSC32_IN 3 46 PA13
PC15/OSC32_OUT 4 45 PA12
PF0/OSC_IN 5 44 PA11
PF1/OSC_OUT 6 43 PA10
NRST 7 42 PA9
PC0 8 41 PA8
LQFP64
PC1 9 40 PC9
PC2 10 39 PC8
PC3 11 38 PC7
VSSA 12 37 PC6
VDDA 13 36 PB15
PA0 14 35 PB14
PA1 15 34 PB13
PA2 16 33 PB12
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PF4
PF5

PC4
PC5
PB0
PB1
PB2
PB10

VSS
VDD
PA3

PA4
PA5
PA6
PA7

PB11

MS32729V1

1. The above figure shows the package top view.

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Pinouts and pin descriptions STM32F030x4 STM32F030x6 STM32F030x8

Figure 4. LQFP48 48-pin package pinout

BOOT0

PA15
PA14
VDD
VSS
PB9
PB8

PB7
PB6
PB5
PB4
PB3
48 47 46 45 44 43 42 41 40 39 38 37
VDD 1 36 PF7
PC13 2 35 PF6
PC14/OSC32_IN 3 34 PA13
PC15/OSC32_OUT 4 33 PA12
PF0/OSC_IN 5 32 PA11
PF1/OSC_OUT 6 31 PA10
LQFP48 PA9
NRST 7 30
VSSA 8 29 PA8
VDDA 9 28 PB15
PA0 10 27 PB14
PA1 11 26 PB13
PA2 12 25 PB12
13 14 15 16 17 18 19 20 21 22 23 24
PA5
PA6
PA3
PA4

PA7

VDD
PB0
PB1
PB2

VSS
PB10
PB11
MS32730V1

1. The above figure shows the package top view.

Figure 5. LQFP32 32-pin package pinout

BOOT0

PA15
VSS

PB7
PB6
PB5
PB4
PB3

32 31 30 29 28 27 26 25
VDD 1 24 PA14
PF0/OSC_IN 2 23 PA13
PF1/OSC_OUT 3 22 PA12
NRST 4 LQFP32 21 PA11
VDDA 5 20 PA10
PA0 6 19 PA9
PA1 7 18 PA8
PA2 8 17 VDD
9 10 11 12 13 14 15 16
PA5
PA6
PA3
PA4

PA7
PB0
PB1
VSS

MS32144V1

1. The above figure shows the package top view.

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STM32F030x4 STM32F030x6 STM32F030x8 Pinouts and pin descriptions

Figure 6. TSSOP20 package pinout

BOOT0 1 20 PA14
PF0/OSC_IN 2 19 PA13
PF1/OSC_OUT 3 18 PA10
NRST 4 17 PA 9
VDDA 5 16 VDD
PA0 6 15 VSS
PA1 7 14 PB1
PA2 8 13 PA7
PA3 9 12 PA6
PA4 10 11 PA5

MS32731V1

1. The above figure shows the package top view.

Table 10. Legend/abbreviations used in the pinout table

Name Abbreviation Definition

Unless otherwise specified in brackets below the pin name, the pin function
Pin name
during and after reset is the same as the actual pin name
S Supply pin
Pin type I Input only pin
I/O Input / output pin
FT 5 V tolerant I/O
FTf 5 V tolerant I/O, FM+ capable
TTa 3.3 V tolerant I/O directly connected to ADC
I/O structure
TC Standard 3.3V I/O
B Dedicated BOOT0 pin
RST Bidirectional reset pin with embedded weak pull-up resistor
Unless otherwise specified by a note, all I/Os are set as floating inputs during
Notes
and after reset.

Alternate functions Functions selected through GPIOx_AFR registers

Pin
functions
Additional functions Functions directly selected/enabled through peripheral registers

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Pinouts and pin descriptions STM32F030x4 STM32F030x6 STM32F030x8

Table 11. Pin definitions

Pin number Pin functions

I/O structure
Pin type
Pin name

TSSOP20
LQFP64

LQFP48

LQFP32
(function after Notes
reset) Alternate functions Additional functions

1 1 - - VDD S Complementary power supply

RTC_TAMP1,
(1) RTC_TS,
2 2 - - PC13 I/O TC -
RTC_OUT,
WKUP2
PC14-OSC32_IN (1)
3 3 - - I/O TC - OSC32_IN
(PC14)
PC15-OSC32_OUT (1)
4 4 - - I/O TC - OSC32_OUT
(PC15)
PF0-OSC_IN
5 5 2 2 I/O FT - OSC_IN
(PF0)
PF1-OSC_OUT
6 6 3 3 I/O FT - OSC_OUT
(PF1)
Device reset input / internal reset output
7 7 4 4 NRST I/O RST
(active low)
8 - - - PC0 I/O TTa EVENTOUT ADC_IN10
9 - - - PC1 I/O TTa EVENTOUT ADC_IN11
10 - - - PC2 I/O TTa EVENTOUT ADC_IN12
11 - - - PC3 I/O TTa EVENTOUT ADC_IN13
12 8 - - VSSA S Analog ground
13 9 5 5 VDDA S Analog power supply
ADC_IN0,
USART1_CTS(2),
14 10 6 6 PA0 I/O TTa RTC_TAMP2,
USART2_CTS(3)
WKUP1
USART1_RTS(2),
15 11 7 7 PA1 I/O TTa USART2_RTS(3), ADC_IN1
EVENTOUT
USART1_TX(2),
16 12 8 8 PA2 I/O TTa USART2_TX(3), ADC_IN2
TIM15_CH1(3)
USART1_RX(2),
17 13 9 9 PA3 I/O TTa USART2_RX(3), ADC_IN3
TIM15_CH2(3)
18 - - - PF4 I/O FT EVENTOUT -
19 - - - PF5 I/O FT EVENTOUT -

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STM32F030x4 STM32F030x6 STM32F030x8 Pinouts and pin descriptions

Table 11. Pin definitions (continued)

Pin number Pin functions

I/O structure
Pin type
Pin name

TSSOP20
LQFP64

LQFP48

LQFP32
(function after Notes
reset) Alternate functions Additional functions

SPI1_NSS,
USART1_CK(2)
20 14 10 10 PA4 I/O TTa ADC_IN4
USART2_CK(3),
TIM14_CH1

21 15 11 11 PA5 I/O TTa SPI1_SCK ADC_IN5

SPI1_MISO,
TIM3_CH1,
22 16 12 12 PA6 I/O TTa TIM1_BKIN, ADC_IN6
TIM16_CH1,
EVENTOUT
SPI1_MOSI,
TIM3_CH2,
TIM14_CH1,
23 17 13 13 PA7 I/O TTa ADC_IN7
TIM1_CH1N,
TIM17_CH1,
EVENTOUT
24 - - - PC4 I/O TTa EVENTOUT ADC_IN14
25 - - - PC5 I/O TTa - ADC_IN15
TIM3_CH3,
26 18 14 - PB0 I/O TTa TIM1_CH2N, ADC_IN8
EVENTOUT
TIM3_CH4,
27 19 15 14 PB1 I/O TTa TIM14_CH1, ADC_IN9
TIM1_CH3N
(4)
28 20 - - PB2 I/O FT - -
I2C1_SCL(2),
29 21 - - PB10 I/O FT -
I2C2_SCL(3)
I2C1_SDA(2),
30 22 - - PB11 I/O FT I2C2_SDA(3), -
EVENTOUT
31 23 16 - VSS S Ground
32 24 17 16 VDD S Digital power supply
SPI1_NSS(2),
SPI2_NSS(3),
33 25 - - PB12 I/O FT -
TIM1_BKIN,
EVENTOUT

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Pinouts and pin descriptions STM32F030x4 STM32F030x6 STM32F030x8

Table 11. Pin definitions (continued)

Pin number Pin functions

I/O structure
Pin type
Pin name

TSSOP20
LQFP64

LQFP48

LQFP32
(function after Notes
reset) Alternate functions Additional functions

SPI1_SCK(2),
34 26 - - PB13 I/O FT SPI2_SCK(3), -
TIM1_CH1N
SPI1_MISO(2),
SPI2_MISO(3),
35 27 - - PB14 I/O FT -
TIM1_CH2N,
TIM15_CH1(3)
SPI1_MOSI(2),
SPI2_MOSI(3),
36 28 - - PB15 I/O FT TIM1_CH3N, RTC_REFIN
TIM15_CH1N(3),
TIM15_CH2(3)
37 - - - PC6 I/O FT TIM3_CH1 -
38 - - - PC7 I/O FT TIM3_CH2 -
39 - - - PC8 I/O FT TIM3_CH3 -
40 - - - PC9 I/O FT TIM3_CH4 -
USART1_CK,
TIM1_CH1,
41 29 18 - PA8 I/O FT -
EVENTOUT,
MCO
USART1_TX,
TIM1_CH2,
42 30 19 17 PA9 I/O FT -
TIM15_BKIN(3)
I2C1_SCL(2)
USART1_RX,
TIM1_CH3,
43 31 20 18 PA10 I/O FT -
TIM17_BKIN
I2C1_SDA(2)
USART1_CTS,
44 32 21 - PA11 I/O FT TIM1_CH4, -
EVENTOUT
USART1_RTS,
45 33 22 - PA12 I/O FT TIM1_ETR, -
EVENTOUT
PA13 (5) IR_OUT,
46 34 23 19 I/O FT -
(SWDIO) SWDIO
I2C1_SCL(2),
47 35 - - PF6 I/O FT -
I2C2_SCL(3)

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STM32F030x4 STM32F030x6 STM32F030x8 Pinouts and pin descriptions

Table 11. Pin definitions (continued)

Pin number Pin functions

I/O structure
Pin type
Pin name

TSSOP20
LQFP64

LQFP48

LQFP32
(function after Notes
reset) Alternate functions Additional functions

I2C1_SDA(2),
48 36 - - PF7 I/O FT -
I2C2_SDA(3)
USART1_TX(2),
PA14 (5)
49 37 24 20 I/O FT USART2_TX(3), -
(SWCLK)
SWCLK
SPI1_NSS,
USART1_RX(2),
50 38 25 - PA15 I/O FT -
USART2_RX(3),
EVENTOUT
51 - - - PC10 I/O FT - -
52 - - - PC11 I/O FT - -
53 - - - PC12 I/O FT - -
54 - - - PD2 I/O FT TIM3_ETR -
SPI1_SCK,
55 39 26 - PB3 I/O FT -
EVENTOUT
SPI1_MISO,
56 40 27 - PB4 I/O FT TIM3_CH1, -
EVENTOUT
SPI1_MOSI,
I2C1_SMBA,
57 41 28 - PB5 I/O FT -
TIM16_BKIN,
TIM3_CH2
I2C1_SCL,
58 42 29 - PB6 I/O FTf USART1_TX, -
TIM16_CH1N
I2C1_SDA,
59 43 30 - PB7 I/O FTf USART1_RX, -
TIM17_CH1N
60 44 31 1 BOOT0 I B Boot memory selection

(5) I2C1_SCL,
61 45 - - PB8 I/O FTf -
TIM16_CH1
I2C1_SDA,
IR_OUT,
62 46 - - PB9 I/O FTf -
TIM17_CH1,
EVENTOUT

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Pinouts and pin descriptions STM32F030x4 STM32F030x6 STM32F030x8

Table 11. Pin definitions (continued)

Pin number Pin functions

I/O structure
Pin type
Pin name

TSSOP20
LQFP64

LQFP48

LQFP32
(function after Notes
reset) Alternate functions Additional functions

63 47 32 15 VSS S Ground
64 48 1 16 VDD S Digital power supply
1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount
of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF.
- These GPIOs must not be used as current sources (e.g. to drive an LED).
2. This feature is available on STM32F030x6 and STM32F030x4 devices only.
3. This feature is available on STM32F030x8 devices only.
4. On LQFP32 package, PB2 and PB8 should be treated as unconnected pins (even when they are not
available on the package, they are not forced to a defined level by hardware).
5. After reset, these pins are configured as SWDIO and SWCLK alternate functions, and the internal pull-up on
SWDIO pin and internal pull-down on SWCLK pin are activated.

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 STM32F030x4 STM32F030x6 STM32F030x8
Table 12. Alternate functions selected through GPIOA_AFR registers for port A
Pin name AF0 AF1 AF2 AF3 AF4 AF5 AF6

USART1_CTS(1)
PA0 - - - - - -
USART2_CTS(2)
USART1_RTS(1)
PA1 EVENTOUT - - - - -
USART2_RTS(2)
USART1_TX(1)
PA2 TIM15_CH1(2) - - - - -
USART2_TX(2)
USART1_RX(1)
PA3 TIM15_CH2(2) - - - - -
USART2_RX(2)
USART1_CK(1)
PA4 SPI1_NSS - - TIM14_CH1 - -
USART2_CK(2)
DocID024849 Rev 1

PA5 SPI1_SCK - - - - - -
PA6 SPI1_MISO TIM3_CH1 TIM1_BKIN - - TIM16_CH1 EVENTOUT
PA7 SPI1_MOSI TIM3_CH2 TIM1_CH1N - TIM14_CH1 TIM17_CH1 EVENTOUT
PA8 MCO USART1_CK TIM1_CH1 EVENTOUT - - -
(2)
PA9 TIM15_BKIN USART1_TX TIM1_CH2 - I2C1_SCL(1) - -
PA10 TIM17_BKIN USART1_RX TIM1_CH3 - I2C1_SDA(1) - -
PA11 EVENTOUT USART1_CTS TIM1_CH4 - - - -

Pinouts and pin descriptions

PA12 EVENTOUT USART1_RTS TIM1_ETR - - - -
PA13 SWDIO IR_OUT - - - - -
USART1_TX(1)
PA14 SWCLK - - - - -
USART2_TX(2)
USART1_RX(1)
PA15 SPI1_NSS - EVENTOUT - - -
USART2_RX(2)
1. This feature is available on STM32F030x6 and STM32F030x4 devices only.
31/88

2. This feature is available on STM32F030x8 devices only.

32/88

Pinouts and pin descriptions

Table 13. Alternate functions selected through GPIOB_AFR registers for port B
Pin name AF0 AF1 AF2 AF3

PB0 EVENTOUT TIM3_CH3 TIM1_CH2N -

PB1 TIM14_CH1 TIM3_CH4 TIM1_CH3N -
PB2 - - - -
PB3 SPI1_SCK EVENTOUT - -
PB4 SPI1_MISO TIM3_CH1 EVENTOUT -
PB5 SPI1_MOSI TIM3_CH2 TIM16_BKIN I2C1_SMBA
PB6 USART1_TX I2C1_SCL TIM16_CH1N -
PB7 USART1_RX I2C1_SDA TIM17_CH1N -
PB8 - I2C1_SCL TIM16_CH1 -
DocID024849 Rev 1

PB9 IR_OUT I2C1_SDA TIM17_CH1 EVENTOUT

(1)
I2C1_SCL
PB10 - - -
I2C2_SCL(2)
I2C1_SDA(1)
PB11 EVENTOUT - -

STM32F030x4 STM32F030x6 STM32F030x8

I2C2_SDA(2)
SPI1_NSS(1)
PB12 EVENTOUT TIM1_BKIN -
SPI2_NSS(2)
SPI1_SCK(1)
PB13 - TIM1_CH1N -
SPI2_SCK(2)
SPI1_MISO(1)
PB14 TIM15_CH1(2) TIM1_CH2N -
SPI2_MISO(2)
SPI1_MOSI(1)
PB15 TIM15_CH2(2) TIM1_CH3N TIM15_CH1N(2)
SPI2_MOSI(2)
1. This feature is available on STM32F030x6 and STM32F030x4 devices only.
2. This feature is available on STM32F030x8 devices only.
STM32F030x4 STM32F030x6 STM32F030x8 Memory mapping

5 Memory mapping

Figure 7. STM32F030x memory map

0xFFFF FFFF

0x4800 17FF
AHB2
7 0x4800 0000
0xE010 0000
Cortex- M Internal
0xE000 0000 Peripherals

reserved
6

0xC000 0000

0x4002 43FF
")#
5 0x4002 0000

reserved
0xA000 0000

0x4001 8000

4 0x1FFF FFFF "1#

reserved
0x1FFF FC00
0x4001 0000
Option Bytes
0x8000 0000 0x1FFF F800

reserved
System memory
0x4000 8000
3 0x1FFF EC00

"1#

0x6000 0000
0x4000 0000

reserved
2

0x4000 0000 Peripherals

0x0801 0000

1
Flash memory

0x2000 0000 SRAM

Y


reserved
CODE
0 0x0001 0000

'MBTI
TZTUFN
NFNPSZ
0x0000 0000 PS
43".
EFQFOEJOH
PO
#005
DPOGJHVSBUJPO

0x0000 0000

Reserved

MS19840V1

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35
Memory mapping STM32F030x4 STM32F030x6 STM32F030x8

Table 14. STM32F030x peripheral register boundary addresses

Bus Boundary address Size Peripheral

0x4800 1800 - 0x5FFF FFFF ~384 MB Reserved

0x4800 1400 - 0x4800 17FF 1 KB GPIOF
0x4800 1000 - 0x4800 13FF 1 KB Reserved
0x4800 0C00 - 0x4800 0FFF 1 KB GPIOD
AHB2
0x4800 0800 - 0x4800 0BFF 1 KB GPIOC
0x4800 0400 - 0x4800 07FF 1 KB GPIOB
0x4800 0000 - 0x4800 03FF 1 KB GPIOA
0x4002 4400 - 0x47FF FFFF ~128 MB Reserved
0x4002 3400 - 0x4002 43FF 4 KB Reserved
0x4002 3000 - 0x4002 33FF 1 KB CRC
0x4002 2400 - 0x4002 2FFF 3 KB Reserved
0x4002 2000 - 0x4002 23FF 1 KB FLASH Interface
AHB1
0x4002 1400 - 0x4002 1FFF 3 KB Reserved
0x4002 1000 - 0x4002 13FF 1 KB RCC
0x4002 0400 - 0x4002 0FFF 3 KB Reserved
0x4002 0000 - 0x4002 03FF 1 KB DMA
0x4001 8000 - 0x4001 FFFF 32 KB Reserved
0x4001 5C00 - 0x4001 7FFF 9 KB Reserved
0x4001 5800 - 0x4001 5BFF 1 KB DBGMCU
0x4001 4C00 - 0x4001 57FF 3 KB Reserved
0x4001 4800 - 0x4001 4BFF 1 KB TIM17
0x4001 4400 - 0x4001 47FF 1 KB TIM16
0x4001 4000 - 0x4001 43FF 1 KB TIM15(1)
0x4001 3C00 - 0x4001 3FFF 1 KB Reserved
0x4001 3800 - 0x4001 3BFF 1 KB USART1
APB
0x4001 3400 - 0x4001 37FF 1 KB Reserved
0x4001 3000 - 0x4001 33FF 1 KB SPI1
0x4001 2C00 - 0x4001 2FFF 1 KB TIM1
0x4001 2800 - 0x4001 2BFF 1 KB Reserved
0x4001 2400 - 0x4001 27FF 1 KB ADC
0x4001 0800 - 0x4001 23FF 7 KB Reserved
0x4001 0400 - 0x4001 07FF 1 KB EXTI
0x4001 0000 - 0x4001 03FF 1 KB SYSCFG
0x4000 8000 - 0x4000 FFFF 32 KB Reserved

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STM32F030x4 STM32F030x6 STM32F030x8 Memory mapping

Table 14. STM32F030x peripheral register boundary addresses (continued)

Bus Boundary address Size Peripheral

0x4000 7400 - 0x4000 7FFF 3 KB Reserved

0x4000 7000 - 0x4000 73FF 1 KB PWR
0x4000 5C00 - 0x4000 6FFF 5 KB Reserved
0x4000 5800 - 0x4000 5BFF 1 KB I2C2(1)
0x4000 5400 - 0x4000 57FF 1 KB I2C1
0x4000 4800 - 0x4000 53FF 3 KB Reserved
0x4000 4400 - 0x4000 47FF 1 KB USART2(1)
0x4000 3C00 - 0x4000 43FF 2 KB Reserved
0x4000 3800 - 0x4000 3BFF 1 KB SPI2(1)
0x4000 3400 - 0x4000 37FF 1 KB Reserved
APB
0x4000 3000 - 0x4000 33FF 1 KB IWDG
0x4000 2C00 - 0x4000 2FFF 1 KB WWDG
0x4000 2800 - 0x4000 2BFF 1 KB RTC
0x4000 2400 - 0x4000 27FF 1 KB Reserved
0x4000 2000 - 0x4000 23FF 1 KB TIM14
0x4000 1400 - 0x4000 1FFF 3 KB Reserved
0x4000 1000 - 0x4000 13FF 1 KB TIM6(1)
0x4000 0800 - 0x4000 0FFF 2 KB Reserved
0x4000 0400 - 0x4000 07FF 1 KB TIM3
0x4000 0000 - 0x4000 03FF 1 KB Reserved
1. This feature is available on STM32F030x8 devices only. For STM32F030x6 and
STM32F060x4, the area is Reserved.

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35
Electrical characteristics STM32F030x4 STM32F030x6 STM32F030x8

6 Electrical characteristics

6.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.

6.1.1 Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3).

6.1.2 Typical values

Unless otherwise specified, typical data are based on TA = 25 °C, VDD = VDDA = 3.3 V. They
are given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2).

6.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.

6.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 8.

6.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 9.

Figure 8. Pin loading conditions Figure 9. Pin input voltage

MCU pin MCU pin

C = 50 pF VIN

MS19210V1 MS19211V1

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6.1.6 Power supply scheme

Figure 10. Power supply scheme

LSE, RTC,
Wake-up logic

Level shifter
OUT
IO
GP I/Os Logic
IN Kernel logic
(CPU,
Digital
VDD
& Memories)
2 × VDD
Regulator
2 × 100 nF
+ 1 × 4.7 μF 2 × VSS

VDDA
VDDA

VREF+ Analog:
10 nF ADC
VREF- RCs, PLL,
+ 1 μF ...
VSSA

MS32141V1

Caution: Each power supply pair (VDD/VSS, VDDA/VSSA etc.) must be decoupled with filtering ceramic
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure the good functionality of
the device.

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6.1.7 Current consumption measurement

Figure 11. Current consumption measurement scheme

IDD
VDD

IDDA
VDDA

MS32142V1

6.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 15: Voltage characteristics,
Table 16: Current characteristics, and Table 17: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.

Table 15. Voltage characteristics(1)

Symbol Ratings Min Max Unit

External main supply voltage (including

VDD–VSS –0.3 4.0 V
VDDA and VDD)
VDD–VDDA Allowed voltage difference for VDD > VDDA - 0.4 V
Input voltage on FT and FTf pins VSS  0.3 VDD + 4.0 V
VIN(2) Input voltage on TTa pins VSS  0.3 4.0 V
Input voltage on any other pin VSS 0.3 4.0 V
|VDDx| Variations between different VDD power pins - 50 mV
Variations between all the different ground
|VSSX VSS| - 50 mV
pins
Electrostatic discharge voltage (human see Section 6.3.12: Electrical
VESD(HBM)
body model) sensitivity characteristics
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the
external power supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 16: Current characteristics for the
maximum allowed injected current values.

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Table 16. Current characteristics

Symbol Ratings Max. Unit

Total current into sum of all VDD_x and VDDSDx power lines
IVDD 120
(source)(1)
Total current out of sum of all VSS_x and VSSSD ground lines
IVSS -120
(sink)(1)
IVDD(PIN) Maximum current into each VDD_x or VDDSDx power pin (source)(1) 100
(1)
IVSS(PIN) Maximum current out of each VSS_x or VSSSD ground pin (sink) -100
Output current sunk by any I/O and control pin 25
IIO(PIN)
Output current source by any I/O and control pin -25 mA

Total output current sunk by sum of all IOs and control pins(2) 80
IIO(PIN)
(2)
Total output current sourced by sum of all IOs and control pins -80
(3)
Injected current on FT, FTf and B pins -5/+0
IINJ(PIN) (4)
Injected current on TC and RST pin ±5
Injected current on TTa pins(5) ±5
IINJ(PIN) Total injected current (sum of all I/O and control pins)(6) ± 25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current
must not be sunk/sourced between two consecutive power supply pins referring to high pin count QFP
packages.
3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified
maximum value.
4. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer to Table 15: Voltage characteristics for the maximum allowed input voltage values.
5. A positive injection is induced by VIN>VDDA while a negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer also to Table 15: Voltage characteristics for the maximum allowed input voltage
values. Negative injection disturbs the analog performance of the device. See note (2) below Table 50: ADC
accuracy.
6. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values).

Table 17. Thermal characteristics

Symbol Ratings Value Unit

TSTG Storage temperature range –65 to +150 °C

TJ Maximum junction temperature 150 °C

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6.3 Operating conditions

6.3.1 General operating conditions

Table 18. General operating conditions

Symbol Parameter Conditions Min Max Unit

fHCLK Internal AHB clock frequency 0 48

MHz
fPCLK Internal APB clock frequency 0 48
VDD Standard operating voltage 2.4 3.6 V
Must have a potential equal to or
VDDA Analog operating voltage 2.4 3.6 V
higher than VDD
Input voltage on FT and FTf pins VSS –0.3 VDD +4.0 V
(1)
VIN Input voltage on TTa pins VSS –0.3 4.0 V
Input voltage on any other pin VSS –0.3 4.0 V
LQFP64 - 444

Power dissipation at TA = 85 °C LQFP48 - 364

PD mW
for suffix 6(2) LQFP32 - 357
TSSOP20 - 182

Ambient temperature for 6 suffix Maximum power dissipation –40 85

TA °C
version Low power dissipation (3)
–40 105
TJ Junction temperature range 6 suffix version –40 105 °C
1. VIN maximum must always be respected. Refer to Table 16: Current characteristics for the maximum allowed
injected current values.
2. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax.
3. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax.

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6.3.2 Operating conditions at power-up / power-down

The parameters given in Table 19 are derived from tests performed under the ambient
temperature condition summarized in Table 18.

Table 19. Operating conditions at power-up / power-down

Symbol Parameter Conditions Min Max Unit

VDD rise time rate 0 

tVDD
VDD fall time rate 20 
µs/V
VDDA rise time rate 0 
tVDDA
VDDA fall time rate 20 

6.3.3 Embedded reset and power control block characteristics

The parameters given in Table 20 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 18: General operating
conditions.

Table 20. Embedded reset and power control block characteristics

Symbol Parameter Conditions Min Typ Max Unit

Power on/power down Falling edge 1.8(2) 1.88 2.06 V

VPOR/PDR(1)
reset threshold Rising edge 1.84 1.92 2.10 V
VPDRhyst(1) PDR hysteresis - 40 - mV
tRSTTEMPO(3) Reset temporization 1.5 2.5 4.5 ms
1. The PDR detector monitors VDD and also VDDA (if kept enabled in the option bytes). The POR
detector monitors only VDD.
2. The product behavior is guaranteed by design down to the minimum VPOR/PDR value.
3. Guaranteed by design, not tested in production.

6.3.4 Embedded reference voltage

The parameters given in Table 21 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 18: General operating
conditions.

Table 21. Embedded internal reference voltage

Symbol Parameter Conditions Min Typ Max Unit

VREFINT Internal reference voltage –40 °C < TA < +85 °C 1.16 1.2 1.24(1) V
ADC sampling time when
TS_vrefint (2) reading the internal - 5.1 17.1(3) µs
reference voltage

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Table 21. Embedded internal reference voltage (continued)

Symbol Parameter Conditions Min Typ Max Unit

Internal reference voltage

VREFINT spread over the temperature VDDA = 3 V ±10 mV - - 10(3) mV
range

TCoeff Temperature coefficient - - 100(3) ppm/°C

1. Data based on characterization results, not tested in production.
2. Shortest sampling time can be determined in the application by multiple iterations.
3. Guaranteed by design, not tested in production.

6.3.5 Supply current characteristics

The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 11: Current consumption
measurement scheme.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to CoreMark code.

Typical and maximum current consumption

The MCU is placed under the following conditions:
 All I/O pins are in input mode with a static value at VDD or VSS (no load)
 All peripherals are disabled except when explicitly mentioned
 The Flash memory access time is adjusted to the fHCLK frequency (0 wait state from 0
to 24 MHz and 1 wait state above 24 MHz)
 Prefetch is ON when the peripherals are enabled, otherwise it is OFF (to enable
prefetch the PRFTBE bit in the FLASH_ACR register must be set before clock setting
and bus prescaling)
 When the peripherals are enabled fPCLK = fHCLK
The parameters given in Table 22 to are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 18: General operating
conditions.

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Table 22. Typical and maximum current consumption from VDD supply at VDD = 3.6
All peripherals enabled

Symbol Parameter Conditions fHCLK Max @ TA(1) Unit

Typ
85 °C

Supply current in 48 MHz 22 22.8

Run mode, code HSI clock, PLL on
24 MHz 12.2 13.2
executing from
Flash HSI clock, PLL off 8 MHz 4.4 5.2
Supply current in 48 MHz 22.2 23.2
Run mode, code HSI clock, PLL on
IDD 24 MHz 11.2 12.2 mA
executing from
RAM HSI clock, PLL off 8 MHz 4.0 4.5
Supply current in 48 MHz 14 15.3
Sleep mode, code HSI clock, PLL on
24 MHz 7.3 7.8
executing from
Flash or RAM HSI clock, PLL off 8 MHz 2.6 2.9
1. Data based on characterization results, not tested in production unless otherwise specified.

Table 23. Typical and maximum current consumption from the VDDA supply
VDDA = 3.6 V

Symbol Parameter Conditions(1) fHCLK Unit

Max @ TA(2)
Typ
85 °C

HSE bypass, PLL on 48 MHz 175 215

Supply current
8 MHz 3.9 4.9
in Run mode, HSE bypass, PLL off
code executing 1 MHz 3.9 4.1
from Flash or
HSI clock, PLL on 48 MHz 244 275
RAM
HSI clock, PLL off 8 MHz 85 105
IDDA µA
HSE bypass, PLL on 48 MHz 174 215
Supply current
8 MHz 3.9 4.9
in Sleep mode, HSE bypass, PLL off
code executing 1 MHz 3.9 4.9
from Flash or
HSI clock, PLL on 48 MHz 244 299
RAM
HSI clock, PLL off 8 MHz 85 105
1. Current consumption from the VDDA supply is independent of whether the peripherals are on or
off. Furthermore when the PLL is off, IDDA is independent from the frequency.
2. Data based on characterization results, not tested in production.

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Table 24. Typical and maximum VDD consumption in Stop and Standby modes
Typ @VDD
Max(1)
(VDD = VDDA)
Symbol Parameter Conditions Unit
3.6 V TA = 85 °C

Regulator in run mode, all

19 48
Supply current in oscillators OFF
Stop mode Regulator in low-power mode, all
IDD 5 32 µA
oscillators OFF
Supply current in
LSI ON and IWDG ON 2 -
Standby mode
1. Data based on characterization results, not tested in production unless otherwise specified.

Table 25. Typical and maximum VDDA consumption in Stop and Standby modes
Typ @VDD
(VDD = Max(1) Unit
Symbol Parameter Conditions VDDA)

3.6 V TA = 85 °C

Regulator in run or low

VDDA monitoring ON

Supply current in
power mode, 2.9 3.5
Stop mode
all oscillators OFF

LSI ON and IWDG ON

3.3 -
Supply current in
Standby mode
LSI OFF and IWDG OFF 2.8 3.5
IDDA µA
VDDA monitoring OFF

Regulator in run mode or

Supply current in
low power, 1.7 -
Stop mode
all oscillators OFF

LSI ON and IWDG ON

2.3 -
Supply current in
Standby mode
LSI OFF and IWDG OFF 1.4 -

1. Data based on characterization results, not tested in production.

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Typical current consumption

The MCU is placed under the following conditions:
 VDD=VDDA=3.3 V
 All I/O pins are in analog input configuration
 The Flash access time is adjusted to fHCLK frequency (0 wait states from 0 to 24 MHz,
1 wait state above)
 Prefetch is ON when the peripherals are enabled, otherwise it is OFF
 When the peripherals are enabled, fPCLK = fHCLK
 PLL is used for frequencies greater than 8 MHz
 AHB prescaler of 2, 4, 8 and 16 is used for the frequencies 4 MHz, 2 MHz, 1 MHz and
500 kHz respectively
 A development tool is connected to the board and the parasitic pull-up current is
around 30 µA

Table 26. Typical current consumption in Run mode, code with data processing
running from Flash
Typ
Symbol Parameter Conditions fHCLK Peripherals Peripherals Unit
enabled disabled

Supply current in Run Running from 48 MHz 23.3 11.5

IDD HSE crystal clock mA
mode from VDD supply 8 MHz 4.5 3.0
8 MHz, code
Supply current in Run executing from 48 MHz 158 158
IDDA µA
mode from VDDA supply Flash 8 MHz 2.43 2.43

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I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 44: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption measured previously (see
Table 26: Typical current consumption in Run mode, code with data processing running
from Flash), the I/Os used by an application also contribute to the current consumption.
When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O
pin circuitry and to charge/discharge the capacitive load (internal or external) connected to
the pin:

I SW = V DD  f SW  C

where
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDD is the MCU supply voltage
fSW is the I/O switching frequency
C is the total capacitance seen by the I/O pin: C = CINT+ CEXT + CS
CS is the PCB board capacitance including the pad pin.
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.

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Table 27. Switching output I/O current consumption

I/O toggling
Symbol Parameter Conditions(1) frequency Typ Unit
(fSW)

4 MHz 0.18
8 MHz 0.37
VDD = 3.3 V
CEXT = 0 pF 16 MHz 0.76
C = CINT + CEXT+ CS
24 MHz 1.39
48 MHz 2.188

I/O current 4 MHz 0.49

ISW mA
consumption VDD = 3.3 V 8 MHz 0.94
CEXT = 22 pF
C = CINT + CEXT+ CS 16 MHz 2.38
24 MHz 3.99
VDD = 3.3 V 4 MHz 0.81
CEXT = 47 pF
8 MHz 1.7
C = CINT + CEXT+ CS
C = Cint 16 MHz 3.67
1. CS = 7 pF (estimated value)

6.3.6 Wakeup time from low-power mode

The wakeup times given in Table 28 is measured on a wakeup phase with a 8-MHz HSI RC
oscillator. The event used to wake up the device depends from the current operating mode:
 Stop or sleep mode: the wakeup event is WFE.
 The wakeup pin used in stop and sleep mode is PA0 and in standby mode is PA1.
All timings are derived from tests performed under ambient temperature and VDD supply
voltage conditions summarized in Table 18: General operating conditions.

Table 28. Low-power mode wakeup timings

Typ @VDD
Symbol Parameter Conditions Max Unit
= 3.3 V

tWUSTOP Wakeup from Stop mode Regulator in run mode 4.2 5

µs
tWUSTANDBY Wakeup from Standby mode 50.96 -
tWUSLEEP Wakeup from Sleep mode 1.1 -

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6.3.7 External clock source characteristics

High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 6.3.14. However,
the recommended clock input waveform is shown in Figure 12: High-speed external clock
source AC timing diagram.

Table 29. High-speed external user clock characteristics

Symbol Parameter(1) Conditions Min Typ Max Unit

User external clock source

fHSE_ext 1 8 32 MHz
frequency
VHSEH OSC_IN input pin high level voltage 0.7VDD - VDD
V
VHSEL OSC_IN input pin low level voltage VSS - 0.3VDD
tw(HSEH)
OSC_IN high or low time 15 - -
tw(HSEL)
ns
tr(HSE)
OSC_IN rise or fall time - - 20
tf(HSE)
1. Guaranteed by design, not tested in production.

Figure 12. High-speed external clock source AC timing diagram

tW(HSEH)

VHSEH
90%
10%
VHSEL

tr(HSE) t
tf(HSE) tW(HSEL)
THSE

MS19214V2

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Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 6.3.14. However,
the recommended clock input waveform is shown in Figure 13.

Table 30. Low-speed external user clock characteristics

Symbol Parameter(1) Conditions Min Typ Max Unit

User External clock source

fLSE_ext - 32.768 1000 kHz
frequency
OSC32_IN input pin high level
VLSEH 0.7VDD - VDD
voltage
V
OSC32_IN input pin low level
VLSEL VSS - 0.3VDD
voltage
tw(LSEH)
OSC32_IN high or low time 450 - -
tw(LSEL)
ns
tr(LSE)
OSC32_IN rise or fall time - - 50
tf(LSE)
1. Guaranteed by design, not tested in production.

Figure 13. Low-speed external clock source AC timing diagram

tW(LSEH)

VLSEH
90%
10%
VLSEL

tr(LSE) t
tf(LSE) tW(LSEL)
TLSE

MS19215V2

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High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 32 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in Table 31. In the
application, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins in order to minimize output distortion and startup stabilization time. Refer
to the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).

Table 31. HSE oscillator characteristics

Symbol Parameter Conditions(1) Min(2) Typ Max(2) Unit

fOSC_IN Oscillator frequency 4 8 32 MHz

RF Feedback resistor - 200 - k
During startup(3) - 8.5
VDD=3.3 V, Rm= 45,
- 0.5 -
IDD HSE current consumption CL=10 pF@8 MHz mA
VDD=3.3 V, Rm= 30,
- 1.5 -
CL=20 pF@32 MHz
gm Oscillator transconductance Startup 10 - - mA/V
(4)
tSU(HSE) Startup time VDD is stabilized - 2 - ms
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. Guaranteed by design, not tested in production.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a
stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator
and it can vary significantly with the crystal manufacturer

For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 14). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2.
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.

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Figure 14. Typical application with an 8 MHz crystal

Resonator with
integrated capacitors
CL1
OSC_IN fHSE
Bias
8 MH z controlled
RF
resonator gain
OSC_OU T
REXT(1)
CL2

MS19876V1

1. REXT value depends on the crystal characteristics.

Low-speed external clock generated from a crystal resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator
oscillator. All the information given in this paragraph are based on design simulation results
obtained with typical external components specified in Table 32. In the application, the
resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).

Table 32. LSE oscillator characteristics (fLSE = 32.768 kHz)

Symbol Parameter Conditions(1) Min(2) Typ Max(2) Unit

LSEDRV[1:0]=00
- 0.5 -
lower driving capability
LSEDRV[1:0]= 01
- 0.8 -
medium low driving capability
IDD LSE current consumption µA
LSEDRV[1:0] = 10
- 1.1 -
medium high driving capability
LSEDRV[1:0]=11
- 1.4 -
higher driving capability
LSEDRV[1:0]=00
5 - -
lower driving capability
LSEDRV[1:0]= 01
8 - -
Oscillator medium low driving capability
gm µA/V
transconductance LSEDRV[1:0] = 10
15 - -
medium high driving capability
LSEDRV[1:0]=11
25 - -
higher driving capability
tSU(LSE)(3) Startup time VDD is stabilized - 2 - s
1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator
design guide for ST microcontrollers”.
2. Guaranteed by design, not tested in production.
3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz
oscillation is reached. This value is measured for a standard crystal and it can vary significantly with the
crystal manufacturer

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Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.

Figure 15. Typical application with a 32.768 kHz crystal

Resonator with
integrated capacitors
CL1
OSC32_IN fLSE
Drive
32.768 kH z programmable
resonator amplifier

OSC32_OU T
CL2

MS30253V1

Note: An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.

6.3.8 Internal clock source characteristics

The parameters given in Table 33 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 18: General operating
conditions. The provided curves are characterization results, not tested in production.

High-speed internal (HSI) RC oscillator

Table 33. HSI oscillator characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

fHSI Frequency - 8 MHz

TRIM HSI user trimming step - - 1(2) %
DuCy(HSI) Duty cycle 45(2) - 55(2) %
Accuracy of the HSI TA = –40 to 85 °C - ±5 - %
ACCHSI oscillator (factory
calibrated)(3) TA = 25 °C - ±1 - %

HSI oscillator startup

tsu(HSI) 1(2) - 2(2) µs
time
HSI oscillator power
IDDA(HSI) - 80 - µA
consumption
1. VDDA = 3.3 V, TA = –40 to 85 °C unless otherwise specified.
2. Guaranteed by design, not tested in production.
3. With user calibration.

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High-speed internal 14 MHz (HSI14) RC oscillator (dedicated to ADC)

Table 34. HSI14 oscillator characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

fHSI14 Frequency - 14 MHz

TRIM HSI14 user-trimming step - - 1(2) %
DuCy(HSI14) Duty cycle 45(2) - 55(2) %
Accuracy of the HSI14
ACCHSI14 TA = –40 to 85 °C - ±5 - %
oscillator (factory calibrated)
tsu(HSI14) HSI14 oscillator startup time 1(2) - 2(2) µs
HSI14 oscillator power
IDDA(HSI14) - 100 - µA
consumption
1. VDDA = 3.3 V, TA = –40 to 85 °C unless otherwise specified.
2. Guaranteed by design, not tested in production.

Low-speed internal (LSI) RC oscillator

Table 35. LSI oscillator characteristics(1)

Symbol Parameter Min Typ Max Unit

fLSI Frequency 30 40 50 kHz

tsu(LSI)(2) LSI oscillator startup time - - 85 µs
IDDA(LSI)(2) LSI oscillator power consumption - 0.75 - µA
1. VDDA = 3.3 V, TA = –40 to 85 °C unless otherwise specified.
2. Guaranteed by design, not tested in production.

6.3.9 PLL characteristics

The parameters given in Table 36 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 18: General operating
conditions.

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Table 36. PLL characteristics

Value
Symbol Parameter Unit
Min Typ Max

PLL input clock(1) 1(2) - 24(2) MHz

fPLL_IN
PLL input clock duty cycle 40(2) - 60 (2)
%
(2)
fPLL_OUT PLL multiplier output clock 16 - 48 MHz
tLOCK PLL lock time - - 200(2) µs
JitterPLL (2)
Cycle-to-cycle jitter - - 300 ps
1. Take care to use the appropriate multiplier factors to obtain PLL input clock values compatible
with the range defined by fPLL_OUT.
2. Guaranteed by design, not tested in production.

6.3.10 Memory characteristics

Flash memory
The characteristics are given at TA = –40 to 85 °C unless otherwise specified.

Table 37. Flash memory characteristics

Symbol Parameter Conditions Min Typ Max(1) Unit

tprog 16-bit programming time TA–40 to +85 °C - 53.5 - µs

tERASE Page (1 KB) erase time TA –40 to +85 °C - 30 - ms
tME Mass erase time TA –40 to +85 °C - 30 - ms
Write mode - - 10 mA
IDD Supply current
Erase mode - - 12 mA
Vprog Programming voltage 2.4 - 3.6 V
1. Guaranteed by design, not tested in production.

Table 38. Flash memory endurance and data retention

Symbol Parameter Conditions Min(1) Unit

NEND Endurance TA = –40 to +85 °C (6 suffix versions) 1 kcycles

tRET (2)
Data retention 1 kcycle at TA = 85 °C 20 Years
1. Data based on characterization results, not tested in production.
2. Cycling performed over the whole temperature range.

6.3.11 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

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Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
 Electrostatic discharge (ESD) (positive and negative) is applied to all device pins
until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2
standard.
 FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 39. They are based on the EMS levels and classes
defined in application note AN1709.

Table 39. EMS characteristics

Level/
Symbol Parameter Conditions
Class

VDD 3.3 V, LQFP64, TA +25 °C,

Voltage limits to be applied on any I/O pin to
VFESD fHCLK 48 MHz 2B
induce a functional disturbance
conforms to IEC 61000-4-2
Fast transient voltage burst limits to be VDD3.3 V, LQFP64, TA +25 °C,
VEFTB applied through 100 pF on VDD and VSS fHCLK 48 MHz 3B
pins to induce a functional disturbance conforms to IEC 61000-4-4

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
 Corrupted program counter
 Unexpected reset
 Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).

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Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.

Table 40. EMI characteristics

Max vs. [fHSE/fHCLK]
Monitored
Symbol Parameter Conditions Unit
frequency band
8/48 MHz

0.1 to 30 MHz -3
VDD 3.6 V, TA 25 °C,
LQFP64 package 30 to 130 MHz 28 dBµV
SEMI Peak level
compliant with IEC 130 MHz to 1GHz 23
61967-2
SAE EMI Level 4 -

6.3.12 Electrical sensitivity characteristics

Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.

Table 41. ESD absolute maximum ratings

Maximum
Symbol Ratings Conditions Class Unit
value(1)

Electrostatic discharge voltage TA +25 °C, conforming

VESD(HBM) 2 2000
(human body model) to JESD22-A114
V
Electrostatic discharge voltage TA +25 °C, conforming
VESD(CDM) II 500
(charge device model) to JESD22-C101
1. Data based on characterization results, not tested in production.

Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
 A supply overvoltage is applied to each power supply pin
 A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latch-up standard.

Table 42. Electrical sensitivities

Symbol Parameter Conditions Class

LU Static latch-up class TA +105 °C conforming to JESD78A II level A

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6.3.13 I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product
operation. However, in order to give an indication of the robustness of the microcontroller in
cases when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (more
than 5 LSB TUE), out of conventional limits of current injection on adjacent pins (more than
–5 µA) or other functional failure (reset occurrence or oscillator frequency deviation, for
example).
The characterization results are given in Table 43.

Table 43. I/O current injection susceptibility

Functional
susceptibility
Symbol Description Unit
Negative Positive
injection injection

Injected current on BOOT0 –0 NA

Injected current on all FT and FTf pins with induced
–5 NA
leakage current on adjacent pins less than –5 µA
mA
IINJ Injected current on all TTa pins with induced leakage
–5 +5
current on adjacent pins less than –5 µA
Injected current on all TC and RESET pins with induced
–5 +5
leakage current on adjacent pins less than –5 µA

6.3.14 I/O port characteristics

General input/output characteristics
Unless otherwise specified, the parameters given in Table 44 are derived from tests
performed under the conditions summarized in Table 18: General operating conditions. All
I/Os are designed as CMOS and TTL compliant.

Table 44. I/O static characteristics

Symbol Parameter Conditions Min Typ Max Unit

TC and TTa I/O - - 0.3 VDD+0.07(1)

Low level input FT and FTf I/O - - 0.475 VDD–0.2(1)

VIL V
voltage BOOT0 - - 0.3 VDD–0.3(1)
All I/Os except BOOT0 pin - - 0.3 VDD

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Table 44. I/O static characteristics (continued)

Symbol Parameter Conditions Min Typ Max Unit

TC and TTa I/O 0.445 VDD+0.398(1) - -

High level input FT and FTf I/O 0.5 VDD+0.2(1) - -

VIH V
voltage BOOT0 0.2 VDD+0.95(1) - -
All I/Os except BOOT0 pin 0.7 VDD - -
(1)
TC and TTa I/O - 200 -
Schmitt trigger
Vhys FT and FTf I/O - 100(1) - mV
hysteresis
BOOT0 - 300(1) -
TC, FT and FTf I/O
TTa in digital mode - -  0.1
VSS  VIN  VDD
TTa in digital mode
Input leakage - - 1
Ilkg VDD  VIN  VDDA µA
current (2)
TTa in analog mode
- -  0.2
VSS  VIN  VDDA
FT and FTf I/O (3)
- - 10
VDD  VIN  5 V
Weak pull-up
RPU equivalent VIN VSS 25 40 55 k
resistor (4)
Weak pull-down
RPD equivalent VIN VDD 25 40 55 k
resistor (4)
I/O pin
CIO - 5 - pF
capacitance
1. Data based on design simulation only. Not tested in production.
2. Leakage could be higher than maximum value, if negative current is injected on adjacent pins. Refer to
Table 43: I/O current injection susceptibility.
3. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled.
4. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS.
This MOS/NMOS contribution to the series resistance is minimum (~10% order).

All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 16 for standard I/Os, and in Figure 17 for
5 V tolerant I/Os.

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Figure 16. TC and TTa I/O input characteristics

3
VIN (V)

2.5
V DD
Tested range = 0.7
V IHmin

2
ents TTL standard requirement
req uirem
ndard
S sta
CMO
1.5
+ 0.398
0.445 V DD
V IHmin = Undefined input range

1
3 VDD
3 VDD + 0.07 VILmax = 0.
VILmax = 0.
TTL standard requirement
irements
ndard requ
0.5 CMOS sta

Tested range

0
2 2.2 2.4 2.6 2.8 3 3.2 3.4 V (V) 3.6
DD
MS32130V1

Figure 17. Five volt tolerant (FT and FTf) I/O input characteristics

3
VIN (V)

2.5
V D
= 0.7 D
Tested range V IHmin
TTL standard requirement
2
ts
emen
ard requir
S stand
1.5 CMO

+ 0.2 Undefined input range

= 0.5 V DD
V IHmin
-0 .2
1 V
= 0.475 DD 3 VDD
V ILmax VILmax = 0.
TTL standard requirement
irements
ndard requ
0.5 CMOS sta
Tested range

0
2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
VDD (V)
MS32131V1

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Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or
source up to +/- 20 mA (with a relaxed VOL/VOH).
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2:
 The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
IVDD (see Table 16: Current characteristics).
 The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
IVSS (see Table 16: Current characteristics).

Output voltage levels

Unless otherwise specified, the parameters given in the table below are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 18: General operating conditions. All I/Os are CMOS and TTL compliant (FT, TTa or
TC unless otherwise specified).

Table 45. Output voltage characteristics

Symbol Parameter Conditions Min Max Unit

Output low level voltage for an I/O pin when 8

VOL(1) - 0.4
pins are sunk at the same time IIO = +8 mA
V
(2) Output high level voltage for an I/O pin when 8 2.7 V < VDD < 3.6 V
VOH VDD–0.4 -
pins are sourced at the same time
Output low level voltage for an I/O pin when 5
VOL(1)(3) - 1.3
pins are sunk at the same time IIO = +20 mA
V
(2)(3) Output high level voltage for an I/O pin when 5 2.7 V < VDD < 3.6 V
VOH VDD–1.3 -
pins are sourced at the same time
Output low level voltage for an I/O pin when 8
VOL(1)(3) - 0.4
pins are sunk at the same time IIO = +6 mA
V
(2)(3) Output high level voltage for an I/O pin when 8 2.4 V < VDD < 2.7 V
VOH VDD–0.4 -
pins are sourced at the same time
Output low level voltage for an FTf I/O pin in
VOLFM+(1) IIO = +20 mA - 0.4 V
FM+ mode
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 16:
Current characteristics and the sum of IIO (I/O ports and control pins) must not exceed IVSS.
2. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 16: Current characteristics and the sum of IIO (I/O ports and control pins) must not exceed IVDD.
3. Data based on characterization results. Not tested in production.

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Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 18 and
Table 46, respectively.
Unless otherwise specified, the parameters given are derived from tests performed under
ambient temperature and VDD supply voltage conditions summarized in Table 18: General
operating conditions.

Table 46. I/O AC characteristics(1)

OSPEEDRy
Symbol Parameter Conditions Min Max Unit
[1:0] value(1)

fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2.4 V to 3.6 V - 2 MHz

Output high to low level
tf(IO)out - 125(3)
x0 fall time
CL = 50 pF, VDD = 2.4 V to 3.6 V ns
Output low to high level (3)
tr(IO)out - 125
rise time
fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2.4 V to 3.6 V - 10 MHz
Output high to low level
tf(IO)out - 25(3)
01 fall time
CL = 50 pF, VDD = 2.4 V to 3.6 V ns
Output low to high level
tr(IO)out - 25(3)
rise time
CL = 30 pF, VDD = 2.7 V to 3.6 V - 50
fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2.7 V to 3.6 V - 30 MHz
CL = 50 pF, VDD = 2.4 V to 2.7 V - 20
11 Output high to low level CL = 30 pF, VDD = 2.7 V to 3.6 V - 5(3)
tf(IO)out
fall time CL = 50 pF, VDD = 2.7 V to 3.6 V - 8(3)
ns
Output low to high level CL = 30 pF, VDD = 2.7 V to 3.6 V - 5(3)
tr(IO)out
rise time CL = 50 pF, VDD = 2.7 V to 3.6 V - 8(3)
fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2.4 V to 3.6 V - 2(3) MHz
FM+ Output high to low level
tf(IO)out CL = 50 pF, VDD = 2.4 V to 3.6 V - 12(3)
configuration fall time
(4) ns
Output low to high level
tr(IO)out CL = 50 pF, VDD = 2.4 V to 3.6 V - 34(3)
rise time
Pulse width of external
tEXTIpw signals detected by the 10 - ns
EXTI controller
1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the RM0091 reference manual for a
description of GPIO Port configuration register.
2. The maximum frequency is defined in Figure 18.
3. Guaranteed by design, not tested in production.
4. When FM+ configuration is set, the I/O speed control is bypassed. Refer to the STM32F0xx reference
manual RM0091 for a detailed description of FM+ I/O configuration.

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Figure 18. I/O AC characteristics definition

90% 10%

50% 50%

10% 90%

EXTERNAL t r(IO)out t f(IO)out

OUTPUT
ON 50 pF T

Maximum frequency is achieved if (t r + t f (≤ 2/3)T and if the duty cycle is (45-55%)

when loaded by 50 pF
MS32132V1

6.3.15 NRST pin characteristics

The NRST pin input driver uses the CMOS technology. It is connected to a permanent pull-
up resistor, RPU (see Table 44: I/O static characteristics).
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 18: General operating conditions.

Table 47. NRST pin characteristics

Symbol Parameter Conditions Min Typ Max Unit

VIL(NRST) NRST input low level voltage –0.3 - 0.8(1)

NRST input high level V
VIH(NRST) 2 - VDD+0.3(1)
voltage
NRST Schmitt trigger
Vhys(NRST) - 200 - mV
voltage hysteresis
Weak pull-up equivalent
RPU VIN VSS 30 40 50 k
resistor(2)
VF(NRST) NRST input filtered pulse - - 100(1) ns
VNF(NRST) NRST input not filtered pulse 300(1) - - ns
1. Guaranteed by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to
the series resistance must be minimum (~10% order).

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Figure 19. Recommended NRST pin protection

VDD
External
reset circuit(1)
RPU Internal Reset
NRST(2)
Filter
0.1 μF

MS19878V1

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 47: NRST pin characteristics. Otherwise the reset will not be taken into account by the device.

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6.3.16 12-bit ADC characteristics

Unless otherwise specified, the parameters given in Table 48 are preliminary values derived
from tests performed under ambient temperature, fPCLK2 frequency and VDDA supply
voltage conditions summarized in Table 18: General operating conditions.
Note: It is recommended to perform a calibration after each power-up.

Table 48. ADC characteristics

Symbol Parameter Conditions Min Typ Max Unit

Analog supply voltage for

VDDA 2.4 - 3.6 V
ADC ON
fADC ADC clock frequency 0.6 - 14 MHz

fS(1) Sampling rate 0.05 - 1 MHz

fADC = 14 MHz - - 823 kHz

fTRIG(1) External trigger frequency
- - 17 1/fADC
VAIN Conversion voltage range 0 - VDDA V
See Equation 1 and
RAIN(1) External input impedance - - 50 k
Table 49 for details

RADC(1) Sampling switch resistance - - 1 k

Internal sample and hold

CADC(1) - - 8 pF
capacitor
fADC = 14 MHz 5.9 µs
tCAL(1) Calibration time
83 1/fADC
fADC = fPCLK/2 = 14 MHz 0.196 µs
fADC = fPCLK/2 5.5 1/fPCLK
tlatr(1) Trigger conversion latency fADC = fPCLK/4 = 12 MHz 0.219 µs
fADC = fPCLK/4 10.5 1/fPCLK
fADC = fHSI14 = 14 MHz 0.188 - 0.259 µs
ADC jitter on trigger
JitterADC fADC = fHSI14 - 1 - 1/fHSI14
conversion
fADC = 14 MHz 0.107 - 17.1 µs
tS(1) Sampling time
1.5 - 239.5 1/fADC
tSTAB(1) Power-up time 0 0 1 µs
fADC = 14 MHz 1 - 18 µs
Total conversion time
tCONV(1) 14 to 252 (tS for sampling +12.5 for
(including sampling time) 1/fADC
successive approximation)
1. Guaranteed by design, not tested in production.

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Equation 1: RAIN max formula

TS
R AIN  -------------------------------------------------------------
- – R ADC
N+2
f ADC  C ADC  ln  2 

The formula above (Equation 1) is used to determine the maximum external impedance
allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).

Table 49. RAIN max for fADC = 14 MHz

Ts (cycles) tS (µs) RAIN max (k)(1)

1.5 0.11 0.4

7.5 0.54 5.9
13.5 0.96 11.4
28.5 2.04 25.2
41.5 2.96 37.2
55.5 3.96 50
71.5 5.11 NA
239.5 17.1 NA
1. Guaranteed by design, not tested in production.

Table 50. ADC accuracy(1)(2)(3)

Symbol Parameter Test conditions Typ Max(4) Unit

ET Total unadjusted error ±3.3 ±4

EO Offset error fPCLK = 48 MHz, ±1.9 ±2.8
fADC = 14 MHz, RAIN < 10 k,
EG Gain error ±2.8 ±3 LSB
VDDA = 2.7 V to 3.6 V
ED Differential linearity error TA = 40 to 85 °C ±0.7 ±1.3
EL Integral linearity error ±1.2 ±1.7
1. ADC DC accuracy values are measured after internal calibration.
2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard
(non-robust) analog input pins should be avoided as this significantly reduces the accuracy of
the conversion being performed on another analog input. It is recommended to add a Schottky
diode (pin to ground) to standard analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in
Section 6.3.14 does not affect the ADC accuracy.
3. Better performance may be achieved in restricted VDDA, frequency and temperature ranges.
4. Data based on characterization results, not tested in production.

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Figure 20. ADC accuracy characteristics

VDDA
1 LSBIDEAL 

4096 EG
(1) Example of an actual transfer curve
4095
(2) The ideal transfer curve
4094 (3) End point correlation line
4093
(2)
ET=Total Unadjusted Error: maximum deviation
ET between the actual and the ideal transfer curves.
7 (3) EO=Offset Error: deviation between the first actual
(1) transition and the first ideal one.
6
EG=Gain Error: deviation between the last ideal
5 transition and the last actual one.
EO EL ED=Differential Linearity Error: maximum deviation
4 between actual steps and the ideal one.
3 EL=Integral Linearity Error: maximum deviation
ED between any actual transition and the end point
2 correlation line.
1 LSBIDEAL
1

0
1 2 3 4 5 6 7 4093 4094 4095 4096
VSSA VDDA MS19880V1

Figure 21. Typical connection diagram using the ADC

VDDA
Sample and hold ADC
VT converter
0.6 V
RAIN(1) AINx
RADC
12-bit
converter
IL±1 μA
Cparasitic VT
VAIN 0.6 V
CADC

MS19881V2

1. Refer to Table 48: ADC characteristics for the values of RAIN, RADC and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 10: Power supply
scheme. The 10 nF capacitor should be ceramic (good quality) and it should be placed as
close as possible to the chip.

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6.3.17 Temperature sensor characteristics

Table 51. TS characteristics

Symbol Parameter Min Typ Max Unit

TL(1) VSENSE linearity with temperature - 1 2 °C

Avg_Slope(1) Average slope 4.0 4.3 4.6 mV/°C
V25 Voltage at 25 °C 1.34 1.43 1.52 V
tSTART(1) Startup time 4 - 10 µs
ADC sampling time when reading the
TS_temp(1)(2) 17.1 - - µs
temperature
1. Guaranteed by design, not tested in production.
2. Shortest sampling time can be determined in the application by multiple iterations.

6.3.18 Timer characteristics

The parameters given in Table 52 are guaranteed by design.
Refer to Section 6.3.14: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).

Table 52. TIMx(1) characteristics

Symbol Parameter Conditions Min Max Unit

1 - tTIMxCLK
tres(TIM) Timer resolution time
fTIMxCLK = 48 MHz 20.8 - ns

Timer external clock 0 fTIMxCLK/2 MHz

fEXT
frequency on CH1 to CH4 f
TIMxCLK = 48 MHz 0 24 MHz
ResTIM Timer resolution TIMx - 16 bit

1 65536 tTIMxCLK
tCOUNTER 16-bit counter clock period
fTIMxCLK = 48 MHz 0.0208 1365 µs

Maximum possible count - 65536 × 65536 tTIMxCLK

tMAX_COUNT
with 32-bit counter fTIMxCLK = 48 MHz - 89.48 s
1. TIMx is used as a general term to refer to the TIM1, TIM3, TIM6, TIM14, TIM15, TIM16 and
TIM17 timers.

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Table 53. IWDG min/max timeout period at 40 kHz (LSI) (1)

Min timeout RL[11:0]= Max timeout RL[11:0]=
Prescaler divider PR[2:0] bits Unit
0x000 0xFFF

/4 0 0.1 409.6
/8 1 0.2 819.2
/16 2 0.4 1638.4
/32 3 0.8 3276.8 ms
/64 4 1.6 6553.6
/128 5 3.2 13107.2
/256 6 or 7 6.4 26214.4
1. These timings are given for a 40 kHz clock but the microcontroller’s internal RC frequency can
vary from 30 to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still
depend on the phasing of the APB interface clock versus the LSI clock so that there is always
a full RC period of uncertainty.

Table 54. WWDG min-max timeout value @48 MHz (PCLK)

Prescaler WDGTB Min timeout value Max timeout value Unit

1 0 0.0853 5.4613
2 1 0.1706 10.9226
ms
4 2 0.3413 21.8453
8 3 0.6826 43.6906

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6.3.19 Communication interfaces

I2C interface characteristics
The I2C interface meets the requirements of the standard I2C communication protocol with
the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” open-
drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is
disabled, but is still present.
The I2C characteristics are described in Table 55. Refer also to Section 6.3.14: I/O port
characteristics for more details on the input/output alternate function characteristics (SDA
and SCL).

Table 55. I2C characteristics(1)

Standard Fast mode Fast mode +
Symbol Parameter Unit
Min Max Min Max Min Max

fSCL SCL clock frequency 0 100 0 400 0 1000 KHz

tLOW Low period of the SCL clock 4.7 - 1.3 - 0.5 - µs
tHIGH High Period of the SCL clock 4 0.6 0.26 - µs
Rise time of both SDA and SCL
tr - 1000 - 300 - 120 ns
signals
Fall time of both SDA and SCL
tf - 300 - 300 - 120 ns
signals
tHD;DAT Data hold time 0 - 0 - 0 - µs
tVD;DAT Data valid time - 3.45(2) - 0.9(2) - 0.45(2) µs
tVD;ACK Data valid acknowledge time - 3.45(2) - 0.9(2) - 0.45(2) µs
tSU;DAT Data setup time 250 - 100 - 50 - ns
Hold time (repeated) START
tHD;STA 4.0 - 0.6 - 0.26 - µs
condition
Set-up time for a repeated
tSU;STA START 4.7 - 0.6 - 0.26 µs
condition
tSU;STO Set-up time for STOP condition 4.0 - 0.6 - 0.26 - µs
Bus free time between a
tBUF 4.7 - 1.3 - 0.5 - µs
STOP and START condition
Cb Capacitive load for each bus line - 400 - 400 - 550 pF
1. The I2C characteristics are the requirements from the I2C bus specification rev03. They are guaranteed by
design when the I2Cx_TIMING register is correctly programmed (refer to reference manual). These
characteristics are not tested in production.
2. The maximum tHD;DAT could be 3.45 µs, 0.9 µs and 0.45 µs for standard mode, fast mode and fast mode
plus, but must be less than the maximum of tVD;DAT or tVD;ACK by a transition time.

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Table 56. I2C analog filter characteristics(1)

Symbol Parameter Min Max Unit

Pulse width of spikes that are

tSP 50 260 ns
suppressed by the analog filter
1. Guaranteed by design, not tested in production.

Figure 22. I2C bus AC waveforms and measurement circuit

VDD_I2C VDD_I2C

Rp Rp MCU
Rs
SDA
I2C bus Rs
SCL

MS19879V3

Legend: Rs: Series protection resistors. Rp: Pull-up resistors. VDD_I2C: I2C bus supply.

SPI characteristics
Unless otherwise specified, the parameters given in Table 57 are derived from tests
performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions
summarized in Table 18: General operating conditions.
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK).

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Table 57. SPI characteristics

Symbol Parameter Conditions Min Max Unit

fSCK Master mode - 18

SPI clock frequency MHz
1/tc(SCK) Slave mode - 18
tr(SCK) SPI clock rise and fall
Capacitive load: C = 15 pF - 6 ns
tf(SCK) time
tsu(NSS)(1) NSS setup time Slave mode 4Tpclk -
(1)
th(NSS) NSS hold time Slave mode 2Tpclk + 10 -
tw(SCKH)(1) Master mode, fPCLK = 36 MHz,
SCK high and low time Tpclk/2 -2 Tpclk/2 + 1
tw(SCKL)(1) presc = 4

tsu(MI) (1) Master mode 4 -

Data input setup time
tsu(SI)(1) Slave mode 5 -
th(MI) (1) Master mode 4 -
Data input hold time ns
(1)
th(SI) Slave mode 5 -
ta(SO)(1)(2) Data output access time Slave mode, fPCLK = 20 MHz 0 3Tpclk
tdis(SO)(1)(3) Data output disable time Slave mode 0 18
(1)
tv(SO) Data output valid time Slave mode (after enable edge) - 22.5
(1)
tv(MO) Data output valid time Master mode (after enable edge) - 6
th(SO)(1) Slave mode (after enable edge) 11.5 -
Data output hold time
(1)
th(MO) Master mode (after enable edge) 2 -
SPI slave input clock
DuCy(SCK) Slave mode 25 75 %
duty cycle
1. Data based on characterization results, not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the
data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the
data in Hi-Z

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Figure 23. SPI timing diagram - slave mode and CPHA = 0

NSS input

tc(SCK)

tSU(NSS) th(NSS)

CPHA= 0
SCK Input

CPOL=0
tw(SCKH)
CPHA= 0 tw(SCKL)
CPOL=1

ta(SO) tv(SO) th(SO) tr(SCK) tdis(SO)

tf(SCK)
MISO
OUT P UT MS B O UT BI T6 OUT LSB OUT
tsu(SI)
MOSI
M SB IN B I T1 IN LSB IN
I NPUT
th(SI)
ai14134c

Figure 24. SPI timing diagram - slave mode and CPHA = 1

NSS input
tSU(NSS) tc(SCK) th(NSS)

CPHA=1
SCK Input

CPOL=0
tw(SCKH)
CPHA=1 tw(SCKL)
CPOL=1

tv(SO) th(SO) tr(SCK) tdis(SO)

ta(SO) tf(SCK)
MISO
OUT P UT MS B O UT BI T6 OUT LSB OUT
tsu(SI) th(SI)
MOSI
M SB IN B I T1 IN LSB IN
I NPUT

ai14135

1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.

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Figure 25. SPI timing diagram - master mode

High

NSS input

tc(SCK)
SCK Output

CPHA= 0
CPOL=0
CPHA= 0
CPOL=1
SCK Output

CPHA=1
CPOL=0
CPHA=1
CPOL=1

tw(SCKH) tr(SCK)
tsu(MI) tw(SCKL) tf(SCK)
MISO
INP UT MS BIN BI T6 IN LSB IN

th(MI)
MOSI
M SB OUT B I T1 OUT LSB OUT
OUTUT
tv(MO) th(MO)

ai14136

1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.

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7 Package characteristics

7.1 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.

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Figure 26. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline

D

D1 ccc C

D3 A
A2
48 33

49 32

b
L1

E3 E1 E

L
A1 K

64
17
Pin 1
identification 1 16 c
5W_ME

1. Drawing is not to scale.

Table 58. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A 1.600 0.0630
A1 0.050 0.150 0.0020 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 0.200 0.0035 0.0079
D 11.800 12.000 12.200 0.4646 0.4724 0.4803
D1 9.800 10.000 10.200 0.3858 0.3937 0.4016
D. 7.500
E 11.800 12.000 12.200 0.4646 0.4724 0.4803
E1 9.800 10.00 10.200 0.3858 0.3937 0.4016
e 0.500 0.0197
k 0° 3.5° 7° 0° 3.5° 7°
L 0.450 0.600 0.75 0.0177 0.0236 0.0295
L1 1.000 0.0394
ccc 0.080 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.

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Figure 27. LQFP64 recommended footprint

48 33

0.3
49 0.5 32

12.7
10.3

10.3
64 17

1.2
1 16
7.8

12.7

ai14909

1. Drawing is not to scale.

2. Dimensions are in millimeters.

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Figure 28. LQFP48 – 7 x 7 mm, 48 pin low-profile quad flat package outline

D1 ccc C

D3 A
A2
36 25

37 24

L1
b
E3 E1 E

48
13 L
A1 K
Pin 1
identification 1 12 c

5B_ME

1. Drawing is not to scale.

Table 59. LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat package mechanical data
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max
A 1.600 0.0630
A1 0.050 0.150 0.0020 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 0.200 0.0035 0.0079
D 8.800 9.000 9.200 0.3465 0.3543 0.3622
D1 6.800 7.000 7.200 0.2677 0.2756 0.2835
D3 5.500 0.2165
E 8.800 9.000 9.200 0.3465 0.3543 0.3622
E1 6.800 7.000 7.200 0.2677 0.2756 0.2835
E3 5.500 0.2165
e 0.500 0.0197
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 1.000 0.0394
k 0° 3.5° 7° 0° 3.5° 7°
ccc 0.080 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.

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Figure 29. LQFP48 recommended footprint

0.50
1.20

0.30
36 25
37 24

0.20
7.30
9.70 5.80

7.30

48 13
1 12

1.20

5.80

9.70

ai14911b

1. Drawing is not to scale.

2. Dimensions are in millimeters.

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Figure 30. LQFP32 – 7 x 7mm 32-pin low-profile quad flat package outline

ccc C
D
D1
D3 A
A2
24 17

16
25 L1
b
E3 E1 E

32
9
L
Pin 1 A1 K
identification 1 8 c

5V_ME

1. Drawing is not to scale.

Table 60. LQFP32 – 7 x 7mm 32-pin low-profile quad flat package mechanical data
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A 1.600 0.0630
A1 0.050 0.150 0.0020 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.300 0.370 0.450 0.0118 0.0146 0.0177
c 0.090 0.200 0.0035 0.0079
D 8.800 9.000 9.200 0.3465 0.3543 0.3622
D1 6.800 7.000 7.200 0.2677 0.2756 0.2835
D3 5.600 0.2205
E 8.800 9.000 9.200 0.3465 0.3543 0.3622
E1 6.800 7.000 7.200 0.2677 0.2756 0.2835
E3 5.600 0.2205
e 0.800 0.0315
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 1.000 0.0394
k 0.0° 3.5° 7.0° 0.0° 3.5° 7.0°
ccc 0.100 0.0039
1. Values in inches are converted from mm and rounded to 4 decimal digits.

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Figure 31. LQFP32 recommended footprint

9.40

7.70

0.54

9.40

0.80
5V_FP

1. Drawing is not to scale.

2. Dimensions are in millimeters.

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Figure 32. TSSOP20 - 20-pin thin shrink small outline

20 11
c

E1 E

1 10

aaa CP
A1 L
A A2
L1

b e
YA_ME

1. Drawing is not to scale.

Table 61. TSSOP20 – 20-pin thin shrink small outline package mechanical data
millimeters inches(1)
Symbol
Min Typ Max Min Typ

A 1.2 0.0472
A1 0.05 0.15 0.002 0.0059
A2 0.8 1 1.05 0.0315 0.0394 0.0413
b 0.19 0.3 0.0075 0.0118
c 0.09 0.2 0.0035 0.0079
D 6.4 6.5 6.6 0.252 0.2559 0.2598
E 6.2 6.4 6.6 0.2441 0.252 0.2598
E1 4.3 4.4 4.5 0.1693 0.1732 0.1772
e 0.65 0.0256
L 0.45 0.6 0.75 0.0177 0.0236 0.0295
L1 1 0.0394
k 0.0° 8.0° 0.0° 8.0°
aaa 0.1 0.0039
1. Values in inches are converted from mm and rounded to 4 decimal digits.

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Figure 33. TSSOP20 recommended footprint

1. Dimensions are in millimeters

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7.2 Thermal characteristics

The maximum chip junction temperature (TJ max) must never exceed the values given in
Table 18: General operating conditions.
The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max x JA)
Where:
 TA max is the maximum ambient temperature in °C,
 JA is the package junction-to-ambient thermal resistance, in C/W,
 PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
 PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = (VOL × IOL) + ((VDD – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.

Table 62. Package thermal characteristics

Symbol Parameter Value Unit

Thermal resistance junction-ambient

45
LQFP64 - 10 × 10 mm / 0.5 mm pitch
Thermal resistance junction-ambient
55
LQFP48 - 7 × 7 mm
JA °C/W
Thermal resistance junction-ambient
56
LQFP32 - 7 × 7 mm
Thermal resistance junction-ambient
110
TSSOP20

7.2.1 Reference document

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org

7.2.2 Selecting the product temperature range

When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Section 8: Part numbering.
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at
maximum dissipation and, to a specific maximum junction temperature.
As applications do not commonly use the STM32F0xx at maximum dissipation, it is useful to
calculate the exact power consumption and junction temperature to determine which
temperature range will be best suited to the application.
The following examples show how to calculate the temperature range needed for a given
application.

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Example 1: High-performance application

Assuming the following application conditions:
Maximum ambient temperature TAmax = 82 °C (measured according to JESD51-2),
IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output
at low level with IOL = 20 mA, VOL= 1.3 V
PINTmax = 50 mA × 3.5 V= 175 mW
PIOmax = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW
This gives: PINTmax = 175 mW and PIOmax = 272 mW:
PDmax = 175 + 272 = 447 mW
Using the values obtained in Table 62 TJmax is calculated as follows:
– For LQFP64, 45 °C/W
TJmax = 82 °C + (45 °C/W × 447 mW) = 82 °C + 20.115 °C = 102.115 °C
This is within the range of the suffix 6 version parts (–40 < TJ < 105 °C) see Table 18:
General operating conditions.
In this case, parts must be ordered at least with the temperature range suffix 6 (see
Section 8: Part numbering).
Note: With this given PDmax we can find the TAmax allowed for a given device temperature range
(order code suffix 6 or 7).
Suffix 6: TAmax = TJmax - (45°C/W × 447 mW) = 105-20.115 = 84.885 °C
Suffix 7: TAmax = TJmax - (45°C/W × 447 mW) = 125-20.115 = 104.885 °C

Example 2: High-temperature application

Using the same rules, it is possible to address applications that run at high ambient
temperatures with a low dissipation, as long as junction temperature TJ remains within the
specified range.
Assuming the following application conditions:
Maximum ambient temperature TAmax = 100 °C (measured according to JESD51-2),
IDDmax = 20 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL= 0.4 V
PINTmax = 20 mA × 3.5 V= 70 mW
PIOmax = 20 × 8 mA × 0.4 V = 64 mW
This gives: PINTmax = 70 mW and PIOmax = 64 mW:
PDmax = 70 + 64 = 134 mW
Thus: PDmax = 134 mW
Using the values obtained in Table 62 TJmax is calculated as follows:
– For LQFP64, 45 °C/W
TJmax = 100 °C + (45 °C/W × 134 mW) = 100 °C + 6.03 °C = 106.03 °C
This is above the range of the suffix 6 version parts (–40 < TJ < 105 °C).
In this case, parts must be ordered at least with the temperature range suffix 7 (see
Section 8: Part numbering) unless we reduce the power dissipation in order to be able to
use suffix 6 parts.

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Refer to Figure 34 to select the required temperature range (suffix 6 or 7) according to your
ambient temperature or power requirements. For suffix 7, refer to STM32F05x devices.

Figure 34. LQFP64 PD max vs. TA

700
600
500
PD (mW) 400 Suffix 6
300
Suffix 7
200
100
0
65 75 85 95 105 115 125 135
TA (°C) MSv32143V1

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8 Part numbering

For a list of available options (memory, package, and so on) or for further information on any
aspect of this device, please contact your nearest ST sales office.

Table 63. Ordering information scheme

Example: STM32 F 030 R 8 T 6 x

Device family
STM32 = ARM-based 32-bit microcontroller

Product type
F = General-purpose

Sub-family
030 = STM32F030xx

Pin count
F = 20 pins
K = 32 pins
C = 48 pins
R = 64 pins

Code size
4 = 16 Kbytes of Flash memory
6 = 32 Kbytes of Flash memory
8 = 64 Kbytes of Flash memory

Package
P = TSSOP
T = LQFP

Temperature range
6 = –40 °C to +85 °C

Options
TR = tape and real

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9 Revision history

Table 64. Document revision history

Date Revision Changes

04-Jul-2013 1 Initial release

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