1

Design and Simulation of a Low-Power Two-Stage

Operational Transconductance Amplifier
Rounok Joardar

Abstract – This paper describes the design and differential stages were considered for this
simulation of a low-power two-stage operational design but were not selected since their
transconductance amplifier (OTA) using a 0.18µ µm
advantages would be compromised by factors
CMOS technology and a 1.8V power supply. It is
shown that with careful design, a low-frequency gain such as loss of swing headroom for a 1.8V
greater than 70dB can be achieved together with high design and increase in power consumption.
phase margin (greater than 45°), fast settling time (less The design approach used in this project
than 40 ns), and low power consumption (0.467 mW). is based on the gm/Id technique. Additionally,
instead of relying on textbook formulas for
I. INTRODUCTION various quantities, pre-simulated technology
A systematic procedure for the design of a two- characterization charts were used for better
stage amplifier is presented in this report that accuracy.
describes how the values of the various circuit
Table I. Summary of design specifications.
components can be derived from the provided Specification This Design
specifications. Table I is a summary of the DC small-signal gain > 70 dB 74.25 dB
various OTA specifications that have to be met. Input-referred offset < 10 µV -1.6 µV
Results obtained from simulations of the final Input Vcm range [0.75, 1.05] [0.75, 1.05]
design are also shown for comparison. Output swing [0.3, 1.5] [0.275, 1.56]
Fig. 1 shows the schematic of the OTA Unity gain frequency > 100 MHz 101 MHz
Phase margin > 45° 55°
circuit used in this design. To achieve the high
Power Consumption < 1 mW 0.467 mW
gain required a two-stage design is used. An Settling Up < 40 ns 21.4 ns
NMOS input differential amplifier is followed by time Down < 40 ns 32.4 ns
a PMOS common source amplifier. Miller CMRR at DC > 70 dB 70.35 dB
compensation with nulling resistor is used to PSRR at DC > 70 dB 76.8 dB
obtain the required phase margin. Other
architectures such as cascoded and telescopic

Fig. 1. Schematic of OTA circuit. Total power consumption is 0.467 mW.

 2
II. THEORY BASED DESIGN near the desired unity gain frequency then it can
be expected that sufficient phase margin will
In this section the sizing and values of various remain. As a result of this strategy the OTA
components used in the OTA design are derived transfer function effectively becomes equal to
from theoretical analysis. These serve as the Av 0
starting point of Spice simulations. A( s ) = . (7)
 s  s 
The two-stage OTA of Fig. 1 is a system 1 − 1 − 
consisting of a single zero and three poles. Its  p1  p 2 
transfer function can be written as [1]: The loop gain expression then is
 s βAv 0
1 −  T (s) = , (8)
 z1   s  s 
A( s ) = Av 0 , (1) 1 − 1 − 
 s  s  s   p1  p 2 
1 − 1 − 1 − 
p p p where β is the "return factor". For this project β
 1  2  3 
is 0.5, assuming the OTA's input capacitance is
where Av0 is the dc gain given by
negligible compared to feedback (Cf) and
g m 2 g m5
Av 0 = , (2) sampling capacitance (Cs).
( g ds 2 + g ds 4 )( g ds 5 + g ds 8 ) At the unity gain frequency ωu, |T(s)| = 1.
z1 is a zero given by From (8) it can be shown that
1  ω2 
z1 = , (3) Av20 β 2ω p21 = ω u2 1 + 2u  . (9)
 1   ω 
C c  − R z   p2 
g
 m5  Equation (9) provides a relation between the two
and p1, p2, and p3 are the three poles of the poles of the system and the desired gain and
system given, respectively, by unity gain frequency.
1 The phase margin (PM) is the additional
p1 = − (4)
C1 + C c C 2 + C c g m5 C c phase required to bring the phase of T(s) to 180.
+ +
g ds 24 g ds 58 g ds 24 g ds 58 It is given as
where gds24 = (gds2 + gds4) and gds58 = (gds5 + gds8), ω 
PM = 90° − tan −1  u  . (10)
g m5 ω 
p2 = − , (5)  p 2 
 C1  The closed loop transfer function of this two-
C1 +  + 1C 2
 Cc  pole system is given by
and Av 0 p1 p 2
H ( s) = 2 (11)
1 s + s ( p1 + p 2 ) + p1 p 2 (1 + β Av 0 )
p3 = − . (6)
R z C1 from which the unit step response, assuming a
In equations (4), (5), and (6) C1 and C2 linear system, is obtained as
represent, respectively the input capacitance of  Av 0  sin( µt + φ 
S (t ) =  1 − e − ρt  , (12)
the second common source stage, and the total  1 + β Av 0  sin(φ ) 
load capacitance. It can be assumed that C1 is
where
equal to Cgs5 and C2 is equal to the load
1
capacitance CL plus (Cdb5 + Cdb8). ρ = (ω p1 + ω p 2 ) , (13)
The design strategy used in this work is to 2
1
choose Cc and Rz such as to cancel the non- 4 βAv 0ω p1ω p 2 − (ω p1 − ω p 2 ) , (14)
2
µ=
dominant pole at p3 with the zero, resulting in a 2
second order (two pole) transfer function. µ
and sin(φ ) = . (15)
Secondly, if these can be chosen such that the µ2 + ρ2
remaining non-dominant pole p2 is placed at or
 3
Using the decay envelop function of (12), i.e. decided to use a tail current of roughly one-tenth
ignoring the sinusoidal oscillation term, gives the of the total current budget, i.e. Itail = 50 µA.
settling time ts as Since the Id/W from technology charts at gm/Id of
1 13 is 2.4 µA/µm for L = 1 µm, the necessary
t s = t slew − ln(ε d ,tol ) , (16)
ρ width for M1 and M2 works out to 10.4 µm. The
where the dynamic error tolerance εd,tol is 0.1% widths of the PMOS transistors M3 and M4 are
and estimated in a similar manner assuming they
| V xstep | −2.8 /( g m 2 / I d 2 ) operate at the same gm/Id of 13. The
t slew = . (17) corresponding Id/W from PMOS technology
β × SR charts is 0.675 µA/µm, which implies the width
The terms Vxstep and slew rate SR in (17) are needed for M3 and M4 is 37 µm. Since Id, gm/Id,
given as follows: and gm/gds are known for these transistors, it is
Cs possible to estimate gm and gds of M1 - M4. This
V xstep = Vidstep , (18)
Cs + C f gives gm1 = gm2 = gm3 = gm4 = 0.325 mS, gds1 =
Id7 / 2 gds2 = 2.58 µS, and gds3 = gds4 = 2.32 µS. From
and SR = . (19) this information the low frequency gain of the
Cc
differential stage is estimated to be 66, i.e. 36.4
The theoretical design of the two-stage OTA dB.
is completed using the expressions given above For the common-source stage it is recognized
for the various characteristics. The manner in that in addition to providing the remaining DC
which this is done is described next. gain, M5 will influence the location of pole p2.
First, it is noted that for a maximum power From (5) it is noted that the location of p2 can be
dissipation of 1 mW with a 1.8V supply voltage, increased by increasing gm5 and keeping Cgs5
the total current budget has to be limited to 555 low. Increasing the width of M5 helps increase
µA. Next, since a DC small signal gain of about its gm but also increases its Cgs and its bias
3162 (70 db) is desired, it is meaningful to aim current. Thus, it is better to reduce the length of
for gain of √3162 = 56 in each of the two stages. M5. However, it should be kept in mind that
For the architectures used in the two stages, this lowering L results in a loss of intrinsic gain
implies an intrinsic gain (gm/gds) of about 112 for gm/gds. It was decided to back off from the
each stage. The logic behind this is as follows. minimum channel length and as a compromise L
Referring to Fig. 1, the gain of the differential = 0.28 µm was chosen for M5. Using similar
stage is given as gm2/(gds2 + gds4). Assuming reasoning as for the differential stage, a gm/Id of
roughly equal gds in M2 and M4, the low 16 was selected to give an intrinsic gain gm5/gds5
frequency gain of the differential amplifier can of about 100 and a Id/W of 1.6 µA/µm.
be approximated as one-half of its intrinsic gain. Next, an approximate value of gm5 can be
Therefore, to get a gain of 56, an intrinsic gain of estimated from (5) assuming C2 = CL, ignoring
112 is desired. The same reasoning is applicable the effect of C1, and taking p2 to be located at 4x
to the common-source stage. To achieve this the desired unity gain frequency of 100 MHz.
level of intrinsic gain in the NMOS input Since CL = 1 pF, the resulting value of gm5 is 2.5
differential stage, it is decided to use L = 1 µm mS. To provide some additional design margin
for M1 and M2. The same L is used for the gm5 = 3 mS is used. This results in a Id of 187 µA
PMOS load transistors M3 and M4 in order to which is rounded up to 200 µA and gds5 of 25 µS.
keep their output conductance low. From
The required width of M5 then is 125 µm.
technology charts generated for L = 1 µm, it is The sizes of the remaining transistors, M6 -
found that an intrinsic gain of about 112 occurs M8, and the reference current are fixed next. Iref
at gm/Id of about 6. In order to keep some margin is chosen to be 50 mA, equal to the tail current of
it is decided to use a gm/Id of 13 which the differential stage. M6 and M7 are sized as
corresponds to an intrinsic gain of 126. 40/10. The long channel length allows the tail
Furthermore, in order to conserve power, it is
 4
resistance to be kept at a high value which helps Regarding CMRR, which is the ratio of the
CMRR. Since M8 needs to carry 4x the reference differential mode gain to the common mode gain
current it needs a 4x larger W/L ratio. Increasing (Acm), it is sufficient to compute this ratio for the
its W to 160 would result in a large Cdb8 which differential stage only. The differential mode
would add to the load on the OTA. Instead, a gain of this stage is already shown to be 36.4 dB.
16/1 size is chosen for M8. Since M8 carries 200 The common mode gain is given by gds7/(2gm3).
µA, its Id/W is 12.5 µA/µm which implies a gm/Id gds7 is estimated in the following manner. M7 is
of 5.8 V-1 and gm/gds of 111 from the technology designed to carry 50 µA and has a width of 40
charts. From this gds8 = 10.5 µS. The low µm, implying a current per width of 1.25
frequency gain of the common source stage is µA/µm. From the technology charts the value of
given by gm5 /( gds5 + gds8) and equals 84.5 (i.e. lambda at this Id/W is 0.13 V-1 for an NMOS
38.5 dB). The total OTA low frequency gain transistor with L = 1. Since M7 has L = 10, its
then works out to 74.9 dB which exceeds the 70 lambda in reality will be lower than this value.
dB specification. Therefore, gds7 will be no higher than 0.13 times
The last remaining part of the design is to Id7, i.e. 6.5 µS. This implies Acm will be at most -
estimate values for the compensation capacitor 40 dB since gm3 is known to be 0.325 mS and the
Cc and the nulling resistor Rz. To estimate a CMRR will be greater than 76.4 dB.
value for Cc the location of the pole p1 is first Values of various additional circuit
estimated as ωu/( β Av0) = 35.7 kHz. Then from specifications can now be calculated using the
(4) Cc is approximated as: expressions given earlier in this section. These
1 ( g ds 2 + g ds 4 )( g ds 5 + g ds 8 ) hand-calculated values are summarized in the
Cc ≈ . (20) Table II. It is noted that the unity gain frequency
2π p1 g m 5
is slightly lower than than desired. At this stage
Inserting the previously obtained values for the
it is considered close enough. During the final
various quantities on the right hand side of (20)
tuning of the design using Spice the unity gain
gives Cc of 259 fF. Since the strategy used in this
frequency will be increased to meet or exceed
design is to attempt to cancel the p3 pole with the
the specification value (e.g. by increasing gm5).
zero, the required value of Rz can be estimated
by equating (3) and (6). The result is: Table II. Summary of hand calculated values of various
Cc design specifications.
Rz = . (21)
g m 5 (C c − C1 ) Specification Hand calculation
DC small-signal gain > 70 dB 74.9 dB
C1 can be approximated as Cgs5, which in turn Unity gain frequency > 100 MHz 90 MHz
can be found from the transit frequency (fT) plots Phase margin > 45° 67.4°
on the technology charts. Since gm/Id of M5 was Power Consumption < 1 mW 0.54 mW
previously estimated as 16, the corresponding fT Settling Up < 40 ns 22 ns
value for L = 0.28 µm is 3.5 GHz. Cgs5 is then time Down < 40 ns 22 ns
CMRR at DC > 70 dB 76.4 dB
obtained as gm/(2π x fT)( Cgs5/ Cgg5) = 250 fF.
Using this value in (21) gives Rz = 9.7K.
III. SIMULATION RESULTS
Since the values of all elements of the design
are now available, it is useful to compute the
Upon completion of the initial design, the
locations of the various poles and zeroes to
schematic of the OTA is input into Cadence and
ensure that the assumptions made during the
simulated. Some minor adjustments are made to
design procedure are satisfied. Using equations
bring the various specifications within their
(3) - (6) the calculated pole and zero values are
acceptable values / ranges. The main adjustments
as follows:
needed were in the sizing of M3 and M4 as well
fp1 = -34.6 kHz
as M8 in order to reduce the input referred offset
fp2 = -215.5 MHz
fp3 = -65.37 MHz voltage to under the specified 10 µV limit and to
fz1 = -65.37 MHz increase gm5 so as to able to meet the minimum
 5
unity gain frequency requirement. Rz also had to (not shown in Fig. 3) is inserted in series with
be adjusted to meet the settling time requirement. the feedback capacitor in order to run a stability
Table III lists the initial and final sizes of the analysis.
various transistors.

Table III. Comparison of the initial and final sizes and

component values.
Component Initial Value Final Value
M1 10.4/1 10/1
M2 10.4/1 10/1
M3 37/1 26/1
M4 37/1 26/1
M5 125/0.28 127/0.28
M6 40/10 10/10 Fig. 3. Circuit setup used for measuring loop gain.
M7 40/10 40/12
M8 16/1 19.8/1
Rz 9.7K 12K
Fig. 4. shows the corresponding results obtained
Cc 259 fF 250 fF from a stability analysis. The unity gain
Iref 50 µA 12.46 µA frequency is 101 MHz and the phase at this
frequency is -124.8 degrees, implying a phase
Fig. 2 shows the open-loop frequency response margin of 55.2 degrees.
of the OTA. The open-loop gain of the OTA is
74.25 dB. The unity gain frequency is 169 MHz
and the phase at this frequency is -157 degrees.

(a)

(a)

(b)
Fig. 4. Loop gain frequency response: (a) magnitude, (b)
phase.

(b)
Fig. 2. Frequency response of OTA: (a) magnitude, (b)
Fig. 5 shows the setup used to measure settling
phase. times from the output voltage transient. Settling
times are measured for both an upward going
Fig. 3 shows the setup used to obtain the loop step input (0.9V to 1.5V in 10 ps risetime) as
gain frequency response. An “iprobe” element
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well as a downward going step input (0.9V to expected from theory the settling transients show
0.3V in 10 ps risetime). some oscillations. These oscillations are clearer
in Fig. 7. The period of the oscillation obtained
from simulations is about 140 MHz. In
comparison, the theoretically expected frequency
from (14) is about 100 MHz.

Fig. 5. Circuit setup used for measuring settling time.

Fig. 6. shows the output voltage settling time

obtained from a transient analysis for a
downward going input step. The settling time for
this case is found to be about 21.4 nanoseconds. (a)

(b)
(a) Fig. 7. Output voltage transient for a upward going input
step function. (a) expanded view and (b) zoomed in view.

Fig. 8 shows the OTA DC gain as a function of

output voltage. The values of the output voltage
at which the gain drops to 67 dB are taken as the
limits of the output swing. From the simulated
results it is seen that the output swing is [0.275,
1.56].

(b)
Fig. 6. Output voltage transient for a downward going
input step function. (a) is expanded view and (b) is a
zoomed in view.

Fig. 7 shows the output voltage settling time

obtained from a transient analysis for an upward
going input step. The settling time for this case is
found to be about 32.4 nanoseconds. As Fig. 8. OTA gain as a function of output voltage.
 7
The total power consumption of the OTA is
Fig. 9 shows the gain of the OTA as a function found by multiplying the total current supplied
of the input common mode voltage. It is seen by the 1.8V power supply when a 0.9V input is
that over the range of the desired input common applied. This current is found to be 259.6 µA,
mode range the gain does not change which implies a total power consumption of
appreciably. 0.467 mW.
Lastly, a discussion is provided to address
differences between the initially calculated
values of the OTA specifications and the final
realized numbers. Table III shows a summary of
this information.

Table III. Summary of hand calculated values of various

design specifications versus final simulated values.
Hand Final
Calculation Simulation
DC small-signal gain 74.9 dB 74.25 dB
Fig. 9. OTA gain as a function of input common mode Unity gain frequency 90 MHz 101 MHz
voltage. Phase margin 67.4° 55°
Power Consumption 0.54 mW 0.467 mW
Fig. 10 shows the CMRR behavior of the OTA. Settling Going up 22 ns 21.4 ns
It is seen that at low frequencies the CMRR is time Going down 22 ns 32.4 ns
CMRR at DC 76.4 dB 70.35 dB
70.35 dB.
The differences in unity gain frequency and
phase margins were expected. During the initial
design by hand it was noted that the unity gain
frequency was a little lower than desired, but it
was decided to do the final tuning in the
simulation phase together with other inevitable
discrepancies. These values, together with the
settling time are dependent on the locations of
the poles and zeroes of the system. During the
final design phase the values of Rz and Cc were
Fig. 10. OTA CMRR as a function of frequency.
modified to attain the desired 100 MHz unity
gain frequency by sacrificing some phase
Fig. 11 shows the PSRR behavior of the OTA. It margin. The settling time difference in the
is seen that at low frequencies PSRR is 76.8 dB. downward step input can be attributed to the fact
that the slewing time was underestimated The
lower power consumption number in the final
design is due to the fact that the reference current
was reduced from 50 µA to 12.46 µA while
increasing the current mirror ratio up to the
allowed limit of 20 in the final design. This
allows a reduction in power consumption. The
difference in CMRR is due to an under-
estimation of gds7 in the hand calculations. M7
operates near the edge of saturation and its gds is
Fig. 11. Magnitude of OTA PSRR as a function of likely to be higher than what is estimated from
frequency.
the technology charts.
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REFERENCES
IV. CONCLUSIONS
[1] P. R. Gray, P. J. Hurst, S. H. Lewis, and R.
The design of a low-power OTA is described G. Meyer, Analysis and Design of Analog
in the report. A pole-zero cancellation strategy is Integrated Circuits, 4th ed. New York: Wiley,
used in this design allowing some flexibility in 2001.
tuning the unity gain frequency, phase margin,
and settling time. The specifications provided are
met or exceeded. An initial design by hand is
done which serves as the starting point for the
final simulation based refinement. Differences
between the hand calculations and final
simulated results are described.