Chapter Five Solutions

1.

a. i. 6Δ
ii. Also 6Δ, since B' passes through only 5 gates.
b. 3Δ

2. a. The truth table for this module is

a b c y s t
0 0 0 0 1 0
0 0 1 0 1 1
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 1 0 0
1 0 1 1 0 1
1 1 0 1 0 1
1 1 1 1 1 0

The maps and equations for these functions are shown next.

y=a+bc s = a' b' + a' c' + a b c t = b' c + b c'

b. The delay from c to y is 2 for each module. The total delay is 32 + 1 (where the
extra delay is to produce c' in the last module).

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1
3. a. bi = ai ci-1 + ai' ci-1' = (ai ⊕ ci-1)' = ai' ⊕ ci-1
ci = ai' ci-1

For the least significant bit, the c input is 1, and thus, b0 = a0 and c0 = a0'. The circuit for the
typical bit (using NAND gates) is

b. The delay is 2n + 1.
c. The truth table for the second module is

a3 a2 c1 c3 b3 b2
0 0 0 0 1 1
0 0 1 1 0 0
0 1 0 0 1 0
0 1 1 0 1 1
1 0 0 0 0 1
1 0 1 0 1 0
1 1 0 0 0 0
1 1 1 0 0 1

c3 = a3' a2' c1

The maps for the other outputs are:

b3 = a3' c1' + a3' a2 + a3 a2' c1

b2 = a2' c1' + a2 c1

The circuit for b3 is the same as that for bi in part a. That for c3 requires a three input NAND
and a NOT, producing a delay of 2 for each 2-bit stage. The circuit for b3 requires four NANDS.

2
 The total delay is n + 1 (two delays per two bits).

4. A carry of two can be shown as 10 (first set of output columns), in which case uv are
never 11. Or, a carry of two can be shown as 11 (second set of output columns), in
which case we just count the number of 1 inputs,

u v x y z f g s f g s
0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 1 0 0 1 0 0 1
0 0 0 1 0 0 0 1 0 0 1
0 0 0 1 1 0 1 0 0 1 0
0 0 1 0 0 0 0 1 0 0 1
0 0 1 0 1 0 1 0 0 1 0
0 0 1 1 0 0 1 0 0 1 0
0 0 1 1 1 0 1 1 0 1 1
0 1 0 0 0 0 0 1 0 0 1
0 1 0 0 1 0 1 0 0 1 0
0 1 0 1 0 0 1 0 0 1 0
0 1 0 1 1 0 1 1 0 1 1
0 1 1 0 0 0 1 0 0 1 0
0 1 1 0 1 0 1 1 0 1 1
0 1 1 1 0 0 1 1 0 1 1
0 1 1 1 1 1 0 0 1 1 0
1 0 0 0 0 0 1 0 X X X
1 0 0 0 1 0 1 1 X X X
1 0 0 1 0 0 1 1 X X X
1 0 0 1 1 1 0 0 X X X
1 0 1 0 0 0 1 1 X X X
1 0 1 0 1 1 0 0 X X X
1 0 1 1 0 1 0 0 X X X
1 0 1 1 1 1 0 1 X X X
1 1 0 0 0 X X X 0 1 0
1 1 0 0 1 X X X 0 1 1
1 1 0 1 0 X X X 0 1 1
1 1 0 1 1 X X X 1 1 0
1 1 1 0 0 X X X 0 1 1
1 1 1 0 1 X X X 1 1 0
1 1 1 1 0 X X X 1 1 0
1 1 1 1 1 X X X 1 1 1

3
The maps for the first solution are shown below

The equations are quite complex. Only the first of the multiple solutions for g is circled on the
maps and listed below. There are two ways to cover the 1's circled in red and seven ways to
cover the 1's circled in green.

4
f=vxyz+uyz+uxy+uxz
g = u y' z' + u x' y' + u x' z' + v x y' + v x' z + v y z' + u' v' x z
+ u' v' y z + u' v' x y
s = v' x' y' z + v' x' y z' + v' x y' z' + v' x y z + v x y' z + v x y z'
+ v x' y' z' + v x' y z'

For the second version, the minimum solution is unique.

f=vxyz+uyz+uxy+uxz
g=u+vx+vy+vz+xy+xz+yz
s = v' x' y' z + v' x' y z' + v' x y' z' + v' x y z + u' v x y' z + u' v x y z'
+ u' v x' y' z' + u' v x' y z + u x y' z' + u x y z +
u x' y' z + u x' y z'

5. A truth table for the product is shown below

a b C d w x y z
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 0
0 0 1 0 0 0 0 0
0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 0
0 1 0 1 0 0 0 1
0 1 1 0 0 0 1 0
0 1 1 1 0 0 1 1
1 0 0 0 0 0 0 0
1 0 0 1 0 0 1 0
1 0 1 0 0 1 0 0
1 0 1 1 0 1 1 0
1 1 0 0 0 0 0 0
1 1 0 1 0 0 1 1
1 1 1 0 0 1 1 0
1 1 1 1 1 0 0 1

5
There is no need to map w; it is a b c d. The other maps are

w=abcd
x = a b' c + a c d'
y = a' b c + a c' d + b c d' + a b' d
z=bd

We could save one gate by sharing in x and y in either of two ways:

x = a b' c + a b c d'
y = a' b c + a c' d + a b c d' + a b' d
or
x = a b' c d + a c d'
y = a' b c + a c' d + b c d' + a b' c d

6. a.

6
 b. Equal = (a3 b3 + a3' b3') (a2 b2 + a2' b2') (a1 b1 + a1' b1')
Greater = a3 b3' + (a3 b3 + a3' b3') a2 b2'
+ (a3 b3 + a3' b3') (a2 b2 + a2' b2') a1 b1'

c. We need 7 2-input ANDs 2 packages

2 3-input ANDs 1 package
1 4-input AND 1 package
3 2-input ORs 1 package
1 3-input ORs 1 package

Packages would have to cost less than 12.5¢ for the AND/OR to be more economical.

If we could use Exclusive-NORs, we would need 3 XNOR (1 package) and 1 2-input AND,
2 3-input ANDS, a 4-input AND and a 3-input OR. That would require only 4 packages. It
would be less expensive if packages cost less than 25¢.

7.
a b C X Y
0 0 0 0 0
0 0 1 0 1
0 1 0 0 0
0 1 1 1 1
1 0 0 0 0
1 0 1 1 1
1 1 0 1 0
1 1 1 1 1

7
8.

The first output decoder is enabled when x is 1 and the second when x is 0. Alternately, we
could have connected the first decoder in any of the following ways.

9.

8
10.

11.
1' 2' 3' 4' 5' 6' 7' C B A
1 1 1 1 1 1 1 0 0 0
0 X X X X X X 0 0 1
1 0 X X X X X 0 1 0
1 1 0 X X X X 0 1 1
1 1 1 0 X X X 1 0 0
1 1 1 1 0 X X 1 0 1
1 1 1 1 1 0 X 1 1 0
1 1 1 1 1 1 0 1 1 1

C = 1' 2' 3' (4' ' + 5' ' + 6' ' + 7' ')
B = 1' (2' ' + 3' ') + 1' 4' 5' (6' ' + 7' ')
A = 1' ' + 2' 3' ' + 2' 4' 5' ' + 2' 4' 6' 7' '

12. See Answers in Appendix B.

9
13.
A B C D F
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 N
0 1 0 1 P
0 1 1 0 Q
0 1 1 1 R
1 0 0 0 S
1 0 0 1 T
1 0 1 0 U
1 0 1 1 V
1 1 0 0 W
1 1 0 1 X
1 1 1 0 Y
1 1 1 1 Z

14. F = A’ B’ W + A’ B X + A B’ Y + A B Z

15. a. i.

10
 ii. We start by mapping the three functions and finding the minimum using
sharing.

F = B C + A B' G = B C' + B' C + {A B or A C} H = B' C + A B'

iii.

11
b. i.

ii. Taking advantage of the maximum amount of sharing, we need only four
terms.

W = B' C' + A' B' C X = B' C' + B C

Y = B C' + A' B' C Z = B C + B C'

12
c. Note that Z = B. That requires a gate.

13
 c. ii. We will map the functions first, and then show the ROM and PLA
implementations.

i.

14
ii.

Note that part ii only requires 6 terms..

iii.

For this part, we do not use sharing.

15
d. i. The ROM is shown below.

ii. The maps are

16
 F = A' B' C' D + A' C D' + A' B C + A C' D' + A C' D
G = A' B' C' D + A B' + A C' D + A C D
H = A' B' C' D + B C + A C' D' + A C D

and the PLA diagram is

iii. For the PAL, we must solve F individually, since the solution above requires four
terms, and the PAL only has three AND gates for each output. The equations are
thus

F = A C' + A' B C + A' C D' + B' C' D

G = A B' + B' C' D + A D
H = A' B' C' D + B C + A C' D' + A C D

We will not show the PAL diagram.

16. For both parts a and c, we need the minterms; for part b, we need to map the functions
to find a shared solution. We can most easily find the minterms from the maps.

17
 WX WX
00 01 11 10 YZ 00 01 11 10
YZ
00 1 00 1 1

01 1 1 1 01 1 1 1

11 1 1 11

10 10
F G
F (W, X, Y, Z) = ∑ m (0, 1, 3, 5, 7, 13)
G (W, X, Y, Z) = ∑ m (0, 1, 8, 9, 13)

F = W' Z + W' X' Y' + W X Y' Z

G = X' Y' + W X Y' Z

a. The ROM diagram is not shown.

b. The PLA diagram is shown below.

W X Y Z

W' Z
W' X' Y'
W X Y' Z
X' Y'

F G

c. From the maps, we can see that we do not have any 1's in the
last row of the maps. Thus, if we use Y and Z to enable the decoders, then we
only need three decoders. (The first decoder is used for minterms 0, 4, 8 and
12; the second for 1, 5, 9, and 13; and the third for 3, 7, 11 and 13.)

18
 W A 0
0
X B
1
8
Y EN1' 2
Z' EN2 3

F
W A 1
0
X B 1
5
9
Y EN1' 2
13
Z EN2 3

G
W A 0 3

X B 1 7

Y' EN1' 2
Z EN2 3

17. The first step is to map the three functions. That will enable us to find the minterms for
parts a and c, and the shared solution for part b.

a. f (a, b, c, d) = Σ m (0, 3, 5, 7, 8, 13, 15)

g (a, b, c, d) = Σ m (0, 3, 4, 5, 6, 8, 12, 13, 14)
h (a, b, c, d) = Σ m (3, 4, 6, 7, 9, 11, 12, 14, 15)

(The ROM diagram is not shown.)

b. f = b' c' d' + a' b' c d + b c' d + b c d

g = a' b' c d + b' c' d' + b d' + b c' d
h = a b' d + b d' + b c d + a' b' c d

19
Only a b' d is not shared; there are a total of six product terms used among the three functions.
The PLA diagram is

c. Since complemented variables and NOT gates are unavailable, we need one
decoder to enable the output decoders. (These produce minterms which are then
ORed appropriately to give the three functions. The OR gates are not shown.)

20
18. We first map the three functions and find minimum sum of products for each.

21
 X = A' B' D' + C D' + A B D + B C
Y = A C' D' + A B D + A' B C + B' C D' or
= A' C D' + B C D + A B C' + A B' D'
Z = B' C' D' + A B D + B C D' + {A B' D' or A C D'}

We can share A B D between X and Z. We can also share it with Y or we can share A B' D'
between Y and Z. In either case, we will need 13 gates with 40 inputs.

The maps below show the solution taking maximum advantage of sharing.

X = A B D + A' B’ C’ D’ + A' B C + B C D' + B’ C’ D’

Y = A C' D' + A B D + A' B C + B’ C’ D’
Z = A B D + A' B’ C’ D’ + A B' D' + B C D'

This requires only 10 gates with 35 inputs. A block diagram of this solution is shown below.

22
b. The solution is straightforward; the diagram is not shown.

c. We need two decoders. A is connected to the enable of the first. The outputs
correspond to the first 8 minterms. A' is used to enable the second, producing the
other 8 minterms. Only three OR gates are needed.

d. The second sum of products solution uses only seven terms (and thus can be
implemented on that PLA). The first requires 10 terms (and would not fit). A
solution with less sharing that uses eight terms would work.

e. The PAL would be implemented with the first solution.

23
19. The carry between the two stages is just

c = a0 b0 + a0 cin + b0 cin
Then
cout = a1 b1 + a1 c + b1 c
s1 = c' a1' b1 + c' a1 b1' + c a1' b1' + c a1 b1
s0 = cin' a0' b0 + cin' a0 b0' + cin a0' b0' + cin a0 b0

The implementation of a PAL is now staightforward, with the c output used as an input for cout
and s1.

20. The maps for the sum of product solutions are shown on the next page.

a. The minimum solutions are:

w = a' e + a' d or a' b' + a' c'
x = c d' e' + b' c'
y = a' c + a c' d'
z = a' d' + a c' e'
w = a' (b' + c') or a' (d + e)
x = (b' + c) (a + b + c')
y = (a' + b + e) (a + c)
z = (a + d') (a' + b + d)

24
25
 b. c. The sum of products solution requires 9 two-input NAND gates and 3 three-input
gates, a total of 4 packages. The product of sums solution requires 8 two-input
NOR gates and 3 three-input ones, only 3 packages. There is no need for a four-
input gate.

d. Only the 1's of each function need be marked on the ROM. For this, the minterm
numbers are useful.

w (a, b, c, d, e) = Σ m (3, 5, 7, 9, 10)

x (a, b, c, d, e) = Σ m (3, 12, 17, 18, 20)
y (a, b, c, d, e) = Σ m (6, 7, 12, 17, 24)
z (a, b, c, d, e) = Σ m (5, 9, 12, 18, 24)

e. f. The minimum sum of product expressions for these can be used.

The diagrams for d, e, and f are straightforward and have been omitted.

21. a. The maps for the minimum solutions are shown on the following page. The
underlined terms are shared.

X1 = B' D'2 + B D + A C'1 + A' C

X2 = B' + C' D' + A D' + A C'1 + A' C D
X3 = D + B' C' + A' B + A C4 ***
or
= D + A' C' + B C + A B'
X4 = B' D'2 + A' B' C5 + A' C D'6 + B C' D + A B D + A C'1
X5 = B' D'2 + A' C D'6 + A C' D'
X6 = A' B C' + A B C + A B' C' + {B' C' D' or A' C' D'} +
{A C D' or A B' D'} + {B C D' or A' B D'}
X7 = B C' + A C'1 + A B3 + A' B' C5 + {A' C D'6* or B D'}
X8 = A B3 + A C4
*
Solving X7 alone, your would use BD' in place of A' C D'. But, the latter is also a prime
implicant and can be shared, saving one gate and two inputs. That is reflected in the count.

26
Package Count
X1: 2 2 2 2 4
X2: 0 2 2 (2) 3 5
X3: 0 2 2 2 4
X4: (2) 3 3 3 3 (2) 6
X5: (2) (3) 3 3
X6: 3 3 3 3 3 3 6
X7: 2 (2) 2 (3) (3) 5
X8: (2) (2) 2

2's: 12 7430s: 4 31 gates/93 inputs

3's: 13 7420s: 1
4's: 2 7410s: 5 (2 left over)
5's 2 7400s: 3 (use one 3-input)
6's: 2 Total: 13 Cost: $3.25

27
28
b. The maps are shown on the following page.

X1 = B' D'1 + A C'3 + A' C D2 + B D

X2 = B' + A' C D2 + A C'3 + C' D' + A C D'8

X3 = D + A C D'8 + B' C' D'10 + A' B D'5

X4 = A' B' C4 + B' D'1 + A C'3 + A' C D'7 + A' B C' D6 + A B C D9

X5 = B' D'1 + A' C D'7 + A C' D'

X6 = A C D'8 + B' C' D'10 + A B C D9 + A' B C' D6 + A B' C' + A' B D'5

X7 = A' B' C4 + A C'3 + A' B C' D6 + A B11 + A' B D'5

X8 = A C + A B11

X1: 2 2 3 2 4
X2: 0 (3) (2) 2 3 5
X3: 0 (3) 3 3 4
X4: 3 (2) (2) 3 4 4 6
X5: (2) (3) 3 3
X6: (3) (3) (4) (4) 3 (3) 6
X7: (3) (2) (4) 2 (3) 5
X8: 2 (2) 2

2's: 7 7430s: 4
3's: 9 7420s: 2
4's: 4 7410s: 3
5's 2 7400s: 2
6's: 2
11 chips

29
30
 c. The PLA implementation of part b would require 18 product terms, one for each
of the product terms shown, including the single literal terms (D' in X2 and B in
X3). We could do this with only 16 product terms if we treated the PLA as a ROM
(that is, created the 16 minterms). This would not have worked for part b, since it
requires gates of more than 8 inputs for those functions with more than 8
minterms (all but X5 and X8).

22. a. All of the solutions for each function, treating this as seven separate
problems are

a = w' x' z' + w' y' z' + w x y + x y z + {w' x' y' or x' y' z} +
+ {w x z or w y' z}
b = x' y' + w' x' z' + w x y + {w x z or w y' z}
c = w' x' z' + w x y + {[w' x' y' + x y' z] or [w' y' z + x y' z] or
w' y' z + w x z]}
d = w x + x y z + w' x' y' + x' y z' + {w' y' z' or x y' z'}
e = z' + w' x' y' + w x + x y
f = w' y' + y z' + w x z
g = w' x' + w' y' z' + w x z + w y z'

31
Taking maximum advantage of sharing, we get the following maps and equations:

32
a = w' x' z'1 + w' y' z'2 + w x y3 + x y z4 + w' x' y'5 + w x z6
b = x' y' + w' x' z'1 + w x y3 + w x z6
c = w' x' z'1 + w x y3 + w' x' y'5 + x y' z
d = w x7 + x y z4 + w' x' y'5 + x' y z' + w' y' z'2
e = z' + w' x' y'5 + w x7 + x y
f = w' y' + y z' + w x z6
g = w' x' + w' y' z'2 + w x z6 + w y z'

7 shared gates
2-in 6 1 7400 (use left over 3's)
3-in 10 4 7410
4-in 4 2 7420
8-in 2 2 7430

22 gates, 69 gate inputs

33
b. A solution that uses 18 gates with 62 gate inputs (but the same number of integrated
circuit packages) is shown in the following maps and table:

34
 a b c d e f g
w'x'y' 3 X X X
w'y'z' 3 X X X X
w'x'z' 3 X X X X
wxz 3 X X X X X X X
wxy 3 X X X
xyz 3 X X X
x'y' 2 X
w'y'z 3 X X
wyz' 3 X X
z' 0 X
yz' 2 X
w'x' 2 X
6 4 4 6 4 4 4

2-in 3 1 7400
3-in 8 3 7410
4-in 5 3 7420
8-in 2 2 7430

c. The PLA can use the solution of part b.

23. a. The maps of the three functions are shown on the next page.

f = c e + a' c' e' + c' d' e'

g = a' c e + a' c' d e' + a b' e' + a b c' e + {a b' c or b' c e}
h = a b c + b c e' + a' c' d e' + a b' e' + a' b d' e

where the underlined terms could be shared. (14 gates, 48 gate inputs).

35
b. The maps are shown on the next page.
f = c' d' e' + a' c e1 + a' c' d e'2 + a b' c e3 + a b c e4
g = a' c e1 + a' c' d e'2 + a b' e'5 + a b c' e + a b' c e3
h = b c e' + a' b d' e + a' c' d e'2 + a b c e4 + a b' e'5

36
c. The PLA follows directly from the solution to part b .

37
24. a.

f = b' c d' + b c' d' + a' b' c' d + a b c d e + {a' c d' e' or a' b d' e'}
g = b' c d' + a' c d' e' + a' b' d + b c' d + a b d e
h = d' e' + b' c d' + a' c' e' + b' c' d + a c d e + {a b' d or a b' c or a b' e'}

b. The maps are shown on the following page.

f = b' c d' + b c' d' + a' b' c' d + a b c d e + a' c d' e'
g = b' c d' + a' c d' e' + a' b' d + b c' d + a b d e
h = d' e' + b' c d' + a' c' e' + b' c' d + a c d e + a b' d

f: 3 3 4 5 4 5
g: (3) (4) 3 3 4 5
h: (3) 2 3 3 4 3 6

5/6 inputs 4 4
4 inputs 4 2
3 input 7 3
2 input 1 0 (use left over 3)
9 ($2.25)
c.

f = d' [b c' + c (b' + a' e')] + d (a' + b c e) (a + b' c')

1 2 3 4 5 6 7 A 8 B 9 10
g = c d' (b' + a' e') + d [b (c' + a e) + a' b']
C 11 6 12 13 14 15 16 17 18
h = a c(d e + b') + e' (d' + a' c') + b' (c d' + c'd)
D 19 20 E 21 22 23 24 25 26 27

Uses 27 2-input gates and 5 3-input gates, 9 packages ($2.25)

38
b.

39
d. The maps are shown below

f = b' c d' + b c' d' + a’ b’ c’ d + a' c d' e' + a b c d e

g = b' c d' + a' c d' e + a' b' d + b c' d + a b c d e
h = b' c d' + d' e' + a’ b’ c’ d’ + a' c' e' + a b' d + a b c d e

40
 f: 3 3 4 4 5 5
g: (3) 4 3 3 (5) 5
h: (3) 2 (4) 3 3 (5) 6

5/6 inputs 4 4
4 inputs 3 2
3 input 6 2
2 input 1 0
8 ($2.00)

e. The expressions of part b require 13 terms and are thus not adequate. The expressions
of part d need only 11. They work, as would something in between.

41
42
 25. Two of the four possibilities are shown – High – Left and Low – Right.

The maps for Version High - Left are shown on the next page. The minimum sum of
product solutions are

A = XZ + W'Y + {W'Y'Z' or X Y' Z'}

B = WY
C = WY + XZ + XY
D = WY' + Y'Z' + W'X'
E = YZ + XZ'
F = WY'
G = WY' + Y'Z'
H = XYZ

With the sharing as shown underlined, this requires 5 three-input gates, 10 two-input gates,
and three inverters (to produce B, F and H). This requires two 7410's (with an extra gate) and
three 7400's (with two extra gates). The three leftover gates can be used for the inverters.

For the version Low - Left, we need the complement of the same maps (not shown),
which produces the following equations:

A = WY + X'Y’Z + {WY'Z' or XY'Z'}

B = W' + Y'
C= W' X' + Y'Z' + {WY' or X'Y'}
D= XZ + XY + WY
E= X' Z' + Y' Z
F = W' + Y
G= Y + W' Z
H= X' + Y' + Z

With the sharing as shown underlined, this requires 6 three-input gates, and 12 two-input
gates. This requires two 7410's and three 7400's. No inverters are required since term B, for
example, just takes the output of a NAND gate with inputs W and Y.

43
44
 The maps on the next page show Low - Right. This solution only requires four
packages.

A = X + Y' Z + WY
B = W' X' + Y' Z' + {W Y' or X' Y'}
C = W' + Y'
D=WY
E = Y' + X' Z'
F = Y + W' Z
G = W' + Y
H = X' + Y' Z + Y Z'

With the sharing as shown underlined, this requires 3 three-input gates, 11 two-input gates,
and one inverter.

For the High - Right, the equations are

A = W' X' Y + {W Y' Z' or X' Y' Z’}
B=WY+XY+XZ
C=WY
D = W' + Y'
E=YZ+XY
F = W' Y' Z' + W Y'
G = W Y'
H = W' Y' Z' + X Y Z

With the sharing as shown underlined, this requires 5 three-input gates, 9 two-input gates, and
two inverters, for five packages.

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