All-analog Digital Multimeter (DMM)

Submitted in partial requirement for the completion of 6.101

Sam Chinnery∗
[email protected]

May 17, 2018

Abstract
This paper details the design and implementation of an all-analog digital multimeter (DMM).
“All-analog” means the design will be implemented using minimal digital logic.1 This is inher-
ently difficult because it requires the use of analog circuitry to both acquire and digitize signals
corresponding to parameters of the device under test (DUT). For this implementation I intro-
duce a novel ADC topology, herein referred to as the analog modulus computation unit (ACU)
for lack of a better name. Functionally, the meter measures one of four quantities: voltage, cur-
rent, resistance or capacitance; in one of four ranges, for a total of 16 operational modes. The
meter incorporates a three-digit seven-segment display for user interface. This design maintains
greater than 5% accuracy across all modes, with many ranges being within ±1%.

∗
Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology
1
Digital logic is used as necessary for multiplexing and flow control

1
Contents
1 Introduction 3

2 Design overview 3

3 Analog frontend 4
3.1 Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2 Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.3 Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.4 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4 Mixed-signal backend 11
4.1 Analog modulus computation unit (ACU) . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2 Seven-segment display controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3 Control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5 Performance 14

6 Conclusion 14

A Schematics 15

B Pictures 27

List of Figures
1 System block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Voltage module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Current module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 Resistance module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5 Single and dual-op amp current pump configurations . . . . . . . . . . . . . . . . . . 8
6 Output and charging waveforms of 555 astable configuration . . . . . . . . . . . . . . 9
7 Capacitance module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
8 Backend block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
9 Magnitude comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
10 Sample and hold amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2
1 Introduction
Digital multimeters are inherently difficult to implement in the analog domain. Displaying the
base-10 representation of a quantity requires circuitry to discretize an analog signal and convert
it into a user-friendly format. This report details the design of a meter that mimics the function-
ality of a traditional digital multimeter using discrete analog components. The design includes a
discrete analog-to-digital converter (ADC), display driver, analog frontend and mixed-signal back-
end. The device is prototyped on a breadboard using through-hole components with the eventual
goal of transferring the design onto a custom printed circuit board (PCB) using surface-mounted
components.
Section 2 is a high-level overview of the entire design, along with a functional block diagram
of the system. Sections 3 and 4 are detailed component-level descriptions of each module in the
frontend and backend respectively. Section 5 is a qualitative analysis of the device’s performance.
Section 6 concludes the report and summarizes the key challenges faced in designing this circuit.
Finally, Appendix A is a comprehensive circuit diagram of the project.

2 Design overview
A block diagram of the system is presented in Figure 1. The design of the meter is divided into
two main sections: frontend and backend. The frontend is mainly analog and consists of four
modules that each convert one parameter to a voltage ranging from 0–5.99 V. The backend is a
mixed-signal circuit comprised of the analog modulus computation unit (ACU), a 1–10 V integer
voltage reference, an analog state machine to store computed values, and a display driver to present
the measured value to the user.

Analog frontend Mixed-signal backend

Integer
Voltage
Voltage
Reference

Control 10
Logic
Current
Display/
4
ACU Decoder

Resistance

3
Input
Terminals 3
State
Capacitance Control

Figure 1: System block diagram

3
 The device under test (DUT) is connected to two input terminals. Depending on which range
the user selects, this signal is connected via an analog multiplexer to one of four frontend modules.
Each module produces an output voltage between 0 and 5.99 V that is proportional to the quantity
being measured. The frontend modules support range switching, and are each configurable to
operate in one of four ranges. Both the current function and range are selected by the user with
rotary switches.
The voltage module contains a programmable attenuator that divides the voltage at the input
terminals by a fixed value to produce a scaled voltage for the backend. The current module is a
selectable shunt resistance designed to be connected in series with a load. A buffer amplifier scales
the voltage dropped across this resistance to yield a voltage proportional to the series current. The
resistance module is a precision voltage-controlled current source that applies a constant current to
the DUT. An amplifier buffers the voltage developed across the load, which is directly proportional
to the resistance.
The output signal from the selected frontend module enters the backend, where it is digitized and
displayed to the user. The ACU combines elements of a flash ADC and a folding ADC to produce a
three-digit BCD output for use with seven-segment displays. It accomplishes this through the use
of nine voltage comparators, with reference voltages set at integer values. The backend’s uniqueness
is in its serialization: it reuses the same circuitry to perform three different computations. Through
use of an analog “state machine,” the ACU implements short-term memory that enables an ADC
to be constructed with fewer components than a traditional flash ADC while preserving accuracy.

3 Analog frontend
The following sections are component-level descriptions of each module in the analog frontend. The
input of each module is connected to the DUT at all times; multiplexing functionality is imple-
mented by use of two relays at the input of each module that isolates the circuit from the input
terminals if it is not currently selected.

Note: These sections and the remaining circuit descriptions make references to the schemat-
ics found in Appendix A. Each section contains the appropriate schematic sheet for that
module. The sheet title and number can be found in the sheet’s title block (located in the
top-right corner of the page when viewed in portrait orientation).

3.1 Voltage
Reference: Appendix A, sheet 10 (“Four-range precision voltage divider/attenuator”)
The voltage module is a precision programmable attenuator that operates in four ranges. The
attenuator is a four-tap resistor divider, which operates according to the same principles as a
standard resistor divider, but with more than two series elements. This topology was chosen
because it presents the DUT with a constant load impedance regardless of the range, consistent
with many traditional multimeters on the market today. To mitigate measurement error due to
the high impedance of the divider, the selected tap is buffered by an instrumentation amplifier that
scales the reading to a value between 0 and 5.99 V. To calculate the values for the five resistors,
we first consider the standard resistor divider equation:
 
R2
Vout = Vin
R1 + R2
where R1 and R2 are connected at a central node and R2 is connected to ground.

4
 Programmable
Attenuator

1/10

Av = 100 Range Scale Vin /Vout

1/100
Input + 1 600 mV 10
Output 2 6.00 V 100
1/1,000 3 60.0 V 1,000
4 600 V 10,000
1/10,000
(b) Measurement ranges

Input −
Range
4
(a) Functional diagram

Figure 2: Voltage module

For an attenuator with N taps, the absolute and relative voltages at the kth tap are given by:
Pk ! PN
n=1 R n Vin Rn
Vout = Vin PN =⇒ = Pn=1
k
(1)
n=1 Rn
Vout n=1 Rn

where Rn is the nth resistor from the zero potential reference point. For this design, a four-
decade divider was chosen, with division ratios (Vin /Vout ) of 101 , 102 , 103 and 104 . Typical digital
voltmeters have a load impedance between 1 and 10 MΩ. This design uses a 10 MΩ attenuation
network to allow for the measurement of high-impedance circuits. From (1) we can see that, for
each tap,
Vin 10 × 106
= Pk
Vout n=1 Rn
Expanding yields the following system of equations:

R + R2 + R3 + R4 + R5

 1
 = 10 000



 R1

 R 1 + R 2 + R3 + R4 + R5
= 1 000





 R1 + R2
R1 + R2 + R3 + R4 + R5 (2)
= 100
R1 + R2 + R3




R + R 2 + R3 + R4 + R5

1

= 10





 R1 + R2 + R3 + R4
= 10 × 106

R1 + R2 + R3 + R4 + R5


This system can be solved numerically to yield R1 = 1 kΩ, R2 = 9 kΩ, R3 = 90 kΩ, R4 = 900 kΩ,

5
and R5 = 9M Ω. Fortunately, Caddock, Inc. manufactures a divider network with exactly these
values, which was used for this project for simplicity.2
The buffer amplifier used for this module and for many others in the design is the INA114.
It was chosen for its low input bias current (2 nA max) and extremely low offset voltage (50 µV
max). As is typical of instrumentation amplifiers, the INA114 provides connections for an external
resistor to set the gain of the amplifier. As given in the INA114 datasheet,3 the output transfer
function is given by:
+ − 50 × 103
Vo = G(Vin − Vin ), where G = 1 + (3)
RG
To obtain the scales listed in Figure 2, the gain of the amplifier should be set to 100. Substituting
G = 100 into (3) yields RG = 505.1 Ω. For greater accuracy, a 100 Ω potentiometer was used in
series with a 470 Ω resistor to provide for user calibration of the voltage gain. Range selection is
accomplished with a CD4066 quad bilateral analog switch, which is used as a multiplexer to select
a tap on the divider network.

3.2 Current
Reference: Appendix A, sheet 3 (“Four-range selectable shunt/current to voltage converter”)
The current module is a four-range selectable current shunt. To measure current, the DUT is
connected in series with the meter, which selects one of four shunt resistances that will be used
to measure current. By Ohm’s Law, the voltage dropped across the resistor is equal to the series
current times the resistance, or V = IR. In all cases, the voltage dropped across the resistor is set
to 300 mV at the maximum rated current for that range, as this at this scale it is easy to construct
shunt resistors using standard 5%, 1/4 watt resistors. Using the ranges shown in Figure 3, the
values of the shunt resistances were determined to be 0.5 Ω, 5 Ω, 50 Ω and 500 Ω.

Input +

Rx
Range Scale Rx
1 600 µA 0.5 Ω
2 6.00 mA 5Ω
Range 3 60.0 mA 50 Ω
4 4 600 mA 500 Ω
Av = 20
(b) Measurement ranges
Input −
Output

(a) Functional diagram

Figure 3: Current module

One terminal of each shunt resistor is connected directly to the positive input terminal, and
the other terminal is connected to an analog multiplexer that selects which resistance to connect

2
Caddock part number 1776-C68
3
Datasheet retrieved from https://www.ti.com/lit/ds/symlink/ina114.pdf

6
to the negative input terminal in order to complete the circuit. For the current module, the analog
multiplexer was constructed with relays instead of a CMOS switch—for current measurements, it
is critical that little to no voltage is lost except in the shunt resistors for the highest accuracy.
According to the CD4066 datasheet4 , the typical on-resistance of one switch is 125 Ω, with VDD =
15 V and TA = 25◦ C. As this is much greater than the entire shunt resistance for the lower ranges,
current measurement would be extremely difficult without the use of relays.
6.00 V
Once again, the INA114 was used to buffer the output, this time with a gain of 300 mV = 20.
For a gain of 20, RG should be 2.632 kΩ. For greater accuracy and to avoid using unusual resistor
values, RG is implemented as a 2.4 kΩ resistor, a 150 Ω resistor, and a 100 Ω potentiometer in
series. For the relays in the current module, as well as those in all other modules, “snubber” diodes
are connected in parallel with the relay coils to avoid damage to other parts of the circuit due to
inductive kickback (back EMF).

3.3 Resistance
Reference: Appendix A, sheet 8 (“Four-range precision current source/resistance to voltage
converter”)
The resistance module consists of a precision voltage-controlled current source (VCCS) driven by a
constant reference voltage, with four selectable current gains. The VCCS applies a constant current
to the DUT, and the voltage developed across the resistor is measured to give a value proportional
to the resistance. By Ohm’s Law, V = IR =⇒ R = VI . For ease of implementation, output
currents were chosen to give a maximum voltage of 6.00 V at the maximum rated resistance for
each range.

Input +

Range Scale Io
Io Av = 1 1 6.00 kΩ 1 µA
2 60.0 kΩ 10 µA
Output 3 600 kΩ 100 µA
Input −
4 6.00 MΩ 1 mA
Range (b) Measurement ranges
4
(a) Functional diagram

Figure 4: Resistance module

As seen in Figure 3b, the current source used to measure resistance must be able to produce a
wide range of currents, up to four decades (from 1 µA to 1 mA). Several current source and current
mirror topologies were tested for this circuit. Simple single-transistor BJT current sources were
unsuitable because of the significance of the base current IB at extremely low output currents. Using
a JFET solves this problem, but the JFET current source suffers from a limited range. Various
Wilson current mirror5 derivatives were tested as well. The Wilson current mirror performed better
than the single transistor source, but as the circuit is composed entirely of BJTs, each transistor
must have a VBE greater than 0.6 V, which becomes a limiting factor when high variability is
desired.
4
Datasheet retrieved from http://www.ti.com/lit/ds/symlink/cd4066b.pdf
5
See https://en.wikipedia.org/wiki/Wilson current mirror

7
 One particularly interesting circuit is the Howland current mirror, which was actually developed
by Professor Bradford Howland of MIT c. 1962.6 Figure 5a shows the original Howland current
pump. The circuit works as a differential amplifier that forces the voltage VREF to appear across
R3 , causing a constant current Io to flow through the load. The current Io can then be derived:
 
1 R1 R3
Io = VREF , assuming = (4)
R3 R2 R4

However, this circuit has one glaring weakness: with normal op-amps, the output cannot swing as
close to the full supply voltage as is necessary. For example, with R1 = R2 = R3 = R4 = 10 kΩ,
the output can only swing to about ±5 V. To solve this problem, an improved Howland current
pump was implemented as shown in Figure 5b.

R
R1 R2
VREF R
−
Vin RS
+
Vin
R

R3 R4 R
Io
Io + −
Load Vin − Vin
Io = Load
RS

(a) Howland current pump (b) Improved Howland current pump

Figure 5: Single and dual-op amp current pump configurations

The dual op-amp configuration solves the problem with the basic configuration—the output
can swing much closer to the rails due to the second op-amp’s use as a buffer. This configuration
is capable of output swings of ±10 V with ±15 V supplies and exhibits a much higher linearity
than the basic configuration. To select the output current for each range, one of four values of RS
is selected with a CD4066. For the desired output currents of 1 µA, 10 µA, 100 µA and 1 mA,
the values of RS can be determined by the equation in Figure 5b to be 1 MΩ, 100 kΩ, 10 kΩ,
and 100 Ω, respectively. Once again, these resistances are implemented with fixed-value resistors
in series with potentiometers to allow the unit to be calibrated for maximum accuracy.

3.4 Capacitance
Reference: Appendix A, sheet 1 (“Four-range capacitance to voltage converter”)
The capacitance module measures the amount of time taken to charge the DUT through a known
resistance. The first stage of this process is the relaxation oscillator, which is implemented using a
555 timer in the astable configuration. In this configuration the timing capacitor both charges and
discharges through the same resistor, resulting in a duty cycle of roughly 50%. The characteristic
waveforms of an astable 555 oscillator can be seen in Figure 6. In this configuration, the output
6
See http://www.ti.com/lit/an/snoa474a/snoa474a.pdf

8
frequency of the astable oscillator can be derived using the familiar RC time constant equation
(many tedious computations omitted):
  
−t 1 1
V (t) = V0 1 − exp =⇒ f = ≈ (5)
τ 2RC ln 2 0.693 (2RC)

If R is held constant, this configuration of the 555 timer is valuable because it generates a signal
whose frequency is inversely proportional to a capacitance, up to some constant. Moreover, due to
the single-resistor circuit, a “scaling factor” can be applied to this frequency and can be varied by
changing only one resistor.

2
Figure 6: Output and charging waveforms of 555 astable configuration

The signal from the output of the 555 timer then is applied to a frequency to voltage converter.
The converter is implemented using an LM331, which is typically used as a voltage-to-frequency
converter.7 However, it lends itself to the opposite purpose as well, as it contains all the requisite
components for implementing a frequency to voltage converter. Much of the LM331 is functionally
similar to the 555 timer—it implements an RC timing function that is triggered by a threshold
comparator with a reference at 2/3 of the supply voltage. Moreover, the LM331 implements an
R-S flip-flop in the trigger circuit and a bandgap voltage reference to allow for more precise timing.
To use the LM331 as a frequency-to-voltage converter, the input signal is first differentiated by
an RC network to produce a string of pulses. These pulses trigger the timing circuit and cause the
device to output a current that is proportional to the input frequency. A resistor is connected in
parallel with the output to convert the output current to a voltage, thus completing the frequency
to voltage converter. The converter in this implementation generates an output voltage with a fixed
slope of 1 V/kHz. This voltage is directly proportional to the frequency, and therefore inversely
proportional to the capacitance.

7
See http://www.ti.com/lit/ds/symlink/lm331.pdf

9
 As shown in Figure 7, the capacitance module next takes the reciprocal of this voltage to
generate a signal that is directly proportional to the capacitance of the DUT. The reciprocal
operation is accomplished by using an analog multiplier in the feedback loop of an op-amp. The
multiplier causes the amplifier to behave as if it were outputting a voltage a factor of A times
higher, where the multiplier computes the product A × B.

4
Range

Input +
Frequency
555 Av = 1
to
Astable Voltage 1
Vout =
Input − Vin Output

VREF

Figure 7: Capacitance module

For this design, four capacitance ranges were implemented: 6.00 nF, 60.0 nF, 600 nF and
6.00 µF. Since the maximum output voltage of the capacitance module should be 6.00 V, it follows
that the minimum input voltage to the reciprocal circuit should be 16 V, as any voltage lower than
that would result in an output higher than 6 V. For the lowest voltage to appear at the output
of the frequency to voltage converter, the lowest frequency must be present at its input, which
means the timing capacitor for the 555 timer must be at its maximum value for the selected range.
Since the frequency to voltage converter was designed to have a slope of 1 V/kHz, the minimum
frequency must be 1000
6 ≈ 167 Hz. Given this and (5), the four values of R for the 555 timer may
be calculated:
1 1000
For range 1 (6 nF), = =⇒ R ≈ 721 kΩ
2R(6 × 10−9 ) ln 2 6

Similar computations for ranges 2 (60 nF), 3 (600 nF) and 4 (6 µF) yield R = 72.1 kΩ, 7.21 kΩ, and
721 Ω, respectively. These resistors are implemented using potentiometers in series with fixed-value
resistors to allow for calibration. The resistors are selected using a CD4066 analog switch. The
very lowest value resistor (721 Ω) appears on the schematic to be lower than expected (max 490 Ω),
but this was done intentionally to compensate for the ∼150 Ω internal resistance of the CD4066.
The frequency to voltage converter is implemented with a conversion slope of 1 V/kHz. This is
adjustable via a potentiometer which slightly varies the reference current input to the LM331. The
output of this frequency-to-voltage converter must be buffered before being used elsewhere, as the
converter has a high output impedance by nature.
Analog division is implemented with the AD633 analog multiplier used in the feedback loop
of an LM358 general-purpose op-amp. As implemented in this design, the division circuit has a
transfer function of:  
V1
Vout = −10
V2
The factor of 10 is due to an internal voltage reference in the AD633. To eliminate this factor, a
reference voltage of 100 mV is used to cancel out the 10. The voltage reference is obtained via a
voltage divider that divides a 1 V reference from elsewhere in the design by 10. As this voltage

10
is the wrong polarity, the INA114 used to buffer the output has a gain of -1 to generate a strictly
positive output voltage.

4 Mixed-signal backend
The following sections contain component-level descriptions of each module in the mixed-signal
backend. At a high level, the backend is simply an analog-to-digital converter that displays the
output voltage from the frontend on a seven-segment display. This function is accomplished by
the analog modulus comparator (ACU), a seven-segment display controller, and various control
logic. The backend circuitry is unlike the frontend because it uses two supply voltages: the same
±15 V supply used for the frontend, and a +5 V supply for all digital ICs. The 74LS07 high-
voltage open-drain hex non-inverting buffer was used for level conversions throughout the backend
as necessary.

4.1 Analog modulus computation unit (ACU)

Reference: Appendix A, sheets 5–6 (“Analog modulus comparator,” sections 1 and 2)

VREF
10

Input
Magnitude
Comparator

0.1
Display/
Priority Decoder
Encoder 4

0.01 State controller

1 2 3
3 3

Av = 10

Figure 8: Backend block diagram

The ACU converts an analog voltage to digital signals through a serialized process. By operating
as a state machine with three states, the ACU reuses the same circuitry to perform all the necessary
computations for conversion. The core of the ACU is a ten-window magnitude comparator and a
priority encoder. The magnitude comparator computes the floor of the input signal (bVin c). Its
output is a ten-bit bus where the lowest n bits are active, where n is the floor of the input signal.
The bits are ordered from lowest to highest (lowest voltage window to highest voltage window) and

11
applied to a priority encoder. The priority encoder assigns a priority to each input and returns the
binary representation of the highest-priority active bit. This process can be seen in Figure 8.
The output of the priority encoder is also used to generate an analog voltage that represents
the floor of the input signal. The binary output is used with an analog multiplexer to select one of
ten integer voltage references. That signal is then subtracted from the input to yield a voltage that
represents the remainder of the input signal when divided by 1 (Vin % 1). A differential amplifier
then multiplies this signal by 10 and stores it in one of two analog “registers.” This forms the basis
of the conversion process—for each digit, the floor of the input signal is computed and displayed
to the user. At the same time, the remainder voltage is generated and stored in memory.
For each of the three states of the ACU, input multiplexing circuitry selects one of three different
signals to be used as the input to the magnitude comparator: the output of the frontend, or one
of two analog “registers.” At the end of state 1, the amplified remainder voltage is stored in the
first register, representing the tenths’ place of the decimal expansion of the input. The process
is repeated again for state 2, this time storing the result in a register that holds the hundredths’
place. For state 3, the input of the ACU is taken from the second register and displayed to the
user. Technically, this means that the ACU computes a four-digit decimal expansion of the input,
but this result is not stored in memory.

10
VREF

1V
Q1 Av = 1

2V Vin
Q2 RL
HOLD
.. CH
.
10 V
Figure 10: Sample and hold amplifier
Q10
Vin

Figure 9: Magnitude comparator

The magnitude comparator is implemented using two LM339 quad comparators and a single
LM393 dual comparator, as shown in Figure 9. The non-inverting input of each comparator is
connected to a reference voltage, and all the inverting inputs are tied together to the module input.
This implements an inverse window comparator function—for example, if the input voltage is 4.5
volts, four comparators will output a logic low. As both the LM339 and LM393 are open-drain
output, all outputs are pulled up to the +5 V supply through resistor networks. Each analog register
is a sample-and-hold amplifier, as seen in Figure 10. For this design, the AD582 was chosen for its
versatility and ease of use. The sample-and-hold amplifier operates as the name suggests—when
the digital input is active, the sampling switch closes and the hold capacitor charges to the input
voltage. When the digital input is inactive, the sampling switch opens and the output amplifier
“holds” the voltage in the capacitor.
As mentioned above, the ACU operates from both a ±15 and +5 V DC supply. The split supply
is used for all analog components (comparators, analog switches, amplifiers and sample-and-hold

12
circuits). The 74LS07 is used with a pull-up network for logic level conversion.8 The 74LS147
priority encoder is used in this implementation.9 The 74LS147 operates with active-low logic, so
2N7000 MOSFETs are used to invert the outputs before connecting them to the seven-segment
display drivers. The DG406 16-channel analog multiplexer is used to select the reference voltage.10
The INA114 with a gain of 10 was used to implement both subtraction and multiplication for the
computed remainder voltages. From (3), RG must be 5.556 kΩ for a gain of 10. This implementation
uses a 5.1 kΩ and a 470 Ω fixed resistor in series with a 100 Ω potentiometer for greater accuracy.

4.2 Seven-segment display controller

Reference: Appendix A, sheet 4 (“Three-digit seven-segment display controller”)
The seven-segment controller is fairly simple. It uses the CD4511 BCD-to-7-segment latch decoder
to convert the inverted output of the priority encoder to a human-readable format.11 The CD4511
was chosen because of its latching feature, which enables the data lines of all three drivers to be
bused together while only updating one digit at a time. The digit switching is accomplished using
the three outputs of the ring oscillator described in Section 4.3. These outputs, however, transition
far too quickly (around 250 Hz) for the display to be readable while updating. To solve this, each
digit select signal is diode OR-ed with a master digit clock so the display updates much more slowly
(about 3 times per second).
For this design I used incandescent seven-segment displays instead of traditional LED displays.
This has the advantage of having a much wider viewing angle than LED displays and being more
aesthetically appealing. Additionally, it can operate regardless of polarity instead of being strictly
common-anode or common-cathode. The disadvantage of this is that the segments draw more
current individually (as much as 20 mA per segment), resulting in an average current draw of
around 300 mA. This, however, is not problematic as the system was designed to be run from an
AC wall transformer with high current output capability.

4.3 Timing and control logic

Reference: Appendix A, sheets 9 and 7 (“Timing and control logic,” sections 1 and 2)
The control logic provides a user interface for the meter. Two rotary switches are employed: one to
select the mode (voltage, current, resistance or capacitance) and another to select the range. The
mode selection switch controls the relays contained in each frontend module to determine which one
is active. Additionally, it drives an analog multiplexer that selects the active input to the backend.
The range selection switch drives the selection inputs of the CD4066 switches contained in every
frontend module.
This module also generates timing signals that are used throughout the design. Three D-type
flip-flops are used to implement a three-state ring (Overbeck) counter.12 The ring counter was
found to be extremely sensitive to interference, often interfering with itself through supply voltage
transients. To mitigate this, an error detection circuit was designed to reset the counter in the
event it returns an invalid output state. Diode logic was used to reset the circuit according to the
following expression (A, B and C are the three outputs of the ring counter):

(AB + BC + AC) + (ABC + ABC)

8
See http://www.ti.com/lit/ds/symlink/sn74ls07.pdf
9
See http://www.ti.com/lit/ds/symlink/sn54ls148.pdf
10
See https://www.intersil.com/content/dam/Intersil/documents/dg40/dg406-407.pdf
11
See http://www.ti.com/lit/ds/symlink/cd4511b.pdf
12
For diagrams and further information, see https://en.wikipedia.org/wiki/Ring counter

13
This handles the five failure modes of the counter. The first three modes occur when one additional
bit is injected into the counter, which results in two outputs being on at the same time. The latter
two occur when the outputs are either all high or low.

5 Performance
When the unit is fully assembled and runs uninterrupted, it operates quite reliably. By far the
least reliable element of the entire circuit is the ring oscillator. The ring oscillator operates in such
a manner that if any interference affects any of the three flip-flop inputs and causes it to change
states, the operation of the oscillator is permanently affected (until the next power cycle). To
mitigate this, the diode logic described in Section 4.3 was used to automatically reset the oscillator
in the event of an error. I believe much of the failures of this module are due to the breadboard
construction—if the circuit were implemented on a PCB with proper grounding and shorter path
lengths, the interference would likely be much less. Similarly, transients on the power rails became
problematic during prototyping, especially due to the 7-segment displays. Substantial amounts of
bypass capacitors partially resolved this problem, keeping supply transients to a maximum of 100
mV. Still, ground loops are an issue as always with breadboards, but this issue would also be fixed
if the design were implemented on a PCB.
By the nature of the ACU, the unit occasionally performs poorly when measuring voltages near
an integer (e.g. 1.01 V). This is due to the offset voltage of the magnitude comparator—it becomes
increasingly difficult to resolve which window a voltage is in (0–1 V or 1–2 V in this case) the nearer
the input voltage is to an integer value. To resolve this, comparators with lower offset voltages
could be used and the voltage references could be made more precise. This would narrow the range
of indeterminate input voltages, resulting in a more consistent measurement.
The measurement accuracy of the unit can be adjusted to be remarkably precise. The voltage,
current, and resistance modules were all able to be calibrated to within ±1 % across all ranges.
The capacitance module was more difficult, as it is more complex so there are more independent
variables that must all be adjusted to achieve a high accuracy. To further complicate things, the
measured capacitance of the DUT can vary slightly with the frequency at which the capacitor is
measured due to varying impedance. Still, the module maintains a ±5 % accuracy across all ranges.

6 Conclusion
Overall, the project was very successful. This project was particularly challenging due to its
complexity: each module has many nuances and difficulties of its own, and there are at least 10
such modules in the project. However, I believe the strength of this design is in its modularity: each
frontend and backend module is a separate circuit that can be debugged and tested individually.
Because of this, it was possible to build each module as a separate “subproject” and get it completely
working before integrating it into the final design.13 This also streamlined the integration process,
as all that needed to be done once all the modules was working was make connections to the control
circuit.
For a future revision, it would be interesting to implement the entire design on a PCB using
more precise components. This would have the effect of reducing overall size, as in its present form
the project occupies seven breadboards. Moreover, improved grounding would reduce the ground
loop effect, mitigate interference and provide for overall more accurate measurements.
13
Anecdotal note: While each module was functional, complete integration of all the modules was not reached
until April 30, the day before checkoffs

14
Appendix A Schematics
The following pages contain a complete schematic diagram of the project. The first sheet is a
top-level system diagram, showing each successive sheet of the schematic as a hierarchical block
and the connections between various blocks. The following pages are diagrams for the individual
modules. The design contains many potentiometers for user calibration, which I saw as a possible
source of confusion for the reader (it could be difficult to determine what they all do). For increased
readability, each potentiometer is accompanied by a description of what it adjusts (for example,
“Av = 10” means the potentiometer should be adjusted to yield a gain of 10 for the amplifier to
which it is connected).

15
 5 4 3 2 1

CTL1 CTL2 VOL REF

OUT_V
nR[4..1] nR[4..1] R[4..1] IN_N OUT VREF[10..1]
IN_P
nV nV EN_V
Voltage reference
nI nI EN_I
nR nR EN_R ACU1 DIS
D D
nC nC EN_C R[4..1]
OUT_V IN A A
OUT_I IN_V EN
B B
OUT_R IN_I
C C
OUT_C IN_R
Voltage D D
IN_C CLK
CUR
FLOOR
MODE0 MODE0
MODE1 MODE1 OUT OUT_I
IN_N OUT
VREF[10..1]
IN_P
Range selection
Modulus comparator

nR[4..1]
CLK
SEL[3..1]
nSEL[3..1] EN

VREF1
VREF7
ACU2 nSEL[3..1]
C C
Timing and control Current
IN OUT Display
RES
VTH
OUT_R
IN_N OUT
FLOOR
+15V +5V IN_P
P1
SEL[3..1]
4 VREF

16
3
2 R[4..1]
1 Multiplexing/storage
EN
-15V
PWR
Resistance
CAP
P2
B IN_N OUT_C B
2
1 IN_P IN_N OUT
IN_P

INPUT VREF

R[4..1]

EN

Capacitance

A A
All-analog Digital Multimeter (DMM)
Title
Top-level system diagram

Size Document Number Rev

A 016-SCH0008 A

Date: Monday, May 14, 2018 Sheet 1 of 11

5 4 3 2 1
 5 4 3 2 1

+15V
EN
+15V
U1
7 3
DSCHG OUT U2 R3
R1 R2

8
5 1 LM331 6.8k
CV GND 10k 10k
D 4 D
6 RST C2

VS
C1 2 THR 2N7000
TRG 7 5
100n Q1 C3 COMPIN RC
8
VCC 6
THRESH 10nF
LM555 2 1
330pF IREF IOUT

GND
FOUT
R4 R5 C4 R6
U3A 12k 68k 1uF 100k

4
3
R1 13 1
CTRL IN/OUT 6nF GAIN
2
14 OUT/IN R7
VDD 100k R8
1k
R9
CD4066B 1.0 V/kHz
C C

U3B 620k +15V

8

R2 12 11 R10
CTRL IN/OUT 60nF GAIN U4A
10
OUT/IN R11 3
14 +
VDD 10k 1
R13 30k
2 -
R12
CD4066B VREF
LM358
4

10k

17
62k
U3C 62k R15 R14
-15V
10k
R3 5 4 U5
CTRL IN/OUT 600nF GAIN +15V
3
OUT/IN R16 6 3
14 OUT VO +VIN
VDD 1k 2
-VIN U6
8

R17
CD4066B 5 U4B 1 7
REF 1 5 + 2 X1 W
B RG X2 B
8 +15V 7 3
U3D 6.2k RG Y1
6 - 4
R4 6 8 7 +15V 6 Y2
CTRL IN/OUT 6uF GAIN V+ LM358 Z
4

9 4
14 OUT/IN R18 V- 8
VDD 100 -15V 5 +VCC
INA114 -VCC
R19 -15V
CD4066B
R[4..1]
AD633
-15V
390 R20
EN
RL1 RL2
10k
4 4
IN_N IN_P
3 3
1 1
2 2
A A
D1 All-analog Digital Multimeter (DMM)
RELAY SPST RELAY SPST
1N914 Title
Four-range capacitance to voltage converter

Size Document Number Rev

A 016-SCH0008A A

Date: Monday, May 14, 2018 Sheet 2 of 11

5 4 3 2 1
 5 4 3 2 1

nR[4..1]
+5V
D +5V D
RL3
R21 RL4
4 1k 4 D2
IN_P
3 3 1N914
1 1
EN
2 2 nR1 nR1
1k
R22 RELAY SPST +5V
1N914 RELAY SPST
D3 R23 RL5
100 4 D4
3 1N914
1
2 nR2 nR2
100
R24 RELAY SPST +5V

R25 RL6
C C
10 4 D5
3 1N914
1
2 nR3 nR3
10
R26 RELAY SPST +5V

R27 RL7
1 4 D6

18
3 1N914
1
2 nR4 nR4
1
R28 RELAY SPST
RL8
4
IN_N
B 3 B
1
2
U7
3 6
RELAY SPST +VIN VO OUT
2
+15V -VIN
5
1 REF
8 RG
RG
R29 R30 R31 7
100 4 V+
Av = 20 V-
150 2.4k
INA114
-15V

A A
All-analog Digital Multimeter (DMM)
Title
Four-range selectable shunt/current to voltage converter

Size Document Number Rev

A 016-SCH0008D A

Date: Monday, May 14, 2018 Sheet 3 of 11

5 4 3 2 1
 5 4 3 2 1

D D

+5V
U8

nSEL[3..1] A 7 13 A1
1 A a 12 B1
B B b
C 2 11 C1
6 C c 10 D1
D D d 9 E1
D7 e
4 15 F1
nSEL1 5 BI f 14 G1
3 LE g
LT X1
1N914 A0208
R32 16
D8 10k VDD

4511
U9
C 1N914 C
7 13 A2
1 A a 12 B2
2 B b 11 C2
6 C c 10 D2
D d 9 E2
D9 e
4 15 F2
nSEL2 5 BI f 14 G2

COM
E1
D1
G1
F1
A1
B1
C1
E2
D2
G2
F2
A2
B2
C2
E3
D3
G3
F3
A3
B3
C3
DP

3 LE g
LT

1
2
3
4
5
6
7
8
9

19
1N914
10
11
12
13
14
15
16
17
18
19
20
21
22
23

R33 16
D10 10k VDD

4511
E1
D1
G1
F1
A1
B1
C1
E2
D2
G2
F2
A2
B2
C2
E3
D3
G3
F3
A3
B3
C3

U10
1N914
7 13 A3
1 A a 12 B3
2 B b 11 C3
B C c B
6 10 D3
D d 9 E3
D11 e
4 15 F3
nSEL3 5 BI f 14 G3
3 LE g
LT
1N914
R34 16
D12 10k VDD

CLK 4511

1N914

A A
All-analog Digital Multimeter (DMM)
Title
Three-digit seven-segment display controller

Size Document Number Rev

A 016-SCH0008F A

Date: Monday, May 14, 2018 Sheet 4 of 11

5 4 3 2 1
 5 4 3 2 1

VREF[10..1]
U11
+15V +15V
CMP1 11 9

3
3
U12A U12B CMP2 12 D1 Q0 7
VREF1 7 + VREF6 5 CMP3 13 D2 Q1 6
+ D3 Q2
1 CMP1 2 CMP6 CMP4 1 14
6 - 4 CMP5 2 D4 Q3
D - D5 D
CMP6 3 +5V
LM339 LM339 CMP7 4 D6

12
12
CMP8 5 D7 16
-15V -15V CMP9 10 D8 VCC 8
D9 GND
+15V +15V
74LS147

3
3
U12C U12D
VREF2 9 + VREF7 11 +
14 CMP2 13 CMP7
8 - 10 -

LM339 LM339

12
12
-15V -15V
+15V +15V Q2 Q3 Q4 Q5
2N7000 2N7000 2N7000 2N7000

3
3
C U13A U13B C
VREF3 7 VREF8 5
+ +
1 CMP3 2 CMP8
6 - 4 -
LM339 LM339 +5V

12
12
-15V -15V +15V
14

U14A U15
+15V +15V
1 2 17 19

20
A15
B15 16 A0 S1 20 VREF1

3
8
U13C U16A A1 S2
C15 15 21 VREF2
VREF4 VREF9 3 74LS07 A2 S3
7

D15 14 22 VREF3
9 + +
14 CMP4 1 CMP9 A3 S4 23 VREF4
2 S5
18 24 VREF5
8 - - U14B
EN S6 25 VREF6

4
3 4

12
LM339 LM393 S7
1 26 VREF7
27 V+ S8 11 VREF8
B -15V -15V V- S9 B
74LS07 10 VREF9
+15V +15V S10 9 VREF10
U14C S11
-15V 8

3
8
U13D U16B 5 6 S12 7
VREF5 11 + VREF10 5 S13 6
+ S14
13 CMP5 7 CMP10 5
74LS07 S15
10 - 6 - 4
4 U14D S16
28

12
LM339 LM393
9 8 D
-15V -15V
DG406
IN 74LS07

CMP[10..1]
A B CD FLOOR

+5V R35 R36 +5V +15V

A A
6 CMP1 CMP6 6 R37 All-analog Digital Multimeter (DMM)
5 CMP2 CMP7 5 A15 5
Title
4 CMP3 CMP8 4 B15 4
Analog modulus comparator, section 1
3 CMP4 CMP9 3 C15 3
1 2 CMP5 CMP10 2 1 D15 2 1
Size Document Number Rev
A 016-SCH0008G A
10k 10k 10k
Date: Monday, May 14, 2018 Sheet 5 of 11
5 4 3 2 1
 5 4 3 2 1

SEL[3..1] +15V +15V +5V +15V

OUT1

U18
+15V R38 D13 R39 R40 R41
10k 1N914 30k 10k 10k 2 7
8 +IN OUT
D D
C5 -IN
1 C6
+5V R42 R43 R44 10 LOGIC+ 4.7n
10k 10k 10k LOGIC-
100n 6

14
U17A CH
Q6 Q7 Q8 3
SEL1 1 2 2N7000 2N7000 2N7000 4 NULL
NULL
R45 9
74LS07 +VS

7
10k 5
NULL -15V -VS
+15V +15V +5V
U17B AD582
SEL2 3 4

MOD
OUT2
74LS07
R46 D14 R47 R48 R49
C C
U17C 10k 1N914 30k 10k 10k U19
SEL3 5 6 C7 2 7
8 +IN OUT
-IN
74LS07
1 C8
SEL3 LOGIC+ 4.7n
100n 10
SEL2 LOGIC-
Q9 Q10 Q11
6
2N7000 2N7000 2N7000 CH
3

21
4 NULL
NULL

SEL1
U21A R50 9
10k 5 +VS
+15V 13 1 -VS
CTRL IN/OUT NULL -15V
2
14 OUT/IN AD582
VDD U21B U21C
B +15V 12 11 +15V 5 4 B
CD4066B CTRL IN/OUT CTRL IN/OUT
10 3 OUT

IN_BUF
14 OUT/IN 14 OUT/IN -15V
VDD VDD U22
CD4066B CD4066B 3 6 MOD
+5V +VIN VO

OUT1
OUT2

R51 5.1k FLOOR 2

-VIN
+15V
+15V 5
D15 REF
RL9 R52 1
1N914 RG
U24 100 8
4 RG

8
5
Av = 10
U23 3 3 6 IN_BUF
+VIN VO R53 470 7
IN 1 2 V+
4
2 +
7 2 +15V R54 -VIN
V-
VTH 3 - 1M 5
1 REF INA114
LM311 RELAY SPST RG -15V
R55 +15V 8

4
1
6
1.2k RG
A D16 A
7 All-analog Digital Multimeter (DMM)
4 V+
V- Title
-15V
Analog modulus comparator, section 2
LED INA114
-15V
Q12 Size Document Number Rev
2N7000 A 016-SCH0008H A

Date: Monday, May 14, 2018 Sheet 6 of 11

5 4 3 2 1
 5 4 3 2 1

+15V +15V

1
1
R56 R57
10k 10k
D D

+5V

7
6
5
4
3
2
5
4
3
2

14
U25A U26

MODE0 1 2 11 3 OUT
10 A X
9 B 13
74LS07 C X0 IN_V

7
14 EN_V
X1 IN_I
+15V 6 15 IN_R
EN X2 12
U25B X3 IN_C Q13
16 1
3 4 7 VDD X4 5 2N7000
MODE1 VEE X5 2 nV
X6 4
nR[4..1] 74LS07 X7
U25C
4051
C EN_I C
nR1 5 6

74LS07 Q14
U25D 2N7000
nI
nR2 9 8

74LS07

22
U25E EN_R
nR3 11 10
Q17
74LS07 2N7000
Q15 Q16

R2
R1
nR
U25F 2N7000 2N7000
nR4 13 12
B R[4..1] B

74LS07 EN_C

Q18

R4
R3

R58
2N7000
nC
100k
R59 D17
10k 1N914
+15V
U27 Q19 Q20
7 3 2N7000 2N7000
DSCHG OUT CLK
5
4 CV
6 RST
A THR R60 +15V A
C9 C10 2 All-analog Digital Multimeter (DMM)
TRG R1 5
1uF 100nF
R2 4 Title
8
VCC R3 3 Timing and control logic, section 2
R4 2 1
LM555 Size Document Number Rev
10k A 016-SCH0008K A

Date: Monday, May 14, 2018 Sheet 7 of 11

5 4 3 2 1
 5 4 3 2 1

+15V
10k

8
R61 U28A
VREF 3 +
1
2 -
D D
LM358

4
R62
10k
-15V
R63

10k
+15V

8
RL10
U28B
R64 + 5 4
7 3
IN_P
- 6 1
EN
10k 2
LM358

4
RELAY SPST
-15V
C D18 RL11 C
1N914
4
+15V
3
IN_N
1
U20A 2
R1 13 1
CTRL IN/OUT 6M GAIN
2 RELAY SPST
OUT/IN R65 U29
14
VDD 100k 3 6

23
+VIN VO OUT
R66 2
CD4066B -VIN
5
U20B 1M 1 REF
+15V 8 RG
R2 12 11 RG
CTRL IN/OUT 600k GAIN
10
OUT/IN R67 7
14 V+
VDD 10k 4
B V- B
R68
CD4066B
INA114
-15V
U20C 100k
R3 5 4
CTRL IN/OUT 60k GAIN
3
14 OUT/IN R69
VDD 1k
R70
CD4066B

U20D 9.1k
R4 6 8
CTRL IN/OUT 6k GAIN
9
14 OUT/IN R71
VDD 100
A A
R72 All-analog Digital Multimeter (DMM)
CD4066B
R[4..1]
Title
Four-range precision current source/resistance to voltage converter
910
Size Document Number Rev
A 016-SCH0008B A

Date: Monday, May 14, 2018 Sheet 8 of 11

5 4 3 2 1
 5 4 3 2 1

D19
+5V +5V +5V +5V
ERROR

1N914
R77 D20
R74 R75 R76
U31 D21 10k 1N914
R73 10k 10k 10k
3 7 10k +5V
OUT DSCHG SAMP
D D
5 FREQ
CV 1N914
4 R78
RST 6 D25 10k
THR 2
TRG
8 D22 D23 D24 D26 D27 D28
VCC 1N914
1N914 1N914 1N914 1N914 1N914 1N914
LM555 D29
Q21
2N7000

1N914
R79
D30 10k
U32A U32B U34A

SEL1
SEL2
SEL3

nSEL1
nSEL2
nSEL3
2 5 12 9 2 5
C D Q D Q D Q C
6 8 6 1N914
+5V 3 Q 11 Q 3 Q
CLK CLK CLK D31
+5V +5V +5V
1 13 1
4 CLR 14 10 CLR 14 4 CLR 14
PRE VCC PRE VCC PRE VCC
1N914
74LS74 74LS74 74LS74
R80 R81
4.7k 4.7k

24
+5V +5V
SW1
+5V +5V 1 3
16

C U33A
R82 2 8 4
C 4 5 2 4
R83 A Y0 nV
SW2 2 6 3 5
VCC

1 B Y1 nI
330 RESET 6 nR
R84 R85 1 Y2 7
10k SW DIP-BCD G Y3 nC
10k 10k C11
B B
1uF
MODE1
MODE0

SW3 74LS139
Q22 nR[4..1]
R86 2N7000 1 3
C U33B

ERROR
Q23 Q25 2 8 4
2N7000 2N7000 C 4 5 14 12 nR1
Q24 A Y0
1.2k 2 6 13 11 nR2
2N7000 D32 1 B Y1
R87 10 nR3
LED Y2
100k 15 9 nR4
SW DIP-BCD G Y3
R88 R89
4.7k 4.7k 74LS139

+5V +5V SEL[3..1]

SEL1
SEL2
SEL3
A D33 D34 D35 D36 D37 D38 D39 D40 A
LED LED LED LED LED LED LED LED All-analog Digital Multimeter (DMM)
nSEL[3..1] Title
Timing and control logic, section 1
nSEL1
Size Document Number Rev
nSEL2

nR1
nR2
nR3
nR4
nV
nI
nR
nC

A 016-SCH0008J A
nSEL3
Date: Monday, May 14, 2018 Sheet 9 of 11
5 4 3 2 1
 5 4 3 2 1

RL12
4
IN_P
3
1 R[4..1]
D EN D
2
R90
9M
1N914 RELAY SPST
+15V
D41 U30A
1 13 R1
2 IN/OUT CTRL
OUT/IN 14
R91 VDD
900k CD4066B

U30B
11 12 R2
10 IN/OUT CTRL
OUT/IN 14
R92 VDD
90k CD4066B
C C
U30C
4 5 R3
3 IN/OUT CTRL
OUT/IN 14
R93 VDD
9k CD4066B
U30D
8 6

25
R4
9 IN/OUT CTRL
OUT/IN 14
R94 VDD
1k CD4066B
RL13
4
IN_N
3
U35
1
B B
2 3 6
+VIN VO OUT
2
CADDOCK -VIN
1776-C68 +15V
RELAY SPST
5
1 REF
8 RG
RG
R96 7
R95 V+
4
100 V-
Av = 100
470
INA114
-15V

A A
All-analog Digital Multimeter (DMM)
Title
Four-range precision voltage divider/attenuator

Size Document Number Rev

A 016-SCH0008C A

Date: Monday, May 14, 2018 Sheet 10 of 11

5 4 3 2 1
 5 4 3 2 1

U36
+15V
AD581/TO
1 2
+VS VOUT
+15V +15V
VRES[10..1]

GND
R97

4
4
D D
U37A U37B
10k

3
VRES1 3 + VRES6 5 +
1 VREF1 7 VREF6
2 6 VRES10 VRES5
- -
LM324 LM324

11
11
R100 R101
R98 R99
-15V -15V 10k 10k
1k 12
REF TRIM
+15V +15V R103 R104
100 100

4
4
U37C U37D
VRES2 VRES7
VRES9 VRES4
10 + 12 +
R102
8 VREF2 14 VREF7
4.3k
9 - 13 -
R105 R106
LM324 LM324 10k 10k

11
11
C C
R107 R108
-15V -15V
-15V 100 100
+15V +15V
VRES8 VRES3

4
4
U38A U38B
VRES3 3 VRES8 5 R109 R110
+ +
1 VREF3 7 VREF8 10k 10k
2 - 6 -

26
R111 R112
LM324 LM324

11
11
100 100

-15V -15V
VRES7 VRES2
+15V +15V
R113 R114

4
8
10k 10k
U38C U39A
VRES4 10 + VRES9 3 +
B R115 R116 B
8 VREF4 1 VREF9
100 100
9 - 2 -
LM324 LM358

4
VRES6 VRES1

11
-15V -15V R117 R118
10k 10k
+15V +15V
R119 R120

4
8
U38D U39B 100 100
VRES5 12 + VRES10 5 +
14 VREF5 7 VREF10
13 - 6 -
VREF[10..1]
LM324 LM358

11
-15V -15V
A A
All-analog Digital Multimeter (DMM)
VRES[10..1]
Title
Precision 1-10V integer voltage reference

Size Document Number Rev

A 016-SCH0008E A

Date: Monday, May 14, 2018 Sheet 11 of 11

5 4 3 2 1
Appendix B Pictures
The following are photos of the project, taken at various stages of development.

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