International Conference on Recent Advancements in Electrical, Electronics and Control Engineering (IConRAEeCE’18) - 4th & 5th May, 2018

Department of EEE, Mepco Schlenk Engineering College (Autonomous), Sivakasi

Design and Analysis of Interleaved SEPIC converter

B.Karthikeyan O.R.Saiayyappa Dr.S.T.Jaya Christa Dr.J.Gnanavadivel
PG scholar, PG scholar Associate Professor Associate Professor
Dept. of EEE, Dept. of EEE Dept. of EEE Dept. of EEE,
Mepco Schlenk Mepco Schlenk Mepco Schlenk Mepco Schlenk
Engineering College, Engineering College, Engineering College, Engineering College,
(Autonomous) (Autonomous) (Autonomous) (Autonomous)
Sivakasi-626 005. Sivakasi-626 005. Sivakasi-626 005. Sivakasi-626 005.
[email protected] [email protected] [email protected] [email protected]
Abstract—This paper presents the design and analysis of efficiency and also system goes to unstable state. The
High gain Interleaved Single Ended Primary Inductor high step-up converter efficiency is improved by using
Converter (SEPIC) for renewable energy applications. coupled inductor [4-5], which generates high voltage
Simulations are carried out using MATLAB Simulink. gain, by adjusting the turns ratio of coupled inductor
Interleaved SEPIC converter operates under both similar to isolated converters. However, the main
continuous and discontinuous modes of operations.
switch is affected by voltage stress and high voltage
Interleaved SEPIC’s output voltage is greater than or less
than or equal to its input voltage. By using interleaved spike due to the leakage inductance of coupled
method, the converter’s switching stress is reduced and inductor. Due to this leakage, the overall conversion
efficiency is also increased. To maintain a constant output efficiency gets reduced. In literature, to overcome the
voltage instead of changing voltage, closed loop control is above demerits, active and passive clamping strategies
required. This converter has low switch voltage and high have been adopted [6]with coupled inductor, which
efficiency. It is used for low input voltage and high-power also increases the cost and size of converters. Some
applications. This paper gives design and analysis of high step-up converters are developed by combining
Interleaved SEPIC converter for an Input voltage of 24V, two converters so as to achieve the high voltage gain,
output voltage of 48V with output power of 100W.
namely: classical boost converter combines with single
Keywords: DC-DC converter, High gain Interleaved ended primary inductor converter (SEPIC)[7,8]and
SEPIC. boost with cuk [9]. These converters have the
switching voltage equal to the average sum of input
I. INTRODUCTION and output voltage. The integrated fly back with boost
converter is proposed in [10-11] where the coupled
Due to proliferation in electricity power demand and inductor is considered as a fly back converter. The
also increase in renewable energy sources, renewable dissipated energy from the leakage inductor is
energy sources are mostly used in the electric power recycled by the load, and it limits the main switching
generation to meet out the demand. The renewable voltage stress. Interleaved boost converter is used to
energy sources are used in residential appliances and reduce the input ripple current and it doubles the
grid connected systems. The renewable energy sources transferable power [12-13]. But the controlling of
are low voltages. In order to increase the voltage or switches becomes complex and exhibits low
high-power applications it is necessary to boost up the conversion efficiency for high voltage applications. To
voltage by using power converters. In this converter overcome the above drawbacks, this paper proposes a
act as a voltage-double circuit in terms of renewable non-isolated high step up converter to generate high
sources. The converters are classified into two types voltage gain using interleaved converter. The proposed
namely, isolated and non-isolated converters. The converter topology utilizes a interleaving in the SEPIC
isolated step up converters have a transformer and by converter. The advantages of this converter are high
varying the turns ratio of the transformer, high voltage voltage conversion, low conduction loss, low voltage
gain can be achieved. Some of those converters are fly stress across the semiconductor devices, fewer
back, push-pull, and forward type convert etc. [1-2]. components and is easy to control. Interleaved SEPIC
The fly back converter has a drawback of high voltage converter operates on both CCM and DCM modes of
stress due to transformer leakage inductances which operations.
reduce the efficiency [3]. Among non-isolated
converter family, the classical boost converter
generates the high step-up voltage gain by using large
duty cycle. This may cause the high switching voltage
stress with reverse recovery issues and reduce the high
step up conversion
International Conference on Recent Advancements in Electrical, Electronics and Control Engineering (IConRAEeCE’18) - 4th & 5th May, 2018
Department of EEE, Mepco Schlenk Engineering College (Autonomous), Sivakasi

Imax2 and L2 is energized to level Imax2 during this

period.

Fig.1 Non-isolated DC-DC converter

Fig.3. Mode-2of operation.
II. CIRCUIT CONFIGURATION
Mode-3:S1 ON and S2 OFF
The circuit diagram of the non-isolated DC-DC
converter is shown in Fig.1. The circuit consists of Inductor L4 de-energizes to Imin2 and C2 gets
switch S1 and S2, inductors L1,L2,L3, and L4, Capacitor charged. The inductor L2 supplies the output capacitor
C1,C2& diodes D1,D2. Compare with the conventional C0 and the load through diode D1. The inductor L1 is
SEPIC converter, instead of using single switch, two energized to Imax1. Inductor L3 energizes to level
switches are used in this converter. It may lead to Imax2 and L2 is de-energized to level Imin2 during
improve the high voltage gain and also the efficiency this period.
and reduces the switching stress. The capacitor C2 is
energized same as to the conventional boost converter.

A. Operating Principle:
The Continuous Conduction Mode (CCM) of the
non-isolated Dc-DC converter is working on four
modes of operation is shown in fig 2,3,4 and 5.
Mode1: Both S1 and S2 are ON
Inductor L1 remains in Imin1 level, L2 remains in
Imax1 and L3 remains in Imin2, L4 remains in
Imax2 during this period. Capacitor C2 and C3
supply L2 and L4 respectively. Output Capacitor Fig.4. Mode-3of operation.
discharges and supplies the load Current to the load
is continuous. Mode-4:Both S1 and S2 OFF

L1 de-energizes and C1 gets charged. L2 supplies

output capacitor and the load through diode D2.
Similarly, L3 de-energizes and C2 gets charged. L4
supplies the output capacitor and the load through D1.

Fig.2. Mode-1 of operation.

Mode2: S1 OFF and S2 ON

Inductor L1 de-energizes to Imin1 and C1 gets Fig.5. Mode-4of operation.

charged. The inductor L4 supplies the output capacitor
C0 and the load through diode D2. The inductor L2 is The main theoretical waveforms for the proposed
energized to Imax1. Inductor L3 energizes to level converter topology under CCM are shown in fig.6.
International Conference on Recent Advancements in Electrical, Electronics and Control Engineering (IConRAEeCE’18) - 4th & 5th May, 2018
Department of EEE, Mepco Schlenk Engineering College (Autonomous), Sivakasi

IV.SIMULATION OF INTERLEAVED SEPIC

CONVERTER

fig.7. shows the Simulink diagram of the

Interleaved SEPIC converter that is supplied by
DC source of 24V and it produces the output of
230V with L and C values as in TABLE I

Fig.6. Theoretical waveforms for CCM Fig.7. Simulation diagram for open loop
. operation of Interleaved SEPIC converter
III. DESIGN OF INTERLEAVED SEPIC
CONVERTER
The Interleaved SEPIC converter operates in
Continuous Conduction Mode at a rating of the
100W and is designed by the following
specifications. The output Voltage (Vout) of the
converter is 48V and theinput voltage (Vin) is 24V.
switching frequency of the converter is 20 kHz and
duty cycle is 66%.
Design of the Interleaved SEPIC is done by the
following equations are mentioned here. Fig.8. Open loop response of Interleaved
The voltage relationship is given by SEPIC converter

Vo = Vin (D)/(1-D)(1) The Output voltage response of the converter is shown

in Fig.8. From the output voltage waveform, it is
where D = Duty cycle inferred that, the desired output voltage is not
achieved, hence a closed loop controller is needed.
V0 = Output Voltage fig.9. shows the closed loop Simulink diagram of the
Interleaved SEPIC converter that is supplied by DC
Vin = Input Voltage
source of 24V and it produces an output of 48V.
The following Table I represents the design
parameters of the Interleaved SEPIC converter

TABLE I Design Specifications of Interleaved

SEPIC converter

PARAMETERS VALUES
Input voltage 24V
Fig.9. Simulation diagram of closed loop
Output Voltage 48 V operation of Interleaved SEPIC converter.
Switching Frequency 20 kHZ
Duty Cycle (α) 66%
Inductance(L) L1& L2 162µH & 142.85µH
Capacitance (C) C1,C2&C0 2.75µF & 0.468 mF
Resistor 23.04Ω
International Conference on Recent Advancements in Electrical, Electronics and Control Engineering (IConRAEeCE’18) - 4th & 5th May, 2018
Department of EEE, Mepco Schlenk Engineering College (Autonomous), Sivakasi

TABLE II VARIATION IN SUPPLY VOLTAGE

S. NO Vs(V) Is(A) Vo(V) Io(A) Ƞ

1 20 3.613 39.20 1.702 92.33
2 24 4.350 47.20 2.049 92.64
3 48 8.770 95.19 4.132 93.44
TABLE II shows the open loop variation in supply
voltage.

TABLE III VARIATION IN DUTY CYCLE

S.
Vs(V) Is(A) D Vo(V) Io(A) Ƞ
NO
Fig.10. Closed loop response of Interleaved 1 24 0.021 0.1 1.864 0.081 29.924
SEPIC converter 2 24 0.081 0.2 5.191 0.225 60.161
3 24 0.217 0.3 9.466 0.411 74.667
From the closed loop output voltage waveform, it is
4 24 0.503 0.4 15.160 0.658 82.603
inferred that, there is zero peak overshoot and settling
time is also less and the desired output voltage is 5 24 1.098 0.5 23.090 1.002 87.797
obtained. From the closed loop current waveform, it 6 24 5.702 0.6 54.160 2.351 93.045
is inferred that, similar to the output voltage 7 24 16.140 0.7 90.880 3.944 92.532
waveform because of resistive load. TABLE III shows the variation in Duty cycle. It is
inferred that, when the Duty cycle of the converter is
V. ANALYSIS OF Interleaved SEPIC varied its output voltage also changes correspondingly.
CONVERTER
In order to scrutinize the effectiveness of the TABLE IV VARIATION IN LOAD RESISTANCE
Interleaved SEPIC converter the simulation analysis
is given below. %LOAD VO
S.NO VS(V) IS(A) IO(A) Ƞ
(Ω) (V)
1 24 0.620 100% 229 0.208 67.18
2 24 1.045 90% 230.7 0.417 79.71
3 24 1.471 80% 233.2 0.625 84.92
4 24 1.898 70% 235.8 0.833 87.73
5 24 2.325 50% 241.6 1.041 89.55
6 24 2.754 40% 244.4 1.248 90.63
7 24 3.185 30% 247.2 1.457 91.49
Fig.11. Inductor Current response of 8 24 3.163 20% 251.4 1.458 92.19
interleaved SEPIC converter 9 24 4.046 10% 308 1.870 92.44
From fig.11.which shows inductor current waveform, it From TABLE IV it is inferred that, when the load
is inferred that, inductor current is above zero and there resistances is varied, the output voltages are reduced.
is no zero crossing in the inductor current waveform Because it resists the flow of current and increases
this converter operates under CCM. the load resistance and Efficiency is also reduced.

TABLE V CLOSED LOOP RESULTS VARIATION

IN SUPPLY VOLTAGE

S.NO VS(V) IS(A) VO(V) IO(A) Ƞ

1 16 6.701 48 2.076 92.94
2 20 5.371 48 2.081 92.99
3 24 4.478 48 2.079 92.85
4 28 3.852 48 2.079 92.52
Fig.12. capacitor voltage response of Interleaved 5 32 3.399 48 2.082 91.88
SEPIC converter TABLE V shows the closed loop analysis of variation
From fig.12, it is inferred that, the sum of the capacitors in supply voltage. Here the input voltage is changed
C1 and C2 voltage is equal to the output voltage of the and constant output voltage is obtained, efficiency is
converter. also increased.
International Conference on Recent Advancements in Electrical, Electronics and Control Engineering (IConRAEeCE’18) - 4th & 5th May, 2018
Department of EEE, Mepco Schlenk Engineering College (Autonomous), Sivakasi

TABLE VI VARIATION IN LOAD inductors for photovoltaic systems. IETPower Electron

2015;8(10):1885–92.
RESISTANCE [5] Gnanavadivel, J., R. Santhiya, and N. Senthil Kumar.
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