DFU Explain
DFU Explain
By DeeGee
To some, this mode is a god send but to others it’s just a pain so let’s
get our heads around DFU and what role it plays in our repairs....
I am providing the information to allow you to understand these circuits and once understood you can then work
out for yourself where the faults are....
Let’s Go......
DFU Mode is a mode in which a device’s Boot ROM code waits to be recovered over USB.
First off we need to know some more about what the DFU mode is so let’s gets the boring out of the way first.
The reason we need this information is this will allow us to determine software or hardware or both...
NORMAL = Once the device is powered on it boots normally into the iOS using the Apple Secure Boot chain
sequence.
This secure boot chain and all apps are checked for Apple signatures to verify its integrity.
The SECURE BOOT ROM is normally the first part to be loaded/executed in normal mode.
Sequence:
1) The Secure BootRom contains Apples CA root public key which is used to verify the signature prior to the next
stage being loaded.
3) The Secure BootRom then verifies the LLB (low level bootloader) signature and if verified then loads the next
stager.
4) The LLB then runs its code and carries out its duties before verifying the next stage for loading this will be the
SSBL / iBoot
5) SSBL /iBoot will then verifies its section and then loads the iOS kernel.
The Secure Boot Chain is there to ensure that the iOS only runs or boots from signed Apple Media / storage /
devices
When the iOS is in this NORMAL state it’s possible to recover ALL data that would be available to the user.
So this means that if any part of the sequence fails or fails to validate then the secure boot chain of events halts and
stops, this in turn then let’s the AP know to send a notification image on to the screen, this image is the recovery
screen.
This restore mode has issues of its own by way of a restore boot loop that can arise from Jailbreaking or data
The only repair in this state is eNAND backup-restore only. Of underlying data.
So we have covered NORMAL mode and RESTORE mode, now for DFU mode....
During the Secure Boot Chain sequence if the Secure Boot ROM cannot be verified or accessed due to corruption
then the AP defaults the device to DFU Mode (Development Firmware Upgrade/Update).
This is a low level diagnostics mode for performing Firmware upgrades to the iOS and the bootloader sections if
corrupt.
Basically the DFU mode allows for the download and transfer/repair to the device over USB of Firmware files and
ROM files for the SECURE BOOT sequence.
2) Once verified then the iBSS and iBSEC are both loaded
iBSS is a custom version of iBoot which verifies the iBSEC loader for loading
3) Once these are loaded the iBSEC then verifies and loads the kernel.
4) The kernel then verifies once more and loads the RAMDISK into memory.
Using this mode an investigator prior to iPhone 4s could side load any usb media and run its own live cd /
bootloader and access the Devices storage just like an usb drive. That why there is a secure signed boot chain.
1) Device
2) BootRom
----------------> Failure = DFU
3) LLB
----------------> Failure = RESTORE
4) iBoot
----------------> Failure = RESTORE
5) Kernel (iOS)
Please also note that the Baseband Modem has its own secure boot chain provided by either Qualcomm / Intel
TSMC and therefore has its own BOOTLOADERS.
So thus far we know that DFU mode kicks in if we have a corrupt secure boot chain process or a corrupt IPSW/iOS
system files but wait there’s more....
Let’s take a look at some failures on different devices and see how they compare if at all and what lines failing cause
a default DFU Mode instance.
There are 3 main areas where these components or circuits attached to them cause DFU MODE:
1) AP/CPU/RAM
2) NAND
3) I2C
This may be by a short to ground, dropped pads, open circuit, low/high pull ups (unwanted), and supply failure
(PMIC) or just a faulty component.
This is a hardware based test, the software boot sequence faults can be deduced by the device behavior and errors.
The checks to follow will cover most if not all of the above three.
Prelim: Known good Dock, Battery and so on trying to reduce our fault variables.
1) Check your DFU logs in iTunes or 3Utools for any information relating to the DFU mode instance.
*U0700
*U1801
*U4001
*U2101
*U2301
VOLTAGE TEST
LINE (v) OHMS DIODE POINT
PMU_TO_AP_BUF_POWER_KEY_L / / / /
PMU_TO_AP_BUF_VOL_DOWN_L / / / /
Please be aware that ANY other line attached can cause the fault on PMIC side including under the PMIC
What can happen to the above three voltages to create an instance of DFU mode kicking in?
1) Any Short circuit to ground of the 3V0_NAND supply will default to DFU
2) Bridging of the 3v supply to 1.8V supply will cause the 1V8 to be pulled high to 3V and the i2C bus cannot
pull low enough to operate and can default to DFU Mode.
3) Missing 1V8, a whole host of issues there as VDD Main will not be produced for starters.
4) There are also eNand detection resistors failing that will cause NO DETECT of eNAND and default to DFU mode.
Then there is also the Touch circuit of 1.8V that can also pull down the i2C bus resulting in 50mA DFU mode.
There are BUCK lines that can pulled too low to allow the inductor to boost it correctly and in that case the inductor
needs testing on BOTH sides to find out where the fault lies.
1V8 SDRAM pulled low we need to remove the inductor and test both pads to check if it’s a PMIC failure.
If it’s ok then you can provide a proper 1V8 tap-off from another source.
VDD_BOOST issues can be checked by testing U2301 for poor connection, shorts etc.
*C1915
*C1912
If VDD BOOST is abnormal then the BUCK line outputs will be affected. These are calculated for induction in design.
LD01
LD03-17
LDO5
LDO6
LD07-8
LDO11-13
U2301:
So VDD VDD_BOOST boosts the VDD MAIN voltage if its low at say 2.7v then the inductor will boost to 3.4v to
power system.
DP1 LINES:
Test inductors: For short or open circuit, these can become shorted from an attached line that IS short to ground.
3) TIGRIS_TO_PMU_INT_R_L = @R2103
5) TRISTAR_TO_PMU_HOST_RESET
TEST:
2) FL0700
3) PMIC_TO_PMU_HOST _RESET
If any of these fail there will be voltage jump/fluctuations and the failure of "TRISTAR_TO_PMU_HOST_RESET" can
result In the PMIC not being able to complete a reset and turns ON/OFF repeatedly.
Turn on the PWRON Button "BUTTON_PWR_KEY_L" circuit and check for VDD Main voltage at inductor L4001
U4001 TESTS:
2) At this stage U4001 opens the 5V signal on to L4001 via PP5V0_USB_RVP line.
3) U4001 internally generates its own 3V LDO output from the TRISTAR BYPASS line.
5) Once authentication has been established U4001 then sends a low level signal to U2101 controller to open the 5V
line to always boot.
24M
Y0700 - C0702-C0703 IN/OUT
R0701 - XTAL_AP_24M_IN
R0702 - XTAL_AP_24M_OUT
There are also the DFU request shortcut command sequence lines to check:
PMU_TO_AP_BUF_POWER_KEY_L
PMU_TO_AP_BUF_VOL_DOWN_L
If the above is faulty in any way then you will not be able to put the device manually into DFU mode as these lines
are responsible for the power/home combo for DFU.
/* Check for Force DFU Mode request pins. Requesting DFU mode is done
by asserting both REQUEST_DFU1 and REQUEST_DFU2, holding them for
the required time, then deasserting REQUEST_DFU1, followed by
deasserting REQUEST_DFU2 after another required hold time.
So in this example we have a 6SP stuck in DFU mode and stuck at 50mA after PWRON / Trigger
From what we saw in the previous i7 series example let’s take a look at this device against
our schedule of tests.
1) CPU
2) NAND
3) I2C
CPU:
L2000
L2001
L2002
L2003
L2010
L2011
L2012
L2013
L2020
L2021
iPhone DFU MODE TROUBLESHOOTING : By DeeGee – copyright 2018
PP1V8_SDRAM = 1.8V [PASS] C2032
L2030
L2040
L2041
L2050
FL3220 = 1.8V
C3220 = 1.8V
NAND CHECKS:
NAND DETECTION:
30mA/50mA/240mA/1A/800mA [PASS]
Connect to iTunes or 3uTools to test mode of operation. Phone is now in normal mode.
The fault was an I2C Line resistor putting the device into DFU MODE.
Example 2:
This 6s came in stuck in DFU mode and always gives the error "unknown error 14"
We check the power supplies and they are all good but still no joy.
Let’s look at the NAND schematic and see what we have to work with.....
As there are tons of circuit lines to check the best way is to remove the eNAND and test each pad for resistance.
After testing we find that the pad M6 is open OL which is not right for that line. This line detects the NAND is
present and if faulty will default the device to DFU Mode.
This line is pulled low to ground and the resistor is faulty and replaced.
The restore process can now be carried out in restore mode and no errors....
Example 3:
Here we have another 6s but this device is stuck in DFU but pulling PWRON / Trigger current of 100mA and stays
there but no boot.
Plug the lightning cable into PC to check usb comms and we are in DFU mode according to 3uTools.
1) AP/CPU [PASS]
2) eNAND [FAIL]
Well we know the CPU is ok as it carries out the partial restore and gives us an error.
* 3V0_NAND = 2.99v
* 0V9_NAND = 0.845V
* PP1V8 = 1.79V
Again we remove the eNAND and test the pads all the resistances are normal and within range, so this is a physical
eNAND failure.
We need to see if we can read the underlying data and we can but the eNAND is only readable so we copy this data
before writing to the new chip.
That was our error while the restore was trying to write to the eNAND it couldn’t due to this fault.
We write our new data to our replacement eNAND with our default codes which seem to increase over iOS updates.
From 3 to 5 including battery and cameras.
This corruption of underlying data can also cause camera issues being reversed and a whole host of other issues,
battery errors and so on so this underlying data integrity is very important.
eNANDs can take up to 400c for nearly 10 minutes before any data is at risk so these chips are quite strong
protecting the data and most of the time its data corruption from bad .ipsw or USB comms from poor cables during
restore causing corruption of the data transfer.
Example 4:
Here we have a 6 Plus with black screen won’t turn on and consuming 60mA after PWRON / Trigger.
Test Schedule:
1) AP/CPU [PASS]
2) eNAND [PASS]
We measure the supplies for the AP and eNAND and all are present and within range.
Now do we remove the eNAND well not quite yet as the current is telling us that the eNAND is not active yet so let’s
move on to the I2C lines?
We test the I2C lines one by one from I2C0 first and methodically move our way on to the next BUS circuit until we
have confirmed all is normal on I2C.
The resistor R0303 is to blame as we have 1.8v in and 0.7v out to the BUS circuit and it should read 1.8v also unless
the bus is already pulled down in which case 0.7v is still too high for pull down.
Before we finish we can’t forget the FORCED DFU for us Board Repairers.
By providing 1.8V to the DFU Test Point we can FORCE the device into DFU mode.
Regards Dee