MC9S08EN32

MC9S08EN16
Data Sheet: Advance Information

HCS08
Microcontrollers

MC9S08EN32
Rev. 2
9/2007

freescale.com
MC9S08EN32 Series Features
8-Bit HCS08 Central Processor Unit (CPU) Peripherals

• 40-MHz HCS08 CPU (20-MHz bus) • ADC — 12-channel, 12-bit resolution, 2.5 μs
• HC08 instruction set with added BGND instruction conversion time, automatic compare function,
• Support for up to 32 interrupt/reset sources 1.7 mV/°C temperature sensor, internal bandgap
reference channel
On-Chip Memory • ACMP1 — One analog comparator with selectable
interrupt on rising, falling, or either edge of comparator
• Flash read/program/erase over full operating voltage output; compare option to fixed internal bandgap
and temperature reference voltage
— MC9S08EN32 = 32K • SCI1 — One SCI supporting LIN 2.0 Protocol and SAE
— MC9S08EN16 = 16K J2602 protocols; Full duplex non-return to zero (NRZ);
• Up to 1K random-access memory (RAM) Master extended break generation; Slave extended
break detection; Wakeup on active edge
Power-Saving Modes • SPI — Full-duplex or single-wire bidirectional;
Double-buffered transmit and receive; Master or Slave
• Two very low power stop modes mode; MSB-first or LSB-first shifting
• Reduced power wait mode • TPM1 — One 4-channel timer/pulse-with modulator;
• Very low power real time interrupt for use in run, wait, Selectable input capture, output compare, or buffered
and stop edge-aligned PWM on each channel
Clock Source Options • RTC — (Real-time counter) 8-bit modulus counter with
binary or decimal based prescaler; Real-time clock
• Oscillator (XOSC) — Loop-control Pierce oscillator; capabilities using external crystal and RTC for precise
Crystal or ceramic resonator range of 31.25 kHz to time base, time-of-day, calendar or task scheduling
38.4 kHz or 1 MHz to 16 MHz functions; Free running on-chip low power oscillator
(1 kHz) for cyclic wake-up without external
• Multi-purpose Clock generator (MCG) — PLL and
components
FLL modes (FLL capable of 1.5% deviation using
internal temperature compensation); Internal reference Input/Output
clock with trim adjustment; External reference with
oscillator/resonator options • 39 general-purpose input/output (I/O) pins and 1
input-only pin
System Protection
• 24 interrupt pins with selectable polarity on each pin
• Watchdog computer operating properly (COP) reset • Hysteresis and configurable pull device on all input
with option to run from backup dedicated 1-kHz pins.
internal clock source or bus clock • Configurable slew rate and drive strength on all output
• Low-voltage detection with reset or interrupt; selectable pins.
trip points
Package Options
• Illegal opcode detection with reset
• Illegal address detection with reset • 48-pin low-profile quad flat-pack (LQFP) — 7x7 mm
• Flash block protect • 32-pin low-profile quad flat-pack (LQFP) — 7x7 mm
• Loss-of-lock protection

Development Support

• Single-wire background debug interface

• On-chip, in-circuit emulation (ICE) with real-time bus
capture
 MC9S08EN32 Data Sheet
Covers MC9S08EN32
MC9S08EN16

MC9S08EN32
Rev. 2
9/2007

Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.

© Freescale Semiconductor, Inc., 2007. All rights reserved.

Revision History

To provide the most up-to-date information, the revision of our documents on the World Wide Web will be
the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://freescale.com/

The following revision history table summarizes changes contained in this document.

Revision Revision Description of Changes

Number Date
1 6/2006 Advance Information for alpha samples customers

2 9/2007 Product Launch. Removed the 64-pin QFN package. Changed from standard to extended
mode for MSCAN registers in register summary. Corrected Block diagrams for SCI.
Updated the latest Temp Sensor information. Made FTSTMOD reserved. Updated device
to use the ADC 12-bit module. Revised the MCG module. Updated the CPU Instruction Set
table. Updated the TPM block module to version 3. Added the TPM block module version
2 as an appendix for devices using 3M05C (or earlier) mask sets. Heavily revised the
Electricals appendix.

© Freescale Semiconductor, Inc., 2007. All rights reserved.

This product incorporates SuperFlash® Technology licensed from SST.

MC9S08EN32 Series Data Sheet, Rev. 2

6 Freescale Semiconductor
 List of Chapters
Chapter Title Page

Chapter 1 Device Overview .............................................................................. 19

Chapter 2 Pins and Connections ..................................................................... 23
Chapter 3 Modes of Operation ......................................................................... 29
Chapter 4 Memory ............................................................................................. 35
Chapter 5 Resets, Interrupts, and General System Control.......................... 59
Chapter 6 Parallel Input/Output Control.......................................................... 75
Chapter 7 Central Processor Unit (S08CPUV3) ............................................ 101
Chapter 8 Multi-Purpose Clock Generator (S08MCGV1) ............................. 121
Chapter 9 Analog Comparator (S08ACMPV3) .............................................. 153
Chapter 10 Analog-to-Digital Converter (S08ADC12V1)................................ 159
Chapter 11 Serial Peripheral Interface (S08SPIV3) ........................................ 187
Chapter 12 Serial Communications Interface (S08SCIV4)............................. 203
Chapter 13 Real-Time Counter (S08RTCV1) ................................................... 223
Chapter 14 Timer Pulse-Width Modulator (S08TPMV3) ................................. 233
Chapter 15 Development Support ................................................................... 259
Appendix A Electrical Characteristics.............................................................. 281
Appendix B Timer Pulse-Width Modulator (TPMV2) ....................................... 303
Appendix C Ordering Information and Mechanical Drawings........................ 317

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 7
 Contents
Section Number Title Page

Chapter 1
Device Overview
1.1 Devices in the MC9S08EN32 Series................................................................................................19
1.2 MCU Block Diagram .......................................................................................................................19
1.3 System Clock Distribution ...............................................................................................................21

Chapter 2
Pins and Connections
2.1 Device Pin Assignment ....................................................................................................................23
2.2 Recommended System Connections ................................................................................................25
2.2.1 Power ................................................................................................................................25
2.2.2 Oscillator ...........................................................................................................................26
2.2.3 RESET ..............................................................................................................................26
2.2.4 Background / Mode Select (BKGD/MS) ..........................................................................27
2.2.5 ADC Reference Pins (VREFH, VREFL) ..............................................................................27
2.2.6 General-Purpose I/O and Peripheral Ports ........................................................................27

Chapter 3
Modes of Operation
3.1 Introduction ......................................................................................................................................29
3.2 Features ............................................................................................................................................29
3.3 Run Mode.........................................................................................................................................29
3.4 Active Background Mode.................................................................................................................29
3.5 Wait Mode ........................................................................................................................................30
3.6 Stop Modes.......................................................................................................................................31
3.6.1 Stop3 Mode .......................................................................................................................31
3.6.2 Stop2 Mode .......................................................................................................................32
3.6.3 On-Chip Peripheral Modules in Stop Modes ....................................................................33

Chapter 4
Memory
4.1 MC9S08EN32 Series Memory Map ................................................................................................35
4.2 Reset and Interrupt Vector Assignments ..........................................................................................36
4.3 Register Addresses and Bit Assignments.........................................................................................37
4.4 RAM.................................................................................................................................................43
4.5 Flash ................................................................................................................................................43
4.5.1 Features .............................................................................................................................43

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Section Number Title Page

4.5.2 Program and Erase Times .................................................................................................44

4.5.3 Program and Erase Command Execution .........................................................................44
4.5.4 Burst Program Execution ..................................................................................................46
4.5.5 Sector Erase Abort ............................................................................................................48
4.5.6 Access Errors ....................................................................................................................49
4.5.7 Block Protection ................................................................................................................50
4.5.8 Vector Redirection ............................................................................................................50
4.5.9 Security .............................................................................................................................50
4.5.10 Flash Registers and Control Bits .......................................................................................52

Chapter 5
Resets, Interrupts, and General System Control
5.1 Introduction ......................................................................................................................................59
5.2 Features ............................................................................................................................................59
5.3 MCU Reset.......................................................................................................................................59
5.4 Computer Operating Properly (COP) Watchdog..............................................................................60
5.5 Interrupts ..........................................................................................................................................61
5.5.1 Interrupt Stack Frame .......................................................................................................62
5.5.2 External Interrupt Request (IRQ) Pin ...............................................................................62
5.5.3 Interrupt Vectors, Sources, and Local Masks ....................................................................63
5.6 Low-Voltage Detect (LVD) System .................................................................................................64
5.6.1 Power-On Reset Operation ...............................................................................................65
5.6.2 Low-Voltage Detection (LVD) Reset Operation ...............................................................65
5.6.3 Low-Voltage Warning (LVW) Interrupt Operation ...........................................................65
5.7 MCLK Output ..................................................................................................................................65
5.8 Reset, Interrupt, and System Control Registers and Control Bits ....................................................66
5.8.1 Interrupt Pin Request Status and Control Register (IRQSC) ............................................67
5.8.2 System Reset Status Register (SRS) .................................................................................68
5.8.3 System Background Debug Force Reset Register (SBDFR) ............................................69
5.8.4 System Options Register 1 (SOPT1) ................................................................................70
5.8.5 System Options Register 2 (SOPT2) ................................................................................71
5.8.6 System Device Identification Register (SDIDH, SDIDL) ................................................72
5.8.7 System Power Management Status and Control 1 Register (SPMSC1) ...........................73
5.8.8 System Power Management Status and Control 2 Register (SPMSC2) ...........................74

Chapter 6
Parallel Input/Output Control
6.1 Port Data and Data Direction ...........................................................................................................75
6.2 Pull-up, Slew Rate, and Drive Strength............................................................................................76
6.3 Pin Interrupts ....................................................................................................................................77
6.3.1 Edge Only Sensitivity .......................................................................................................77
6.3.2 Edge and Level Sensitivity ................................................................................................77

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Section Number Title Page

6.3.3 Pull-up/Pull-down Resistors .............................................................................................78

6.3.4 Pin Interrupt Initialization .................................................................................................78
6.4 Pin Behavior in Stop Modes.............................................................................................................78
6.5 Parallel I/O and Pin Control Registers .............................................................................................78
6.5.1 Port A Registers ................................................................................................................79
6.5.2 Port B Registers ................................................................................................................83
6.5.3 Port C Registers ................................................................................................................86
6.5.4 Port D Registers ................................................................................................................88
6.5.5 Port E Registers .................................................................................................................92
6.5.6 Port F Registers .................................................................................................................95
6.5.7 Port G Registers ................................................................................................................98

Chapter 7
Central Processor Unit (S08CPUV3)
7.1 Introduction ....................................................................................................................................101
7.1.1 Features ...........................................................................................................................101
7.2 Programmer’s Model and CPU Registers ......................................................................................102
7.2.1 Accumulator (A) .............................................................................................................102
7.2.2 Index Register (H:X) .......................................................................................................102
7.2.3 Stack Pointer (SP) ...........................................................................................................103
7.2.4 Program Counter (PC) ....................................................................................................103
7.2.5 Condition Code Register (CCR) .....................................................................................103
7.3 Addressing Modes..........................................................................................................................105
7.3.1 Inherent Addressing Mode (INH) ...................................................................................105
7.3.2 Relative Addressing Mode (REL) ...................................................................................105
7.3.3 Immediate Addressing Mode (IMM) ..............................................................................105
7.3.4 Direct Addressing Mode (DIR) ......................................................................................105
7.3.5 Extended Addressing Mode (EXT) ................................................................................106
7.3.6 Indexed Addressing Mode ..............................................................................................106
7.4 Special Operations..........................................................................................................................107
7.4.1 Reset Sequence ...............................................................................................................107
7.4.2 Interrupt Sequence ..........................................................................................................107
7.4.3 Wait Mode Operation ......................................................................................................108
7.4.4 Stop Mode Operation ......................................................................................................108
7.4.5 BGND Instruction ...........................................................................................................109
7.5 HCS08 Instruction Set Summary ...................................................................................................110

Chapter 8
Multi-Purpose Clock Generator (S08MCGV1)
8.1 Introduction ....................................................................................................................................121
8.1.1 Features ...........................................................................................................................123
8.1.2 Modes of Operation ........................................................................................................125

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Section Number Title Page

8.2 External Signal Description ...........................................................................................................125

8.3 Register Definition .........................................................................................................................126
8.3.1 MCG Control Register 1 (MCGC1) ...............................................................................126
8.3.2 MCG Control Register 2 (MCGC2) ...............................................................................127
8.3.3 MCG Trim Register (MCGTRM) ...................................................................................128
8.3.4 MCG Status and Control Register (MCGSC) .................................................................129
8.3.5 MCG Control Register 3 (MCGC3) ...............................................................................130
8.4 Functional Description ...................................................................................................................132
8.4.1 Operational Modes ..........................................................................................................132
8.4.2 Mode Switching ..............................................................................................................136
8.4.3 Bus Frequency Divider ...................................................................................................137
8.4.4 Low Power Bit Usage .....................................................................................................137
8.4.5 Internal Reference Clock ................................................................................................137
8.4.6 External Reference Clock ...............................................................................................137
8.4.7 Fixed Frequency Clock ...................................................................................................138
8.5 Initialization / Application Information .........................................................................................138
8.5.1 MCG Module Initialization Sequence ............................................................................138
8.5.2 MCG Mode Switching ....................................................................................................139
8.5.3 Calibrating the Internal Reference Clock (IRC) .............................................................150

Chapter 9
Analog Comparator (S08ACMPV3)
9.1 Introduction ....................................................................................................................................153
9.1.1 ACMP Configuration Information ..................................................................................153
9.1.2 Features ...........................................................................................................................155
9.1.3 Modes of Operation ........................................................................................................155
9.1.4 Block Diagram ................................................................................................................156
9.2 External Signal Description ...........................................................................................................156
9.3 Memory Map/Register Definition ..................................................................................................157
9.3.1 ACMP1 Status and Control Register (ACMP1SC) .........................................................157
9.4 Functional Description ...................................................................................................................158

Chapter 10
Analog-to-Digital Converter (S08ADC12V1)
10.1 Introduction ....................................................................................................................................159
10.1.1 Analog Power and Ground Signal Names ......................................................................159
10.1.2 Channel Assignments ......................................................................................................159
10.1.3 Alternate Clock ...............................................................................................................160
10.1.4 Hardware Trigger ............................................................................................................160
10.1.5 Temperature Sensor ........................................................................................................161
10.1.6 Features ...........................................................................................................................163
10.1.7 Block Diagram ................................................................................................................163

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12 Freescale Semiconductor
Section Number Title Page

10.2 External Signal Description ...........................................................................................................164

10.2.1 Analog Power (VDDAD) ..................................................................................................165
10.2.2 Analog Ground (VSSAD) .................................................................................................165
10.2.3 Voltage Reference High (VREFH) ...................................................................................165
10.2.4 Voltage Reference Low (VREFL) .....................................................................................165
10.2.5 Analog Channel Inputs (ADx) ........................................................................................165
10.3 Register Definition .........................................................................................................................165
10.3.1 Status and Control Register 1 (ADCSC1) ......................................................................165
10.3.2 Status and Control Register 2 (ADCSC2) ......................................................................167
10.3.3 Data Result High Register (ADCRH) .............................................................................168
10.3.4 Data Result Low Register (ADCRL) ..............................................................................168
10.3.5 Compare Value High Register (ADCCVH) ....................................................................169
10.3.6 Compare Value Low Register (ADCCVL) .....................................................................169
10.3.7 Configuration Register (ADCCFG) ................................................................................169
10.3.8 Pin Control 1 Register (APCTL1) ..................................................................................171
10.3.9 Pin Control 2 Register (APCTL2) ..................................................................................172
10.3.10Pin Control 3 Register (APCTL3) ..................................................................................173
10.4 Functional Description ...................................................................................................................174
10.4.1 Clock Select and Divide Control ....................................................................................174
10.4.2 Input Select and Pin Control ...........................................................................................175
10.4.3 Hardware Trigger ............................................................................................................175
10.4.4 Conversion Control .........................................................................................................175
10.4.5 Automatic Compare Function .........................................................................................178
10.4.6 MCU Wait Mode Operation ............................................................................................178
10.4.7 MCU Stop3 Mode Operation ..........................................................................................178
10.4.8 MCU Stop1 and Stop2 Mode Operation .........................................................................179
10.5 Initialization Information ...............................................................................................................179
10.5.1 ADC Module Initialization Example .............................................................................179
10.6 Application Information.................................................................................................................181
10.6.1 External Pins and Routing ..............................................................................................181
10.6.2 Sources of Error ..............................................................................................................183

Chapter 11
Serial Peripheral Interface (S08SPIV3)
11.1 Introduction ....................................................................................................................................187
11.1.1 Features ...........................................................................................................................189
11.1.2 Block Diagrams ..............................................................................................................189
11.1.3 SPI Baud Rate Generation ..............................................................................................191
11.2 External Signal Description ...........................................................................................................192
11.2.1 SPSCK — SPI Serial Clock ............................................................................................192
11.2.2 MOSI — Master Data Out, Slave Data In ......................................................................192
11.2.3 MISO — Master Data In, Slave Data Out ......................................................................192

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Section Number Title Page

11.2.4 SS — Slave Select ...........................................................................................................192

11.3 Modes of Operation........................................................................................................................193
11.3.1 SPI in Stop Modes ..........................................................................................................193
11.4 Register Definition .........................................................................................................................193
11.4.1 SPI Control Register 1 (SPIC1) ......................................................................................193
11.4.2 SPI Control Register 2 (SPIC2) ......................................................................................194
11.4.3 SPI Baud Rate Register (SPIBR) ....................................................................................195
11.4.4 SPI Status Register (SPIS) ..............................................................................................196
11.4.5 SPI Data Register (SPID) ................................................................................................197
11.5 Functional Description ...................................................................................................................198
11.5.1 SPI Clock Formats ..........................................................................................................198
11.5.2 SPI Interrupts ..................................................................................................................201
11.5.3 Mode Fault Detection .....................................................................................................201

Chapter 12
Serial Communications Interface (S08SCIV4)
12.1 Introduction ....................................................................................................................................203
12.1.1 Features ...........................................................................................................................205
12.1.2 Modes of Operation ........................................................................................................205
12.1.3 Block Diagram ................................................................................................................206
12.2 Register Definition .........................................................................................................................208
12.2.1 SCI Baud Rate Registers (SCI1BDH, SCI1BDL) ..........................................................208
12.2.2 SCI Control Register 1 (SCI1C1) ...................................................................................209
12.2.3 SCI Control Register 2 (SCI1C2) ...................................................................................210
12.2.4 SCI Status Register 1 (SCI1S1) ......................................................................................211
12.2.5 SCI Status Register 2 (SCI1S2) ......................................................................................213
12.2.6 SCI Control Register 3 (SCI1C3) ...................................................................................214
12.2.7 SCI Data Register (SCI1D) .............................................................................................215
12.3 Functional Description ...................................................................................................................215
12.3.1 Baud Rate Generation .....................................................................................................215
12.3.2 Transmitter Functional Description ................................................................................216
12.3.3 Receiver Functional Description .....................................................................................217
12.3.4 Interrupts and Status Flags ..............................................................................................219
12.3.5 Additional SCI Functions ...............................................................................................220

Chapter 13
Real-Time Counter (S08RTCV1)
13.1 Introduction ....................................................................................................................................223
13.1.1 RTC Clock Signal Names ...............................................................................................223
13.1.2 Features ...........................................................................................................................225
13.1.3 Modes of Operation ........................................................................................................225
13.1.4 Block Diagram ................................................................................................................226

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14 Freescale Semiconductor
Section Number Title Page

13.2 External Signal Description ...........................................................................................................226

13.3 Register Definition .........................................................................................................................226
13.3.1 RTC Status and Control Register (RTCSC) ....................................................................227
13.3.2 RTC Counter Register (RTCCNT) ..................................................................................228
13.3.3 RTC Modulo Register (RTCMOD) ................................................................................228
13.4 Functional Description ...................................................................................................................229
13.4.1 RTC Operation Example .................................................................................................230
13.5 Initialization/Application Information ...........................................................................................230

Chapter 14
Timer Pulse-Width Modulator (S08TPMV3)
14.1 Introduction ....................................................................................................................................233
14.1.1 Features ...........................................................................................................................235
14.1.2 Modes of Operation ........................................................................................................235
14.1.3 Block Diagram ................................................................................................................236
14.2 Signal Description ..........................................................................................................................238
14.2.1 Detailed Signal Descriptions ...........................................................................................238
14.3 Register Definition .........................................................................................................................242
14.3.1 TPM Status and Control Register (TPM1SC) ................................................................242
14.3.2 TPM-Counter Registers (TPM1CNTH:TPM1CNTL) ....................................................243
14.3.3 TPM Counter Modulo Registers (TPM1MODH:TPM1MODL) ....................................244
14.3.4 TPM Channel n Status and Control Register (TPM1CnSC) ..........................................245
14.3.5 TPM Channel Value Registers (TPM1CnVH:TPM1CnVL) ..........................................246
14.4 Functional Description ...................................................................................................................248
14.4.1 Counter ............................................................................................................................248
14.4.2 Channel Mode Selection .................................................................................................250
14.5 Reset Overview ..............................................................................................................................253
14.5.1 General ............................................................................................................................253
14.5.2 Description of Reset Operation .......................................................................................253
14.6 Interrupts ........................................................................................................................................253
14.6.1 General ............................................................................................................................253
14.6.2 Description of Interrupt Operation ..................................................................................254
14.7 The differences from TPM v2 to TPM v3......................................................................................255

Chapter 15
Development Support
15.1 Introduction ....................................................................................................................................259
15.1.1 Forcing Active Background ............................................................................................259
15.1.2 Features ...........................................................................................................................260
15.2 Background Debug Controller (BDC) ...........................................................................................260
15.2.1 BKGD Pin Description ...................................................................................................261
15.2.2 Communication Details ..................................................................................................262

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15.2.3 BDC Commands .............................................................................................................266

15.2.4 BDC Hardware Breakpoint .............................................................................................268
15.3 On-Chip Debug System (DBG) .....................................................................................................269
15.3.1 Comparators A and B ......................................................................................................269
15.3.2 Bus Capture Information and FIFO Operation ...............................................................269
15.3.3 Change-of-Flow Information ..........................................................................................270
15.3.4 Tag vs. Force Breakpoints and Triggers .........................................................................270
15.3.5 Trigger Modes .................................................................................................................271
15.3.6 Hardware Breakpoints ....................................................................................................273
15.4 Register Definition .........................................................................................................................273
15.4.1 BDC Registers and Control Bits .....................................................................................273
15.4.2 System Background Debug Force Reset Register (SBDFR) ..........................................275
15.4.3 DBG Registers and Control Bits .....................................................................................276

Appendix A
Electrical Characteristics
A.1 Introduction ...................................................................................................................................281
A.2 Parameter Classification ................................................................................................................281
A.3 Absolute Maximum Ratings ..........................................................................................................281
A.4 Thermal Characteristics .................................................................................................................282
A.5 ESD Protection and Latch-Up Immunity ......................................................................................284
A.6 DC Characteristics .........................................................................................................................285
A.7 Supply Current Characteristics ......................................................................................................287
A.8 Analog Comparator (ACMP) Electricals ......................................................................................288
A.9 ADC Characteristics ......................................................................................................................288
A.10 External Oscillator (XOSC) Characteristics .................................................................................292
A.11 MCG Specifications ......................................................................................................................293
A.12 AC Characteristics .........................................................................................................................295
A.12.1 Control Timing ...............................................................................................................295
A.12.2 Timer/PWM ....................................................................................................................296
A.12.3 SPI ...................................................................................................................................298
A.13 Flash ..............................................................................................................................................301
A.14 EMC Performance .........................................................................................................................301
A.14.1 Radiated Emissions .........................................................................................................302

Appendix B
Timer Pulse-Width Modulator (TPMV2)
B.1 Introduction ....................................................................................................................................303
B.2 Features ..........................................................................................................................................303
B.3 Block Diagram ...............................................................................................................................303
B.4 External Signal Description ...........................................................................................................305
B.4.1 External TPM Clock Sources ..........................................................................................305

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B.4.2 TPM1CHn — TPM1 Channel n I/O Pins .......................................................................305

B.5 Register Definition .........................................................................................................................305
B.5.1 Timer Status and Control Register (TPM1SC) ...............................................................306
B.5.2 Timer Counter Registers (TPM1CNTH:TPM1CNTL) ...................................................307
B.5.3 Timer Counter Modulo Registers (TPM1MODH:TPM1MODL) ..................................308
B.5.4 Timer Channel n Status and Control Register (TPM1CnSC) .........................................309
B.5.5 Timer Channel Value Registers (TPM1CnVH:TPM1CnVL) .........................................310
B.6 Functional Description ...................................................................................................................311
B.6.1 Counter ............................................................................................................................311
B.6.2 Channel Mode Selection .................................................................................................312
B.6.3 Center-Aligned PWM Mode ...........................................................................................314
B.7 TPM Interrupts ...............................................................................................................................315
B.7.1 Clearing Timer Interrupt Flags .......................................................................................315
B.7.2 Timer Overflow Interrupt Description ............................................................................315
B.7.3 Channel Event Interrupt Description ..............................................................................316
B.7.4 PWM End-of-Duty-Cycle Events ...................................................................................316

Appendix C
Ordering Information and Mechanical Drawings
C.1 Ordering Information ....................................................................................................................317
C.1.1 MC9S08EN32 Series Devices ........................................................................................317
C.2 Mechanical Drawings ....................................................................................................................317

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Freescale Semiconductor 17
Chapter 1
Device Overview
Controller Area Network MC9S08EN32 Series devices provide peripheral flexibility and offer a pin and
code compatibility with MC9S08DN60, MC9S08DV60, and MC9S08DZ60 Series devices when more
memory and peripheral expansion is required.

1.1 Devices in the MC9S08EN32 Series

This data sheet covers members of the MC9S08EN32 Series of MCUs:
• MC9S08EN32
• MC9S08EN16
Table 1-1 summarizes the feature set available in the MC9S08EN32 Series.
Table 1-1. MC9S08EN32 Series Features by MCU and Pin Count

Feature MC9S08EN32 MC9S08EN16

Flash size 33792 16896
(bytes)
RAM size (bytes) 1024 512
Pin quantity 48 32 48 32
ACMP1 yes
ADC channels 12 10 12 10
DBG yes
IRQ yes
MCG yes
RTC yes
SCI1 yes
SPI yes
TPM1 channels 4
XOSC yes
COP Watchdog yes

1.2 MCU Block Diagram

Figure 1-1 is the MC9S08EN32 Series system-level block diagram.

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Freescale Semiconductor 19
Chapter 1 Device Overview

HCS08 CORE PTA7/PIA7/ADP7/IRQ

PTA6/PIA6/ADP6
PTA5/PIA5/ADP5
CPU

PORT A
PTA4/PIA4/ADP4
ACMP1O
ANALOG COMPARATOR PTA3/PIA3/ADP3/ACMP1O
BKGD/MS ACMP1-
(ACMP1) PTA2/PIA2/ADP2/ACMP1-
BDC BKP ACMP1+
PTA1/PIA1/ADP1/ACMP1+
PTA0/PIA0/ADP0/MCLK
HCS08 SYSTEM CONTROL
PTB7/PIB7
RESETS AND INTERRUPTS PTB6/PIB6
RESET
MODES OF OPERATION PTB5/PIB5

PORT B
POWER MANAGEMENT PTB4/PIB4
PTB3/PIB3/ADP11
8 PTB2/PIB2/ADP10
COP LVD PTB1/PIB1/ADP9
IRQ

ADP7-ADP0 PTB0/PIB0/ADP8
INT IRQ
12-CHANNEL,10-BIT
ADP11-ADP8
ANALOG-TO-DIGITAL
VREFH
CONVERTER (ADC)
VREFL
VDDA
VSSA

TPM1CH3–TPM1CH0
PTD7/PID7
USER Flash 4-CHANNEL TIMER/PWM 6 PTD6/PID6
MODULE (TPM1) TPM1CLK
MC9S08EN32 = 32K PTD5/PID5/TPM1CH3
MC9S08EN16 = 16K

PORT D
PTD4/PID4/TPM1CH2
PTD3/PID3/TPM1CH1
PTD2/PID2/TPM1CH0
PTD1/PID1
PTD0/PID0
PTE7
PTE6
MISO
USER RAM PTE5/MISO
MOSI
PORT E

MC9S08EN32 = 1 KBYTE SERIAL PERIPHERAL PTE4/MOSI

SPSCK
MC9S08EN16 = 512 BYTES INTERFACE MODULE (SPI) PTE3/SPSCK
SS
PTE2/SS
RxD1
PTE1/RxD1
DEBUG MODULE (DBG) SERIAL COMMUNICATIONS TxD1
PTE0/TxD1
INTERFACE (SCI1)

REAL TIME COUNTER (RTC) PTF5

PORT F

PTF4
VDD PTF3
VDD VOLTAGE PTF2/TPM1CLK
VSS REGULATOR PTF1
VSS PTF0

MULTI-PURPOSE
CLOCK GENERATOR
PORT G

(MCG)
XTAL
PTG1/XTAL
OSCILLATOR (XOSC) EXTAL
PTG0/EXTAL
- VREFH/VREFL internally connected to VDDA/VSSA
- VDD and VSS pins are each internally connected to two pads in 32-pin package - Pin not connected in 32-pin package

Figure 1-1. MC9S08EN32/16 Block Diagram

MC9S08EN32 Series Data Sheet, Rev. 2

20 Freescale Semiconductor
 Chapter 1 Device Overview

Table 1-2 provides the functional version of the on-chip modules.

Table 1-2. Module Versions

Module Version
Central Processor Unit (CPU) 3
Multi-Purpose Clock Generator (MCG) 1
Analog Comparator (ACMP) 3
Analog-to-Digital Converter (ADC) 1
Serial Peripheral Interface (SPI) 3
Serial Communications Interface (SCI) 4
Real-Time Counter (RTC) 1
Timer Pulse Width Modulator (TPM) 31
Debug Module (DBG) 2
1
3M05C and older masks have TPM version 2.

1.3 System Clock Distribution

Figure 1-2 shows a simplified clock connection diagram. Some modules in the MCU have selectable clock
inputs as shown. The clock inputs to the modules indicate the clock(s) that are used to drive the module
function.
The following are the clocks used in this MCU:
• BUSCLK — The frequency of the bus is always half of MCGOUT.
• LPO — Independent 1-kHz clock that can be selected as the source for the COP and RTC modules.
• MCGOUT — Primary output of the MCG and is twice the bus frequency.
• MCGLCLK — Development tools can select this clock source to speed up BDC communications
in systems where BUSCLK is configured to run at a very slow frequency.
• MCGERCLK — External reference clock can be selected as the RTC clock source. It can also be
used as the alternate clock for the ADC.
• MCGIRCLK — Internal reference clock can be selected as the RTC clock source.
• MCGFFCLK — Fixed frequency clock can be selected as clock source for the TPM1.
• TPM1CLK — External input clock source for TPM1.

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 21
 Chapter 1 Device Overview

TPM1CLK

1 kHZ COP TPM1 SCI1 SPI

RTC
LPO
MCGERCLK
MCGIRCLK

MCG MCGFFCLK FFCLK*

÷2

MCGOUT BUSCLK
÷2
MCGLCLK

XOSC
CPU BDC ADC Flash

ADC has min and max Flash has frequency

EXTAL XTAL frequency requirements. requirements for program
See the ADC chapter and erase operation. See
* The fixed frequency clock (FFCLK) is internally
and electricals appendix the electricals appendix
synchronized to the bus clock and must not exceed one half
of the bus clock frequency.
for details. for details.

Figure 1-2. MC9S08EN32/16 System Clock Distribution Diagram

MC9S08EN32 Series Data Sheet, Rev. 2

22 Freescale Semiconductor
Chapter 2
Pins and Connections
This section describes signals that connect to package pins. It includes pinout diagrams, recommended
system connections, and detailed discussions of signals.

2.1 Device Pin Assignment

This section shows the pin assignments for MC9S08EN32 Series MCUs in the available packages.

PTA3/PIA3/ADP3/ACMP1O

PTA1/PIA1/ADP1/ACMP1+
PTA2/PIA2/ADP2/ACMP1-
PTB3/PIB3/ADP11

PTB2/PIB2/ADP10
PTA6/PIA6/ADP6

PTA5/PIA5/ADP5

PTA4/PIA4/ADP4
VDDA/VREFH
VSSA/VREFL
PTB5/PIB5

PTB4/PIB4
48
47
46
45
44
43
42
41
40
39
38
37

PTB6/PIB6 1 36 PTB1/PIB1/ADP9
PTA7/PIA7/ADP7/IRQ 2 35 PTA0/PIA0/ADP0/MCLK
PTB7/PIB7 3 34 PTB0/PIB0/ADP8
VDD 4 33 BKGD/MS
VSS 5 32 PTD7/PID7
PTG0/EXTAL 6 31 PTD6/PID6
PTG1/XTAL
48-Pin LQFP 30 VDD
7
RESET 8 29 VSS
PTF4 9 28 PTD5/PID5/TPM1CH3
PTF5 10 27 PTD4/PID4/TPM1CH2
PTE0/TxD1 11 26 PTD3/PID3/TPM1CH1
PTE1/RxD1 12 25 PTD2/PID2/TPM1CH0
13
14
15
16
17
18
19
20
21
22
23
24
PTE4/MOSI
PTE5/MISO
PTE2/SS
PTE3/SPSCK

PTF0
PTF1
PTF2/TPM1CLK
PTF3
PTE6
PTE7
PTD0/PID0
PTD1/PID1

VREFH and VREFL are internally connected to VDDA and VSSA, respectively.

Figure 2-1. 48-Pin LQFP

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 23
Chapter 2 Pins and Connections

PTA3/ADP3/ACMPO

PTA1/ADP1/ACMP+
PTA2/ADP2/ACMP-
PTA6/PIA6/ADP6

PTA5/PIA5/ADP5

PTA4/PIA4/ADP4

VDDA/VREFH

VSSA/VREFL
32 25
31 30 29 28 27 26
PTA7/PIA7/ADP7/IRQ 1 24 PTB1/PIB1/ADP9

VDD 2 23 PTA0/PIA0/ADP0/MCLK

VSS 3 22 PTB0/PIB0/ADP8

PTG0/EXTAL 4 21 BKGD/MS
32-Pin LQFP
PTG1/XTAL 5 20 PTD5/PID5/TPM1CH3

RESET 6 19 PTD4/PID4/TPM1CH2

PTE0/TxD1 7 18 PTD3/PID3/TPM1CH1

PTE1/RxD1 8 17 PTD2/PID2/TPM1CH0
10 11 12 13 14 15
9 16
PTE2/SS

PTE3/SPSCK

PTE4/MOSI

PTE5/MISO

PTE6

PTE7

PTD0/PID0

PTD1/PID1

VREFH and VREFL are internally connected to VDDA and VSSA, respectively.
Figure 2-2. 32-Pin LQFP

MC9S08EN32 Series Data Sheet, Rev. 2

24 Freescale Semiconductor
 Chapter 2 Pins and Connections

2.2 Recommended System Connections

Figure 2-3 shows pin connections that are common to MC9S08EN32 Series application systems.
VDD MC9S08EN32
PTA0/PIA0/ADP0/MCLK
+ CBY
CBLK + PTA1/PIA1/ADP1/ACMP1+
5V 10 μF 0.1 μF
PTA2/PIA2/ADP2/ACMP1-
VSS
PTA3/PIA3/ADP3/ACMP1O
PORT
VDDA A PTA4/PIA4/ADP4
SYSTEM
POWER CBY VREFH PTA5/PIA5/ADP5
0.1 μF PTA6/PIA6/ADP6
VREFL IRQ
PTA7/PIA7/ADP7/IRQ
VSSA

BACKGROUND HEADER
PTB0/PIB0/ADP8
VDD PTB1/PIB1/ADP9
BKGD/MS
VDD PTB2/PIB2/ADP10
PORT PTB3/PIB3/ADP11
4.7 kΩ–10 kΩ
B PTB4/PIB4
PTB5/PIB5
RESET
PTB6/PIB6
OPTIONAL 0.1 μF PTB7/PIB7
MANUAL
RESET

PTD0/PID0
PTD1/PID1
PTD2/PID2/TPM1CH0
RF
RS PORT PTD3/PID3/TPM1CH1
D PTD4/PID4/TPM1CH2
C1 X1 C2
PTD5/PID5/TPM1CH3
PTD6/PID6
PTG0/EXTAL PORT PTD7/PID7
NOTES:
1. External crystal circuit not PTG1/XTAL G
required if using the internal
clock option.
2. RESET pin can only be used to
reset into user mode, you can PTE0/TxD1
not enter BDM using RESET PTE1/RxD1
pin. BDM can be entered by TPM1CLK
holding MS low during POR or PORT PTE2/SS
writing a 1 to BDFR in SBDFR PTF4
with MS low after issuing BDM F PORT PTE3/SPSCK
PTF5
command. E PTE4/MOSI
3. RC filter on RESET pin
recommended for noisy PTE5/MISO
environments.
4. For 32-pin and 48-pin PTE6
packages: VDDA and VSSA are
double bonded to VREFH and PTE7
VREFL respectively.

Figure 2-3. Basic System Connections (Shown in 48-Pin Package)

2.2.1 Power
VDD and VSS are the primary power supply pins for the MCU. This voltage source supplies power to all
I/O buffer circuitry and to an internal voltage regulator. The internal voltage regulator provides regulated
lower-voltage source to the CPU and other internal circuitry of the MCU.

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 25
Chapter 2 Pins and Connections

Typically, application systems have two separate capacitors across the power pins. In this case, there
should be a bulk electrolytic capacitor, such as a 10-μF tantalum capacitor, to provide bulk charge storage
for the overall system and a 0.1-μF ceramic bypass capacitor located as near to the MCU power pins as
practical to suppress high-frequency noise. The MC9S08EN32 Series has two VDD pins except on the
32-pin package. Each pin must have a bypass capacitor for best noise suppression.
VDDA and VSSA are the analog power supply pins for the MCU. This voltage source supplies power to the
ADC module. A 0.1-μF ceramic bypass capacitor should be located as near to the MCU power pins as
practical to suppress high-frequency noise.

2.2.2 Oscillator
Immediately after reset, the MCU uses an internally generated clock provided by the multi-purpose clock
generator (MCG) module. For more information on the MCG, see Chapter 8, “Multi-Purpose Clock
Generator (S08MCGV1).”
The oscillator (XOSC) in this MCU is a Pierce oscillator that can accommodate a crystal or ceramic
resonator. Rather than a crystal or ceramic resonator, an external oscillator can be connected to the EXTAL
input pin.
Refer to Figure 2-3 for the following discussion. RS (when used) and RF should be low-inductance
resistors such as carbon composition resistors. Wire-wound resistors and some metal film resistors have
too much inductance. C1 and C2 normally should be high-quality ceramic capacitors that are specifically
designed for high-frequency applications.
RF is used to provide a bias path to keep the EXTAL input in its linear range during crystal startup; its value
is not generally critical. Typical systems use 1 MΩ to 10 MΩ. Higher values are sensitive to humidity, and
lower values reduce gain and (in extreme cases) could prevent startup.
C1 and C2 are typically in the 5-pF to 25-pF range and are chosen to match the requirements of a specific
crystal or resonator. Be sure to take into account printed circuit board (PCB) capacitance and MCU pin
capacitance when selecting C1 and C2. The crystal manufacturer typically specifies a load capacitance
which is the series combination of C1 and C2 (which are usually the same size). As a first-order
approximation, use 10 pF as an estimate of combined pin and PCB capacitance for each oscillator pin
(EXTAL and XTAL).

2.2.3 RESET
RESET is a dedicated pin with a pull-up device built in. It has input hysteresis, a high current output driver,
and no output slew rate control. Internal power-on reset and low-voltage reset circuitry typically make
external reset circuitry unnecessary. This pin is normally connected to the standard 6-pin background
debug connector so a development system can directly reset the MCU system. If desired, a manual external
reset can be added by supplying a simple switch to ground (pull reset pin low to force a reset).
Whenever any reset is initiated (whether from an external signal or from an internal system), the RESET
pin is driven low for about 34 bus cycles. The reset circuitry decodes the cause of reset and records it by
setting a corresponding bit in the system reset status register (SRS).

MC9S08EN32 Series Data Sheet, Rev. 2

26 Freescale Semiconductor
 Chapter 2 Pins and Connections

2.2.4 Background / Mode Select (BKGD/MS)

While in reset, the BKGD/MS pin functions as a mode select pin. Immediately after reset rises, the pin
functions as the background pin and can be used for background debug communication. While functioning
as a background or mode select pin, the pin includes an internal pull-up device, input hysteresis, a standard
output driver, and no output slew rate control.
If nothing is connected to this pin, the MCU will enter normal operating mode at the rising edge of reset.
If a debug system is connected to the 6-pin standard background debug header, it can hold BKGD low
during the rising edge of reset which forces the MCU to active background mode.
The BKGD/MS pin is used primarily for background debug controller (BDC) communications using a
custom protocol that uses 16 clock cycles of the target MCU’s BDC clock per bit time. The target MCU’s
BDC clock could be as fast as the bus clock rate, so there should never be any significant capacitance
connected to the BKGD/MS pin that could interfere with background serial communications.
Although the BKGD/MS pin is a pseudo open-drain pin, the background debug communication protocol
provides brief, actively driven, high speedup pulses to ensure fast rise times. Small capacitances from
cables and the absolute value of the internal pull-up device play almost no role in determining rise and fall
times on the BKGD/MS pin.

2.2.5 ADC Reference Pins (VREFH, VREFL)

The VREFH and VREFL pins are the voltage reference high and voltage reference low inputs, respectively,
for the ADC module.

2.2.6 General-Purpose I/O and Peripheral Ports

The MC9S08EN32 Series series of MCUs support up to 39 general-purpose I/O pins and 1 input-only pin,
which are shared with on-chip peripheral functions (timers, serial I/O, ADC, etc.).
When a port pin is configured as a general-purpose output or a peripheral uses the port pin as an output,
software can select one of two drive strengths and enable or disable slew rate control. When a port pin is
configured as a general-purpose input or a peripheral uses the port pin as an input, software can enable a
pull-up device. Immediately after reset, all of these pins are configured as high-impedance general-purpose
inputs with internal pull-up devices disabled.
When an on-chip peripheral system is controlling a pin, data direction control bits still determine what is
read from port data registers even though the peripheral module controls the pin direction by controlling
the enable for the pin’s output buffer. For information about controlling these pins as general-purpose I/O
pins, see Chapter 6, “Parallel Input/Output Control.”
NOTE
To avoid extra current drain from floating input pins, the reset initialization
routine in the application program should either enable on-chip pull-up
devices or change the direction of unused or non-bonded pins to outputs so
they do not float.

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 27
Chapter 2 Pins and Connections

Table 2-1. Pin Availability by Package Pin-Count

Pin Pin
<-- Lowest Priority --> Highest <-- Lowest Priority --> Highest
Number Number

Port Port
48 32 Alt 1 Alt 2 48 32 Alt 1 Alt 2
Pin/Interrupt Pin/Interrupt

1 — PTB6 PIB6 26 18 PTD3 PID3 TPM1CH1

2 1 PTA7 PIA7 ADP7 IRQ 27 19 PTD4 PID4 TPM1CH2
3 — PTB7 PIB7 28 20 PTD5 PID5 TPM1CH3
4 2 VDD 29 — VSS
5 3 VSS 30 — VDD
6 4 PTG0 EXTAL 31 — PTD6 PID6
7 5 PTG1 XTAL 32 — PTD7 PID7
8 6 RESET 33 21 BKGD MS
9 — PTF4 34 22 PTB0 PIB0 ADP8
10 — PTF5 35 23 PTA0 PIA0 ADP0 MCLK
11 7 PTE0 TxD1 36 24 PTB1 PIB1 ADP9
12 8 PTE1 RxD1 37 25 PTA1 PIA1 ADP11 ACMP1+1
13 9 PTE2 SS 38 — PTB2 PIB2 ADP10
14 10 PTE3 SPSCK 39 26 PTA2 PIA2 ADP2 ACMP1-1
15 11 PTE4 MOSI 40 — PTB3 PIB3 ADP11
16 12 PTE5 MISO 41 27 PTA3 PIA3 ADP3 ACMP1O
17 — PTF0 42 28 VSSA
18 — PTF1 VREFL
19 — PTF2 TPM1CLK 43 29 VREFH
20 — PTF3 VDDA
21 13 PTE6 44 30 PTA4 PIA4 ADP4
22 14 PTE7 45 — PTB4 PIB4
23 15 PTD0 PID0 46 31 PTA5 PIA5 ADP5
24 16 PTD1 PID1 47 — PTB5 PIB5
25 17 PTD2 PID2 TPM1CH0 48 32 PTA6 PIA6 ADP6

1. If both of these analog modules are enabled they both will have access to the pin.
2. Pin does not contain a clamp diode to VDD and should not be driven above VDD. The voltage measured on this pin when
internal pull-up is enabled may be as low as VDD – 0.7 V. The internal gates connected to this pin are pulled to VDD.

MC9S08EN32 Series Data Sheet, Rev. 2

28 Freescale Semiconductor
Chapter 3
Modes of Operation
3.1 Introduction
The operating modes of the MC9S08EN32 Series are described in this chapter. Entry into each mode, exit
from each mode, and functionality while in each of the modes are described.

3.2 Features
• Active background mode for code development
• Wait mode — CPU shuts down to conserve power; system clocks are running and full regulation
is maintained
• Stop modes — System clocks are stopped and voltage regulator is in standby
— Stop3 — All internal circuits are powered for fast recovery
— Stop2 — Partial power down of internal circuits; RAM content is retained

3.3 Run Mode

This is the normal operating mode for the MC9S08EN32 Series. This mode is selected when the
BKGD/MS pin is high at the rising edge of reset. In this mode, the CPU executes code from internal
memory with execution beginning at the address fetched from memory at 0xFFFE–0xFFFF after reset.

3.4 Active Background Mode

The active background mode functions are managed through the background debug controller (BDC) in
the HCS08 core. The BDC, together with the on-chip debug module (DBG), provide the means for
analyzing MCU operation during software development.
Active background mode is entered in any of five ways:
• When the BKGD/MS pin is low at the rising edge of reset
• When a BACKGROUND command is received through the BKGD/MS pin
• When a BGND instruction is executed
• When encountering a BDC breakpoint
• When encountering a DBG breakpoint
After entering active background mode, the CPU is held in a suspended state waiting for serial background
commands rather than executing instructions from the user application program.

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 29
Chapter 3 Modes of Operation

Background commands are of two types:

• Non-intrusive commands, defined as commands that can be issued while the user program is
running. Non-intrusive commands can be issued through the BKGD/MS pin while the MCU is in
run mode; non-intrusive commands can also be executed when the MCU is in the active
background mode. Non-intrusive commands include:
— Memory access commands
— Memory-access-with-status commands
— BDC register access commands
— The BACKGROUND command
• Active background commands, which can only be executed while the MCU is in active background
mode. Active background commands include commands to:
— Read or write CPU registers
— Trace one user program instruction at a time
— Leave active background mode to return to the user application program (GO)
The active background mode is used to program a bootloader or user application program into the Flash
program memory before the MCU is operated in run mode for the first time. When the MC9S08EN32
Series is shipped from the Freescale Semiconductor factory, the Flash program memory is erased by
default unless specifically noted so there is no program that could be executed in run mode until the Flash
memory is initially programmed. The active background mode can also be used to erase and reprogram
the Flash memory after it has been previously programmed.
For additional information about the active background mode, refer to the Development Support chapter.

3.5 Wait Mode

Wait mode is entered by executing a WAIT instruction. Upon execution of the WAIT instruction, the CPU
enters a low-power state in which it is not clocked. The I bit in CCR is cleared when the CPU enters the
wait mode, enabling interrupts. When an interrupt request occurs, the CPU exits the wait mode and
resumes processing, beginning with the stacking operations leading to the interrupt service routine.
While the MCU is in wait mode, there are some restrictions on which background debug commands can
be used. Only the BACKGROUND command and memory-access-with-status commands are available
when the MCU is in wait mode. The memory-access-with-status commands do not allow memory access,
but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND
command can be used to wake the MCU from wait mode and enter active background mode.

MC9S08EN32 Series Data Sheet, Rev. 2

30 Freescale Semiconductor
 Chapter 3 Modes of Operation

3.6 Stop Modes

One of two stop modes is entered upon execution of a STOP instruction when the STOPE bit in SOPT1
register is set. In both stop modes, all internal clocks are halted. The MCG module can be configured to
leave the reference clocks running. See Chapter 8, “Multi-Purpose Clock Generator (S08MCGV1),” for
more information.
Table 3-1 shows all of the control bits that affect stop mode selection and the mode selected under various
conditions. The selected mode is entered following the execution of a STOP instruction.
Table 3-1. Stop Mode Selection

STOPE ENBDM 1 LVDE LVDSE PPDC Stop Mode

0 x x x Stop modes disabled; illegal opcode reset if STOP instruction executed

1 1 x x Stop3 with BDM enabled 2

1 0 Both bits must be 1 x Stop3 with voltage regulator active

1 0 Either bit a 0 0 Stop3

1 0 Either bit a 0 1 Stop2

1
ENBDM is located in the BDCSCR, which is only accessible through BDC commands, see Section 15.4.1.1, “BDC Status and
Control Register (BDCSCR)”.
2 When in Stop3 mode with BDM enabled, The S
IDD will be near RIDD levels because internal clocks are enabled.

3.6.1 Stop3 Mode

Stop3 mode is entered by executing a STOP instruction under the conditions as shown in Table 3-1. The
states of all of the internal registers and logic, RAM contents, and I/O pin states are maintained.
Exit from stop3 is done by asserting RESET or an asynchronous interrupt pin. The asynchronous interrupt
pins are IRQ, PIA0–PIA7, PIB0–PIB7, and PID0–PID7. Exit from stop3 can also be done by the
low-voltage detect (LVD) reset, low-voltage warning (LVW) interrupt, ADC conversion complete
interrupt, real-time clock (RTC) interrupt or SCI receiver interrupt.
If stop3 is exited by means of the RESET pin, the MCU will be reset and operation will resume after
fetching the reset vector. Exit by means of an interrupt will result in the MCU fetching the appropriate
interrupt vector.

3.6.1.1 LVD Enabled in Stop3 Mode

The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below
the LVD voltage. If the LVD is enabled in stop (LVDE and LVDSE bits in SPMSC1 both set) at the time
the CPU executes a STOP instruction, then the voltage regulator remains active during stop mode.
For the ADC to operate the LVD must be left enabled when entering stop3.

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 31
Chapter 3 Modes of Operation

3.6.1.2 Active BDM Enabled in Stop3 Mode

Entry into the active background mode from run mode is enabled if ENBDM in BDCSCR is set. This
register is described in Chapter 15, “Development Support.” If ENBDM is set when the CPU executes a
STOP instruction, the system clocks to the background debug logic remain active when the MCU enters
stop mode. Because of this, background debug communication remains possible. In addition, the voltage
regulator does not enter its low-power standby state but maintains full internal regulation.
Most background commands are not available in stop mode. The memory-access-with-status commands
do not allow memory access, but they report an error indicating that the MCU is in either stop or wait
mode. The BACKGROUND command can be used to wake the MCU from stop and enter active
background mode if the ENBDM bit is set. After entering background debug mode, all background
commands are available.

3.6.2 Stop2 Mode

Stop2 mode is entered by executing a STOP instruction under the conditions as shown in Table 3-1. Most
of the internal circuitry of the MCU is powered off in stop2 with the exception of the RAM. Upon entering
stop2, all I/O pin control signals are latched so that the pins retain their states during stop2.
Exit from stop2 is performed by asserting RESET. On 3M05C or older masksets only, exit from stop2 can
also be performed by asserting PTA7/ADP7/IRQ.

NOTE
On 3M05C or older masksets only, PTA7/ADP7/IRQ is an active low
wake-up and must be configured as an input prior to executing a STOP
instruction to avoid an immediate exit from stop2. PTA7/ADP7/IRQ can be
disabled as a wake-up if it is configured as a high driven output. For lowest
power consumption in stop2, this pin should not be left open when
configured as input (enable the internal pullup; or tie an external
pullup/down device; or set pin as output).
In addition, the real-time counter (RTC) can wake the MCU from stop2, if enabled.
Upon wake-up from stop2 mode, the MCU starts up as from a power-on reset (POR):
• All module control and status registers are reset
• The LVD reset function is enabled and the MCU remains in the reset state if VDD is below the LVD
trip point (low trip point selected due to POR)
• The CPU takes the reset vector
In addition to the above, upon waking up from stop2, the PPDF bit in SPMSC2 is set. This flag is used to
direct user code to go to a stop2 recovery routine. PPDF remains set and the I/O pin states remain latched
until a 1 is written to PPDACK in SPMSC2.

MC9S08EN32 Series Data Sheet, Rev. 2

32 Freescale Semiconductor
 Chapter 3 Modes of Operation

To maintain I/O states for pins that were configured as general-purpose I/O before entering stop2, the user
must restore the contents of the I/O port registers, which have been saved in RAM, to the port registers
before writing to the PPDACK bit. If the port registers are not restored from RAM before writing to
PPDACK, then the pins will switch to their reset states when PPDACK is written.
For pins that were configured as peripheral I/O, the user must reconfigure the peripheral module that
interfaces to the pin before writing to the PPDACK bit. If the peripheral module is not enabled before
writing to PPDACK, the pins will be controlled by their associated port control registers when the I/O
latches are opened.

3.6.3 On-Chip Peripheral Modules in Stop Modes

When the MCU enters any stop mode, system clocks to the internal peripheral modules are stopped. Even
in the exception case (ENBDM = 1), where clocks to the background debug logic continue to operate,
clocks to the peripheral systems are halted to reduce power consumption. Refer to Section 3.6.2, “Stop2
Mode” and Section 3.6.1, “Stop3 Mode” for specific information on system behavior in stop modes.
Table 3-2. Stop Mode Behavior

Mode
Peripheral
Stop2 Stop3

CPU Off Standby

RAM Standby Standby
Flash Off Standby
Parallel Port Registers Off Standby
ACMP Off Off
ADC Off Optionally On1
MCG Off Optionally On2
RTC Optionally On3 Optionally On3
SCI Off Standby
SPI Off Standby
TPM Off Standby
Voltage Regulator Off Optionally On4
XOSC Off Optionally On5
I/O Pins States Held States Held
BDM Off6 Optionally On
LVD/LVW Off7 Optionally On
1
Requires the asynchronous ADC clock and LVD to be enabled, else in standby.
2
IRCLKEN and IREFSTEN set in MCGC1, else in standby.
3 Requires the RTC to be enabled, else in standby.
4
Requires the LVD or BDC to be enabled.
5 ERCLKEN and EREFSTEN set in MCGC2 for, else in standby. For high frequency
range (RANGE in MCGC2 set) requires the LVD to also be enabled in stop3.
6
If ENBDM is set when entering stop2, the MCU will actually enter stop3.

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 33
Chapter 3 Modes of Operation

7
If LVDSE is set when entering stop2, the MCU will actually enter stop3.

MC9S08EN32 Series Data Sheet, Rev. 2

34 Freescale Semiconductor
Chapter 4
Memory
4.1 MC9S08EN32 Series Memory Map
On-chip memory in the MC9S08EN32 Series consists of RAM and Flash program memory for nonvolatile
data storage, and I/O and control/status registers. The registers are divided into three groups:
• Direct-page registers (0x0000 through 0x007F)
• High-page registers (0x1800 through 0x18FF)
• Nonvolatile registers (0xFFB0 through 0xFFBF)

0x0000 0x0000
DIRECT PAGE REGISTERS DIRECT PAGE REGISTERS
0x007F 128 BYTES 0x007F 128 BYTES
0x0080 0x0080
RAM RAM
1024 BYTES 512 BYTES
0x027F
0x047F 0x0280
0x0480

UNIMPLEMENTED UNIMPLEMENTED
4992 BYTES 5504 BYTES

0x17FF 0x17FF
0x1800 0x1800
HIGH PAGE REGISTERS HIGH PAGE REGISTERS
256 BYTES 256 BYTES
0x18FF 0x18FF
0x1900 0x1900
UNIMPLEMENTED UNIMPLEMENTED
25,344 BYTES 42,240 BYTES

0x7BFF
0x7C00
0xBDFF
0xBE00
FLASH FLASH
33,792 BYTES 16,896 BYTES

0xFFFF 0xFFFF
MC9S08EN32 MC9S08EN16

Figure 4-1. MC9S08EN32/16 Memory Map

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 35
Chapter 4 Memory

4.2 Reset and Interrupt Vector Assignments

Table 4-1 shows address assignments for reset and interrupt vectors. The vector names shown in this table
are the labels used in the MC9S08EN32 Series equate file provided by Freescale Semiconductor.
Table 4-1. Reset and Interrupt Vectors

Address
Vector Vector Name
(High/Low)

0xFFC0:0xFFC1 Reserved —
0xFFC2:0xFFC3 ACMP1 Vacmp1
0xFFC4:0xFFCB Reserved —
0xFFCC:0xFFCD RTC Vrtc
0xFFCE:0xFFCF Reserved —
0xFFD0:0xFFD1 ADC Conversion Vadc
0xFFD2:0xFFD3 Port A, Port B, Port D Vport
0xFFD4:0xFFD9 Reserved —
0xFFDA:0xFFDB SCI1 Transmit Vsci1tx
0xFFDC:0xFFDD SCI1 Receive Vsci1rx
0xFFDE:0xFFDF SCI1 Error Vsci1err
0xFFE0:0xFFE1 SPI Vspi
0xFFE2:0xFFE7 Reserved —
0xFFE8:0xFFE9 TPM1 Overflow Vtpm1ovf
0xFFEA:0xFFED Reserved —
0xFFEE:0xFFEF TPM1 Channel 3 Vtpm1ch3
0xFFF0:0xFFF1 TPM1 Channel 2 Vtpm1ch2
0xFFF2:0xFFF3 TPM1 Channel 1 Vtpm1ch1
0xFFF4:0xFFF5 TPM1 Channel 0 Vtpm1ch0
0xFFF6:0xFFF7 MCG Loss of lock Vlol
0xFFF8:0xFFF9 Low-Voltage Detect Vlvd
0xFFFA:0xFFFB IRQ Virq
0xFFFC:0xFFFD SWI Vswi
0xFFFE:0xFFFF Reset Vreset

MC9S08EN32 Series Data Sheet, Rev. 2

36 Freescale Semiconductor
 Chapter 4 Memory

4.3 Register Addresses and Bit Assignments

The registers in the MC9S08EN32 Series are divided into these groups:
• Direct-page registers are located in the first 128 locations in the memory map; these are accessible
with efficient direct addressing mode instructions.
• High-page registers are used much less often, so they are located above 0x1800 in the memory
map. This leaves more room in the direct page for more frequently used registers and RAM.
• The nonvolatile register area consists of a block of 16 locations in Flash memory at
0xFFB0–0xFFBF. Nonvolatile register locations include:
— NVPROT and NVOPT are loaded into working registers at reset
— An 8-byte backdoor comparison key that optionally allows a user to gain controlled access to
secure memory
Because the nonvolatile register locations are Flash memory, they must be erased and programmed
like other Flash memory locations.
Direct-page registers can be accessed with efficient direct addressing mode instructions. Bit manipulation
instructions can be used to access any bit in any direct-page register. Table 4-2 is a summary of all
user-accessible direct-page registers and control bits.
The direct page registers in Table 4-2 can use the more efficient direct addressing mode, which requires
only the lower byte of the address. Because of this, the lower byte of the address in column one is shown
in bold text. In Table 4-3 and Table 4-4, the whole address in column one is shown in bold. In Table 4-2,
Table 4-3, and Table 4-4, the register names in column two are shown in bold to set them apart from the
bit names to the right. Cells that are not associated with named bits are shaded. A shaded cell with a 0
indicates this unused bit always reads as a 0. Shaded cells with dashes indicate unused or reserved bit
locations that could read as 1s or 0s.

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 37
 Chapter 4 Memory

Table 4-2. Direct-Page Register Summary (Sheet 1 of 3)

Register
Address Bit 7 6 5 4 3 2 1 Bit 0
Name
0x0000 PTAD PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0
0x0001 PTADD PTADD7 PTADD6 PTADD5 PTADD4 PTADD3 PTADD2 PTADD1 PTADD0
0x0002 PTBD PTBD7 PTBD6 PTBD5 PTBD4 PTBD3 PTBD2 PTBD1 PTBD0
0x0003 PTBDD PTBDD7 PTBDD6 PTBDD5 PTBDD4 PTBDD3 PTBDD2 PTBDD1 PTBDD0
0x0004 INIT11
Reserved — User software must initialize INIT1 and INIT2 to value 0xFF
0x0005 INIT2
0x0006 PTDD PTDD7 PTDD6 PTDD5 PTDD4 PTDD3 PTDD2 PTDD1 PTDD0
0x0007 PTDDD PTDDD7 PTDDD6 PTDDD5 PTDDD4 PTDDD3 PTDDD2 PTDDD1 PTDDD0
0x0008 PTED PTED7 PTED6 PTED5 PTED4 PTED3 PTED2 PTED1 PTED0
0x0009 PTEDD PTEDD7 PTEDD6 PTEDD5 PTEDD4 PTEDD3 PTEDD2 PTEDD1 PTEDD0
0x000A PTFD PTFD7 PTFD6 PTFD5 PTFD4 PTFD3 PTFD2 PTFD1 PTFD0
0x000B PTFDD PTFDD7 PTFDD6 PTFDD5 PTFDD4 PTFDD3 PTFDD2 PTFDD1 PTFDD0
0x000C PTGD 0 0 PTGD5 PTGD4 PTGD3 PTGD2 PTGD1 PTGD0
0x000D PTGDD 0 0 PTGDD5 PTGDD4 PTGDD3 PTGDD2 PTGDD1 PTGDD0
0x000E ACMP1SC ACME ACBGS ACF ACIE ACO ACOPE ACMOD1 ACMOD0
0x000F Reserved — — — — — — — —
0x0010 ADCSC1 COCO AIEN ADCO ADCH
0x0011 ADCSC2 ADACT ADTRG ACFE ACFGT 0 0 — —
0x0012 ADCRH 0 0 0 0 ADR11 ADR10 ADR9 ADR8
0x0013 ADCRL ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
0x0014 ADCCVH 0 0 0 0 ADCV11 ADCV10 ADCV9 ADCV8
0x0015 ADCCVL ADCV7 ADCV6 ADCV5 ADCV4 ADCV3 ADCV2 ADCV1 ADCV0
0x0016 ADCCFG ADLPC ADIV ADLSMP MODE ADICLK
0x0017 APCTL1 ADPC7 ADPC6 ADPC5 ADPC4 ADPC3 ADPC2 ADPC1 ADPC0
0x0018 APCTL2 ADPC15 ADPC14 ADPC13 ADPC12 ADPC11 ADPC10 ADPC9 ADPC8
0x0019 APCTL3 ADPC23 ADPC22 ADPC21 ADPC20 ADPC19 ADPC18 ADPC17 ADPC16
0x001A– — — — — — — — —
Reserved
0x001B — — — — — — — —
0x001C IRQSC 0 IRQPDD IRQEDG IRQPE IRQF IRQACK IRQIE IRQMOD
0x001D– — — — — — — — —
Reserved
0x001F — — — — — — — —
0x0020 TPM1SC TOF TOIE CPWMS CLKSB CLKSA PS2 PS1 PS0
0x0021 TPM1CNTH Bit 15 14 13 12 11 10 9 Bit 8
0x0022 TPM1CNTL Bit 7 6 5 4 3 2 1 Bit 0
0x0023 TPM1MODH Bit 15 14 13 12 11 10 9 Bit 8
0x0024 TPM1MODL Bit 7 6 5 4 3 2 1 Bit 0
0x0025 TPM1C0SC CH0F CH0IE MS0B MS0A ELS0B ELS0A 0 0
0x0026 TPM1C0VH Bit 15 14 13 12 11 10 9 Bit 8
0x0027 TPM1C0VL Bit 7 6 5 4 3 2 1 Bit 0

MC9S08EN32 Series Data Sheet, Rev. 2

38 Freescale Semiconductor
 Chapter 4 Memory

Table 4-2. Direct-Page Register Summary (Sheet 2 of 3)

Register
Address Bit 7 6 5 4 3 2 1 Bit 0
Name
0x0028 TPM1C1SC CH1F CH1IE MS1B MS1A ELS1B ELS1A 0 0
0x0029 TPM1C1VH Bit 15 14 13 12 11 10 9 Bit 8
0x002A TPM1C1VL Bit 7 6 5 4 3 2 1 Bit 0
0x002B TPM1C2SC CH2F CH2IE MS2B MS2A ELS2B ELS2A 0 0
0x002C TPM1C2VH Bit 15 14 13 12 11 10 9 Bit 8
0x002D TPM1C2VL Bit 7 6 5 4 3 2 1 Bit 0
0x002E TPM1C3SC CH3F CH3IE MS3B MS3A ELS3B ELS3A 0 0
0x002F TPM1C3VH Bit 15 14 13 12 11 10 9 Bit 8
0x0030 TPM1C3VL Bit 7 6 5 4 3 2 1 Bit 0
0x0031 TPM1C4SC CH4F CH4IE MS4B MS4A ELS4B ELS4A 0 0
0x0032 TPM1C4VH Bit 15 14 13 12 11 10 9 Bit 8
0x0033 TPM1C4VL Bit 7 6 5 4 3 2 1 Bit 0
0x0034 TPM1C5SC CH5F CH5IE MS5B MS5A ELS5B ELS5A 0 0
0x0035 TPM1C5VH Bit 15 14 13 12 11 10 9 Bit 8
0x0036 TPM1C5VL Bit 7 6 5 4 3 2 1 Bit 0
0x0037 Reserved — — — — — — — —
0x0038 SCI1BDH LBKDIE RXEDGIE 0 SBR12 SBR11 SBR10 SBR9 SBR8
0x0039 SCI1BDL SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0
0x003A SCI1C1 LOOPS SCISWAI RSRC M WAKE ILT PE PT
0x003B SCI1C2 TIE TCIE RIE ILIE TE RE RWU SBK
0x003C SCI1S1 TDRE TC RDRF IDLE OR NF FE PF
0x003D SCI1S2 LBKDIF RXEDGIF 0 RXINV RWUID BRK13 LBKDE RAF
0x003E SCI1C3 R8 T8 TXDIR TXINV ORIE NEIE FEIE PEIE
0x003F SCI1D Bit 7 6 5 4 3 2 1 Bit 0
0x0040– — — — — — — — —
Reserved
0x0047 — — — — — — — —
0x0048 MCGC1 CLKS RDIV IREFS IRCLKEN IREFSTEN
0x0049 MCGC2 BDIV RANGE HGO LP EREFS ERCLKEN EREFSTEN
0x004A MCGTRM TRIM
0x004B MCGSC LOLS LOCK PLLST IREFST CLKST OSCINIT FTRIM
0x004C MCGC3 LOLIE PLLS CME 0 VDIV
0x004D– — — — — — — — —
Reserved
0x004F — — — — — — — —
0x0050 SPIC1 SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE
0x0051 SPIC2 0 0 0 MODFEN BIDIROE 0 SPISWAI SPC0
0x0052 SPIBR 0 SPPR2 SPPR1 SPPR0 0 SPR2 SPR1 SPR0
0x0053 SPIS SPRF 0 SPTEF MODF 0 0 0 0
0x0054 Reserved 0 0 0 0 0 0 0 0
0x0055 SPID Bit 7 6 5 4 3 2 1 Bit 0

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 39
 Chapter 4 Memory

Table 4-2. Direct-Page Register Summary (Sheet 3 of 3)

Register
Address Bit 7 6 5 4 3 2 1 Bit 0
Name
0x0056– — — — — — — — —
Reserved
0x005F — — — — — — — —
0x0060–
Reserved — — — — — — — —
0x006B
0x006C RTCSC RTIF RTCLKS RTIE RTCPS
0x006D RTCCNT RTCCNT
0x006E RTCMOD RTCMOD
0x006F Reserved — — — — — — — —
0x0070– — — — — — — — —
Reserved
0x007F — — — — — — — —
1

High-page registers, shown in Table 4-3, are accessed much less often than other I/O and control registers
so they have been located outside the direct addressable memory space, starting at 0x1800.
Table 4-3. High-Page Register Summary (Sheet 1 of 3)

Address Register Name Bit 7 6 5 4 3 2 1 Bit 0

0x1800 SRS POR PIN COP ILOP ILAD LOCS LVD 0
0x1801 SBDFR 0 0 0 0 0 0 0 BDFR
0x1802 SOPT1 COPT STOPE SCI2PS IICPS 0 0 0
0x1803 SOPT2 COPCLKS COPW 0 ADHTS 0 MCSEL
0x1804 – — — — — — — — —
Reserved
0x1805 — — — — — — — —
0x1806 SDIDH — — — — ID11 ID10 ID9 ID8
0x1807 SDIDL ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
0x1808 Reserved — — — — — — — —
0x1809 SPMSC1 LVWF LVWACK LVWIE LVDRE LVDSE LVDE 0 BGBE
0x180A SPMSC2 0 0 LVDV LVWV PPDF PPDACK 0 PPDC
0x180B– — — — — — — — —
Reserved
0x180F — — — — — — — —
0x1810 DBGCAH Bit 15 14 13 12 11 10 9 Bit 8
0x1811 DBGCAL Bit 7 6 5 4 3 2 1 Bit 0
0x1812 DBGCBH Bit 15 14 13 12 11 10 9 Bit 8
0x1813 DBGCBL Bit 7 6 5 4 3 2 1 Bit 0
0x1814 DBGFH Bit 15 14 13 12 11 10 9 Bit 8
0x1815 DBGFL Bit 7 6 5 4 3 2 1 Bit 0
0x1816 DBGC DBGEN ARM TAG BRKEN RWA RWAEN RWB RWBEN
0x1817 DBGT TRGSEL BEGIN 0 0 TRG3 TRG2 TRG1 TRG0
0x1818 DBGS AF BF ARMF 0 CNT3 CNT2 CNT1 CNT0
0x1819– — — — — — — — —
Reserved
0x181F — — — — — — — —

MC9S08EN32 Series Data Sheet, Rev. 2

40 Freescale Semiconductor
 Chapter 4 Memory

Table 4-3. High-Page Register Summary (Sheet 2 of 3)

Address Register Name Bit 7 6 5 4 3 2 1 Bit 0

0x1820 FCDIV DIVLD PRDIV8 DIV
0x1821 FOPT KEYEN FNORED Reserved 0 0 0 SEC
0x1822 Reserved — — — — — — — —
0x1823 FCNFG 0 — KEYACC Reserved1 0 0 0 1
0x1824 FPROT Reserved FPS
0x1825 FSTAT FCBEF FCCF FPVIOL FACCERR 0 FBLANK 0 0
0x1826 FCMD FCMD
0x1827– — — — — — — — —
Reserved
0x183F — — — — — — — —
0x1840 PTAPE PTAPE7 PTAPE6 PTAPE5 PTAPE4 PTAPE3 PTAPE2 PTAPE1 PTAPE0
0x1841 PTASE PTASE7 PTASE6 PTASE5 PTASE4 PTASE3 PTASE2 PTASE1 PTASE0
0x1842 PTADS PTADS7 PTADS6 PTADS5 PTADS4 PTADS3 PTADS2 PTADS1 PTADS0
0x1843 Reserved — — — — — — — —
0x1844 PTASC 0 0 0 0 PTAIF PTAACK PTAIE PTAMOD
0x1845 PTAPS PTAPS7 PTAPS6 PTAPS5 PTAPS4 PTAPS3 PTAPS2 PTAPS1 PTAPS0
0x1846 PTAES PTAES7 PTAES6 PTAES5 PTAES4 PTAES3 PTAES2 PTAES1 PTAES0
0x1847 Reserved — — — — — — — —
0x1848 PTBPE PTBPE7 PTBPE6 PTBPE5 PTBPE4 PTBPE3 PTBPE2 PTBPE1 PTBPE0
0x1849 PTBSE PTBSE7 PTBSE6 PTBSE5 PTBSE4 PTBSE3 PTBSE2 PTBSE1 PTBSE0
0x184A PTBDS PTBDS7 PTBDS6 PTBDS5 PTBDS4 PTBDS3 PTBDS2 PTBDS1 PTBDS0
0x184B Reserved — — — — — — — —
0x184C PTBSC 0 0 0 0 PTBIF PTBACK PTBIE PTBMOD
0x184D PTBPS PTBPS7 PTBPS6 PTBPS5 PTBPS4 PTBPS3 PTBPS2 PTBPS1 PTBPS0
0x184E PTBES PTBES7 PTBES6 PTBES5 PTBES4 PTBES3 PTBES2 PTBES1 PTBES0
0x184F Reserved — — — — — — — —
0x1850– — — — — — — — —
Reserved
0x1857 — — — — — — — —
0x1858 PTDPE PTDPE7 PTDPE6 PTDPE5 PTDPE4 PTDPE3 PTDPE2 PTDPE1 PTDPE0
0x1859 PTDSE PTDSE7 PTDSE6 PTDSE5 PTDSE4 PTDSE3 PTDSE2 PTDSE1 PTDSE0
0x185A PTDDS PTDDS7 PTDDS6 PTDDS5 PTDDS4 PTDDS3 PTDDS2 PTDDS1 PTDDS0
0x185B Reserved — — — — — — — —
0x185C PTDSC 0 0 0 0 PTDIF PTDACK PTDIE PTDMOD
0x185D PTDPS PTDPS7 PTDPS6 PTDPS5 PTDPS4 PTDPS3 PTDPS2 PTDPS1 PTDPS0
0x185E PTDES PTDES7 PTDES6 PTDES5 PTDES4 PTDES3 PTDES2 PTDES1 PTDES0
0x185F Reserved — — — — — — — —
0x1860 PTEPE PTEPE7 PTEPE6 PTEPE5 PTEPE4 PTEPE3 PTEPE2 PTEPE1 PTEPE0
0x1861 PTESE PTESE7 PTESE6 PTESE5 PTESE4 PTESE3 PTESE2 PTESE1 PTESE0
0x1862 PTEDS PTEDS7 PTEDS6 PTEDS5 PTEDS4 PTEDS3 PTEDS2 PTEDS1 PTEDS0
0x1863– — — — — — — — —
Reserved
0x1867 — — — — — — — —

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 41
Chapter 4 Memory

Table 4-3. High-Page Register Summary (Sheet 3 of 3)

Address Register Name Bit 7 6 5 4 3 2 1 Bit 0

0x1868 PTFPE PTFPE7 PTFPE6 PTFPE5 PTFPE4 PTFPE3 PTFPE2 PTFPE1 PTFPE0
0x1869 PTFSE PTFSE7 PTFSE6 PTFSE5 PTFSE4 PTFSE3 PTFSE2 PTFSE1 PTFSE0
0x186A PTFDS PTFDS7 PTFDS6 PTFDS5 PTFDS4 PTFDS3 PTFDS2 PTFDS1 PTFDS0
0x186B– — — — — — — — —
Reserved
0x186F — — — — — — — —
0x1870 PTGPE 0 0 PTGPE5 PTGPE4 PTGPE3 PTGPE2 PTGPE1 PTGPE0
0x1871 PTGSE 0 0 PTGSE5 PTGSE4 PTGSE3 PTGSE2 PTGSE1 PTGSE0
0x1872 PTGDS 0 0 PTGDS5 PTGDS4 PTGDS3 PTGDS2 PTGDS1 PTGDS0
0x1873– — — — — — — — —
Reserved
0x18FF — — — — — — — —
1
This bit is reserved. User must write a 1 to this bit. Failing to do so may result in unexpected behavior.

Nonvolatile Flash registers, shown in Table 4-4, are located in the Flash memory. These registers include
an 8-byte backdoor key, NVBACKKEY, which can be used to gain access to secure memory resources.
During reset events, the contents of NVPROT and NVOPT in the nonvolatile register area of the Flash
memory are transferred into corresponding FPROT and FOPT working registers in the high-page registers
to control security and block protection options.
Table 4-4. Nonvolatile Register Summary

Address Register Name Bit 7 6 5 4 3 2 1 Bit 0

0xFFAE Reserved for
0 0 0 0 0 0 0 FTRIM
storage of FTRIM
0xFFAF Res. for storage of
TRIM
MCGTRM
0xFFB0– NVBACKKEY
8-Byte Comparison Key
0xFFB7
0xFFB8– Reserved — — — — — — — —
0xFFBC — — — — — — — —
0xFFBD NVPROT Reserved FPS
0xFFBE Reserved — — — — — — — —
0xFFBF NVOPT KEYEN FNORED — 0 0 0 SEC

Provided the key enable (KEYEN) bit is 1, the 8-byte comparison key can be used to temporarily
disengage memory security. This key mechanism can be accessed only through user code running in secure
memory. (A security key cannot be entered directly through background debug commands.) This security
key can be disabled completely by programming the KEYEN bit to 0. If the security key is disabled, the
only way to disengage security is by mass erasing the Flash if needed (normally through the background
debug interface) and verifying that Flash is blank. To avoid returning to secure mode after the next reset,
program the security bits (SEC) to the unsecured state (1:0).

MC9S08EN32 Series Data Sheet, Rev. 2

42 Freescale Semiconductor
 Chapter 4 Memory

4.4 RAM
The MC9S08EN32 Series includes static RAM. The locations in RAM below 0x0100 can be accessed
using the more efficient direct addressing mode, and any single bit in this area can be accessed with the bit
manipulation instructions (BCLR, BSET, BRCLR, and BRSET). Locating the most frequently accessed
program variables in this area of RAM is preferred.
The RAM retains data while the MCU is in low-power wait, stop2, or stop3 mode. At power-on the
contents of RAM are uninitialized. RAM data is unaffected by any reset if the supply voltage does not drop
below the minimum value for RAM retention (VRAM).
For compatibility with M68HC05 MCUs, the HCS08 resets the stack pointer to 0x00FF. In the
MC9S08EN32 Series, it is usually best to reinitialize the stack pointer to the top of the RAM so the direct
page RAM can be used for frequently accessed RAM variables and bit-addressable program variables.
Include the following 2-instruction sequence in your reset initialization routine (where RamLast is equated
to the highest address of the RAM in the Freescale Semiconductor equate file).
LDHX #RamLast+1 ;point one past RAM
TXS ;SP<-(H:X-1)

When security is enabled, the RAM is considered a secure memory resource and is not accessible through
BDM or code executing from non-secure memory. See Section 4.5.9, “Security”, for a detailed description
of the security feature.

4.5 Flash
MC9S08EN32 Series devices include Flash memory intended primarily for program and data storage.
In-circuit programming allows the operating program and data to be loaded into Flash after final assembly
of the application product. It is possible to program the arrays through the single-wire background debug
interface. Because no special voltages are needed for erase and programming operations, in-application
programming is also possible through other software-controlled communication paths. For a more detailed
discussion of in-circuit and in-application programming, refer to the HCS08 Family Reference Manual,
Volume I, Freescale Semiconductor document order number HCS08RMv1.

4.5.1 Features
Features of the Flash include:
• Array size (see Table 1-1 for exact array sizes)
• Flash sector size: 768 bytes
• Single power supply program and erase
• Command interface for fast program and erase operation
• Up to 100,000 program/erase cycles at typical voltage and temperature
• Flexible block protection and vector redirection
• Security feature for Flash and RAM
• Burst programming capability
• Sector erase abort

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 43
Chapter 4 Memory

4.5.2 Program and Erase Times

Before any program or erase command can be accepted, the Flash clock divider register (FCDIV) must be
written to set the internal clock for the Flash module to a frequency (fFCLK) between 150 kHz and 200 kHz
(see Section 4.5.10.1, “Flash Clock Divider Register (FCDIV)”). This register can be written only once,
so normally this write is performed during reset initialization. The user must ensure that FACCERR is not
set before writing to the FCDIV register. One period of the resulting clock (1/fFCLK) is used by the
command processor to time program and erase pulses. An integer number of these timing pulses is used
by the command processor to complete a program or erase command.
Table 4-5 shows program and erase times. The bus clock frequency and FCDIV determine the frequency
of FCLK (fFCLK). The time for one cycle of FCLK is tFCLK = 1/fFCLK. The times are shown as a number
of cycles of FCLK and as an absolute time for the case where tFCLK = 5 μs. Program and erase times
shown include overhead for the command state machine and enabling and disabling of program and erase
voltages.
Table 4-5. Program and Erase Times

Parameter Cycles of FCLK Time if FCLK = 200 kHz

Byte program 9 45 μs
Burst program 4 20 μs1
Sector erase 4000 20 ms
Mass erase 20,000 100 ms
Sector erase abort 4 20 μs1
1
Excluding start/end overhead

4.5.3 Program and Erase Command Execution

The FCDIV register must be initialized after any reset and any error flag is cleared before beginning
command execution. The command execution steps are:
1. Write a data value to an address in the Flash array. The address and data information from this write
is latched into the Flash interface. This write is a required first step in any command sequence. For
erase and blank check commands, the value of the data is not important. For sector erase
commands, the address can be any address in the sector of Flash to be erased. For mass erase and
blank check commands, the address can be any address in the Flash .
NOTE
Before programming a particular byte in the Flash , the sector in which that
particular byte resides must be erased by a mass or sector erase operation.
Reprogramming bits in an already programmed byte without first
performing an erase operation may disturb data stored in the Flash memory.
2. Write the command code for the desired command to FCMD. The six valid commands are blank
check (0x05), byte program (0x20), burst program (0x25), sector erase (0x40), mass erase1 (0x41),
and sector erase abort (0x47). The command code is latched into the command buffer.

1. A mass erase is possible only when the Flash block is fully unprotected.

MC9S08EN32 Series Data Sheet, Rev. 2

44 Freescale Semiconductor
 Chapter 4 Memory

3. Write a 1 to the FCBEF bit in FSTAT to clear FCBEF and launch the command (including its
address and data information).
A partial command sequence can be aborted manually by writing a 0 to FCBEF any time after the
write to the memory array and before writing the 1 that clears FCBEF and launches the complete
command. Aborting a command in this way sets the FACCERR access error flag which must be
cleared before starting a new command.
A strictly monitored procedure must be obeyed or the command will not be accepted. This
minimizes the possibility of any unintended changes to the memory contents. The command
complete flag (FCCF) indicates when a command is complete. The command sequence must be
completed by clearing FCBEF to launch the command. Figure 4-2 is a flowchart for executing all
of the commands except for burst programming and sector erase abort.
4. Wait until the FCCF bit in FSTAT is set. As soon as FCCF= 1, the operation has completed
successfully.

(1) Required only once

WRITE TO FCDIV(1)
after reset.

PROGRAM AND START

ERASE FLOW

0
FACCERR?

CLEAR ERROR

WRITE TO FLASH TO BUFFER

ADDRESS AND DATA

WRITE COMMAND TO FCMD

WRITE 1 TO FCBEF (2)

Wait at least four bus cycles
TO LAUNCH COMMAND before checking FCBEF or FCCF.
AND CLEAR FCBEF (2)

YES
FPVIOL OR
FACCERR? ERROR EXIT

NO

0
FCCF?
1
DONE

Figure 4-2. Program and Erase Flowchart

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 45
Chapter 4 Memory

4.5.4 Burst Program Execution

The burst program command is used to program sequential bytes of data in less time than would be
required using the standard program command. This is possible because the high voltage to the Flash array
does not need to be disabled between program operations. Ordinarily, when a program or erase command
is issued, an internal charge pump associated with the Flash memory must be enabled to supply high
voltage to the array. Upon completion of the command, the charge pump is turned off. When a burst
program command is issued, the charge pump is enabled and remains enabled after completion of the burst
program operation if these two conditions are met:
• The next burst program command sequence has begun before the FCCF bit is set.
• The next sequential address selects a byte on the same burst block as the current byte being
programmed. A burst block in this Flash memory consists of 32 bytes. A new burst block begins
at each 32-byte address boundary.
The first byte of a series of sequential bytes being programmed in burst mode will take the same amount
of time to program as a byte programmed in standard mode. Subsequent bytes will program in the burst
program time provided that the conditions above are met. If the next sequential address is the beginning of
a new row, the program time for that byte will be the standard time instead of the burst time. This is because
the high voltage to the array must be disabled and then enabled again. If a new burst command has not been
queued before the current command completes, then the charge pump will be disabled and high voltage
removed from the array.
A flowchart to execute the burst program operation is shown in Figure 4-3.

MC9S08EN32 Series Data Sheet, Rev. 2

46 Freescale Semiconductor
 Chapter 4 Memory

(1) Required only once

WRITE TO FCDIV(1)
after reset.

BURST PROGRAM START

FLOW

0
FACCERR?
1

CLEAR ERROR

0
FCBEF?
1
WRITE TO Flash
TO BUFFER ADDRESS AND DATA

WRITE COMMAND TO FCMD

WRITE 1 TO FCBEF (2)

Wait at least four bus cycles
TO LAUNCH COMMAND before checking FCBEF or FCCF.
AND CLEAR FCBEF (2)

YES
FPVIOL OR
FACCERR? ERROR EXIT

NO
YES
NEW BURST COMMAND?
NO

0
FCCF?
1
DONE

Figure 4-3. Burst Program Flowchart

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 47
Chapter 4 Memory

4.5.5 Sector Erase Abort

The sector erase abort operation will terminate the active sector erase operation so that other sectors are
available for read and program operations without waiting for the sector erase operation to complete.
The sector erase abort command write sequence is as follows:
1. Write to any Flash address to start the command write sequence for the sector erase abort
command. The address and data written are ignored.
2. Write the sector erase abort command, 0x47, to the FCMD register.
3. Clear the FCBEF flag in the FSTAT register by writing a 1 to FCBEF to launch the sector erase
abort command.
If the sector erase abort command is launched resulting in the early termination of an active sector erase
operation, the FACCERR flag will set once the operation completes as indicated by the FCCF flag being
set. The FACCERR flag sets to inform the user that the Flash sector may not be fully erased and a new
sector erase command must be launched before programming any location in that specific sector.
If the sector erase abort command is launched but the active sector erase operation completes normally,
the FACCERR flag will not set upon completion of the operation as indicated by the FCCF flag being set.
Therefore, if the FACCERR flag is not set after the sector erase abort command has completed, a sector
being erased when the abort command was launched will be fully erased.
A flowchart to execute the sector erase abort operation is shown in Figure 4-4.

SECTOR ERASE
START
ABORT FLOW

1
FCCF?

0
WRITE TO Flash
TO BUFFER ADDRESS AND DATA

WRITE 0x47 TO FCMD

WRITE 1 TO FCBEF (2) Wait at least four bus cycles

TO LAUNCH COMMAND before checking FCBEF or FCCF.
AND CLEAR FCBEF (2)

0
FCCF?
1
0
SECTOR ERASE COMPLETED FACCERR?
1
SECTOR ERASE ABORTED

Figure 4-4. Sector Erase Abort Flowchart

MC9S08EN32 Series Data Sheet, Rev. 2

48 Freescale Semiconductor
 Chapter 4 Memory

NOTE
The FCBEF flag will not set after launching the sector erase abort command.
If an attempt is made to start a new command write sequence with a sector
erase abort operation active, the FACCERR flag in the FSTAT register will
be set. A new command write sequence may be started after clearing the
ACCERR flag, if set.
NOTE
The sector erase abort command should be used sparingly since a sector
erase operation that is aborted counts as a complete program/erase cycle.

4.5.6 Access Errors

An access error occurs whenever the command execution protocol is violated.
Any of the following specific actions will cause the access error flag (FACCERR) in FSTAT to be set.
FACCERR must be cleared by writing a 1 to FACCERR in FSTAT before any command can be processed.
• Writing to a Flash address before the internal Flash clock frequency has been set by writing to the
FCDIV register.
• Writing to a Flash address while FCBEF is not set. (A new command cannot be started until the
command buffer is empty.)
• Writing a second time to a Flash address before launching the previous command. (There is only
one write to Flash for every command.)
• Writing a second time to FCMD before launching the previous command. (There is only one write
to FCMD for every command.)
• Writing to any Flash control register other than FCMD after writing to a Flash address.
• Writing any command code other than the six allowed codes (0x05, 0x20, 0x25, 0x40, 0x41, or
0x47) to FCMD.
• Writing any Flash control register other than to write to FSTAT (to clear FCBEF and launch the
command) after writing the command to FCMD.
• The MCU enters stop mode while a program or erase command is in progress. (The command is
aborted.)
• Writing the byte program, burst program, sector erase or sector erase abort command code (0x20,
0x25, 0x40, or 0x47) with a background debug command while the MCU is secured. (The
background debug controller can do blank check and mass erase commands only when the MCU
is secure.)
• Writing 0 to FCBEF to cancel a partial command.

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 49
Chapter 4 Memory

4.5.7 Block Protection

The block protection feature prevents the protected region of Flash from program or erase changes. Block
protection is controlled through the Flash protection register (FPROT). The FPS bits determine the
protected region of Flash. See Section 4.5.10.4, “Flash Protection Register (FPROT and NVPROT).”
After exit from reset, FPROT is loaded with the contents of the NVPROT location, which is in the
nonvolatile register block of the Flash memory. Any FPROT write that attempts to decrease the size of the
protected region will be ignored. Because NVPROT is within the last sector of Flash, if any amount of
memory is protected, NVPROT is itself protected and cannot be unprotected (intentionally or
unintentionally) by the application software. FPROT can be written through background debug
commands, which provides a way to erase and reprogram protected Flash memory.
One use for block protection is to block protect an area of Flash memory for a bootloader program. this
bootloader program can call a routine outside of Flash that can be used to sector erase the rest of the Flash
memory and reprogram it. The bootloader is protected even if MCU power is lost during an erase and
reprogram operation.

4.5.8 Vector Redirection

While any Flash is block protected, the reset and interrupt vectors will be protected. Vector redirection
allows users to modify interrupt vector information without unprotecting bootloader and reset vector
space. Vector redirection is enabled by programming the FNORED bit in the NVOPT register located at
address 0xFFBF to 0. For redirection to occur, at least some portion of the Flash memory must be block
protected by programming the NVPROT register located at address 0xFFBD. All interrupt vectors
(memory locations 0xFFC0–0xFFFD) are redirected, though the reset vector (0xFFFE:0xFFFF) is not.
For example, if 1536 bytes of Flash are protected, the protected address region is from 0xFA00 through
0xFFFF. The interrupt vectors (0xFFC0–0xFFFD) are redirected to the locations 0xF9C0–0xF9FD. If
vector redirection is enabled and an interrupt occurs, the values in the locations 0xF9E0:0xF9E1 are used
for the vector instead of the values in the locations 0xFFE0:0xFFE1. This allows the user to reprogram the
unprotected portion of the Flash with new program code including new interrupt vector values while
leaving the protected area, which includes the default vector locations, unchanged.

4.5.9 Security
The MC9S08EN32 Series includes circuitry to prevent unauthorized access to the contents of Flash and
RAM memory. When security is engaged, Flash and RAM are considered secure resources. Direct-page
registers, high-page registers, and the background debug controller are considered unsecured resources.
Programs executing within secure memory have normal access to any MCU memory locations and
resources. Attempts to access a secure memory location with a program executing from an unsecured
memory space or through the background debug interface are blocked (writes are ignored and reads return
all 0s).
Security is engaged or disengaged based on the state of two register bits (SEC[1:0]) in the FOPT register.
During reset, the contents of the nonvolatile location NVOPT are copied from Flash into the working
FOPT register in high-page register space. A user engages security by programming the NVOPT location,
which can be performed at the same time the Flash memory is programmed. The 1:0 state disengages

MC9S08EN32 Series Data Sheet, Rev. 2

50 Freescale Semiconductor
 Chapter 4 Memory

security; the other three combinations engage security. Notice the erased state (1:1) makes the MCU
secure. During development, whenever the Flash is erased, it is good practice to immediately program the
SEC0 bit to 0 in NVOPT so SEC = 1:0. This would allow the MCU to remain unsecured after a subsequent
reset.
The on-chip debug module cannot be enabled while the MCU is secure. The separate background debug
controller can be used for background memory access commands, but the MCU cannot enter active
background mode except by holding BKGD low at the rising edge of reset.
A user can choose to allow or disallow a security unlocking mechanism through an 8-byte backdoor
security key. If the nonvolatile KEYEN bit in NVOPT/FOPT is 0, the backdoor key is disabled and there
is no way to disengage security without completely erasing all Flash locations. If KEYEN is 1, a secure
user program can temporarily disengage security by:
1. Writing 1 to KEYACC in the FCNFG register. This makes the Flash module interpret writes to the
backdoor comparison key locations (NVBACKKEY through NVBACKKEY+7) as values to be
compared against the key rather than as the first step in a Flash program or erase command.
2. Writing the user-entered key values to the NVBACKKEY through NVBACKKEY+7 locations.
These writes must be performed in order starting with the value for NVBACKKEY and ending
with NVBACKKEY+7. STHX must not be used for these writes because these writes cannot be
performed on adjacent bus cycles. User software normally would get the key codes from outside
the MCU system through a communication interface such as a serial I/O.
3. Writing 0 to KEYACC in the FCNFG register. If the 8-byte key that was written matches the key
stored in the Flash locations, SEC bits are automatically changed to 1:0 and security will be
disengaged until the next reset.
The security key can be written only from secure memory (either RAM or Flash), so it cannot be entered
through background commands without the cooperation of a secure user program.
The backdoor comparison key (NVBACKKEY through NVBACKKEY+7) is located in Flash memory
locations in the nonvolatile register space so users can program these locations exactly as they would
program any other Flash memory location. The nonvolatile registers are in the same 768-byte block of
Flash as the reset and interrupt vectors, so block protecting that space also block protects the backdoor
comparison key. Block protects cannot be changed from user application programs, so if the vector space
is block protected, the backdoor security key mechanism cannot permanently change the block protect,
security settings, or the backdoor key.
Security can always be disengaged through the background debug interface by taking these steps:
1. Disable any block protections by writing FPROT. FPROT can be written only with background
debug commands, not from application software.
2. Mass erase Flash if necessary.
3. Blank check Flash. Provided Flash is completely erased, security is disengaged until the next reset.
To avoid returning to secure mode after the next reset, program NVOPT so SEC = 1:0.

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 51
Chapter 4 Memory

4.5.10 Flash Registers and Control Bits

The Flash module has seven 8-bit registers in the high-page register space and three locations in the
nonvolatile register space in Flash memory. Two of those locations are copied into two corresponding
high-page control registers at reset. There is also an 8-byte comparison key in Flash memory. Refer to
Table 4-3 and Table 4-4 for the absolute address assignments for all Flash registers. This section refers to
registers and control bits only by their names. A Freescale Semiconductor-provided equate or header file
normally is used to translate these names into the appropriate absolute addresses.

4.5.10.1 Flash Clock Divider Register (FCDIV)

Bit 7 of this register is a read-only flag. Bits 6:0 may be read at any time but can be written only one time.
Before any erase or programming operations are possible, write to this register to set the frequency of the
clock for the nonvolatile memory system within acceptable limits.

7 6 5 4 3 2 1 0

R DIVLD
PRDIV8 DIV
W

Reset 0 0 0 0 0 0 0 0

= Unimplemented or Reserved

Figure 4-5. Flash Clock Divider Register (FCDIV)

Table 4-6. FCDIV Register Field Descriptions

Field Description

7 Divisor Loaded Status Flag — When set, this read-only status flag indicates that the FCDIV register has been
DIVLD written since reset. Reset clears this bit and the first write to this register causes this bit to become set regardless
of the data written.
0 FCDIV has not been written since reset; erase and program operations disabled for Flash.
1 FCDIV has been written since reset; erase and program operations enabled for Flash.

6 Prescale (Divide) Flash Clock by 8 (This bit is write once.)

PRDIV8 0 Clock input to the Flash clock divider is the bus rate clock.
1 Clock input to the Flash clock divider is the bus rate clock divided by 8.

5:0 Divisor for Flash Clock Divider — These bits are write once. The Flash clock divider divides the bus rate clock
DIV (or the bus rate clock divided by 8 if PRDIV8 = 1) by the value in the 6-bit DIV field plus one. The resulting
frequency of the internal Flash clock must fall within the range of 200 kHz to 150 kHz for proper Flash operations.
Program/Erase timing pulses are one cycle of this internal Flash clock which corresponds to a range of 5 μs to
6.7 μs. The automated programming logic uses an integer number of these pulses to complete an erase or
program operation. See Equation 4-1 and Equation 4-2.

if PRDIV8 = 0 — fFCLK = fBus ÷ (DIV + 1) Eqn. 4-1

if PRDIV8 = 1 — fFCLK = fBus ÷ (8 × (DIV + 1)) Eqn. 4-2

Table 4-7 shows the appropriate values for PRDIV8 and DIV for selected bus frequencies.

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52 Freescale Semiconductor
 Chapter 4 Memory

Table 4-7. Flash Clock Divider Settings

PRDIV8 DIV Program/Erase Timing Pulse

fBus fFCLK
(Binary) (Decimal) (5 μs Min, 6.7 μs Max)

20 MHz 1 12 192.3 kHz 5.2 μs

10 MHz 0 49 200 kHz 5 μs
8 MHz 0 39 200 kHz 5 μs
4 MHz 0 19 200 kHz 5 μs
2 MHz 0 9 200 kHz 5 μs
1 MHz 0 4 200 kHz 5 μs
200 kHz 0 0 200 kHz 5 μs
150 kHz 0 0 150 kHz 6.7 μs

4.5.10.2 Flash Options Register (FOPT and NVOPT)

During reset, the contents of the nonvolatile location NVOPT are copied from Flash into FOPT. To change
the value in this register, erase and reprogram the NVOPT location in Flash memory as usual and then issue
a new MCU reset.

7 6 5 4 3 2 1 0

R KEYEN FNORED 0 0 0 SEC

Reserved
W

Reset F F F 0 0 0 F F

= Unimplemented or Reserved F = loaded from nonvolatile location NVOPT during reset

Figure 4-6. Flash Options Register (FOPT)

Table 4-8. FOPT Register Field Descriptions

Field Description

7 Backdoor Key Mechanism Enable — When this bit is 0, the backdoor key mechanism cannot be used to
KEYEN disengage security. The backdoor key mechanism is accessible only from user (secured) firmware. BDM
commands cannot be used to write key comparison values that would unlock the backdoor key. For more detailed
information about the backdoor key mechanism, refer to Section 4.5.9, “Security.”
0 No backdoor key access allowed.
1 If user firmware writes an 8-byte value that matches the nonvolatile backdoor key (NVBACKKEY through
NVBACKKEY+7 in that order), security is temporarily disengaged until the next MCU reset.

6 Vector Redirection Disable — When this bit is 1, then vector redirection is disabled.
FNORED 0 Vector redirection enabled.
1 Vector redirection disabled.

1:0 Security State Code — This 2-bit field determines the security state of the MCU as shown in Table 4-9. When
SEC the MCU is secure, the contents of RAM and Flash memory cannot be accessed by instructions from any
unsecured source including the background debug interface. SEC changes to 1:0 after successful backdoor key
entry or a successful blank check of Flash. For more detailed information about security, refer to Section 4.5.9,
“Security.”

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Freescale Semiconductor 53
Chapter 4 Memory

Table 4-9. Security States1

SEC[1:0] Description

0:0 secure
0:1 secure
1:0 unsecured
1:1 secure
1
SEC changes to 1:0 after successful backdoor key entry
or a successful blank check of Flash.

4.5.10.3 Flash Configuration Register (FCNFG)

7 6 5 4 3 2 1 0

R 0 0 0 0 1
Reserved KEYACC Reserved1
W
Reset 0 0 0 1 0 0 0 1

= Unimplemented or Reserved

Figure 4-7. Flash Configuration Register (FCNFG)

1 User must write a 1 to this bit. Failing to do so may result in unexpected behavior.

Table 4-10. FCNFG Register Field Descriptions

Field Description

5 Enable Writing of Access Key — This bit enables writing of the backdoor comparison key. For more detailed
KEYACC information about the backdoor key mechanism, refer to Section 4.5.9, “Security.”
0 Writes to 0xFFB0–0xFFB7 are interpreted as the start of a Flash programming or erase command.
1 Writes to NVBACKKEY (0xFFB0–0xFFB7) are interpreted as comparison key writes.

4.5.10.4 Flash Protection Register (FPROT and NVPROT)

The FPROT register defines which Flash and EEPROM sectors are protected against program and erase
operations.
During the reset sequence, the FPROT register is loaded from the nonvolatile location NVPROT. To
change the protection that will be loaded during the reset sequence, the sector containing NVPROT must
be unprotected and erased, then NVPROT can be reprogrammed.
FPROT bits are readable at any time and writable as long as the size of the protected region is being
increased. Any write to FPROT that attempts to decrease the size of the protected memory will be ignored.
Trying to alter data in any protected area will result in a protection violation error and the FPVIOL flag
will be set in the FSTAT register. Mass erase is not possible if any one of the sectors is protected.

MC9S08EN32 Series Data Sheet, Rev. 2

54 Freescale Semiconductor
 Chapter 4 Memory

7 6 5 4 3 2 1 0

R
Reserved Reserved FPS1
W

Reset This register is loaded from nonvolatile location NVPROT during reset.

Figure 4-8. Flash Protection Register (FPROT)

Table 4-11. FPROT Register Field Descriptions

Field Description

5:0 Flash Protect Select Bits — This 6-bit field determines the protected Flash locations that cannot be erased or
FPS programmed. SeeTable 4-12.

Table 4-12. Flash Block Protection

FPS Address Area Protected Memory Size Protected (bytes) Number of Sectors Protected

0x3F N/A 0 0

0x3E 0xFA00–0xFFFF 1.5K 2

0x3D 0xF400–0xFFFF 3K 4

0x3C 0xEE00–0xFFFF 4.5K 6

0x3B 0xE800–0xFFFF 6K 8

... ... ... ...

0x37 0xD000–0xFFFF 12K 16

0x36 0xCA00–0xFFFF 13.5K 18

0x35 0xC400–0xFFFF 15K 20

0x34 0xBE00–0xFFFF 16.5K 22

... ... ... ...

0x2C 0x8E00–0xFFFF 28.5K 38

0x2B 0x8800–0xFFFF 30K 40

0x2A 0x8200–0xFFFF 31.5K 42

0x29–0x00 0x7C00–0xFFFF 33K 44

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 55
Chapter 4 Memory

4.5.10.5 Flash Status Register (FSTAT)

7 6 5 4 3 2 1 0

R FCCF 0 FBLANK 0 0
FCBEF FPVIOL FACCERR
W

Reset 1 1 0 0 0 0 0 0

= Unimplemented or Reserved

Figure 4-9. Flash Status Register (FSTAT)

Table 4-13. FSTAT Register Field Descriptions

Field Description

7 Command Buffer Empty Flag — The FCBEF bit is used to launch commands. It also indicates that the
FCBEF command buffer is empty so that a new command sequence can be executed when performing burst
programming. The FCBEF bit is cleared by writing a 1 to it or when a burst program command is transferred to
the array for programming. Only burst program commands can be buffered.
0 Command buffer is full (not ready for additional commands).
1 A new burst program command can be written to the command buffer.

6 Command Complete Flag — FCCF is set automatically when the command buffer is empty and no command
FCCF is being processed. FCCF is cleared automatically when a new command is started (by writing 1 to FCBEF to
register a command). Writing to FCCF has no meaning or effect.
0 Command in progress
1 All commands complete

5 Protection Violation Flag — FPVIOL is set automatically when a command that attempts to erase or program
FPVIOL a location in a protected block is launched (the erroneous command is ignored). FPVIOL is cleared by writing a
1 to FPVIOL.
0 No protection violation.
1 An attempt was made to erase or program a protected location.

4 Access Error Flag — FACCERR is set automatically when the proper command sequence is not obeyed exactly
FACCERR (the erroneous command is ignored), if a program or erase operation is attempted before the FCDIV register has
been initialized, or if the MCU enters stop while a command was in progress. For a more detailed discussion of
the exact actions that are considered access errors, see Section 4.5.6, “Access Errors.” FACCERR is cleared by
writing a 1 to FACCERR. Writing a 0 to FACCERR has no meaning or effect.
0 No access error.
1 An access error has occurred.

2 Verified as All Blank (erased) Flag — FBLANK is set automatically at the conclusion of a blank check command
FBLANK if the entire Flash array was verified to be erased. FBLANK is cleared by clearing FCBEF to write a new valid
command. Writing to FBLANK has no meaning or effect.
0 After a blank check command is completed and FCCF = 1, FBLANK = 0 indicates the Flash array is not
completely erased.
1 After a blank check command is completed and FCCF = 1, FBLANK = 1 indicates the Flash array is
completely erased (all 0xFFFF).

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56 Freescale Semiconductor
 Chapter 4 Memory

4.5.10.6 Flash Command Register (FCMD)

Only six command codes are recognized in normal user modes, as shown in Table 4-14. All other
command codes are illegal and generate an access error. Refer to Section 4.5.3, “Program and Erase
Command Execution,” for a detailed discussion of Flash programming and erase operations.
7 6 5 4 3 2 1 0

R 0 0 0 0 0 0 0 0

W FCMD

Reset 0 0 0 0 0 0 0 0

Figure 4-10. Flash Command Register (FCMD)

Table 4-14. Flash Commands

Command FCMD Equate File Label

Blank check 0x05 mBlank

Byte program 0x20 mByteProg

Burst program 0x25 mBurstProg

Sector erase 0x40 mSectorErase

Mass erase 0x41 mMassErase

Sector erase abort 0x47 mEraseAbort

It is not necessary to perform a blank check command after a mass erase operation. Only blank check is
required as part of the security unlocking mechanism.

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Chapter 4 Memory

MC9S08EN32 Series Data Sheet, Rev. 2

58 Freescale Semiconductor
Chapter 5
Resets, Interrupts, and General System Control
5.1 Introduction
This section discusses basic reset and interrupt mechanisms and their various sources in the MC9S08EN32
Series. Some interrupt sources from peripheral modules are discussed in greater detail within other
sections of this data sheet. This section gathers basic information about all reset and interrupt sources in
one place for easy reference. A few reset and interrupt sources, including the computer operating properly
(COP) watchdog, are not part of on-chip peripheral systems with their own chapters.

5.2 Features
Reset and interrupt features include:
• Multiple sources of reset for flexible system configuration and reliable operation
• Reset status register (SRS) to indicate source of most recent reset
• Separate interrupt vector for each module (reduces polling overhead); see Table 5-1

5.3 MCU Reset

Resetting the MCU provides a way to start processing from a known set of initial conditions. During reset,
most control and status registers are forced to initial values and the program counter is loaded from the
reset vector (0xFFFE:0xFFFF). On-chip peripheral modules are disabled and I/O pins are initially
configured as general-purpose high-impedance inputs with pull-up devices disabled. The I bit in the
condition code register (CCR) is set to block maskable interrupts so the user program has a chance to
initialize the stack pointer (SP) and system control settings. (See the CPU chapter for information on the
Interrupt (I) bit.) SP is forced to 0x00FF at reset.
The MC9S08EN32 Series has eight sources for reset:
• Power-on reset (POR)
• External pin reset (PIN)
• Computer operating properly (COP) timer
• Illegal opcode detect (ILOP)
• Illegal address detect (ILAD)
• Low-voltage detect (LVD)
• Loss of clock (LOC)
• Background debug forced reset (BDFR)
Each of these sources, with the exception of the background debug forced reset, has an associated bit in
the system reset status register (SRS).

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 59
Chapter 5 Resets, Interrupts, and General System Control

5.4 Computer Operating Properly (COP) Watchdog

The COP watchdog is intended to force a system reset when the application software fails to execute as
expected. To prevent a system reset from the COP timer (when it is enabled), application software must
reset the COP counter periodically. If the application program gets lost and fails to reset the COP counter
before it times out, a system reset is generated to force the system back to a known starting point.
After any reset, the COP watchdog is enabled (see Section 5.8.4, “System Options Register 1 (SOPT1),”
for additional information). If the COP watchdog is not used in an application, it can be disabled by
clearing COPT bits in SOPT1.
The COP counter is reset by writing 0x55 and 0xAA (in this order) to the address of SRS during the
selected timeout period. Writes do not affect the data in the read-only SRS. As soon as the write sequence
is done, the COP timeout period is restarted. If the program fails to do this during the time-out period, the
MCU will reset. Also, if any value other than 0x55 or 0xAA is written to SRS, the MCU is immediately
reset.
The COPCLKS bit in SOPT2 (see Section 5.8.5, “System Options Register 2 (SOPT2),” for additional
information) selects the clock source used for the COP timer. The clock source options are either the bus
clock or an internal 1-kHz clock source. With each clock source, there are three associated time-outs
controlled by the COPT bits in SOPT1. Table 5-6 summaries the control functions of the COPCLKS and
COPT bits. The COP watchdog defaults to operation from the 1-kHz clock source and the longest time-out
(210 cycles).
When the bus clock source is selected, windowed COP operation is available by setting COPW in the
SOPT2 register. In this mode, writes to the SRS register to clear the COP timer must occur in the last 25%
of the selected timeout period. A premature write immediately resets the MCU. When the 1-kHz clock
source is selected, windowed COP operation is not available.
The COP counter is initialized by the first writes to the SOPT1 and SOPT2 registers and after any system
reset. Subsequent writes to SOPT1 and SOPT2 have no effect on COP operation. Even if the application
will use the reset default settings of COPT, COPCLKS, and COPW bits, the user should write to the
write-once SOPT1 and SOPT2 registers during reset initialization to lock in the settings. This will prevent
accidental changes if the application program gets lost.
The write to SRS that services (clears) the COP counter should not be placed in an interrupt service routine
(ISR) because the ISR could continue to be executed periodically even if the main application program
fails.
If the bus clock source is selected, the COP counter does not increment while the MCU is in background
debug mode or while the system is in stop mode. The COP counter resumes when the MCU exits
background debug mode or stop mode.
If the 1-kHz clock source is selected, the COP counter is re-initialized to zero upon entry to either
background debug mode or stop mode and begins from zero upon exit from background debug mode or
stop mode.

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 Chapter 5 Resets, Interrupts, and General System Control

5.5 Interrupts
Interrupts provide a way to save the current CPU status and registers, execute an interrupt service routine
(ISR), and then restore the CPU status so processing resumes where it left off before the interrupt. Other
than the software interrupt (SWI), which is a program instruction, interrupts are caused by hardware events
such as an edge on the IRQ pin or a timer-overflow event. The debug module can also generate an SWI
under certain circumstances.
If an event occurs in an enabled interrupt source, an associated read-only status flag will become set. The
CPU will not respond unless the local interrupt enable is a 1 to enable the interrupt and the I bit in the CCR
is 0 to allow interrupts. The global interrupt mask (I bit) in the CCR is initially set after reset which
prevents all maskable interrupt sources. The user program initializes the stack pointer and performs other
system setup before clearing the I bit to allow the CPU to respond to interrupts.
When the CPU receives a qualified interrupt request, it completes the current instruction before responding
to the interrupt. The interrupt sequence obeys the same cycle-by-cycle sequence as the SWI instruction and
consists of:
• Saving the CPU registers on the stack
• Setting the I bit in the CCR to mask further interrupts
• Fetching the interrupt vector for the highest-priority interrupt that is currently pending
• Filling the instruction queue with the first three bytes of program information starting from the
address fetched from the interrupt vector locations
While the CPU is responding to the interrupt, the I bit is automatically set to avoid the possibility of another
interrupt interrupting the ISR itself (this is called nesting of interrupts). Normally, the I bit is restored to 0
when the CCR is restored from the value stacked on entry to the ISR. In rare cases, the I bit can be cleared
inside an ISR (after clearing the status flag that generated the interrupt) so that other interrupts can be
serviced without waiting for the first service routine to finish. This practice is not recommended for anyone
other than the most experienced programmers because it can lead to subtle program errors that are difficult
to debug.
The interrupt service routine ends with a return-from-interrupt (RTI) instruction which restores the CCR,
A, X, and PC registers to their pre-interrupt values by reading the previously saved information from the
stack.
NOTE
For compatibility with M68HC08 devices, the H register is not
automatically saved and restored. It is good programming practice to push
H onto the stack at the start of the interrupt service routine (ISR) and restore
it immediately before the RTI that is used to return from the ISR.
If more than one interrupt is pending when the I bit is cleared, the highest priority source is serviced first
(see Table 5-1).

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Chapter 5 Resets, Interrupts, and General System Control

5.5.1 Interrupt Stack Frame

Figure 5-1 shows the contents and organization of a stack frame. Before the interrupt, the stack pointer
(SP) points at the next available byte location on the stack. The current values of CPU registers are stored
on the stack starting with the low-order byte of the program counter (PCL) and ending with the CCR. After
stacking, the SP points at the next available location on the stack which is the address that is one less than
the address where the CCR was saved. The PC value that is stacked is the address of the instruction in the
main program that would have executed next if the interrupt had not occurred.
UNSTACKING TOWARD LOWER ADDRESSES
ORDER

7 0
SP AFTER
INTERRUPT STACKING
5 1 CONDITION CODE REGISTER
4 2 ACCUMULATOR
3 3 INDEX REGISTER (LOW BYTE X)*
2 4 PROGRAM COUNTER HIGH
SP BEFORE
1 5 PROGRAM COUNTER LOW
THE INTERRUPT

STACKING TOWARD HIGHER ADDRESSES

ORDER
* High byte (H) of index register is not automatically stacked.

Figure 5-1. Interrupt Stack Frame

When an RTI instruction is executed, these values are recovered from the stack in reverse order. As part of
the RTI sequence, the CPU fills the instruction pipeline by reading three bytes of program information,
starting from the PC address recovered from the stack.
The status flag corresponding to the interrupt source must be acknowledged (cleared) before returning
from the ISR. Typically, the flag is cleared at the beginning of the ISR so that if another interrupt is
generated by this same source, it will be registered so it can be serviced after completion of the current ISR.

5.5.2 External Interrupt Request (IRQ) Pin

External interrupts are managed by the IRQ status and control register, IRQSC. When the IRQ function is
enabled, synchronous logic monitors the pin for edge-only or edge-and-level events. When the MCU is in
stop mode and system clocks are shut down, a separate asynchronous path is used so the IRQ (if enabled)
can wake the MCU.

5.5.2.1 Pin Configuration Options

The IRQ pin enable (IRQPE) control bit in IRQSC must be 1 in order for the IRQ pin to act as the interrupt
request (IRQ) input. As an IRQ input, the user can choose the polarity of edges or levels detected
(IRQEDG), whether the pin detects edges-only or edges and levels (IRQMOD), and whether an event
causes an interrupt or only sets the IRQF flag which can be polled by software.

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 Chapter 5 Resets, Interrupts, and General System Control

The IRQ pin, when enabled, defaults to use an internal pull device (IRQPDD = 0), the device is a pull-up
or pull-down depending on the polarity chosen. If the user desires to use an external pull-up or pull-down,
the IRQPDD can be written to a 1 to turn off the internal device.
BIH and BIL instructions may be used to detect the level on the IRQ pin when the pin is configured to act
as the IRQ input.
NOTE
This pin does not contain a clamp diode to VDD and should not be driven
above VDD. The voltage measured on the internally pulled up IRQ pin may
be as low as VDD – 0.7 V. The internal gates connected to this pin are pulled
all the way to VDD.

5.5.2.2 Edge and Level Sensitivity

The IRQMOD control bit reconfigures the detection logic so it detects edge events and pin levels. In the
edge and level detection mode, the IRQF status flag becomes set when an edge is detected (when the IRQ
pin changes from the deasserted to the asserted level), but the flag is continuously set (and cannot be
cleared) as long as the IRQ pin remains at the asserted level.

5.5.3 Interrupt Vectors, Sources, and Local Masks

Table 5-1 provides a summary of all interrupt sources. Higher-priority sources are located toward the
bottom of the table. The high-order byte of the address for the interrupt service routine is located at the
first address in the vector address column, and the low-order byte of the address for the interrupt service
routine is located at the next higher address.
When an interrupt condition occurs, an associated flag bit becomes set. If the associated local interrupt
enable is 1, an interrupt request is sent to the CPU. Within the CPU, if the global interrupt mask (I bit in
the CCR) is 0, the CPU will finish the current instruction; stack the PCL, PCH, X, A, and CCR CPU
registers; set the I bit; and then fetch the interrupt vector for the highest priority pending interrupt.
Processing then continues in the interrupt service routine.

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Chapter 5 Resets, Interrupts, and General System Control

Table 5-1. Vector Summary1

Vector Address Vector
Module Source Enable Description
No. (High/Low) Name
31 0xFFC0/0xFFC1 (Reserved)
30 0xFFC2/0xFFC3 Vacmp1 ACMP1 ACF ACIE Analog comparator
29–26 0xFFC4/0xFFC5– (Reserved)
0xFFCA/0xFFCB
25 0xFFCC/0xFFCD Vrtc RTC RTIF RTIE Real-time interrupt
24 0xFFCE/0xFFCF (Reserved)
23 0xFFD0/0xFFD1 Vadc ADC COCO AIEN ADC
22 0xFFD2/0xFFD3 Vport Port A,B,D PTAIF, PTBIF, PTAIE, PTBIE, PTDIE Port Pins
PTDIF
21–19 0xFFD4/0xFFD5– (Reserved)
0xFFD8/0xFFD9
18 0xFFDA/0xFFDB Vsci1tx SCI1 TDRE, TC TIE, TCIE SCI1 transmit
17 0xFFDC/0xFFDD Vsci1rx SCI1 IDLE, LBKDIF, ILIE, LBKDIE, RIE, SCI1 receive
RDRF, RXEDGIF RXEDGIE
16 0xFFDE/0xFFDF Vsci1err SCI1 OR, NF, ORIE, NFIE, SCI1 error
FE, PF FEIE, PFIE
15 0xFFE0/0xFFE1 Vspi SPI SPIF, MODF, SPIE, SPIE, SPTIE SPI
SPTEF
14–12 0xFFE2/0xFFE3– (Reserved)
0xFFE6/0xFFE7
11 0xFFE8/0xFFE9 Vtpm1ovf TPM1 TOF TOIE TPM1 overflow
10–9 0xFFEA/0xFFEB– (Reserved)
0xFFEC/0xFFED
8 0xFFEE/0xFFEF Vtpm1ch3 TPM1 CH3F CH3IE TPM1 channel 3
7 0xFFF0/0xFFF1 Vtpm1ch2 TPM1 CH2F CH2IE TPM1 channel 2
6 0xFFF2/0xFFF3 Vtpm1ch1 TPM1 CH1F CH1IE TPM1 channel 1
5 0xFFF4/0xFFF5 Vtpm1ch0 TPM1 CH0F CH0IE TPM1 channel 0
4 0xFFF6/0xFFF7 Vlol MCG LOLS LOLIE MCG loss of lock
3 0xFFF8/0xFFF9 Vlvd System LVWF LVWIE Low-voltage warning
control
2 0xFFFA/0xFFFB Virq IRQ IRQF IRQIE IRQ pin
1 0xFFFC/0xFFFD Vswi Core SWI Instruction — Software interrupt
0 0xFFFE/0xFFFF Vreset System COP, COPE Watchdog timer
control LOC, CME Loss-of-clock
LVD, LVDRE Low-voltage detect
RESET, — External pin
ILOP, — Illegal opcode
ILAD, — Illegal address
POR, — Power-on-reset
BDFR — BDM-forced reset
1
Vector priority is shown from lowest (first row) to highest (last row). For example, Vreset is the highest priority vector.

5.6 Low-Voltage Detect (LVD) System

The MC9S08EN32 Series includes a system to protect against low-voltage conditions in order to protect
memory contents and control MCU system states during supply voltage variations. The system is
comprised of a power-on reset (POR) circuit and a LVD circuit with trip voltages for warning and

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 Chapter 5 Resets, Interrupts, and General System Control

detection. The LVD circuit is enabled when LVDE in SPMSC1 is set to 1. The LVD is disabled upon
entering any of the stop modes unless LVDSE is set in SPMSC1. If LVDSE and LVDE are both set, then
the MCU cannot enter stop2 (it will enter stop3 instead), and the current consumption in stop3 with the
LVD enabled will be higher.

5.6.1 Power-On Reset Operation

When power is initially applied to the MCU, or when the supply voltage drops below the power-on reset
rearm voltage level, VPOR, the POR circuit will cause a reset condition. As the supply voltage rises, the
LVD circuit will hold the MCU in reset until the supply has risen above the low-voltage detection low
threshold, VLVDL. Both the POR bit and the LVD bit in SRS are set following a POR.

5.6.2 Low-Voltage Detection (LVD) Reset Operation

The LVD can be configured to generate a reset upon detection of a low-voltage condition by setting
LVDRE to 1. The low-voltage detection threshold is determined by the LVDV bit. After an LVD reset has
occurred, the LVD system will hold the MCU in reset until the supply voltage has risen above the
low-voltage detection threshold. The LVD bit in the SRS register is set following either an LVD reset or
POR.

5.6.3 Low-Voltage Warning (LVW) Interrupt Operation

The LVD system has a low-voltage warning flag to indicate to the user that the supply voltage is
approaching the low-voltage condition. When a low-voltage warning condition is detected and is
configured for interrupt operation (LVWIE set to 1), LVWF in SPMSC1 will be set and an LVW interrupt
request will occur.

5.7 MCLK Output

The PTA0 pin is shared with the MCLK clock output. If the MCSEL bits are all zeroes, the MCLK clock
is disabled. Setting any of the MCSEL bits causes the PTA0 pin to output a divided version of the internal
MCU bus clock regardless of the state of the port data direction control bit for the pin. The divide ratio is
determined by the MCSEL bits. The slew rate and drive strength for the pin are controlled by PTASE0 and
PTADS0, respectively. The maximum clock output frequency is limited if slew rate control is enabled, see
the electrical specifications for the maximum frequency under different conditions.

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Chapter 5 Resets, Interrupts, and General System Control

5.8 Reset, Interrupt, and System Control Registers and Control Bits
One 8-bit register in the direct page register space and eight 8-bit registers in the high-page register space
are related to reset and interrupt systems.
Refer to Table 4-2 and Table 4-3 in Chapter 4, “Memory,” of this data sheet for the absolute address
assignments for all registers. This section refers to registers and control bits only by their names. A
Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
Some control bits in the SOPT1 and SPMSC2 registers are related to modes of operation. Although brief
descriptions of these bits are provided here, the related functions are discussed in greater detail in
Chapter 3, “Modes of Operation.”

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 Chapter 5 Resets, Interrupts, and General System Control

5.8.1 Interrupt Pin Request Status and Control Register (IRQSC)

This direct page register includes status and control bits which are used to configure the IRQ function,
report status, and acknowledge IRQ events.
7 6 5 4 3 2 1 0

R 0 IRQF 0
IRQPDD IRQEDG IRQPE IRQIE IRQMOD
W IRQACK

Reset 0 0 0 0 0 0 0 0

= Unimplemented or Reserved

Figure 5-2. Interrupt Request Status and Control Register (IRQSC)

Table 5-2. IRQSC Register Field Descriptions

Field Description

6 Interrupt Request (IRQ) Pull Device Disable— This read/write control bit is used to disable the internal
IRQPDD pull-up/pull-down device when the IRQ pin is enabled (IRQPE = 1) allowing for an external device to be used.
0 IRQ pull device enabled if IRQPE = 1.
1 IRQ pull device disabled if IRQPE = 1.

5 Interrupt Request (IRQ) Edge Select — This read/write control bit is used to select the polarity of edges or
IRQEDG levels on the IRQ pin that cause IRQF to be set. The IRQMOD control bit determines whether the IRQ pin is
sensitive to both edges and levels or only edges. When the IRQ pin is enabled as the IRQ input and is configured
to detect rising edges, it has a pull-down. When the IRQ pin is enabled as the IRQ input and is configured to
detect falling edges, it has a pull-up.
0 IRQ is falling edge or falling edge/low-level sensitive.
1 IRQ is rising edge or rising edge/high-level sensitive.

4 IRQ Pin Enable — This read/write control bit enables the IRQ pin function. When this bit is set the IRQ pin can
IRQPE be used as an interrupt request.
0 IRQ pin function is disabled.
1 IRQ pin function is enabled.

3 IRQ Flag — This read-only status bit indicates when an interrupt request event has occurred.
IRQF 0 No IRQ request.
1 IRQ event detected.

2 IRQ Acknowledge — This write-only bit is used to acknowledge interrupt request events (write 1 to clear IRQF).
IRQACK Writing 0 has no meaning or effect. Reads always return 0. If edge-and-level detection is selected (IRQMOD = 1),
IRQF cannot be cleared while the IRQ pin remains at its asserted level.

1 IRQ Interrupt Enable — This read/write control bit determines whether IRQ events generate an interrupt
IRQIE request.
0 Interrupt request when IRQF set is disabled (use polling).
1 Interrupt requested whenever IRQF = 1.

0 IRQ Detection Mode — This read/write control bit selects either edge-only detection or edge-and-level
IRQMOD detection. The IRQEDG control bit determines the polarity of edges and levels that are detected as interrupt
request events. See Section 5.5.2.2, “Edge and Level Sensitivity” for more details.
0 IRQ event on falling edges or rising edges only.
1 IRQ event on falling edges and low levels or on rising edges and high levels.

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Chapter 5 Resets, Interrupts, and General System Control

5.8.2 System Reset Status Register (SRS)

This high page register includes read-only status flags to indicate the source of the most recent reset. When
a debug host forces reset by writing 1 to BDFR in the SBDFR register, none of the status bits in SRS will
be set. Writing any value to this register address causes a COP reset when the COP is enabled except the
values 0x55 and 0xAA. Writing a 0x55-0xAA sequence to this address clears the COP watchdog timer
without affecting the contents of this register. The reset state of these bits depends on what caused the
MCU to reset.

7 6 5 4 3 2 1 0

R POR PIN COP ILOP ILAD LOC LVD 0

W Writing 0x55, 0xAA to SRS address clears COP watchdog timer.

POR: 1 0 0 0 0 0 1 0
LVD: u 0 0 0 0 0 1 0
Any other
0 Note(1) Note(1) Note(1) Note(1) 0 0 0
reset:

1
Any of these reset sources that are active at the time of reset entry will cause the corresponding bit(s) to be set; bits
corresponding to sources that are not active at the time of reset entry will be cleared.
Figure 5-3. System Reset Status (SRS)

Table 5-3. SRS Register Field Descriptions

Field Description

7 Power-On Reset — Reset was caused by the power-on detection logic. Because the internal supply voltage was
POR ramping up at the time, the low-voltage reset (LVD) status bit is also set to indicate that the reset occurred while
the internal supply was below the LVD threshold.
0 Reset not caused by POR.
1 POR caused reset.

6 External Reset Pin — Reset was caused by an active-low level on the external reset pin.
PIN 0 Reset not caused by external reset pin.
1 Reset came from external reset pin.

5 Computer Operating Properly (COP) Watchdog — Reset was caused by the COP watchdog timer timing out.
COP This reset source can be blocked by COPE = 0.
0 Reset not caused by COP timeout.
1 Reset caused by COP timeout.

4 Illegal Opcode — Reset was caused by an attempt to execute an unimplemented or illegal opcode. The STOP
ILOP instruction is considered illegal if stop is disabled by STOPE = 0 in the SOPT register. The BGND instruction is
considered illegal if active background mode is disabled by ENBDM = 0 in the BDCSC register.
0 Reset not caused by an illegal opcode.
1 Reset caused by an illegal opcode.

3 Illegal Address — Reset was caused by an attempt to access either data or an instruction at an unimplemented
ILAD memory address.
0 Reset not caused by an illegal address.
1 Reset caused by an illegal address.

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 Chapter 5 Resets, Interrupts, and General System Control

Table 5-3. SRS Register Field Descriptions

Field Description

2 Loss of Clock — Reset was caused by a loss of external clock.

LOC 0 Reset not caused by loss of external clock
1 Reset caused by loss of external clock

1 Low-Voltage Detect — If the LVDRE bit is set and the supply drops below the LVD trip voltage, an LVD reset will
LVD occur. This bit is also set by POR.
0 Reset not caused by LVD trip or POR.
1 Reset caused by LVD trip or POR.

5.8.3 System Background Debug Force Reset Register (SBDFR)

This high page register contains a single write-only control bit. A serial background command such as
WRITE_BYTE must be used to write to SBDFR. Attempts to write this register from a user program are
ignored. Reads always return 0x00.
7 6 5 4 3 2 1 0

R 0 0 0 0 0 0 0 0

W BDFR1

Reset: 0 0 0 0 0 0 0 0
= Unimplemented or Reserved

1
BDFR is writable only through serial background debug commands, not from user programs.

Figure 5-4. System Background Debug Force Reset Register (SBDFR)

Table 5-4. SBDFR Register Field Descriptions

Field Description

0 Background Debug Force Reset — A serial background command such as WRITE_BYTE can be used to allow
BDFR an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot
be written from a user program.

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Chapter 5 Resets, Interrupts, and General System Control

5.8.4 System Options Register 1 (SOPT1)

This high page register is a write-once register so only the first write after reset is honored. It can be read
at any time. Any subsequent attempt to write to SOPT1 (intentionally or unintentionally) is ignored to
avoid accidental changes to these sensitive settings. This register should be written during the user’s reset
initialization program to set the desired controls even if the desired settings are the same as the reset
settings.
7 6 5 4 3 2 1 0

R 0 0 0
COPT STOPE Reserved Reserved
W

Reset: 1 1 0 0 0 0 0 0

= Unimplemented or Reserved

Figure 5-5. System Options Register 1 (SOPT1)

Table 5-5. SOPT1 Register Field Descriptions

Field Description
7:6 COP Watchdog Timeout — These write-once bits select the timeout period of the COP. COPT along with
COPT[1:0] COPCLKS in SOPT2 defines the COP timeout period. See Table 5-6.
5 Stop Mode Enable — This write-once bit is used to enable stop mode. If stop mode is disabled and a user
STOPE program attempts to execute a STOP instruction, an illegal opcode reset is forced.
0 Stop mode disabled.
1 Stop mode enabled.

Table 5-6. COP Configuration Options

Control Bits COP Window1 Opens

Clock Source COP Overflow Count
COPCLKS COPT[1:0] (COPW = 1)

N/A 0:0 N/A N/A COP is disabled

0 0:1 1 kHz N/A 25 cycles (32 ms2)
0 1:0 1 kHz N/A 28 cycles (256 ms1)
0 1:1 1 kHz N/A 210 cycles (1.024 s1)
1 0:1 Bus 6144 cycles 213 cycles
1 1:0 Bus 49,152 cycles 216 cycles
1 1:1 Bus 196,608 cycles 218 cycles
1
Windowed COP operation requires the user to clear the COP timer in the last 25% of the selected timeout period. This column
displays the minimum number of clock counts required before the COP timer can be reset when in windowed COP mode
(COPW = 1).
2 Values shown in milliseconds based on t
LPO = 1 ms. See tLPO in the appendix Section A.12.1, “Control Timing,” for the
tolerance of this value.

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 Chapter 5 Resets, Interrupts, and General System Control

5.8.5 System Options Register 2 (SOPT2)

This high page register contains bits to configure MCU specific features on the MC9S08EN32 Series
devices.
7 6 5 4 3 2 1 0

R 0 0
COPCLKS1 COPW1 ADHTS MCSEL
W

Reset: 0 0 0 0 0 0 0 0

= Unimplemented or Reserved

Figure 5-6. System Options Register 2 (SOPT2)

1
This bit can be written only one time after reset. Additional writes are ignored.

Table 5-7. SOPT2 Register Field Descriptions

Field Description

7 COP Watchdog Clock Select — This write-once bit selects the clock source of the COP watchdog. See
COPCLKS Table 5-6 for details.
0 Internal 1-kHz clock is source to COP.
1 Bus clock is source to COP.

6 COP Window — This write-once bit selects the COP operation mode. When set, the 0x55-0xAA write sequence
COPW to the SRS register must occur in the last 25% of the selected period. Any write to the SRS register during the
first 75% of the selected period will reset the MCU.
0 Normal COP operation.
1 Window COP operation.

4 ADC Hardware Trigger Select — This bit selects which hardware trigger initiates conversion for the analog to
ADHTS digital converter when the ADC hardware trigger is enabled (ADCTRG is set in ADCSC2 register).
0 Real Time Counter (RTC) overflow.
1 External Interrupt Request (IRQ) pin.

2:0 MCLK Divide Select— These bits enable the MCLK output on PTA0 pin and select the divide ratio for the MCLK
MCSEL output according to the formula below when the MCSEL bits are not equal to all zeroes. In case that the MCSEL
bits are all zeroes, the MCLK output is disabled.
MCLK frequency = Bus Clock frequency (2 * MCSEL)

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5.8.6 System Device Identification Register (SDIDH, SDIDL)

These high page read-only registers are included so host development systems can identify the HCS08
derivative and revision number. This allows the development software to recognize where specific memory
blocks, registers, and control bits are located in a target MCU.

7 6 5 4 3 2 1 0

R Reserved ID11 ID10 ID9 ID8

Reset: 01 01 01 01 0 0 0 0

= Unimplemented or Reserved

1
The revision number that is hard coded into these bits reflects the current silicon revision level.
Figure 5-7. System Device Identification Register — High (SDIDH)

Table 5-8. SDIDH Register Field Descriptions

Field Description

3:0 Part Identification Number — MC9S08EN32 Series MCUs are hard-coded to the value 0x00E. See also ID bits
ID[11:8] in Table 5-9.

7 6 5 4 3 2 1 0

R ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0

Reset: 0 0 0 0 1 1 1 0

= Unimplemented or Reserved

Figure 5-8. System Device Identification Register — Low (SDIDL)

Table 5-9. SDIDL Register Field Descriptions

Field Description

7:0 Part Identification Number — MC9S08EN32 Series MCUs are hard-coded to the value 0x00E. See also ID bits
ID[7:0] in Table 5-8.

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 Chapter 5 Resets, Interrupts, and General System Control

5.8.7 System Power Management Status and Control 1 Register

(SPMSC1)
This high page register contains status and control bits to support the low-voltage detect function, and to
enable the bandgap voltage reference for use by the ADC and ACMP modules. This register should be
written during the user’s reset initialization program to set the desired controls even if the desired settings
are the same as the reset settings.

7 6 5 4 3 2 1 0
1
R LVWF 0 0
LVWIE LVDRE2 LVDSE LVDE2 BGBE
W LVWACK

Reset: 0 0 0 1 1 1 0 0

= Unimplemented or Reserved

1
LVWF will be set in the case when VSupply transitions below the trip point or after reset and VSupply is already below VLVW.
2
This bit can be written only one time after reset. Additional writes are ignored.
Figure 5-9. System Power Management Status and Control 1 Register (SPMSC1)

Table 5-10. SPMSC1 Register Field Descriptions

Field Description

7 Low-Voltage Warning Flag — The LVWF bit indicates the low-voltage warning status.
LVWF 0 low-voltage warning is not present.
1 low-voltage warning is present or was present.

6 Low-Voltage Warning Acknowledge — If LVWF = 1, a low-voltage condition has occurred. To acknowledge this
LVWACK low-voltage warning, write 1 to LVWACK, which will automatically clear LVWF to 0 if the low-voltage warning is
no longer present.

5 Low-Voltage Warning Interrupt Enable — This bit enables hardware interrupt requests for LVWF.
LVWIE 0 Hardware interrupt disabled (use polling).
1 Request a hardware interrupt when LVWF = 1.

4 Low-Voltage Detect Reset Enable — This write-once bit enables LVD events to generate a hardware reset
LVDRE (provided LVDE = 1).
0 LVD events do not generate hardware resets.
1 Force an MCU reset when an enabled low-voltage detect event occurs.

3 Low-Voltage Detect Stop Enable — Provided LVDE = 1, this read/write bit determines whether the low-voltage
LVDSE detect function operates when the MCU is in stop mode.
0 Low-voltage detect disabled during stop mode.
1 Low-voltage detect enabled during stop mode.

2 Low-Voltage Detect Enable — This write-once bit enables low-voltage detect logic and qualifies the operation
LVDE of other bits in this register.
0 LVD logic disabled.
1 LVD logic enabled.

0 Bandgap Buffer Enable — This bit enables an internal buffer for the bandgap voltage reference for use by the
BGBE ADC and ACMP modules on one of its internal channels.
0 Bandgap buffer disabled.
1 Bandgap buffer enabled.

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Chapter 5 Resets, Interrupts, and General System Control

5.8.8 System Power Management Status and Control 2 Register

(SPMSC2)
This register is used to report the status of the low-voltage warning function, and to configure the stop
mode behavior of the MCU. This register should be written during the user’s reset initialization program
to set the desired controls even if the desired settings are the same as the reset settings.
7 6 5 4 3 2 1 0

R 0 0 PPDF 0 0
LVDV1 LVWV PPDC2
W PPDACK

Power-on Reset: 0 0 0 0 0 0 0 0

LVD Reset: 0 0 u u 0 0 0 0

Any other Reset: 0 0 u u 0 0 0 0

= Unimplemented or Reserved u = Unaffected by reset

1
This bit can be written only one time after power-on reset. Additional writes are ignored.
2
This bit can be written only one time after reset. Additional writes are ignored.

Figure 5-10. System Power Management Status and Control 2 Register (SPMSC2)

Table 5-11. SPMSC2 Register Field Descriptions

Field Description

5 Low-Voltage Detect Voltage Select — This write-once bit selects the low-voltage detect (LVD) trip point setting.
LVDV It also selects the warning voltage range. See Table 5-12.

4 Low-Voltage Warning Voltage Select — This bit selects the low-voltage warning (LVW) trip point voltage. See
LVWV Table 5-12.

3 Partial Power Down Flag — This read-only status bit indicates that the MCU has recovered from stop2 mode.
PPDF 0 MCU has not recovered from stop2 mode.
1 MCU recovered from stop2 mode.

2 Partial Power Down Acknowledge — Writing a 1 to PPDACK clears the PPDF bit.
PPDACK

0 Partial Power Down Control — This write-once bit controls whether stop2 or stop3 mode is selected.
PPDC 0 Stop3 mode enabled.
1 Stop2, partial power down, mode enabled.

Table 5-12. LVD and LVW Trip Point Typical Values1

LVDV:LVWV LVW Trip Point LVD Trip Point

0:0 VLVW0 = 2.74 V VLVD0 = 2.56 V

0:1 VLVW1 = 2.92 V
1:0 VLVW2 = 4.3 V VLVD1 = 4.0 V
1:1 VLVW3 = 4.6 V
1
See Electrical Characteristics appendix for minimum and maximum values.

MC9S08EN32 Series Data Sheet, Rev. 2

74 Freescale Semiconductor
Chapter 6
Parallel Input/Output Control
This section explains software controls related to parallel input/output (I/O) and pin control. The
MC9S08EN32 Series has seven parallel I/O ports which include a total of up to 39 I/O pins and one
input-only pin. See Chapter 2, “Pins and Connections,” for more information about pin assignments and
external hardware considerations of these pins.
Many of these pins are shared with on-chip peripherals such as timer systems, communication systems, or
pin interrupts as shown in Table 2-1. The peripheral modules have priority over the general-purpose I/O
functions so that when a peripheral is enabled, the I/O functions associated with the shared pins are
disabled.
After reset, the shared peripheral functions are disabled and the pins are configured as inputs
(PTxDDn = 0). The pin control functions for each pin are configured as follows: slew rate control enabled
(PTxSEn = 1), low drive strength selected (PTxDSn = 0), and internal pull-ups disabled (PTxPEn = 0).
NOTE
Not all general-purpose I/O pins are available on all packages. To avoid
extra current drain from floating input pins, the user’s reset initialization
routine in the application program must either enable on-chip pull-up
devices or change the direction of unconnected pins to outputs so the pins
do not float.

6.1 Port Data and Data Direction

Reading and writing of parallel I/Os are performed through the port data registers. The direction, either
input or output, is controlled through the port data direction registers. The parallel I/O port function for an
individual pin is illustrated in the block diagram shown in Figure 6-1.
The data direction control bit (PTxDDn) determines whether the output buffer for the associated pin is
enabled, and also controls the source for port data register reads. The input buffer for the associated pin is
always enabled unless the pin is enabled as an analog function or is an output-only pin.
When a shared digital function is enabled for a pin, the output buffer is controlled by the shared function.
However, the data direction register bit will continue to control the source for reads of the port data register.
When a shared analog function is enabled for a pin, both the input and output buffers are disabled. A value
of 0 is read for any port data bit where the bit is an input (PTxDDn = 0) and the input buffer is disabled.
In general, whenever a pin is shared with both an alternate digital function and an analog function, the
analog function has priority such that if both the digital and analog functions are enabled, the analog
function controls the pin.

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 75
Chapter 6 Parallel Input/Output Control

It is a good programming practice to write to the port data register before changing the direction of a port
pin to become an output. This ensures that the pin will not be driven momentarily with an old data value
that happened to be in the port data register.
PTxDDn
D Q Output Enable

PTxDn
D Q Output Data

1
Port Read
Data
0 Synchronizer Input Data

BUSCLK
Figure 6-1. Parallel I/O Block Diagram

6.2 Pull-up, Slew Rate, and Drive Strength

Associated with the parallel I/O ports is a set of registers located in the high page register space that operate
independently of the parallel I/O registers. These registers are used to control pull-ups, slew rate, and drive
strength for the pins.
An internal pull-up device can be enabled for each port pin by setting the corresponding bit in the pull-up
enable register (PTxPEn). The pull-up device is disabled if the pin is configured as an output by the parallel
I/O control logic or any shared peripheral function regardless of the state of the corresponding pull-up
enable register bit. The pull-up device is also disabled if the pin is controlled by an analog function.
Slew rate control can be enabled for each port pin by setting the corresponding bit in the slew rate control
register (PTxSEn). When enabled, slew control limits the rate at which an output can transition in order to
reduce EMC emissions. Slew rate control has no effect on pins that are configured as inputs.
NOTE
Slew rate reset default values may differ between engineering samples and
final production parts. Always initialize slew rate control to the desired
value to ensure correct operation.
An output pin can be selected to have high output drive strength by setting the corresponding bit in the
drive strength select register (PTxDSn). When high drive is selected, a pin is capable of sourcing and
sinking greater current. Even though every I/O pin can be selected as high drive, the user must ensure that
the total current source and sink limits for the MCU are not exceeded. Drive strength selection is intended
to affect the DC behavior of I/O pins. However, the AC behavior is also affected. High drive allows a pin

MC9S08EN32 Series Data Sheet, Rev. 2

76 Freescale Semiconductor
 Chapter 6 Parallel Input/Output Control

to drive a greater load with the same switching speed as a low drive enabled pin into a smaller load.
Because of this, the EMC emissions may be affected by enabling pins as high drive.

6.3 Pin Interrupts

Port A, port B, and port D pins can be configured as external interrupt inputs and as an external means of
waking the MCU from stop or wait low-power modes.
The block diagram for each port interrupt logic is shown Figure 6-2.
PTxACK BUSCLK
1 VDD RESET
PTxIF
PTxn 0
S PTxPS0 D CLR Q
SYNCHRONIZER
CK
PTxES0
PORT STOP STOP BYPASS PTx
INTERRUPT FF INTERRUPT
1
REQUEST
PTxn 0
S PTxPSn PTxMOD
PTxIE
PTxESn

Figure 6-2. Port Interrupt Block Diagram

Writing to the PTxPSn bits in the port interrupt pin select register (PTxPS) independently enables or
disables each port pin. Each port can be configured as edge sensitive or edge and level sensitive based on
the PTxMOD bit in the port interrupt status and control register (PTxSC). Edge sensitivity can be software
programmed to be either falling or rising; the level can be either low or high. The polarity of the edge or
edge and level sensitivity is selected using the PTxESn bits in the port interrupt edge select register
(PTxES).
Synchronous logic is used to detect edges. Prior to detecting an edge, enabled port inputs must be at the
deasserted logic level. A falling edge is detected when an enabled port input signal is seen as a logic 1 (the
deasserted level) during one bus cycle and then a logic 0 (the asserted level) during the next cycle. A rising
edge is detected when the input signal is seen as a logic 0 during one bus cycle and then a logic 1 during
the next cycle.

6.3.1 Edge Only Sensitivity

A valid edge on an enabled port pin will set PTxIF in PTxSC. If PTxIE in PTxSC is set, an interrupt request
will be presented to the CPU. Clearing of PTxIF is accomplished by writing a 1 to PTxACK in PTxSC.

6.3.2 Edge and Level Sensitivity

A valid edge or level on an enabled port pin will set PTxIF in PTxSC. If PTxIE in PTxSC is set, an interrupt
request will be presented to the CPU. Clearing of PTxIF is accomplished by writing a 1 to PTxACK in
PTxSC provided all enabled port inputs are at their deasserted levels. PTxIF will remain set if any enabled
port pin is asserted while attempting to clear by writing a 1 to PTxACK.

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Freescale Semiconductor 77
Chapter 6 Parallel Input/Output Control

6.3.3 Pull-up/Pull-down Resistors

The port interrupt pins can be configured to use an internal pull-up/pull-down resistor using the associated
I/O port pull-up enable register. If an internal resistor is enabled, the PTxES register is used to select
whether the resistor is a pull-up (PTxESn = 0) or a pull-down (PTxESn = 1).

6.3.4 Pin Interrupt Initialization

When an interrupt pin is first enabled, it is possible to get a false interrupt flag. To prevent a false interrupt
request during pin interrupt initialization, the user should do the following:
1. Mask interrupts by clearing PTxIE in PTxSC.
2. Select the pin polarity by setting the appropriate PTxESn bits in PTxES.
3. If using internal pull-up/pull-down device, configure the associated pull enable bits in PTxPE.
4. Enable the interrupt pins by setting the appropriate PTxPSn bits in PTxPS.
5. Write to PTxACK in PTxSC to clear any false interrupts.
6. Set PTxIE in PTxSC to enable interrupts.

6.4 Pin Behavior in Stop Modes

Pin behavior following execution of a STOP instruction depends on the stop mode that is entered. An
explanation of pin behavior for the various stop modes follows:
• Stop2 mode is a partial power-down mode, whereby I/O latches are maintained in their state as
before the STOP instruction was executed. CPU register status and the state of I/O registers should
be saved in RAM before the STOP instruction is executed to place the MCU in stop2 mode. Upon
recovery from stop2 mode, before accessing any I/O, the user should examine the state of the PPDF
bit in the SPMSC2 register. If the PPDF bit is 0, I/O must be initialized as if a power on reset had
occurred. If the PPDF bit is 1, peripherals may require initialization to be restored to their pre-stop
condition. This can be done using data previously stored in RAM if it was saved before the STOP
instruction was executed. The user must then write a 1 to the PPDACK bit in the SPMSC2 register.
Access to I/O is now permitted again in the user application program.
• In stop3 mode, all I/O is maintained because internal logic circuity stays powered up. Upon
recovery, normal I/O function is available to the user.

6.5 Parallel I/O and Pin Control Registers

This section provides information about the registers associated with the parallel I/O ports. The data and
data direction registers are located in page zero of the memory map. The pull up, slew rate, drive strength,
and interrupt control registers are located in the high page section of the memory map.
Refer to tables in Chapter 4, “Memory,” for the absolute address assignments for all parallel I/O and their
pin control registers. This section refers to registers and control bits only by their names. A Freescale
Semiconductor-provided equate or header file normally is used to translate these names into the
appropriate absolute addresses.

MC9S08EN32 Series Data Sheet, Rev. 2

78 Freescale Semiconductor
 Chapter 6 Parallel Input/Output Control

6.5.1 Port A Registers

Port A is controlled by the registers listed below.

6.5.1.1 Port A Data Register (PTAD)

7 6 5 4 3 2 1 0

R
PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0
W

Reset: 0 0 0 0 0 0 0 0

Figure 6-3. Port A Data Register (PTAD)

Table 6-1. PTAD Register Field Descriptions

Field Description

7:0 Port A Data Register Bits — For port A pins that are inputs, reads return the logic level on the pin. For port A
PTAD[7:0] pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port A pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTAD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pull-ups/pull-downs disabled.

6.5.1.2 Port A Data Direction Register (PTADD)

7 6 5 4 3 2 1 0

R
PTADD7 PTADD6 PTADD5 PTADD4 PTADD3 PTADD2 PTADD1 PTADD0
W

Reset: 0 0 0 0 0 0 0 0

Figure 6-4. Port A Data Direction Register (PTADD)

Table 6-2. PTADD Register Field Descriptions

Field Description

7:0 Data Direction for Port A Bits — These read/write bits control the direction of port A pins and what is read for
PTADD[7:0] PTAD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port A bit n and PTAD reads return the contents of PTADn.

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 79
Chapter 6 Parallel Input/Output Control

6.5.1.3 Port A Pull Enable Register (PTAPE)

7 6 5 4 3 2 1 0

R
PTAPE7 PTAPE6 PTAPE5 PTAPE4 PTAPE3 PTAPE2 PTAPE1 PTAPE0
W

Reset: 0 0 0 0 0 0 0 0

Figure 6-5. Internal Pull Enable for Port A Register (PTAPE)

Table 6-3. PTAPE Register Field Descriptions

Field Description

7:0 Internal Pull Enable for Port A Bits — Each of these control bits determines if the internal pull-up or pull-down
PTAPE[7:0] device is enabled for the associated PTA pin. For port A pins that are configured as outputs, these bits have no
effect and the internal pull devices are disabled.
0 Internal pull-up/pull-down device disabled for port A bit n.
1 Internal pull-up/pull-down device enabled for port A bit n.

NOTE
Pull-down devices only apply when using pin interrupt functions, when
corresponding edge select and pin select functions are configured.

6.5.1.4 Port A Slew Rate Enable Register (PTASE)

7 6 5 4 3 2 1 0

R
PTASE7 PTASE6 PTASE5 PTASE4 PTASE3 PTASE2 PTASE1 PTASE0
W

Reset: 0 0 0 0 0 0 0 0

Figure 6-6. Slew Rate Enable for Port A Register (PTASE)

Table 6-4. PTASE Register Field Descriptions

Field Description

7:0 Output Slew Rate Enable for Port A Bits — Each of these control bits determines if the output slew rate control
PTASE[7:0] is enabled for the associated PTA pin. For port A pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port A bit n.
1 Output slew rate control enabled for port A bit n.

Note: Slew rate reset default values may differ between engineering samples and final production parts. Always initialize slew
rate control to the desired value to ensure correct operation.

MC9S08EN32 Series Data Sheet, Rev. 2

80 Freescale Semiconductor
 Chapter 6 Parallel Input/Output Control

6.5.1.5 Port A Drive Strength Selection Register (PTADS)

7 6 5 4 3 2 1 0

R
PTADS7 PTADS6 PTADS5 PTADS4 PTADS3 PTADS2 PTADS1 PTADS0
W

Reset: 0 0 0 0 0 0 0 0

Figure 6-7. Drive Strength Selection for Port A Register (PTADS)

Table 6-5. PTADS Register Field Descriptions

Field Description

7:0 Output Drive Strength Selection for Port A Bits — Each of these control bits selects between low and high
PTADS[7:0] output drive for the associated PTA pin. For port A pins that are configured as inputs, these bits have no effect.
0 Low output drive strength selected for port A bit n.
1 High output drive strength selected for port A bit n.

6.5.1.6 Port A Interrupt Status and Control Register (PTASC)

7 6 5 4 3 2 1 0

R 0 0 0 0 PTAIF 0
PTAIE PTAMOD
W PTAACK

Reset: 0 0 0 0 0 0 0 0

= Unimplemented or Reserved

Figure 6-8. Port A Interrupt Status and Control Register (PTASC)

Table 6-6. PTASC Register Field Descriptions

Field Description

3 Port A Interrupt Flag — PTAIF indicates when a port A interrupt is detected. Writes have no effect on PTAIF.
PTAIF 0 No port A interrupt detected.
1 Port A interrupt detected.

2 Port A Interrupt Acknowledge — Writing a 1 to PTAACK is part of the flag clearing mechanism. PTAACK
PTAACK always reads as 0.

1 Port A Interrupt Enable — PTAIE determines whether a port A interrupt is requested.

PTAIE 0 Port A interrupt request not enabled.
1 Port A interrupt request enabled.

0 Port A Detection Mode — PTAMOD (along with the PTAES bits) controls the detection mode of the port A
PTAMOD interrupt pins.
0 Port A pins detect edges only.
1 Port A pins detect both edges and levels.

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Freescale Semiconductor 81
Chapter 6 Parallel Input/Output Control

6.5.1.7 Port A Interrupt Pin Select Register (PTAPS)

7 6 5 4 3 2 1 0

R
PTAPS7 PTAPS6 PTAPS5 PTAPS4 PTAPS3 PTAPS2 PTAPS1 PTAPS0
W

Reset: 0 0 0 0 0 0 0 0

Figure 6-9. Port A Interrupt Pin Select Register (PTAPS)

Table 6-7. PTAPS Register Field Descriptions

Field Description

7:0 Port A Interrupt Pin Selects — Each of the PTAPSn bits enable the corresponding port A interrupt pin.
PTAPS[7:0] 0 Pin not enabled as interrupt.
1 Pin enabled as interrupt.

6.5.1.8 Port A Interrupt Edge Select Register (PTAES)

7 6 5 4 3 2 1 0

R
PTAES7 PTAES6 PTAES5 PTAES4 PTAES3 PTAES2 PTAES1 PTAES0
W

Reset: 0 0 0 0 0 0 0 0

Figure 6-10. Port A Edge Select Register (PTAES)

Table 6-8. PTAES Register Field Descriptions

Field Description

7:0 Port A Edge Selects — Each of the PTAESn bits serves a dual purpose by selecting the polarity of the active
PTAES[7:0] interrupt edge as well as selecting a pull-up or pull-down device if enabled.
0 A pull-up device is connected to the associated pin and detects falling edge/low level for interrupt generation.
1 A pull-down device is connected to the associated pin and detects rising edge/high level for interrupt
generation.

MC9S08EN32 Series Data Sheet, Rev. 2

82 Freescale Semiconductor
 Chapter 6 Parallel Input/Output Control

6.5.2 Port B Registers

Port B is controlled by the registers listed below.

6.5.2.1 Port B Data Register (PTBD)

7 6 5 4 3 2 1 0

R
PTBD7 PTBD6 PTBD5 PTBD4 PTBD3 PTBD2 PTBD1 PTBD0
W

Reset: 0 0 0 0 0 0 0 0

Figure 6-11. Port B Data Register (PTBD)

Table 6-9. PTBD Register Field Descriptions

Field Description

7:0 Port B Data Register Bits — For port B pins that are inputs, reads return the logic level on the pin. For port B
PTBD[7:0] pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port B pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTBD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pull-ups/pull-downs disabled.

6.5.2.2 Port B Data Direction Register (PTBDD)

7 6 5 4 3 2 1 0

R
PTBDD7 PTBDD6 PTBDD5 PTBDD4 PTBDD3 PTBDD2 PTBDD1 PTBDD0
W

Reset: 0 0 0 0 0 0 0 0

Figure 6-12. Port B Data Direction Register (PTBDD)

Table 6-10. PTBDD Register Field Descriptions

Field Description

7:0 Data Direction for Port B Bits — These read/write bits control the direction of port B pins and what is read for
PTBDD[7:0] PTBD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port B bit n and PTBD reads return the contents of PTBDn.

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 83
Chapter 6 Parallel Input/Output Control

6.5.2.3 Port B Pull Enable Register (PTBPE)

7 6 5 4 3 2 1 0

R
PTBPE7 PTBPE6 PTBPE5 PTBPE4 PTBPE3 PTBPE2 PTBPE1 PTBPE0
W

Reset: 0 0 0 0 0 0 0 0

Figure 6-13. Internal Pull Enable for Port B Register (PTBPE)

Table 6-11. PTBPE Register Field Descriptions

Field Description

7:0 Internal Pull Enable for Port B Bits — Each of these control bits determines if the internal pull-up or pull-down
PTBPE[7:0] device is enabled for the associated PTB pin. For port B pins that are configured as outputs, these bits have no
effect and the internal pull devices are disabled.
0 Internal pull-up/pull-down device disabled for port B bit n.
1 Internal pull-up/pull-down device enabled for port B bit n.

NOTE
Pull-down devices only apply when using pin interrupt functions, when
corresponding edge select and pin select functions are configured.

6.5.2.4 Port B Slew Rate Enable Register (PTBSE)

7 6 5 4 3 2 1 0

R
PTBSE7 PTBSE6 PTBSE5 PTBSE4 PTBSE3 PTBSE2 PTBSE1 PTBSE0
W

Reset: 0 0 0 0 0 0 0 0

Figure 6-14. Slew Rate Enable for Port B Register (PTBSE)

Table 6-12. PTBSE Register Field Descriptions

Field Description

7:0 Output Slew Rate Enable for Port B Bits — Each of these control bits determines if the output slew rate control
PTBSE[7:0] is enabled for the associated PTB pin. For port B pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port B bit n.
1 Output slew rate control enabled for port B bit n.

Note: Slew rate reset default values may differ between engineering samples and final production parts. Always initialize slew
rate control to the desired value to ensure correct operation.

MC9S08EN32 Series Data Sheet, Rev. 2

84 Freescale Semiconductor
 Chapter 6 Parallel Input/Output Control

6.5.2.5 Port B Drive Strength Selection Register (PTBDS)

7 6 5 4 3 2 1 0

R
PTBDS7 PTBDS6 PTBDS5 PTBDS4 PTBDS3 PTBDS2 PTBDS1 PTBDS0
W

Reset: 0 0 0 0 0 0 0 0

Figure 6-15. Drive Strength Selection for Port B Register (PTBDS)

Table 6-13. PTBDS Register Field Descriptions

Field Description

7:0 Output Drive Strength Selection for Port B Bits — Each of these control bits selects between low and high
PTBDS[7:0] output drive for the associated PTB pin. For port B pins that are configured as inputs, these bits have no effect.
0 Low output drive strength selected for port B bit n.
1 High output drive strength selected for port B bit n.

6.5.2.6 Port B Interrupt Status and Control Register (PTBSC)

7 6 5 4 3 2 1 0

R 0 0 0 0 PTBIF 0
PTBIE PTBMOD
W PTBACK

Reset: 0 0 0 0 0 0 0 0

= Unimplemented or Reserved

Figure 6-16. Port B Interrupt Status and Control Register (PTBSC)

Table 6-14. PTBSC Register Field Descriptions

Field Description

3 Port B Interrupt Flag — PTBIF indicates when a Port B interrupt is detected. Writes have no effect on PTBIF.
PTBIF 0 No Port B interrupt detected.
1 Port B interrupt detected.

2 Port B Interrupt Acknowledge — Writing a 1 to PTBACK is part of the flag clearing mechanism. PTBACK
PTBACK always reads as 0.

1 Port B Interrupt Enable — PTBIE determines whether a port B interrupt is requested.

PTBIE 0 Port B interrupt request not enabled.
1 Port B interrupt request enabled.

0 Port B Detection Mode — PTBMOD (along with the PTBES bits) controls the detection mode of the port B
PTBMOD interrupt pins.
0 Port B pins detect edges only.
1 Port B pins detect both edges and levels.

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 85
Chapter 6 Parallel Input/Output Control

6.5.2.7 Port B Interrupt Pin Select Register (PTBPS)

7 6 5 4 3 2 1 0

R
PTBPS7 PTBPS6 PTBPS5 PTBPS4 PTBPS3 PTBPS2 PTBPS1 PTBPS0
W

Reset: 0 0 0 0 0 0 0 0

Figure 6-17. Port B Interrupt Pin Select Register (PTBPS)

Table 6-15. PTBPS Register Field Descriptions

Field Description

7:0 Port B Interrupt Pin Selects — Each of the PTBPSn bits enable the corresponding port B interrupt pin.
PTBPS[7:0] 0 Pin not enabled as interrupt.
1 Pin enabled as interrupt.

6.5.2.8 Port B Interrupt Edge Select Register (PTBES)

7 6 5 4 3 2 1 0

R
PTBES7 PTBES6 PTBES5 PTBES4 PTBES3 PTBES2 PTBES1 PTBES0
W

Reset: 0 0 0 0 0 0 0 0

Figure 6-18. Port B Edge Select Register (PTBES)

Table 6-16. PTBES Register Field Descriptions

Field Description

7:0 Port B Edge Selects — Each of the PTBESn bits serves a dual purpose by selecting the polarity of the active
PTBES[7:0] interrupt edge as well as selecting a pull-up or pull-down device if enabled.
0 A pull-up device is connected to the associated pin and detects falling edge/low level for interrupt generation.
1 A pull-down device is connected to the associated pin and detects rising edge/high level for interrupt
generation.

NOTE
Pull-down devices only apply when using pin interrupt functions, when
corresponding edge select and pin select functions are configured.
Note: Slew rate reset default values may differ between engineering samples and final production parts. Always initialize slew
rate control to the desired value to ensure correct operation.

6.5.3 Port C Registers

MC9S08EN32 Series devices do not have a port C. The user must write both INIT1 and INIT2 to 0xFF.

MC9S08EN32 Series Data Sheet, Rev. 2

86 Freescale Semiconductor
 Chapter 6 Parallel Input/Output Control

7 6 5 4 3 2 1 0

R
User must write this register to 0xFF
W

Reset: 0 0 0 0 0 0 0 0

Figure 6-19. Initialize Register 1 (INIT1)

Table 6-17. INIT1 Register Field Descriptions

Field Description

7:0 Port C Initialization — This entire register must be written to 0xFF

7 6 5 4 3 2 1 0

R
User must write this register to 0xFF
W

Reset: 0 0 0 0 0 0 0 0

Figure 6-20. Initialize Register 2 (INIT2)

Table 6-18. INIT2 Register Field Descriptions

Field Description

7:0 Port C Initialization — This entire register must be written to 0xFF

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 87
Chapter 6 Parallel Input/Output Control

6.5.4 Port D Registers

Port D is controlled by the registers listed below.

6.5.4.1 Port D Data Register (PTDD)

7 6 5 4 3 2 1 0

R
PTDD7 PTDD6 PTDD5 PTDD4 PTDD3 PTDD2 PTDD1 PTDD0
W

Reset: 0 0 0 0 0 0 0 0

Figure 6-21. Port D Data Register (PTDD)

Table 6-19. PTDD Register Field Descriptions

Field Description

7:0 Port D Data Register Bits — For port D pins that are inputs, reads return the logic level on the pin. For port D
PTDD[7:0] pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port D pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTDD to all 0s, but these 0s are not driven out the corresponding pins because reset also
configures all port pins as high-impedance inputs with pull-ups/pull-downs disabled.

6.5.4.2 Port D Data Direction Register (PTDDD)

7 6 5 4 3 2 1 0

R
PTDDD7 PTDDD6 PTDDD5 PTDDD4 PTDDD3 PTDDD2 PTDDD1 PTDDD0
W

Reset: 0 0 0 0 0 0 0 0

Figure 6-22. Port D Data Direction Register (PTDDD)

Table 6-20. PTDDD Register Field Descriptions

Field Description

7:0 Data Direction for Port D Bits — These read/write bits control the direction of port D pins and what is read for
PTDDD[7:0] PTDD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port D bit n and PTDD reads return the contents of PTDDn.

MC9S08EN32 Series Data Sheet, Rev. 2

88 Freescale Semiconductor
 Chapter 6 Parallel Input/Output Control

6.5.4.3 Port D Pull Enable Register (PTDPE)

7 6 5 4 3 2 1 0

R
PTDPE7 PTDPE6 PTDPE5 PTDPE4 PTDPE3 PTDPE2 PTDPE1 PTDPE0
W

Reset: 0 0 0 0 0 0 0 0

Figure 6-23. Internal Pull Enable for Port D Register (PTDPE)

Table 6-21. PTDPE Register Field Descriptions

Field Description

7:0 Internal Pull Enable for Port D Bits — Each of these control bits determines if the internal pull-up or pull-down
PTDPE[7:0] device is enabled for the associated PTD pin. For port D pins that are configured as outputs, these bits have no
effect and the internal pull devices are disabled.
0 Internal pull-up/pull-down device disabled for port D bit n.
1 Internal pull-up/pull-down device enabled for port D bit n.

NOTE
Pull-down devices only apply when using pin interrupt functions, when
corresponding edge select and pin select functions are configured.

6.5.4.4 Port D Slew Rate Enable Register (PTDSE)

7 6 5 4 3 2 1 0

R
PTDSE7 PTDSE6 PTDSE5 PTDSE4 PTDSE3 PTDSE2 PTDSE1 PTDSE0
W

Reset: 0 0 0 0 0 0 0 0

Figure 6-24. Slew Rate Enable for Port D Register (PTDSE)

Table 6-22. PTDSE Register Field Descriptions

Field Description

7:0 Output Slew Rate Enable for Port D Bits — Each of these control bits determines if the output slew rate control
PTDSE[7:0] is enabled for the associated PTD pin. For port D pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port D bit n.
1 Output slew rate control enabled for port D bit n.

Note: Slew rate reset default values may differ between engineering samples and final production parts. Always initialize slew
rate control to the desired value to ensure correct operation.

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Chapter 6 Parallel Input/Output Control

6.5.4.5 Port D Drive Strength Selection Register (PTDDS)

7 6 5 4 3 2 1 0

R
PTDDS7 PTDDS6 PTDDS5 PTDDS4 PTDDS3 PTDDS2 PTDDS1 PTDDS0
W

Reset: 0 0 0 0 0 0 0 0

Figure 6-25. Drive Strength Selection for Port D Register (PTDDS)

Table 6-23. PTDDS Register Field Descriptions

Field Description

7:0 Output Drive Strength Selection for Port D Bits — Each of these control bits selects between low and high
PTDDS[7:0] output drive for the associated PTD pin. For port D pins that are configured as inputs, these bits have no effect.
0 Low output drive strength selected for port D bit n.
1 High output drive strength selected for port D bit n.

6.5.4.6 Port D Interrupt Status and Control Register (PTDSC)

7 6 5 4 3 2 1 0

R 0 0 0 0 PTDIF 0
PTDIE PTDMOD
W PTDACK

Reset: 0 0 0 0 0 0 0 0

= Unimplemented or Reserved

Figure 6-26. Port D Interrupt Status and Control Register (PTDSC)

Table 6-24. PTDSC Register Field Descriptions

Field Description

3 Port D Interrupt Flag — PTDIF indicates when a port D interrupt is detected. Writes have no effect on PTDIF.
PTDIF 0 No port D interrupt detected.
1 Port D interrupt detected.

2 Port D Interrupt Acknowledge — Writing a 1 to PTDACK is part of the flag clearing mechanism. PTDACK
PTDACK always reads as 0.

1 Port D Interrupt Enable — PTDIE determines whether a port D interrupt is requested.

PTDIE 0 Port D interrupt request not enabled.
1 Port D interrupt request enabled.

0 Port A Detection Mode — PTDMOD (along with the PTDES bits) controls the detection mode of the port D
PTDMOD interrupt pins.
0 Port D pins detect edges only.
1 Port D pins detect both edges and levels.

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 Chapter 6 Parallel Input/Output Control

6.5.4.7 Port D Interrupt Pin Select Register (PTDPS)

7 6 5 4 3 2 1 0

R
PTDPS7 PTDPS6 PTDPS5 PTDPS4 PTDPS3 PTDPS2 PTDPS1 PTDPS0
W

Reset: 0 0 0 0 0 0 0 0

Figure 6-27. Port D Interrupt Pin Select Register (PTDPS)

Table 6-25. PTDPS Register Field Descriptions

Field Description

7:0 Port D Interrupt Pin Selects — Each of the PTDPSn bits enable the corresponding port D interrupt pin.
PTDPS[7:0] 0 Pin not enabled as interrupt.
1 Pin enabled as interrupt.

6.5.4.8 Port D Interrupt Edge Select Register (PTDES)

7 6 5 4 3 2 1 0

R
PTDES7 PTDES6 PTDES5 PTDES4 PTDES3 PTDES2 PTDES1 PTDES0
W

Reset: 0 0 0 0 0 0 0 0

Figure 6-28. Port D Edge Select Register (PTDES)

Table 6-26. PTDES Register Field Descriptions

Field Description

7:0 Port D Edge Selects — Each of the PTDESn bits serves a dual purpose by selecting the polarity of the active
PTDES[7:0] interrupt edge as well as selecting a pull-up or pull-down device if enabled.
0 A pull-up device is connected to the associated pin and detects falling edge/low level for interrupt generation.
1 A pull-down device is connected to the associated pin and detects rising edge/high level for interrupt
generation.

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6.5.5 Port E Registers

Port E is controlled by the registers listed below.

6.5.5.1 Port E Data Register (PTED)

7 6 5 4 3 2 1 0

R
PTED7 PTED6 PTED5 PTED4 PTED3 PTED2 PTED11 PTED0
W

Reset: 0 0 0 0 0 0 0 0

Figure 6-29. Port E Data Register (PTED)

1
Reads of this bit always return the pin value of the associated pin, regardless of the value stored in the port data direction bit.

Table 6-27. PTED Register Field Descriptions

Field Description

7:0 Port E Data Register Bits — For port E pins that are inputs, reads return the logic level on the pin. For port E
PTED[7:0] pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port E pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTED to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pull-ups disabled.

6.5.5.2 Port E Data Direction Register (PTEDD)

7 6 5 4 3 2 1 0

R
PTEDD7 PTEDD6 PTEDD5 PTEDD4 PTEDD3 PTEDD2 PTEDD11 PTEDD0
W

Reset: 0 0 0 0 0 0 0 0

Figure 6-30. Port E Data Direction Register (PTEDD)

1 PTEDD1 has no effect on the input-only PTE1 pin.

Table 6-28. PTEDD Register Field Descriptions

Field Description

7:0 Data Direction for Port E Bits — These read/write bits control the direction of port E pins and what is read for
PTEDD[7:0] PTED reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port E bit n and PTED reads return the contents of PTEDn.

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 Chapter 6 Parallel Input/Output Control

6.5.5.3 Port E Pull Enable Register (PTEPE)

7 6 5 4 3 2 1 0

R
PTEPE7 PTEPE6 PTEPE5 PTEPE4 PTEPE3 PTEPE2 PTEPE1 PTEPE0
W

Reset: 0 0 0 0 0 0 0 0

Figure 6-31. Internal Pull Enable for Port E Register (PTEPE)

Table 6-29. PTEPE Register Field Descriptions

Field Description

7:0 Internal Pull Enable for Port E Bits — Each of these control bits determines if the internal pull-up device is
PTEPE[7:0] enabled for the associated PTE pin. For port E pins that are configured as outputs, these bits have no effect and
the internal pull devices are disabled.
0 Internal pull-up device disabled for port E bit n.
1 Internal pull-up device enabled for port E bit n.

NOTE
Pull-down devices only apply when using pin interrupt functions, when
corresponding edge select and pin select functions are configured.

6.5.5.4 Port E Slew Rate Enable Register (PTESE)

7 6 5 4 3 2 1 0

R
PTESE7 PTESE6 PTESE5 PTESE4 PTESE3 PTESE2 PTESE11 PTESE0
W

Reset: 0 0 0 0 0 0 0 0

Figure 6-32. Slew Rate Enable for Port E Register (PTESE)

1
PTESE1 has no effect on the input-only PTE1 pin.

Table 6-30. PTESE Register Field Descriptions

Field Description

7:0 Output Slew Rate Enable for Port E Bits — Each of these control bits determines if the output slew rate control
PTESE[7:0] is enabled for the associated PTE pin. For port E pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port E bit n.
1 Output slew rate control enabled for port E bit n.

Note: Slew rate reset default values may differ between engineering samples and final production parts. Always initialize slew
rate control to the desired value to ensure correct operation.

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Freescale Semiconductor 93
Chapter 6 Parallel Input/Output Control

6.5.5.5 Port E Drive Strength Selection Register (PTEDS)

7 6 5 4 3 2 1 0

R
PTEDS7 PTEDS6 PTEDS5 PTEDS4 PTEDS3 PTEDS2 PTEDS11 PTEDS0
W

Reset: 0 0 0 0 0 0 0 0

Figure 6-33. Drive Strength Selection for Port E Register (PTEDS)

1
PTEDS1 has no effect on the input-only PTE1 pin.

Table 6-31. PTEDS Register Field Descriptions

Field Description

7:0 Output Drive Strength Selection for Port E Bits — Each of these control bits selects between low and high
PTEDS[7:0] output drive for the associated PTE pin. For port E pins that are configured as inputs, these bits have no effect.
0 Low output drive strength selected for port E bit n.
1 High output drive strength selected for port E bit n.

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 Chapter 6 Parallel Input/Output Control

6.5.6 Port F Registers

Port F is controlled by the registers listed below.

6.5.6.1 Port F Data Register (PTFD)

7 6 5 4 3 2 1 0

R
R1 R1 PTFD5 PTFD4 PTFD3 PTFD2 PTFD1 PTFD0
W

Reset: 0 0 0 0 0 0 0 0

= Unimplemented or Reserved

Figure 6-34. Port F Data Register (PTFD)

1
Must be initialized to a value of 1 by user software.

Table 6-32. PTFD Register Field Descriptions

Field Description

5:0 Port F Data Register Bits — For port F pins that are inputs, reads return the logic level on the pin. For port F
PTFD[5:0] pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port F pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTFD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pull-ups disabled.

6.5.6.2 Port F Data Direction Register (PTFDD)

7 6 5 4 3 2 1 0

R
R1 R1 PTFDD5 PTFDD4 PTFDD3 PTFDD2 PTFDD1 PTFDD0
W

Reset: 0 0 0 0 0 0 0 0

= Unimplemented or Reserved

Figure 6-35. Port F Data Direction Register (PTFDD)

1
Must be initialized to a value of 1 by user software.

Table 6-33. PTFDD Register Field Descriptions

Field Description

5:0 Data Direction for Port F Bits — These read/write bits control the direction of port F pins and what is read for
PTFDD[5:0] PTFD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port F bit n and PTFD reads return the contents of PTFDn.

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6.5.6.3 Port F Pull Enable Register (PTFPE)

7 6 5 4 3 2 1 0

R
R R PTFPE5 PTFPE4 PTFPE3 PTFPE2 PTFPE1 PTFPE0
W

Reset: 0 0 0 0 0 0 0 0

= Unimplemented or Reserved

Figure 6-36. Internal Pull Enable for Port F Register (PTFPE)

Table 6-34. PTFPE Register Field Descriptions

Field Description

5:0 Internal Pull Enable for Port F Bits — Each of these control bits determines if the internal pull-up device is
PTFPE[5:0] enabled for the associated PTF pin. For port F pins that are configured as outputs, these bits have no effect and
the internal pull devices are disabled.
0 Internal pull-up device disabled for port F bit n.
1 Internal pull-up device enabled for port F bit n.

NOTE
Pull-down devices only apply when using pin interrupt functions, when
corresponding edge select and pin select functions are configured.

6.5.6.4 Port F Slew Rate Enable Register (PTFSE)

7 6 5 4 3 2 1 0

R
R R PTFSE5 PTFSE4 PTFSE3 PTFSE2 PTFSE1 PTFSE0
W

Reset: 0 0 0 0 0 0 0 0

= Unimplemented or Reserved

Figure 6-37. Slew Rate Enable for Port F Register (PTFSE)

Table 6-35. PTFSE Register Field Descriptions

Field Description

5:0 Output Slew Rate Enable for Port F Bits — Each of these control bits determines if the output slew rate control
PTFSE[5:0] is enabled for the associated PTF pin. For port F pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port F bit n.
1 Output slew rate control enabled for port F bit n.

Note: Slew rate reset default values may differ between engineering samples and final production parts. Always initialize slew
rate control to the desired value to ensure correct operation.

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 Chapter 6 Parallel Input/Output Control

6.5.6.5 Port F Drive Strength Selection Register (PTFDS)

7 6 5 4 3 2 1 0

R
R R PTFDS5 PTFDS4 PTFDS3 PTFDS2 PTFDS1 PTFDS0
W

Reset: 0 0 0 0 0 0 0 0

= Unimplemented or Reserved

Figure 6-38. Drive Strength Selection for Port F Register (PTFDS)

Table 6-36. PTFDS Register Field Descriptions

Field Description

5:0 Output Drive Strength Selection for Port F Bits — Each of these control bits selects between low and high
PTFDS[5:0] output drive for the associated PTF pin. For port F pins that are configured as inputs, these bits have no effect.
0 Low output drive strength selected for port F bit n.
1 High output drive strength selected for port F bit n.

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6.5.7 Port G Registers

Port G is controlled by the registers listed below.

6.5.7.1 Port G Data Register (PTGD)

7 6 5 4 3 2 1 0

R 0 0
R1 R1 R1 R1 PTGD1 PTGD0
W

Reset: 0 0 0 0 0 0 0 0

= Unimplemented or Reserved

Figure 6-39. Port G Data Register (PTGD)

1
Must be initialized to a value of 1 by user software.

Table 6-37. PTGD Register Field Descriptions

Field Description

1:0 Port G Data Register Bits — For port G pins that are inputs, reads return the logic level on the pin. For port G
PTGD[1:0] pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port G pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTGD to all 0s, but these 0s are not driven out the corresponding pins because reset also
configures all port pins as high-impedance inputs with pull-ups disabled.

6.5.7.2 Port G Data Direction Register (PTGDD)

7 6 5 4 3 2 1 0

R 0 0
R1 R1 R1 R1 PTGDD1 PTGDD0
W

Reset: 0 0 0 0 0 0 0 0

= Unimplemented or Reserved

Figure 6-40. Port G Data Direction Register (PTGDD)

1
Must be initialized to a value of 1 by user software.

Table 6-38. PTGDD Register Field Descriptions

Field Description

1:0 Data Direction for Port G Bits — These read/write bits control the direction of port G pins and what is read for
PTGDD[1:0] PTGD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port G bit n and PTGD reads return the contents of PTGDn.

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 Chapter 6 Parallel Input/Output Control

6.5.7.3 Port G Pull Enable Register (PTGPE)

7 6 5 4 3 2 1 0

R 0 0
R R R R PTGPE1 PTGPE0
W

Reset: 0 0 0 0 0 0 0 0

= Unimplemented or Reserved

Figure 6-41. Internal Pull Enable for Port G Register (PTGPE)

Table 6-39. PTGPE Register Field Descriptions

Field Description

1:0 Internal Pull Enable for Port G Bits — Each of these control bits determines if the internal pull-up device is
PTGPE[1:0] enabled for the associated PTG pin. For port G pins that are configured as outputs, these bits have no effect and
the internal pull devices are disabled.
0 Internal pull-up device disabled for port G bit n.
1 Internal pull-up device enabled for port G bit n.

NOTE
Pull-down devices only apply when using pin interrupt functions, when
corresponding edge select and pin select functions are configured.

6.5.7.4 Port G Slew Rate Enable Register (PTGSE)

7 6 5 4 3 2 1 0

R 0 0
R R R R PTGSE1 PTGSE0
W

Reset: 0 0 0 0 0 0 0 0

= Unimplemented or Reserved

Figure 6-42. Slew Rate Enable for Port G Register (PTGSE)

Table 6-40. PTGSE Register Field Descriptions

Field Description

1:0 Output Slew Rate Enable for Port G Bits — Each of these control bits determines if the output slew rate control
PTGSE[1:0] is enabled for the associated PTG pin. For port G pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port G bit n.
1 Output slew rate control enabled for port G bit n.

Note: Slew rate reset default values may differ between engineering samples and final production parts. Always initialize slew
rate control to the desired value to ensure correct operation.

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Freescale Semiconductor 99
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6.5.7.5 Port G Drive Strength Selection Register (PTGDS)

7 6 5 4 3 2 1 0

R 0 0
R R R R PTGDS1 PTGDS0
W

Reset: 0 0 0 0 0 0 0 0

= Unimplemented or Reserved

Figure 6-43. Drive Strength Selection for Port G Register (PTGDS)

Table 6-41. PTGDS Register Field Descriptions

Field Description

1:0 Output Drive Strength Selection for Port G Bits — Each of these control bits selects between low and high
PTGDS[1:0] output drive for the associated PTG pin. For port G pins that are configured as inputs, these bits have no effect.
0 Low output drive strength selected for port G bit n.
1 High output drive strength selected for port G bit n.

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Chapter 7
Central Processor Unit (S08CPUV3)
7.1 Introduction
This section provides summary information about the registers, addressing modes, and instruction set of
the CPU of the HCS08 Family. For a more detailed discussion, refer to the HCS08 Family Reference
Manual, volume 1, Freescale Semiconductor document order number HCS08RMV1/D.
The HCS08 CPU is fully source- and object-code-compatible with the M68HC08 CPU. Several
instructions and enhanced addressing modes were added to improve C compiler efficiency and to support
a new background debug system which replaces the monitor mode of earlier M68HC08 microcontrollers
(MCU).

7.1.1 Features
Features of the HCS08 CPU include:
• Object code fully upward-compatible with M68HC05 and M68HC08 Families
• All registers and memory are mapped to a single 64-Kbyte address space
• 16-bit stack pointer (any size stack anywhere in 64-Kbyte address space)
• 16-bit index register (H:X) with powerful indexed addressing modes
• 8-bit accumulator (A)
• Many instructions treat X as a second general-purpose 8-bit register
• Seven addressing modes:
— Inherent — Operands in internal registers
— Relative — 8-bit signed offset to branch destination
— Immediate — Operand in next object code byte(s)
— Direct — Operand in memory at 0x0000–0x00FF
— Extended — Operand anywhere in 64-Kbyte address space
— Indexed relative to H:X — Five submodes including auto increment
— Indexed relative to SP — Improves C efficiency dramatically
• Memory-to-memory data move instructions with four address mode combinations
• Overflow, half-carry, negative, zero, and carry condition codes support conditional branching on
the results of signed, unsigned, and binary-coded decimal (BCD) operations
• Efficient bit manipulation instructions
• Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions
• STOP and WAIT instructions to invoke low-power operating modes

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7.2 Programmer’s Model and CPU Registers

Figure 7-1 shows the five CPU registers. CPU registers are not part of the memory map.
7 0
ACCUMULATOR A

16-BIT INDEX REGISTER H:X

H INDEX REGISTER (HIGH) INDEX REGISTER (LOW) X
15 8 7 0
STACK POINTER SP
15 0
PROGRAM COUNTER PC

7 0
CONDITION CODE REGISTER V 1 1 H I N Z C CCR

CARRY
ZERO
NEGATIVE
INTERRUPT MASK
HALF-CARRY (FROM BIT 3)
TWO’S COMPLEMENT OVERFLOW
Figure 7-1. CPU Registers

7.2.1 Accumulator (A)

The A accumulator is a general-purpose 8-bit register. One operand input to the arithmetic logic unit
(ALU) is connected to the accumulator and the ALU results are often stored into the A accumulator after
arithmetic and logical operations. The accumulator can be loaded from memory using various addressing
modes to specify the address where the loaded data comes from, or the contents of A can be stored to
memory using various addressing modes to specify the address where data from A will be stored.
Reset has no effect on the contents of the A accumulator.

7.2.2 Index Register (H:X)

This 16-bit register is actually two separate 8-bit registers (H and X), which often work together as a 16-bit
address pointer where H holds the upper byte of an address and X holds the lower byte of the address. All
indexed addressing mode instructions use the full 16-bit value in H:X as an index reference pointer;
however, for compatibility with the earlier M68HC05 Family, some instructions operate only on the
low-order 8-bit half (X).
Many instructions treat X as a second general-purpose 8-bit register that can be used to hold 8-bit data
values. X can be cleared, incremented, decremented, complemented, negated, shifted, or rotated. Transfer
instructions allow data to be transferred from A or transferred to A where arithmetic and logical operations
can then be performed.
For compatibility with the earlier M68HC05 Family, H is forced to 0x00 during reset. Reset has no effect
on the contents of X.

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7.2.3 Stack Pointer (SP)

This 16-bit address pointer register points at the next available location on the automatic last-in-first-out
(LIFO) stack. The stack may be located anywhere in the 64-Kbyte address space that has RAM and can
be any size up to the amount of available RAM. The stack is used to automatically save the return address
for subroutine calls, the return address and CPU registers during interrupts, and for local variables. The
AIS (add immediate to stack pointer) instruction adds an 8-bit signed immediate value to SP. This is most
often used to allocate or deallocate space for local variables on the stack.
SP is forced to 0x00FF at reset for compatibility with the earlier M68HC05 Family. HCS08 programs
normally change the value in SP to the address of the last location (highest address) in on-chip RAM
during reset initialization to free up direct page RAM (from the end of the on-chip registers to 0x00FF).
The RSP (reset stack pointer) instruction was included for compatibility with the M68HC05 Family and
is seldom used in new HCS08 programs because it only affects the low-order half of the stack pointer.

7.2.4 Program Counter (PC)

The program counter is a 16-bit register that contains the address of the next instruction or operand to be
fetched.
During normal program execution, the program counter automatically increments to the next sequential
memory location every time an instruction or operand is fetched. Jump, branch, interrupt, and return
operations load the program counter with an address other than that of the next sequential location. This
is called a change-of-flow.
During reset, the program counter is loaded with the reset vector that is located at 0xFFFE and 0xFFFF.
The vector stored there is the address of the first instruction that will be executed after exiting the reset
state.

7.2.5 Condition Code Register (CCR)

The 8-bit condition code register contains the interrupt mask (I) and five flags that indicate the results of
the instruction just executed. Bits 6 and 5 are set permanently to 1. The following paragraphs describe the
functions of the condition code bits in general terms. For a more detailed explanation of how each
instruction sets the CCR bits, refer to the HCS08 Family Reference Manual, volume 1, Freescale
Semiconductor document order number HCS08RMv1.

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7 0
CONDITION CODE REGISTER V 1 1 H I N Z C CCR

CARRY
ZERO
NEGATIVE
INTERRUPT MASK
HALF-CARRY (FROM BIT 3)
TWO’S COMPLEMENT OVERFLOW

Figure 7-2. Condition Code Register

Table 7-1. CCR Register Field Descriptions

Field Description

7 Two’s Complement Overflow Flag — The CPU sets the overflow flag when a two’s complement overflow occurs.
V The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag.
0 No overflow
1 Overflow

4 Half-Carry Flag — The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during
H an add-without-carry (ADD) or add-with-carry (ADC) operation. The half-carry flag is required for binary-coded
decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and C condition code bits to
automatically add a correction value to the result from a previous ADD or ADC on BCD operands to correct the
result to a valid BCD value.
0 No carry between bits 3 and 4
1 Carry between bits 3 and 4

3 Interrupt Mask Bit — When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts
I are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but before the first instruction of the interrupt service
routine is executed.
Interrupts are not recognized at the instruction boundary after any instruction that clears I (CLI or TAP). This
ensures that the next instruction after a CLI or TAP will always be executed without the possibility of an intervening
interrupt, provided I was set.
0 Interrupts enabled
1 Interrupts disabled

2 Negative Flag — The CPU sets the negative flag when an arithmetic operation, logic operation, or data
N manipulation produces a negative result, setting bit 7 of the result. Simply loading or storing an 8-bit or 16-bit value
causes N to be set if the most significant bit of the loaded or stored value was 1.
0 Non-negative result
1 Negative result

1 Zero Flag — The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation
Z produces a result of 0x00 or 0x0000. Simply loading or storing an 8-bit or 16-bit value causes Z to be set if the
loaded or stored value was all 0s.
0 Non-zero result
1 Zero result

0 Carry/Borrow Flag — The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit
C 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test and
branch, shift, and rotate — also clear or set the carry/borrow flag.
0 No carry out of bit 7
1 Carry out of bit 7

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7.3 Addressing Modes

Addressing modes define the way the CPU accesses operands and data. In the HCS08, all memory, status
and control registers, and input/output (I/O) ports share a single 64-Kbyte linear address space so a 16-bit
binary address can uniquely identify any memory location. This arrangement means that the same
instructions that access variables in RAM can also be used to access I/O and control registers or nonvolatile
program space.
Some instructions use more than one addressing mode. For instance, move instructions use one addressing
mode to specify the source operand and a second addressing mode to specify the destination address.
Instructions such as BRCLR, BRSET, CBEQ, and DBNZ use one addressing mode to specify the location
of an operand for a test and then use relative addressing mode to specify the branch destination address
when the tested condition is true. For BRCLR, BRSET, CBEQ, and DBNZ, the addressing mode listed in
the instruction set tables is the addressing mode needed to access the operand to be tested, and relative
addressing mode is implied for the branch destination.

7.3.1 Inherent Addressing Mode (INH)

In this addressing mode, operands needed to complete the instruction (if any) are located within CPU
registers so the CPU does not need to access memory to get any operands.

7.3.2 Relative Addressing Mode (REL)

Relative addressing mode is used to specify the destination location for branch instructions. A signed 8-bit
offset value is located in the memory location immediately following the opcode. During execution, if the
branch condition is true, the signed offset is sign-extended to a 16-bit value and is added to the current
contents of the program counter, which causes program execution to continue at the branch destination
address.

7.3.3 Immediate Addressing Mode (IMM)

In immediate addressing mode, the operand needed to complete the instruction is included in the object
code immediately following the instruction opcode in memory. In the case of a 16-bit immediate operand,
the high-order byte is located in the next memory location after the opcode, and the low-order byte is
located in the next memory location after that.

7.3.4 Direct Addressing Mode (DIR)

In direct addressing mode, the instruction includes the low-order eight bits of an address in the direct page
(0x0000–0x00FF). During execution a 16-bit address is formed by concatenating an implied 0x00 for the
high-order half of the address and the direct address from the instruction to get the 16-bit address where
the desired operand is located. This is faster and more memory efficient than specifying a complete 16-bit
address for the operand.

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7.3.5 Extended Addressing Mode (EXT)

In extended addressing mode, the full 16-bit address of the operand is located in the next two bytes of
program memory after the opcode (high byte first).

7.3.6 Indexed Addressing Mode

Indexed addressing mode has seven variations including five that use the 16-bit H:X index register pair and
two that use the stack pointer as the base reference.

7.3.6.1 Indexed, No Offset (IX)

This variation of indexed addressing uses the 16-bit value in the H:X index register pair as the address of
the operand needed to complete the instruction.

7.3.6.2 Indexed, No Offset with Post Increment (IX+)

This variation of indexed addressing uses the 16-bit value in the H:X index register pair as the address of
the operand needed to complete the instruction. The index register pair is then incremented
(H:X = H:X + 0x0001) after the operand has been fetched. This addressing mode is only used for MOV
and CBEQ instructions.

7.3.6.3 Indexed, 8-Bit Offset (IX1)

This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus an unsigned
8-bit offset included in the instruction as the address of the operand needed to complete the instruction.

7.3.6.4 Indexed, 8-Bit Offset with Post Increment (IX1+)

This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus an unsigned
8-bit offset included in the instruction as the address of the operand needed to complete the instruction.
The index register pair is then incremented (H:X = H:X + 0x0001) after the operand has been fetched. This
addressing mode is used only for the CBEQ instruction.

7.3.6.5 Indexed, 16-Bit Offset (IX2)

This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus a 16-bit offset
included in the instruction as the address of the operand needed to complete the instruction.

7.3.6.6 SP-Relative, 8-Bit Offset (SP1)

This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus an unsigned 8-bit
offset included in the instruction as the address of the operand needed to complete the instruction.

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7.3.6.7 SP-Relative, 16-Bit Offset (SP2)

This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus a 16-bit offset
included in the instruction as the address of the operand needed to complete the instruction.

7.4 Special Operations

The CPU performs a few special operations that are similar to instructions but do not have opcodes like
other CPU instructions. In addition, a few instructions such as STOP and WAIT directly affect other MCU
circuitry. This section provides additional information about these operations.

7.4.1 Reset Sequence

Reset can be caused by a power-on-reset (POR) event, internal conditions such as the COP (computer
operating properly) watchdog, or by assertion of an external active-low reset pin. When a reset event
occurs, the CPU immediately stops whatever it is doing (the MCU does not wait for an instruction
boundary before responding to a reset event). For a more detailed discussion about how the MCU
recognizes resets and determines the source, refer to the Resets, Interrupts, and System Configuration
chapter.
The reset event is considered concluded when the sequence to determine whether the reset came from an
internal source is done and when the reset pin is no longer asserted. At the conclusion of a reset event, the
CPU performs a 6-cycle sequence to fetch the reset vector from 0xFFFE and 0xFFFF and to fill the
instruction queue in preparation for execution of the first program instruction.

7.4.2 Interrupt Sequence

When an interrupt is requested, the CPU completes the current instruction before responding to the
interrupt. At this point, the program counter is pointing at the start of the next instruction, which is where
the CPU should return after servicing the interrupt. The CPU responds to an interrupt by performing the
same sequence of operations as for a software interrupt (SWI) instruction, except the address used for the
vector fetch is determined by the highest priority interrupt that is pending when the interrupt sequence
started.
The CPU sequence for an interrupt is:
1. Store the contents of PCL, PCH, X, A, and CCR on the stack, in that order.
2. Set the I bit in the CCR.
3. Fetch the high-order half of the interrupt vector.
4. Fetch the low-order half of the interrupt vector.
5. Delay for one free bus cycle.
6. Fetch three bytes of program information starting at the address indicated by the interrupt vector
to fill the instruction queue in preparation for execution of the first instruction in the interrupt
service routine.
After the CCR contents are pushed onto the stack, the I bit in the CCR is set to prevent other interrupts
while in the interrupt service routine. Although it is possible to clear the I bit with an instruction in the

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interrupt service routine, this would allow nesting of interrupts (which is not recommended because it
leads to programs that are difficult to debug and maintain).
For compatibility with the earlier M68HC05 MCUs, the high-order half of the H:X index register pair (H)
is not saved on the stack as part of the interrupt sequence. The user must use a PSHH instruction at the
beginning of the service routine to save H and then use a PULH instruction just before the RTI that ends
the interrupt service routine. It is not necessary to save H if you are certain that the interrupt service routine
does not use any instructions or auto-increment addressing modes that might change the value of H.
The software interrupt (SWI) instruction is like a hardware interrupt except that it is not masked by the
global I bit in the CCR and it is associated with an instruction opcode within the program so it is not
asynchronous to program execution.

7.4.3 Wait Mode Operation

The WAIT instruction enables interrupts by clearing the I bit in the CCR. It then halts the clocks to the
CPU to reduce overall power consumption while the CPU is waiting for the interrupt or reset event that
will wake the CPU from wait mode. When an interrupt or reset event occurs, the CPU clocks will resume
and the interrupt or reset event will be processed normally.
If a serial BACKGROUND command is issued to the MCU through the background debug interface while
the CPU is in wait mode, CPU clocks will resume and the CPU will enter active background mode where
other serial background commands can be processed. This ensures that a host development system can still
gain access to a target MCU even if it is in wait mode.

7.4.4 Stop Mode Operation

Usually, all system clocks, including the crystal oscillator (when used), are halted during stop mode to
minimize power consumption. In such systems, external circuitry is needed to control the time spent in
stop mode and to issue a signal to wake up the target MCU when it is time to resume processing. Unlike
the earlier M68HC05 and M68HC08 MCUs, the HCS08 can be configured to keep a minimum set of
clocks running in stop mode. This optionally allows an internal periodic signal to wake the target MCU
from stop mode.
When a host debug system is connected to the background debug pin (BKGD) and the ENBDM control
bit has been set by a serial command through the background interface (or because the MCU was reset into
active background mode), the oscillator is forced to remain active when the MCU enters stop mode. In this
case, if a serial BACKGROUND command is issued to the MCU through the background debug interface
while the CPU is in stop mode, CPU clocks will resume and the CPU will enter active background mode
where other serial background commands can be processed. This ensures that a host development system
can still gain access to a target MCU even if it is in stop mode.
Recovery from stop mode depends on the particular HCS08 and whether the oscillator was stopped in stop
mode. Refer to the Modes of Operation chapter for more details.

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7.4.5 BGND Instruction

The BGND instruction is new to the HCS08 compared to the M68HC08. BGND would not be used in
normal user programs because it forces the CPU to stop processing user instructions and enter the active
background mode. The only way to resume execution of the user program is through reset or by a host
debug system issuing a GO, TRACE1, or TAGGO serial command through the background debug
interface.
Software-based breakpoints can be set by replacing an opcode at the desired breakpoint address with the
BGND opcode. When the program reaches this breakpoint address, the CPU is forced to active background
mode rather than continuing the user program.

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7.5 HCS08 Instruction Set Summary

Table 7-2 provides a summary of the HCS08 instruction set in all possible addressing modes. The table
shows operand construction, execution time in internal bus clock cycles, and cycle-by-cycle details for
each addressing mode variation of each instruction.

Table 7-2. Instruction Set Summary (Sheet 1 of 9)

Address
Affect

Cycles
Mode
Source Cyc-by-Cyc on CCR
Operation Object Code
Form Details
V11H INZC
ADC #opr8i IMM A9 ii 2 pp
ADC opr8a DIR B9 dd 3 rpp
ADC opr16a EXT C9 hh ll 4 prpp
ADC oprx16,X Add with Carry IX2 D9 ee ff 4 prpp
↕ 1 1 ↕ – ↕ ↕ ↕
ADC oprx8,X A ← (A) + (M) + (C) IX1 E9 ff 3 rpp
ADC ,X IX F9 3 rfp
ADC oprx16,SP SP2 9E D9 ee ff 5 pprpp
ADC oprx8,SP SP1 9E E9 ff 4 prpp

ADD #opr8i IMM AB ii 2 pp

ADD opr8a DIR BB dd 3 rpp
ADD opr16a EXT CB hh ll 4 prpp
ADD oprx16,X Add without Carry IX2 DB ee ff 4 prpp
↕ 1 1 ↕ – ↕ ↕ ↕
ADD oprx8,X A ← (A) + (M) IX1 EB ff 3 rpp
ADD ,X IX FB 3 rfp
ADD oprx16,SP SP2 9E DB ee ff 5 pprpp
ADD oprx8,SP SP1 9E EB ff 4 prpp

Add Immediate Value (Signed) to

AIS #opr8i Stack Pointer IMM A7 ii 2 pp – 1 1 – – – – –
SP ← (SP) + (M)

Add Immediate Value (Signed) to

AIX #opr8i Index Register (H:X) IMM AF ii 2 pp – 1 1 – – – – –
H:X ← (H:X) + (M)

AND #opr8i IMM A4 ii 2 pp

AND opr8a DIR B4 dd 3 rpp
AND opr16a EXT C4 hh ll 4 prpp
AND oprx16,X Logical AND IX2 D4 ee ff 4 prpp
0 1 1 – – ↕ ↕ –
AND oprx8,X A ← (A) & (M) IX1 E4 ff 3 rpp
AND ,X IX F4 3 rfp
AND oprx16,SP SP2 9E D4 ee ff 5 pprpp
AND oprx8,SP SP1 9E E4 ff 4 prpp

ASL opr8a Arithmetic Shift Left DIR 38 dd 5 rfwpp

ASLA INH 48 1 p
ASLX C 0 INH 58 1 p
↕ 1 1 – – ↕ ↕ ↕
ASL oprx8,X b7 b0 IX1 68 ff 5 rfwpp
ASL ,X IX 78 4 rfwp
ASL oprx8,SP (Same as LSL) SP1 9E 68 ff 6 prfwpp

ASR opr8a DIR 37 dd 5 rfwpp

ASRA Arithmetic Shift Right INH 47 1 p
ASRX INH 57 1 p
C
↕ 1 1 – – ↕ ↕ ↕
ASR oprx8,X IX1 67 ff 5 rfwpp
ASR ,X b7 b0 IX 77 4 rfwp
ASR oprx8,SP SP1 9E 67 ff 6 prfwpp

MC9S08EN32 Series Data Sheet, Rev. 2

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 Chapter 7 Central Processor Unit (S08CPUV3)

Table 7-2. Instruction Set Summary (Sheet 2 of 9)

Address
Affect

Cycles
Mode
Source Cyc-by-Cyc on CCR
Operation Object Code
Form Details
V11H INZC
Branch if Carry Bit Clear
BCC rel REL 24 rr 3 ppp – 1 1 – – – – –
(if C = 0)

DIR (b0) 11 dd 5 rfwpp

DIR (b1) 13 dd 5 rfwpp
DIR (b2) 15 dd 5 rfwpp
Clear Bit n in Memory DIR (b3) 17 dd 5 rfwpp
BCLR n,opr8a – 1 1 – – – – –
(Mn ← 0) DIR (b4) 19 dd 5 rfwpp
DIR (b5) 1B dd 5 rfwpp
DIR (b6) 1D dd 5 rfwpp
DIR (b7) 1F dd 5 rfwpp

Branch if Carry Bit Set (if C = 1)

BCS rel REL 25 rr 3 ppp – 1 1 – – – – –
(Same as BLO)

BEQ rel Branch if Equal (if Z = 1) REL 27 rr 3 ppp – 1 1 – – – – –

Branch if Greater Than or Equal To

BGE rel REL 90 rr 3 ppp – 1 1 – – – – –
(if N ⊕ V = 0) (Signed)

Enter active background if ENBDM=1

BGND Waits for and processes BDM commands INH 82 5+ fp...ppp – 1 1 – – – – –
until GO, TRACE1, or TAGGO

Branch if Greater Than (if Z | (N ⊕ V) = 0)

BGT rel REL 92 rr 3 ppp – 1 1 – – – – –
(Signed)

BHCC rel Branch if Half Carry Bit Clear (if H = 0) REL 28 rr 3 ppp – 1 1 – – – – –

BHCS rel Branch if Half Carry Bit Set (if H = 1) REL 29 rr 3 ppp – 1 1 – – – – –

BHI rel Branch if Higher (if C | Z = 0) REL 22 rr 3 ppp – 1 1 – – – – –

Branch if Higher or Same (if C = 0)

BHS rel REL 24 rr 3 ppp – 1 1 – – – – –
(Same as BCC)

BIH rel Branch if IRQ Pin High (if IRQ pin = 1) REL 2F rr 3 ppp – 1 1 – – – – –

BIL rel Branch if IRQ Pin Low (if IRQ pin = 0) REL 2E rr 3 ppp – 1 1 – – – – –

BIT #opr8i IMM A5 ii 2 pp

BIT opr8a DIR B5 dd 3 rpp
BIT opr16a EXT C5 hh ll 4 prpp
Bit Test
BIT oprx16,X IX2 D5 ee ff 4 prpp
(A) & (M) 0 1 1 – – ↕ ↕ –
BIT oprx8,X IX1 E5 ff 3 rpp
(CCR Updated but Operands Not Changed)
BIT ,X IX F5 3 rfp
BIT oprx16,SP SP2 9E D5 ee ff 5 pprpp
BIT oprx8,SP SP1 9E E5 ff 4 prpp

Branch if Less Than or Equal To

BLE rel REL 93 rr 3 ppp – 1 1 – – – – –
(if Z | (N ⊕ V) = 1) (Signed)

BLO rel Branch if Lower (if C = 1) (Same as BCS) REL 25 rr 3 ppp – 1 1 – – – – –

BLS rel Branch if Lower or Same (if C | Z = 1) REL 23 rr 3 ppp – 1 1 – – – – –

BLT rel Branch if Less Than (if N ⊕ V = 1) (Signed) REL 91 rr 3 ppp – 1 1 – – – – –

BMC rel Branch if Interrupt Mask Clear (if I = 0) REL 2C rr 3 ppp – 1 1 – – – – –

BMI rel Branch if Minus (if N = 1) REL 2B rr 3 ppp – 1 1 – – – – –

BMS rel Branch if Interrupt Mask Set (if I = 1) REL 2D rr 3 ppp – 1 1 – – – – –

BNE rel Branch if Not Equal (if Z = 0) REL 26 rr 3 ppp – 1 1 – – – – –

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Table 7-2. Instruction Set Summary (Sheet 3 of 9)

Address
Affect

Cycles
Mode
Source Cyc-by-Cyc on CCR
Operation Object Code
Form Details
V11H INZC
BPL rel Branch if Plus (if N = 0) REL 2A rr 3 ppp – 1 1 – – – – –

BRA rel Branch Always (if I = 1) REL 20 rr 3 ppp – 1 1 – – – – –

DIR (b0) 01 dd rr 5 rpppp

DIR (b1) 03 dd rr 5 rpppp
DIR (b2) 05 dd rr 5 rpppp
DIR (b3) 07 dd rr 5 rpppp
BRCLR n,opr8a,rel Branch if Bit n in Memory Clear (if (Mn) = 0) – 1 1 – – – – ↕
DIR (b4) 09 dd rr 5 rpppp
DIR (b5) 0B dd rr 5 rpppp
DIR (b6) 0D dd rr 5 rpppp
DIR (b7) 0F dd rr 5 rpppp

BRN rel Branch Never (if I = 0) REL 21 rr 3 ppp – 1 1 – – – – –

DIR (b0) 00 dd rr 5 rpppp

DIR (b1) 02 dd rr 5 rpppp
DIR (b2) 04 dd rr 5 rpppp
DIR (b3) 06 dd rr 5 rpppp
BRSET n,opr8a,rel Branch if Bit n in Memory Set (if (Mn) = 1) – 1 1 – – – – ↕
DIR (b4) 08 dd rr 5 rpppp
DIR (b5) 0A dd rr 5 rpppp
DIR (b6) 0C dd rr 5 rpppp
DIR (b7) 0E dd rr 5 rpppp

DIR (b0) 10 dd 5 rfwpp

DIR (b1) 12 dd 5 rfwpp
DIR (b2) 14 dd 5 rfwpp
DIR (b3) 16 dd 5 rfwpp
BSET n,opr8a Set Bit n in Memory (Mn ← 1) – 1 1 – – – – –
DIR (b4) 18 dd 5 rfwpp
DIR (b5) 1A dd 5 rfwpp
DIR (b6) 1C dd 5 rfwpp
DIR (b7) 1E dd 5 rfwpp

Branch to Subroutine
PC ← (PC) + $0002
BSR rel push (PCL); SP ← (SP) – $0001 REL AD rr 5 ssppp – 1 1 – – – – –
push (PCH); SP ← (SP) – $0001
PC ← (PC) + rel

CBEQ opr8a,rel Compare and... Branch if (A) = (M) DIR 31 dd rr 5 rpppp

CBEQA #opr8i,rel Branch if (A) = (M) IMM 41 ii rr 4 pppp
CBEQX #opr8i,rel Branch if (X) = (M) IMM 51 ii rr 4 pppp
– 1 1 – – – – –
CBEQ oprx8,X+,rel Branch if (A) = (M) IX1+ 61 ff rr 5 rpppp
CBEQ ,X+,rel Branch if (A) = (M) IX+ 71 rr 5 rfppp
CBEQ oprx8,SP,rel Branch if (A) = (M) SP1 9E 61 ff rr 6 prpppp

CLC Clear Carry Bit (C ← 0) INH 98 1 p – 1 1 – – – – 0

CLI Clear Interrupt Mask Bit (I ← 0) INH 9A 1 p – 1 1 – 0 – – –

CLR opr8a Clear M ← $00 DIR 3F dd 5 rfwpp

CLRA A ← $00 INH 4F 1 p
CLRX X ← $00 INH 5F 1 p
CLRH H ← $00 INH 8C 1 p 0 1 1 – – 0 1 –
CLR oprx8,X M ← $00 IX1 6F ff 5 rfwpp
CLR ,X M ← $00 IX 7F 4 rfwp
CLR oprx8,SP M ← $00 SP1 9E 6F ff 6 prfwpp

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Table 7-2. Instruction Set Summary (Sheet 4 of 9)

Address
Affect

Cycles
Mode
Source Cyc-by-Cyc on CCR
Operation Object Code
Form Details
V11H INZC
CMP #opr8i IMM A1 ii 2 pp
CMP opr8a DIR B1 dd 3 rpp
CMP opr16a EXT C1 hh ll 4 prpp
Compare Accumulator with Memory
CMP oprx16,X IX2 D1 ee ff 4 prpp
A–M ↕ 1 1 – – ↕ ↕ ↕
CMP oprx8,X IX1 E1 ff 3 rpp
(CCR Updated But Operands Not Changed)
CMP ,X IX F1 3 rfp
CMP oprx16,SP SP2 9E D1 ee ff 5 pprpp
CMP oprx8,SP SP1 9E E1 ff 4 prpp

COM opr8a Complement M ← (M)= $FF – (M) DIR 33 dd 5 rfwpp

COMA (One’s Complement) A ← (A) = $FF – (A) INH 43 1 p
COMX X ← (X) = $FF – (X) INH 53 1 p
0 1 1 – – ↕ ↕ 1
COM oprx8,X M ← (M) = $FF – (M) IX1 63 ff 5 rfwpp
COM ,X M ← (M) = $FF – (M) IX 73 4 rfwp
COM oprx8,SP M ← (M) = $FF – (M) SP1 9E 63 ff 6 prfwpp

CPHX opr16a EXT 3E hh ll 6 prrfpp

Compare Index Register (H:X) with Memory
CPHX #opr16i IMM 65 jj kk 3 ppp
(H:X) – (M:M + $0001) ↕ 1 1 – – ↕ ↕ ↕
CPHX opr8a DIR 75 dd 5 rrfpp
(CCR Updated But Operands Not Changed)
CPHX oprx8,SP SP1 9E F3 ff 6 prrfpp

CPX #opr8i IMM A3 ii 2 pp

CPX opr8a DIR B3 dd 3 rpp
CPX opr16a Compare X (Index Register Low) with EXT C3 hh ll 4 prpp
CPX oprx16,X Memory IX2 D3 ee ff 4 prpp
↕ 1 1 – – ↕ ↕ ↕
CPX oprx8,X X–M IX1 E3 ff 3 rpp
CPX ,X (CCR Updated But Operands Not Changed) IX F3 3 rfp
CPX oprx16,SP SP2 9E D3 ee ff 5 pprpp
CPX oprx8,SP SP1 9E E3 ff 4 prpp

Decimal Adjust Accumulator

DAA INH 72 1 p U 1 1 – – ↕ ↕ ↕
After ADD or ADC of BCD Values

DBNZ opr8a,rel DIR 3B dd rr 7 rfwpppp

DBNZA rel INH 4B rr 4 fppp
Decrement A, X, or M and Branch if Not Zero
DBNZX rel INH 5B rr 4 fppp
(if (result) ≠ 0) – 1 1 – – – – –
DBNZ oprx8,X,rel IX1 6B ff rr 7 rfwpppp
DBNZX Affects X Not H
DBNZ ,X,rel IX 7B rr 6 rfwppp
DBNZ oprx8,SP,rel SP1 9E 6B ff rr 8 prfwpppp

DEC opr8a Decrement M ← (M) – $01 DIR 3A dd 5 rfwpp

DECA A ← (A) – $01 INH 4A 1 p
DECX X ← (X) – $01 INH 5A 1 p
↕ 1 1 – – ↕ ↕ –
DEC oprx8,X M ← (M) – $01 IX1 6A ff 5 rfwpp
DEC ,X M ← (M) – $01 IX 7A 4 rfwp
DEC oprx8,SP M ← (M) – $01 SP1 9E 6A ff 6 prfwpp

Divide
DIV INH 52 6 fffffp – 1 1 – – – ↕ ↕
A ← (H:A)÷(X); H ← Remainder

EOR #opr8i Exclusive OR Memory with Accumulator IMM A8 ii 2 pp

EOR opr8a A ← (A ⊕ M) DIR B8 dd 3 rpp
EOR opr16a EXT C8 hh ll 4 prpp
EOR oprx16,X IX2 D8 ee ff 4 prpp
0 1 1 – – ↕ ↕ –
EOR oprx8,X IX1 E8 ff 3 rpp
EOR ,X IX F8 3 rfp
EOR oprx16,SP SP2 9E D8 ee ff 5 pprpp
EOR oprx8,SP SP1 9E E8 ff 4 prpp

MC9S08EN32 Series Data Sheet, Rev. 2

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Table 7-2. Instruction Set Summary (Sheet 5 of 9)

Address
Affect

Cycles
Mode
Source Cyc-by-Cyc on CCR
Operation Object Code
Form Details
V11H INZC
INC opr8a Increment M ← (M) + $01 DIR 3C dd 5 rfwpp
INCA A ← (A) + $01 INH 4C 1 p
INCX X ← (X) + $01 INH 5C 1 p
↕ 1 1 – – ↕ ↕ –
INC oprx8,X M ← (M) + $01 IX1 6C ff 5 rfwpp
INC ,X M ← (M) + $01 IX 7C 4 rfwp
INC oprx8,SP M ← (M) + $01 SP1 9E 6C ff 6 prfwpp

JMP opr8a DIR BC dd 3 ppp

JMP opr16a EXT CC hh ll 4 pppp
Jump
JMP oprx16,X IX2 DC ee ff 4 pppp – 1 1 – – – – –
PC ← Jump Address
JMP oprx8,X IX1 EC ff 3 ppp
JMP ,X IX FC 3 ppp

JSR opr8a Jump to Subroutine DIR BD dd 5 ssppp

JSR opr16a PC ← (PC) + n (n = 1, 2, or 3) EXT CD hh ll 6 pssppp
JSR oprx16,X Push (PCL); SP ← (SP) – $0001 IX2 DD ee ff 6 pssppp – 1 1 – – – – –
JSR oprx8,X Push (PCH); SP ← (SP) – $0001 IX1 ED ff 5 ssppp
JSR ,X PC ← Unconditional Address IX FD 5 ssppp

LDA #opr8i IMM A6 ii 2 pp

LDA opr8a DIR B6 dd 3 rpp
LDA opr16a EXT C6 hh ll 4 prpp
LDA oprx16,X Load Accumulator from Memory IX2 D6 ee ff 4 prpp
0 1 1 – – ↕ ↕ –
LDA oprx8,X A ← (M) IX1 E6 ff 3 rpp
LDA ,X IX F6 3 rfp
LDA oprx16,SP SP2 9E D6 ee ff 5 pprpp
LDA oprx8,SP SP1 9E E6 ff 4 prpp

LDHX #opr16i IMM 45 jj kk 3 ppp

LDHX opr8a DIR 55 dd 4 rrpp
LDHX opr16a EXT 32 hh ll 5 prrpp
Load Index Register (H:X)
LDHX ,X IX 9E AE 5 prrfp 0 1 1 – – ↕ ↕ –
H:X ← (M:M + $0001)
LDHX oprx16,X IX2 9E BE ee ff 6 pprrpp
LDHX oprx8,X IX1 9E CE ff 5 prrpp
LDHX oprx8,SP SP1 9E FE ff 5 prrpp

LDX #opr8i IMM AE ii 2 pp

LDX opr8a DIR BE dd 3 rpp
LDX opr16a EXT CE hh ll 4 prpp
LDX oprx16,X Load X (Index Register Low) from Memory IX2 DE ee ff 4 prpp
0 1 1 – – ↕ ↕ –
LDX oprx8,X X ← (M) IX1 EE ff 3 rpp
LDX ,X IX FE 3 rfp
LDX oprx16,SP SP2 9E DE ee ff 5 pprpp
LDX oprx8,SP SP1 9E EE ff 4 prpp

LSL opr8a Logical Shift Left DIR 38 dd 5 rfwpp

LSLA INH 48 1 p
LSLX C 0 INH 58 1 p
↕ 1 1 – – ↕ ↕ ↕
LSL oprx8,X b7 b0 IX1 68 ff 5 rfwpp
LSL ,X IX 78 4 rfwp
LSL oprx8,SP (Same as ASL) SP1 9E 68 ff 6 prfwpp

LSR opr8a DIR 34 dd 5 rfwpp

Logical Shift Right
LSRA INH 44 1 p
LSRX INH 54 1 p
0 C
↕ 1 1 – – 0 ↕ ↕
LSR oprx8,X IX1 64 ff 5 rfwpp
LSR ,X b7 b0 IX 74 4 rfwp
LSR oprx8,SP SP1 9E 64 ff 6 prfwpp

MC9S08EN32 Series Data Sheet, Rev. 2

114 Freescale Semiconductor
 Chapter 7 Central Processor Unit (S08CPUV3)

Table 7-2. Instruction Set Summary (Sheet 6 of 9)

Address
Affect

Cycles
Mode
Source Cyc-by-Cyc on CCR
Operation Object Code
Form Details
V11H INZC
MOV opr8a,opr8a Move DIR/DIR 4E dd dd 5 rpwpp
MOV opr8a,X+ (M)destination ← (M)source DIR/IX+ 5E dd 5 rfwpp
0 1 1 – – ↕ ↕ –
MOV #opr8i,opr8a In IX+/DIR and DIR/IX+ Modes, IMM/DIR 6E ii dd 4 pwpp
MOV ,X+,opr8a H:X ← (H:X) + $0001 IX+/DIR 7E dd 5 rfwpp

Unsigned multiply
MUL INH 42 5 ffffp – 1 1 0 – – – 0
X:A ← (X) × (A)

NEG opr8a Negate M ← – (M) = $00 – (M) DIR 30 dd 5 rfwpp

NEGA (Two’s Complement) A ← – (A) = $00 – (A) INH 40 1 p
NEGX X ← – (X) = $00 – (X) INH 50 1 p
↕ 1 1 – – ↕ ↕ ↕
NEG oprx8,X M ← – (M) = $00 – (M) IX1 60 ff 5 rfwpp
NEG ,X M ← – (M) = $00 – (M) IX 70 4 rfwp
NEG oprx8,SP M ← – (M) = $00 – (M) SP1 9E 60 ff 6 prfwpp

NOP No Operation — Uses 1 Bus Cycle INH 9D 1 p – 1 1 – – – – –

Nibble Swap Accumulator

NSA INH 62 1 p – 1 1 – – – – –
A ← (A[3:0]:A[7:4])

ORA #opr8i IMM AA ii 2 pp

ORA opr8a DIR BA dd 3 rpp
ORA opr16a EXT CA hh ll 4 prpp
ORA oprx16,X Inclusive OR Accumulator and Memory IX2 DA ee ff 4 prpp
0 1 1 – – ↕ ↕ –
ORA oprx8,X A ← (A) | (M) IX1 EA ff 3 rpp
ORA ,X IX FA 3 rfp
ORA oprx16,SP SP2 9E DA ee ff 5 pprpp
ORA oprx8,SP SP1 9E EA ff 4 prpp

Push Accumulator onto Stack

PSHA INH 87 2 sp – 1 1 – – – – –
Push (A); SP ← (SP) – $0001

Push H (Index Register High) onto Stack

PSHH INH 8B 2 sp – 1 1 – – – – –
Push (H); SP ← (SP) – $0001

Push X (Index Register Low) onto Stack

PSHX INH 89 2 sp – 1 1 – – – – –
Push (X); SP ← (SP) – $0001

Pull Accumulator from Stack

PULA INH 86 3 ufp – 1 1 – – – – –
SP ← (SP + $0001); Pull (A)

Pull H (Index Register High) from Stack

PULH INH 8A 3 ufp – 1 1 – – – – –
SP ← (SP + $0001); Pull (H)

Pull X (Index Register Low) from Stack

PULX INH 88 3 ufp – 1 1 – – – – –
SP ← (SP + $0001); Pull (X)

ROL opr8a Rotate Left through Carry DIR 39 dd 5 rfwpp

ROLA INH 49 1 p
ROLX INH 59 1 p
C ↕ 1 1 – – ↕ ↕ ↕
ROL oprx8,X IX1 69 ff 5 rfwpp
ROL ,X b7 b0 IX 79 4 rfwp
ROL oprx8,SP SP1 9E 69 ff 6 prfwpp
ROR opr8a Rotate Right through Carry DIR 36 dd 5 rfwpp
RORA INH 46 1 p
RORX INH 56 1 p
C ↕ 1 1 – – ↕ ↕ ↕
ROR oprx8,X IX1 66 ff 5 rfwpp
ROR ,X b7 b0 IX 76 4 rfwp
ROR oprx8,SP SP1 9E 66 ff 6 prfwpp

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 115
Chapter 7 Central Processor Unit (S08CPUV3)

Table 7-2. Instruction Set Summary (Sheet 7 of 9)

Address
Affect

Cycles
Mode
Source Cyc-by-Cyc on CCR
Operation Object Code
Form Details
V11H INZC
Reset Stack Pointer (Low Byte)
RSP SPL ← $FF INH 9C 1 p – 1 1 – – – – –
(High Byte Not Affected)

Return from Interrupt

SP ← (SP) + $0001; Pull (CCR)
SP ← (SP) + $0001; Pull (A)
RTI INH 80 9 uuuuufppp ↕ 1 1 ↕ ↕ ↕ ↕ ↕
SP ← (SP) + $0001; Pull (X)
SP ← (SP) + $0001; Pull (PCH)
SP ← (SP) + $0001; Pull (PCL)

Return from Subroutine

RTS SP ← SP + $0001; Pull (PCH) INH 81 5 ufppp – 1 1 – – – – –
SP ← SP + $0001; Pull (PCL)

SBC #opr8i IMM A2 ii 2 pp

SBC opr8a DIR B2 dd 3 rpp
SBC opr16a EXT C2 hh ll 4 prpp
SBC oprx16,X Subtract with Carry IX2 D2 ee ff 4 prpp
↕ 1 1 – – ↕ ↕ ↕
SBC oprx8,X A ← (A) – (M) – (C) IX1 E2 ff 3 rpp
SBC ,X IX F2 3 rfp
SBC oprx16,SP SP2 9E D2 ee ff 5 pprpp
SBC oprx8,SP SP1 9E E2 ff 4 prpp

Set Carry Bit

SEC INH 99 1 p – 1 1 – – – – 1
(C ← 1)

Set Interrupt Mask Bit

SEI INH 9B 1 p – 1 1 – 1 – – –
(I ← 1)

STA opr8a DIR B7 dd 3 wpp

STA opr16a EXT C7 hh ll 4 pwpp
STA oprx16,X IX2 D7 ee ff 4 pwpp
Store Accumulator in Memory
STA oprx8,X IX1 E7 ff 3 wpp 0 1 1 – – ↕ ↕ –
M ← (A)
STA ,X IX F7 2 wp
STA oprx16,SP SP2 9E D7 ee ff 5 ppwpp
STA oprx8,SP SP1 9E E7 ff 4 pwpp

STHX opr8a DIR 35 dd 4 wwpp

Store H:X (Index Reg.)
STHX opr16a EXT 96 hh ll 5 pwwpp 0 1 1 – – ↕ ↕ –
(M:M + $0001) ← (H:X)
STHX oprx8,SP SP1 9E FF ff 5 pwwpp

Enable Interrupts: Stop Processing

STOP Refer to MCU Documentation INH 8E 2 fp... – 1 1 – 0 – – –
I bit ← 0; Stop Processing

STX opr8a DIR BF dd 3 wpp

STX opr16a EXT CF hh ll 4 pwpp
STX oprx16,X Store X (Low 8 Bits of Index Register) IX2 DF ee ff 4 pwpp
STX oprx8,X in Memory IX1 EF ff 3 wpp 0 1 1 – – ↕ ↕ –
STX ,X M ← (X) IX FF 2 wp
STX oprx16,SP SP2 9E DF ee ff 5 ppwpp
STX oprx8,SP SP1 9E EF ff 4 pwpp

MC9S08EN32 Series Data Sheet, Rev. 2

116 Freescale Semiconductor
 Chapter 7 Central Processor Unit (S08CPUV3)

Table 7-2. Instruction Set Summary (Sheet 8 of 9)

Address
Affect

Cycles
Mode
Source Cyc-by-Cyc on CCR
Operation Object Code
Form Details
V11H INZC
SUB #opr8i IMM A0 ii 2 pp
SUB opr8a DIR B0 dd 3 rpp
SUB opr16a EXT C0 hh ll 4 prpp
SUB oprx16,X Subtract IX2 D0 ee ff 4 prpp
↕ 1 1 – – ↕ ↕ ↕
SUB oprx8,X A ← (A) – (M) IX1 E0 ff 3 rpp
SUB ,X IX F0 3 rfp
SUB oprx16,SP SP2 9E D0 ee ff 5 pprpp
SUB oprx8,SP SP1 9E E0 ff 4 prpp

Software Interrupt
PC ← (PC) + $0001
Push (PCL); SP ← (SP) – $0001
Push (PCH); SP ← (SP) – $0001
Push (X); SP ← (SP) – $0001
SWI INH 83 11 sssssvvfppp – 1 1 – 1 – – –
Push (A); SP ← (SP) – $0001
Push (CCR); SP ← (SP) – $0001
I ← 1;
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte

Transfer Accumulator to CCR

TAP INH 84 1 p ↕ 1 1 ↕ ↕ ↕ ↕ ↕
CCR ← (A)

Transfer Accumulator to X (Index Register

TAX Low) INH 97 1 p – 1 1 – – – – –
X ← (A)

Transfer CCR to Accumulator

TPA INH 85 1 p – 1 1 – – – – –
A ← (CCR)

TST opr8a Test for Negative or Zero (M) – $00 DIR 3D dd 4 rfpp
TSTA (A) – $00 INH 4D 1 p
TSTX (X) – $00 INH 5D 1 p
0 1 1 – – ↕ ↕ –
TST oprx8,X (M) – $00 IX1 6D ff 4 rfpp
TST ,X (M) – $00 IX 7D 3 rfp
TST oprx8,SP (M) – $00 SP1 9E 6D ff 5 prfpp

Transfer SP to Index Reg.

TSX INH 95 2 fp – 1 1 – – – – –
H:X ← (SP) + $0001

Transfer X (Index Reg. Low) to Accumulator

TXA INH 9F 1 p – 1 1 – – – – –
A ← (X)

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 117
Chapter 7 Central Processor Unit (S08CPUV3)

Table 7-2. Instruction Set Summary (Sheet 9 of 9)

Address
Affect

Cycles
Mode
Source Cyc-by-Cyc on CCR
Operation Object Code
Form Details
V11H INZC
Transfer Index Reg. to SP
TXS INH 94 2 fp – 1 1 – – – – –
SP ← (H:X) – $0001

Enable Interrupts; Wait for Interrupt

WAIT INH 8F 2+ fp... – 1 1 – 0 – – –
I bit ← 0; Halt CPU

Source Form: Everything in the source forms columns, except expressions in italic characters, is literal information which must appear in the
assembly source file exactly as shown. The initial 3- to 5-letter mnemonic and the characters (# , ( ) and +) are always a literal characters.
n Any label or expression that evaluates to a single integer in the range 0-7.
opr8i Any label or expression that evaluates to an 8-bit immediate value.
opr16i Any label or expression that evaluates to a 16-bit immediate value.
opr8a Any label or expression that evaluates to an 8-bit direct-page address ($00xx).
opr16a Any label or expression that evaluates to a 16-bit address.
oprx8 Any label or expression that evaluates to an unsigned 8-bit value, used for indexed addressing.
oprx16 Any label or expression that evaluates to a 16-bit value, used for indexed addressing.
rel Any label or expression that refers to an address that is within –128 to +127 locations from the start of the next instruction.

Operation Symbols: Addressing Modes:

A Accumulator DIR Direct addressing mode
CCR Condition code register EXT Extended addressing mode
H Index register high byte IMM Immediate addressing mode
M Memory location INH Inherent addressing mode
n Any bit IX Indexed, no offset addressing mode
opr Operand (one or two bytes) IX1 Indexed, 8-bit offset addressing mode
PC Program counter IX2 Indexed, 16-bit offset addressing mode
PCH Program counter high byte IX+ Indexed, no offset, post increment addressing mode
PCL Program counter low byte IX1+ Indexed, 8-bit offset, post increment addressing mode
rel Relative program counter offset byte REL Relative addressing mode
SP Stack pointer SP1 Stack pointer, 8-bit offset addressing mode
SPL Stack pointer low byte SP2 Stack pointer 16-bit offset addressing mode
X Index register low byte
& Logical AND Cycle-by-Cycle Codes:
| Logical OR f Free cycle. This indicates a cycle where the CPU
does not require use of the system buses. An f
⊕ Logical EXCLUSIVE OR
cycle is always one cycle of the system bus clock
() Contents of
and is always a read cycle.
+ Add
p Progryam fetch; read from next consecutive
– Subtract, Negation (two’s complement)
location in program memory
× Multiply
r Read 8-bit operand
÷ Divide
s Push (write) one byte onto stack
# Immediate value
u Pop (read) one byte from stack
← Loaded with
v Read vector from $FFxx (high byte first)
: Concatenated with
w Write 8-bit operand

CCR Bits: CCR Effects:

V Overflow bit ↕ Set or cleared
H Half-carry bit – Not affected
I Interrupt mask U Undefined
N Negative bit
Z Zero bit
C Carry/borrow bit

MC9S08EN32 Series Data Sheet, Rev. 2

118 Freescale Semiconductor
 Chapter 7 Central Processor Unit (S08CPUV3)

Table 7-3. Opcode Map (Sheet 1 of 2)

Bit-Manipulation Branch Read-Modify-Write Control Register/Memory
00 5 10 5 20 3 30 5 40 1 50 1 60 5 70 4 80 9 90 3 A0 2 B0 3 C0 4 D0 4 E0 3 F0 3
BRSET0 BSET0 BRA NEG NEGA NEGX NEG NEG RTI BGE SUB SUB SUB SUB SUB SUB
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 REL 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
01 5 11 5 21 3 31 5 41 4 51 4 61 5 71 5 81 6 91 3 A1 2 B1 3 C1 4 D1 4 E1 3 F1 3
BRCLR0 BCLR0 BRN CBEQ CBEQA CBEQX CBEQ CBEQ RTS BLT CMP CMP CMP CMP CMP CMP
3 DIR 2 DIR 2 REL 3 DIR 3 IMM 3 IMM 3 IX1+ 2 IX+ 1 INH 2 REL 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
02 5 12 5 22 3 32 5 42 5 52 6 62 1 72 1 82 5+ 92 3 A2 2 B2 3 C2 4 D2 4 E2 3 F2 3
BRSET1 BSET1 BHI LDHX MUL DIV NSA DAA BGND BGT SBC SBC SBC SBC SBC SBC
3 DIR 2 DIR 2 REL 3 EXT 1 INH 1 INH 1 INH 1 INH 1 INH 2 REL 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
03 5 13 5 23 3 33 5 43 1 53 1 63 5 73 4 83 11 93 3 A3 2 B3 3 C3 4 D3 4 E3 3 F3 3
BRCLR1 BCLR1 BLS COM COMA COMX COM COM SWI BLE CPX CPX CPX CPX CPX CPX
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 REL 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
04 5 14 5 24 3 34 5 44 1 54 1 64 5 74 4 84 1 94 2 A4 2 B4 3 C4 4 D4 4 E4 3 F4 3
BRSET2 BSET2 BCC LSR LSRA LSRX LSR LSR TAP TXS AND AND AND AND AND AND
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
05 5 15 5 25 3 35 4 45 3 55 4 65 3 75 5 85 1 95 2 A5 2 B5 3 C5 4 D5 4 E5 3 F5 3
BRCLR2 BCLR2 BCS STHX LDHX LDHX CPHX CPHX TPA TSX BIT BIT BIT BIT BIT BIT
3 DIR 2 DIR 2 REL 2 DIR 3 IMM 2 DIR 3 IMM 2 DIR 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
06 5 16 5 26 3 36 5 46 1 56 1 66 5 76 4 86 3 96 5 A6 2 B6 3 C6 4 D6 4 E6 3 F6 3
BRSET3 BSET3 BNE ROR RORA RORX ROR ROR PULA STHX LDA LDA LDA LDA LDA LDA
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 3 EXT 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
07 5 17 5 27 3 37 5 47 1 57 1 67 5 77 4 87 2 97 1 A7 2 B7 3 C7 4 D7 4 E7 3 F7 2
BRCLR3 BCLR3 BEQ ASR ASRA ASRX ASR ASR PSHA TAX AIS STA STA STA STA STA
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
08 5 18 5 28 3 38 5 48 1 58 1 68 5 78 4 88 3 98 1 A8 2 B8 3 C8 4 D8 4 E8 3 F8 3
BRSET4 BSET4 BHCC LSL LSLA LSLX LSL LSL PULX CLC EOR EOR EOR EOR EOR EOR
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
09 5 19 5 29 3 39 5 49 1 59 1 69 5 79 4 89 2 99 1 A9 2 B9 3 C9 4 D9 4 E9 3 F9 3
BRCLR4 BCLR4 BHCS ROL ROLA ROLX ROL ROL PSHX SEC ADC ADC ADC ADC ADC ADC
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
0A 5 1A 5 2A 3 3A 5 4A 1 5A 1 6A 5 7A 4 8A 3 9A 1 AA 2 BA 3 CA 4 DA 4 EA 3 FA 3
BRSET5 BSET5 BPL DEC DECA DECX DEC DEC PULH CLI ORA ORA ORA ORA ORA ORA
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
0B 5 1B 5 2B 3 3B 7 4B 4 5B 4 6B 7 7B 6 8B 2 9B 1 AB 2 BB 3 CB 4 DB 4 EB 3 FB 3
BRCLR5 BCLR5 BMI DBNZ DBNZA DBNZX DBNZ DBNZ PSHH SEI ADD ADD ADD ADD ADD ADD
3 DIR 2 DIR 2 REL 3 DIR 2 INH 2 INH 3 IX1 2 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
0C 5 1C 5 2C 3 3C 5 4C 1 5C 1 6C 5 7C 4 8C 1 9C 1 BC 3 CC 4 DC 4 EC 3 FC 3
BRSET6 BSET6 BMC INC INCA INCX INC INC CLRH RSP JMP JMP JMP JMP JMP
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
0D 5 1D 5 2D 3 3D 4 4D 1 5D 1 6D 4 7D 3 9D 1 AD 5 BD 5 CD 6 DD 6 ED 5 FD 5
BRCLR6 BCLR6 BMS TST TSTA TSTX TST TST NOP BSR JSR JSR JSR JSR JSR
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 REL 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
0E 5 1E 5 2E 3 3E 6 4E 5 5E 5 6E 4 7E 5 8E 2+ 9E AE 2 BE 3 CE 4 DE 4 EE 3 FE 3
BRSET7 BSET7 BIL CPHX MOV MOV MOV MOV STOP Page 2 LDX LDX LDX LDX LDX LDX
3 DIR 2 DIR 2 REL 3 EXT 3 DD 2 DIX+ 3 IMD 2 IX+D 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
0F 5 1F 5 2F 3 3F 5 4F 1 5F 1 6F 5 7F 4 8F 2+ 9F 1 AF 2 BF 3 CF 4 DF 4 EF 3 FF 2
BRCLR7 BCLR7 BIH CLR CLRA CLRX CLR CLR WAIT TXA AIX STX STX STX STX STX
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

INH Inherent REL Relative SP1 Stack Pointer, 8-Bit Offset

IMM Immediate IX Indexed, No Offset SP2 Stack Pointer, 16-Bit Offset
DIR Direct IX1 Indexed, 8-Bit Offset IX+ Indexed, No Offset with
EXT Extended IX2 Indexed, 16-Bit Offset Post Increment
DD DIR to DIR IMD IMM to DIR IX1+ Indexed, 1-Byte Offset with
IX+D IX+ to DIR DIX+ DIR to IX+ Post Increment Opcode in
Hexadecimal F0 3 HCS08 Cycles
SUB Instruction Mnemonic
Number of Bytes 1 IX Addressing Mode

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 119
 Chapter 7 Central Processor Unit (S08CPUV3)

Table 7-3. Opcode Map (Sheet 2 of 2)

Bit-Manipulation Branch Read-Modify-Write Control Register/Memory
9E60 6 9ED0 5 9EE0 4
NEG SUB SUB
3 SP1 4 SP2 3 SP1
9E61 6 9ED1 5 9EE1 4
CBEQ CMP CMP
4 SP1 4 SP2 3 SP1
9ED2 5 9EE2 4
SBC SBC
4 SP2 3 SP1
9E63 6 9ED3 5 9EE3 4 9EF3 6
COM CPX CPX CPHX
3 SP1 4 SP2 3 SP1 3 SP1
9E64 6 9ED4 5 9EE4 4
LSR AND AND
3 SP1 4 SP2 3 SP1
9ED5 5 9EE5 4
BIT BIT
4 SP2 3 SP1
9E66 6 9ED6 5 9EE6 4
ROR LDA LDA
3 SP1 4 SP2 3 SP1
9E67 6 9ED7 5 9EE7 4
ASR STA STA
3 SP1 4 SP2 3 SP1
9E68 6 9ED8 5 9EE8 4
LSL EOR EOR
3 SP1 4 SP2 3 SP1
9E69 6 9ED9 5 9EE9 4
ROL ADC ADC
3 SP1 4 SP2 3 SP1
9E6A 6 9EDA 5 9EEA 4
DEC ORA ORA
3 SP1 4 SP2 3 SP1
9E6B 8 9EDB 5 9EEB 4
DBNZ ADD ADD
4 SP1 4 SP2 3 SP1
9E6C 6
INC
3 SP1
9E6D 5
TST
3 SP1
9EAE 5 9EBE 6 9ECE 5 9EDE 5 9EEE 4 9EFE 5
LDHX LDHX LDHX LDX LDX LDHX
2 IX 4 IX2 3 IX1 4 SP2 3 SP1 3 SP1
9E6F 6 9EDF 5 9EEF 4 9EFF 5
CLR STX STX STHX
3 SP1 4 SP2 3 SP1 3 SP1

INH Inherent REL Relative SP1 Stack Pointer, 8-Bit Offset

IMM Immediate IX Indexed, No Offset SP2 Stack Pointer, 16-Bit Offset
DIR Direct IX1 Indexed, 8-Bit Offset IX+ Indexed, No Offset with
EXT Extended IX2 Indexed, 16-Bit Offset Post Increment
DD DIR to DIR IMD IMM to DIR IX1+ Indexed, 1-Byte Offset with
IX+D IX+ to DIR DIX+ DIR to IX+ Post Increment

Note: All Sheet 2 Opcodes are Preceded by the Page 2 Prebyte (9E) Prebyte (9E) and Opcode in
Hexadecimal 9E60 6
HCS08 Cycles
NEG Instruction Mnemonic
Number of Bytes 3 SP1 Addressing Mode

MC9S08EN32 Series Data Sheet, Rev. 2

120 Freescale Semiconductor
Chapter 8
Multi-Purpose Clock Generator (S08MCGV1)
8.1 Introduction
The multi-purpose clock generator (MCG) module provides several clock source choices for the MCU.
The module contains a frequency-locked loop (FLL) and a phase-locked loop (PLL) that are controllable
by either an internal or an external reference clock. The module can select either of the FLL or PLL clocks,
or either of the internal or external reference clocks as a source for the MCU system clock. Whichever
clock source is chosen, it is passed through a reduced bus divider which allows a lower output clock
frequency to be derived. The MCG also controls an external oscillator (XOSC) for the use of a crystal or
resonator as the external reference clock.
All devices in the MC9S08EN32 Series feature the MCG module.
NOTE
Refer to Section 1.3, “System Clock Distribution,” for detailed view of the
distribution clock sources throughout the chip.

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 121
Chapter 8 Multi-Purpose Clock Generator (S08MCGV1)

HCS08 CORE PTA7/PIA7/ADP7/IRQ

PTA6/PIA6/ADP6
PTA5/PIA5/ADP5
CPU

PORT A
PTA4/PIA4/ADP4
ACMP1O
ANALOG COMPARATOR PTA3/PIA3/ADP3/ACMP1O
BKGD/MS ACMP1-
(ACMP1) PTA2/PIA2/ADP2/ACMP1-
BDC BKP ACMP1+
PTA1/PIA1/ADP1/ACMP1+
PTA0/PIA0/ADP0/MCLK
HCS08 SYSTEM CONTROL
PTB7/PIB7
RESETS AND INTERRUPTS PTB6/PIB6
RESET
MODES OF OPERATION PTB5/PIB5

PORT B
POWER MANAGEMENT PTB4/PIB4
PTB3/PIB3/ADP11
8 PTB2/PIB2/ADP10
COP LVD PTB1/PIB1/ADP9
IRQ

ADP7-ADP0 PTB0/PIB0/ADP8
INT IRQ
12-CHANNEL,10-BIT
ADP11-ADP8
ANALOG-TO-DIGITAL
VREFH
CONVERTER (ADC)
VREFL
VDDA
VSSA

TPM1CH3–TPM1CH0
PTD7/PID7
USER FLASH 4-CHANNEL TIMER/PWM 6 PTD6/PID6
MODULE (TPM1) TPM1CLK
MC9S08EN32 = 32K PTD5/PID5/TPM1CH3
MC9S08EN16 = 16K

PORT D
PTD4/PID4/TPM1CH2
PTD3/PID3/TPM1CH1
PTD2/PID2/TPM1CH0
PTD1/PID1
PTD0/PID0
PTE7
PTE6
MISO
USER RAM PTE5/MISO
MOSI
PORT E

MC9S08EN32 = 1 KBYTE SERIAL PERIPHERAL PTE4/MOSI

SPSCK
MC9S08EN16 = 512 BYTES INTERFACE MODULE (SPI) PTE3/SPSCK
SS
PTE2/SS
RxD1
PTE1/RxD1
DEBUG MODULE (DBG) SERIAL COMMUNICATIONS TxD1
PTE0/TxD1
INTERFACE (SCI1)

REAL TIME COUNTER (RTC) PTF5

PORT F

PTF4
VDD PTF3
VDD VOLTAGE PTF2/TPM1CLK
VSS REGULATOR PTF1
VSS PTF0

MULTI-PURPOSE
CLOCK GENERATOR
PORT G

(MCG)
XTAL
PTG1/XTAL
OSCILLATOR (XOSC) EXTAL
PTG0/EXTAL
- VREFH/VREFL internally connected to VDDA/VSSA
- VDD and VSS pins are each internally connected to two pads in 32-pin package - Pin not connected in 32-pin package

Figure 8-1. MC9S08EN32 Block Diagram

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8.1.1 Features
Key features of the MCG module are:
• Frequency-locked loop (FLL)
— 0.2% resolution using internal 32-kHz reference
— 2% deviation over voltage and temperature using internal 32-kHz reference
— Internal or external reference can be used to control the FLL
• Phase-locked loop (PLL)
— Voltage-controlled oscillator (VCO)
— Modulo VCO frequency divider
— Phase/Frequency detector
— Integrated loop filter
— Lock detector with interrupt capability
• Internal reference clock
— Nine trim bits for accuracy
— Can be selected as the clock source for the MCU
• External reference clock
— Control for external oscillator
— Clock monitor with reset capability
— Can be selected as the clock source for the MCU
• Reference divider is provided
• Clock source selected can be divided down by 1, 2, 4, or 8
• BDC clock (MCGLCLK) is provided as a constant divide by 2 of the DCO output whether in an
FLL or PLL mode.

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External Oscillator
(XOSC)

ERCLKEN MCGERCLK
RANGE EREFS

HGO EREFSTEN IRCLKEN MCGIRCLK

CME
IREFSTEN CLKS BDIV

Clock
Monitor / 2n
Internal MCGOUT
n=0-3
Reference LP
LOC OSCINIT Clock

IREFS 9 DCOOUT
DCO
TRIM

Lock
PLLS Detector
/ 2n RDIV_CLK
Filter
n=0-7
FLL LOLS LOCK
MCGFFCLK
RDIV
LP
VCOOUT /2 MCGLCLK

Phase Charge
Detector Pump VCO

Internal
VDIV Filter
PLL

/(4,8,12,...,40)

Multi-purpose Clock Generator (MCG)

Figure 8-2. Multi-Purpose Clock Generator (MCG) Block Diagram

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8.1.2 Modes of Operation

There are nine modes of operation for the MCG:
• FLL Engaged Internal (FEI)
• FLL Engaged External (FEE)
• FLL Bypassed Internal (FBI)
• FLL Bypassed External (FBE)
• PLL Engaged External (PEE)
• PLL Bypassed External (PBE)
• Bypassed Low Power Internal (BLPI)
• Bypassed Low Power External (BLPE)
• Stop
For details see Section 8.4.1, “Operational Modes".

8.2 External Signal Description

There are no MCG signals that connect off chip.

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8.3 Register Definition

8.3.1 MCG Control Register 1 (MCGC1)

7 6 5 4 3 2 1 0

R
CLKS RDIV IREFS IRCLKEN IREFSTEN
W

Reset: 0 0 0 0 0 1 0 0

Figure 8-3. MCG Control Register 1 (MCGC1)

Table 8-1. MCG Control Register 1 Field Descriptions

Field Description

7:6 Clock Source Select — Selects the system clock source.

CLKS 00 Encoding 0 — Output of FLL or PLL is selected.
01 Encoding 1 — Internal reference clock is selected.
10 Encoding 2 — External reference clock is selected.
11 Encoding 3 — Reserved, defaults to 00.

5:3 Reference Divider — Selects the amount to divide down the reference clock selected by the IREFS bit. If the
RDIV FLL is selected, the resulting frequency must be in the range 31.25 kHz to 39.0625 kHz. If the PLL is selected,
the resulting frequency must be in the range 1 MHz to 2 MHz.
000 Encoding 0 — Divides reference clock by 1 (reset default)
001 Encoding 1 — Divides reference clock by 2
010 Encoding 2 — Divides reference clock by 4
011 Encoding 3 — Divides reference clock by 8
100 Encoding 4 — Divides reference clock by 16
101 Encoding 5 — Divides reference clock by 32
110 Encoding 6 — Divides reference clock by 64
111 Encoding 7 — Divides reference clock by 128

2 Internal Reference Select — Selects the reference clock source.

IREFS 1 Internal reference clock selected
0 External reference clock selected

1 Internal Reference Clock Enable — Enables the internal reference clock for use as MCGIRCLK.
IRCLKEN 1 MCGIRCLK active
0 MCGIRCLK inactive

0 Internal Reference Stop Enable — Controls whether or not the internal reference clock remains enabled when
IREFSTEN the MCG enters stop mode.
1 Internal reference clock stays enabled in stop if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI mode before
entering stop
0 Internal reference clock is disabled in stop

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8.3.2 MCG Control Register 2 (MCGC2)

7 6 5 4 3 2 1 0

R
BDIV RANGE HGO LP EREFS ERCLKEN EREFSTEN
W

Reset: 0 1 0 0 0 0 0 0

Figure 8-4. MCG Control Register 2 (MCGC2)

Table 8-2. MCG Control Register 2 Field Descriptions

Field Description

7:6 Bus Frequency Divider — Selects the amount to divide down the clock source selected by the CLKS bits in the
BDIV MCGC1 register. This controls the bus frequency.
00 Encoding 0 — Divides selected clock by 1
01 Encoding 1 — Divides selected clock by 2 (reset default)
10 Encoding 2 — Divides selected clock by 4
11 Encoding 3 — Divides selected clock by 8

5 Frequency Range Select — Selects the frequency range for the external oscillator or external clock source.
RANGE 1 High frequency range selected for the external oscillator of 1 MHz to 16 MHz (1 MHz to 40 MHz for external
clock source)
0 Low frequency range selected for the external oscillator of 32 kHz to 100 kHz (32 kHz to 1 MHz for external
clock source)

4 High Gain Oscillator Select — Controls the external oscillator mode of operation.
HGO 1 Configure external oscillator for high gain operation
0 Configure external oscillator for low power operation

3 Low Power Select — Controls whether the FLL (or PLL) is disabled in bypassed modes.
LP 1 FLL (or PLL) is disabled in bypass modes (lower power).
0 FLL (or PLL) is not disabled in bypass modes.

2 External Reference Select — Selects the source for the external reference clock.
EREFS 1 Oscillator requested
0 External Clock Source requested

1 External Reference Enable — Enables the external reference clock for use as MCGERCLK.
ERCLKEN 1 MCGERCLK active
0 MCGERCLK inactive

0 External Reference Stop Enable — Controls whether or not the external reference clock remains enabled when
EREFSTEN the MCG enters stop mode.
1 External reference clock stays enabled in stop if ERCLKEN is set or if MCG is in FEE, FBE, PEE, PBE, or
BLPE mode before entering stop
0 External reference clock is disabled in stop

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8.3.3 MCG Trim Register (MCGTRM)

7 6 5 4 3 2 1 0

R
TRIM
W

POR: 1 0 0 0 0 0 0 0

Reset: U U U U U U U U

Figure 8-5. MCG Trim Register (MCGTRM)

Table 8-3. MCG Trim Register Field Descriptions

Field Description

7:0 MCG Trim Setting — Controls the internal reference clock frequency by controlling the internal reference clock
TRIM period. The TRIM bits are binary weighted (i.e., bit 1 will adjust twice as much as bit 0). Increasing the binary
value in TRIM will increase the period, and decreasing the value will decrease the period.

An additional fine trim bit is available in MCGSC as the FTRIM bit.

If a TRIM[7:0] value stored in nonvolatile memory is to be used, it’s the user’s responsibility to copy that value
from the nonvolatile memory location to this register.

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8.3.4 MCG Status and Control Register (MCGSC)

7 6 5 4 3 2 1 0

R LOLS LOCK PLLST IREFST CLKST OSCINIT

FTRIM
W

POR: 0 0 0 1 0 0 0 0
Reset: 0 0 0 1 0 0 0 U

Figure 8-6. MCG Status and Control Register (MCGSC)

Table 8-4. MCG Status and Control Register Field Descriptions

Field Description

7 Loss of Lock Status — This bit is a sticky indication of lock status for the FLL or PLL. LOLS is set when lock
LOLS detection is enabled and after acquiring lock, the FLL or PLL output frequency has fallen outside the lock exit
frequency tolerance, Dunl. LOLIE determines whether an interrupt request is made when set. LOLS is cleared by
reset or by writing a logic 1 to LOLS when LOLS is set. Writing a logic 0 to LOLS has no effect.
0 FLL or PLL has not lost lock since LOLS was last cleared.
1 FLL or PLL has lost lock since LOLS was last cleared.

6 Lock Status — Indicates whether the FLL or PLL has acquired lock. Lock detection is disabled when both the
LOCK FLL and PLL are disabled. If the lock status bit is set then changing the value of any of the following bits IREFS,
PLLS, RDIV[2:0], TRIM[7:0] (if in FEI or FBI modes), or VDIV[3:0] (if in PBE or PEE modes), will cause the lock
status bit to clear and stay cleared until the FLL or PLL has reacquired lock. Stop mode entry will also cause the
lock status bit to clear and stay cleared until the FLL or PLL has reacquired lock. Entry into BLPI or BLPE mode
will also cause the lock status bit to clear and stay cleared until the MCG has exited these modes and the FLL
or PLL has reacquired lock.
0 FLL or PLL is currently unlocked.
1 FLL or PLL is currently locked.

5 PLL Select Status — The PLLST bit indicates the current source for the PLLS clock. The PLLST bit does not
PLLST update immediately after a write to the PLLS bit due to internal synchronization between clock domains.
0 Source of PLLS clock is FLL clock.
1 Source of PLLS clock is PLL clock.

4 Internal Reference Status — The IREFST bit indicates the current source for the reference clock. The IREFST
IREFST bit does not update immediately after a write to the IREFS bit due to internal synchronization between clock
domains.
0 Source of reference clock is external reference clock (oscillator or external clock source as determined by the
EREFS bit in the MCGC2 register).
1 Source of reference clock is internal reference clock.

3:2 Clock Mode Status — The CLKST bits indicate the current clock mode. The CLKST bits do not update
CLKST immediately after a write to the CLKS bits due to internal synchronization between clock domains.
00 Encoding 0 — Output of FLL is selected.
01 Encoding 1 — Internal reference clock is selected.
10 Encoding 2 — External reference clock is selected.
11 Encoding 3 — Output of PLL is selected.

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Table 8-4. MCG Status and Control Register Field Descriptions (continued)

Field Description

1 OSC Initialization — If the external reference clock is selected by ERCLKEN or by the MCG being in FEE, FBE,
OSCINIT PEE, PBE, or BLPE mode, and if EREFS is set, then this bit is set after the initialization cycles of the external
oscillator clock have completed. This bit is only cleared when either EREFS is cleared or when the MCG is in
either FEI, FBI, or BLPI mode and ERCLKEN is cleared.

0 MCG Fine Trim — Controls the smallest adjustment of the internal reference clock frequency. Setting FTRIM
FTRIM will increase the period and clearing FTRIM will decrease the period by the smallest amount possible.

If an FTRIM value stored in nonvolatile memory is to be used, it’s the user’s responsibility to copy that value from
the nonvolatile memory location to this register’s FTRIM bit.

8.3.5 MCG Control Register 3 (MCGC3)

7 6 5 4 3 2 1 0

R 0
LOLIE PLLS CME VDIV
W

Reset: 0 0 0 0 0 0 0 1

Figure 8-7. MCG PLL Register (MCGPLL)

Table 8-5. MCG PLL Register Field Descriptions

Field Description

7 Loss of Lock Interrupt Enable — Determines if an interrupt request is made following a loss of lock indication.
LOLIE The LOLIE bit only has an effect when LOLS is set.
0 No request on loss of lock.
1 Generate an interrupt request on loss of lock.

6 PLL Select — Controls whether the PLL or FLL is selected. If the PLLS bit is clear, the PLL is disabled in all
PLLS modes. If the PLLS is set, the FLL is disabled in all modes.
1 PLL is selected
0 FLL is selected

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Table 8-5. MCG PLL Register Field Descriptions (continued)

Field Description

5 Clock Monitor Enable — Determines if a reset request is made following a loss of external clock indication. The
CME CME bit should only be set to a logic 1 when either the MCG is in an operational mode that uses the external
clock (FEE, FBE, PEE, PBE, or BLPE) or the external reference is enabled (ERCLKEN=1 in the MCGC2
register). Whenever the CME bit is set to a logic 1, the value of the RANGE bit in the MCGC2 register should not
be changed.
0 Clock monitor is disabled.
1 Generate a reset request on loss of external clock.

3:0 VCO Divider — Selects the amount to divide down the VCO output of PLL. The VDIV bits establish the
VDIV multiplication factor (M) applied to the reference clock frequency.
0000 Encoding 0 — Reserved.
0001 Encoding 1 — Multiply by 4.
0010 Encoding 2 — Multiply by 8.
0011 Encoding 3 — Multiply by 12.
0100 Encoding 4 — Multiply by 16.
0101 Encoding 5 — Multiply by 20.
0110 Encoding 6 — Multiply by 24.
0111 Encoding 7 — Multiply by 28.
1000 Encoding 8 — Multiply by 32.
1001 Encoding 9 — Multiply by 36.
1010 Encoding 10 — Multiply by 40.
1011 Encoding 11 — Reserved (default to M=40).
11xx Encoding 12-15 — Reserved (default to M=40).

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8.4 Functional Description

8.4.1 Operational Modes

IREFS=1 IREFS=0
CLKS=00 FLL Engaged FLL Engaged CLKS=00
PLLS=0 Internal (FEI) External (FEE) PLLS=0

IREFS=1 IREFS=0
CLKS=01 CLKS=10
PLLS=0 PLLS=0
BDM Enabled FLL Bypassed FLL Bypassed BDM Enabled
or LP=0 or LP=0
Internal (FBI) External (FBE)

Bypassed Bypassed IREFS=0

IREFS=1 Low Power
Low Power CLKS=10
CLKS=01 External (BLPE) BDM Disabled
Internal (BLPI)
BDM Disabled
and LP=1 and LP=1
PLL Bypassed IREFS=0
External (PBE) CLKS=10
PLLS=1
BDM Enabled
or LP=0

PLL Engaged IREFS=0

External (PEE) CLKS=00
PLLS=1

Returns to state that was active

Entered from any state Stop before MCU entered stop, unless
when MCU enters stop RESET occurs while in stop.

Figure 8-8. Clock Switching Modes

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The nine states of the MCG are shown as a state diagram and are described below. The arrows indicate the
allowed movements between the states.

8.4.1.1 FLL Engaged Internal (FEI)

FLL engaged internal (FEI) is the default mode of operation and is entered when all the following
conditions occur:
• CLKS bits are written to 00
• IREFS bit is written to 1
• PLLS bit is written to 0
• RDIV bits are written to 000. Since the internal reference clock frequency should already be in the
range of 31.25 kHz to 39.0625 kHz after it is trimmed, no further frequency divide is necessary.
In FLL engaged internal mode, the MCGOUT clock is derived from the FLL clock, which is controlled by
the internal reference clock. The FLL clock frequency locks to 1024 times the reference frequency, as
selected by the RDIV bits. The MCGLCLK is derived from the FLL and the PLL is disabled in a low power
state.

8.4.1.2 FLL Engaged External (FEE)

The FLL engaged external (FEE) mode is entered when all the following conditions occur:
• CLKS bits are written to 00
• IREFS bit is written to 0
• PLLS bit is written to 0
• RDIV bits are written to divide reference clock to be within the range of 31.25 kHz to 39.0625 kHz
In FLL engaged external mode, the MCGOUT clock is derived from the FLL clock which is controlled by
the external reference clock. The external reference clock which is enabled can be an external
crystal/resonator or it can be another external clock source.The FLL clock frequency locks to 1024 times
the reference frequency, as selected by the RDIV bits. The MCGLCLK is derived from the FLL and the
PLL is disabled in a low power state.

8.4.1.3 FLL Bypassed Internal (FBI)

In FLL bypassed internal (FBI) mode, the MCGOUT clock is derived from the internal reference clock
and the FLL is operational but its output clock is not used. This mode is useful to allow the FLL to acquire
its target frequency while the MCGOUT clock is driven from the internal reference clock.
The FLL bypassed internal mode is entered when all the following conditions occur:
• CLKS bits are written to 01
• IREFS bit is written to 1
• PLLS bit is written to 0
• RDIV bits are written to 000. Since the internal reference clock frequency should already be in the
range of 31.25 kHz to 39.0625 kHz after it is trimmed, no further frequency divide is necessary.

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• LP bit is written to 0
In FLL bypassed internal mode, the MCGOUT clock is derived from the internal reference clock. The FLL
clock is controlled by the internal reference clock, and the FLL clock frequency locks to 1024 times the
reference frequency, as selected by the RDIV bits. The MCGLCLK is derived from the FLL and the PLL
is disabled in a low power state.

8.4.1.4 FLL Bypassed External (FBE)

In FLL bypassed external (FBE) mode, the MCGOUT clock is derived from the external reference clock
and the FLL is operational but its output clock is not used. This mode is useful to allow the FLL to acquire
its target frequency while the MCGOUT clock is driven from the external reference clock.
The FLL bypassed external mode is entered when all the following conditions occur:
• CLKS bits are written to 10
• IREFS bit is written to 0
• PLLS bit is written to 0
• RDIV bits are written to divide reference clock to be within the range of 31.25 kHz to 39.0625 kHz
• LP bit is written to 0
In FLL bypassed external mode, the MCGOUT clock is derived from the external reference clock. The
external reference clock which is enabled can be an external crystal/resonator or it can be another external
clock source.The FLL clock is controlled by the external reference clock, and the FLL clock frequency
locks to 1024 times the reference frequency, as selected by the RDIV bits. The MCGLCLK is derived from
the FLL and the PLL is disabled in a low power state.
NOTE
It is possible to briefly operate in FBE mode with an FLL reference clock
frequency that is greater than the specified maximum frequency. This can be
necessary in applications that operate in PEE mode using an external crystal
with a frequency above 5 MHz. Please see 8.5.2.4, “Example # 4: Moving
from FEI to PEE Mode: External Crystal = 8 MHz, Bus Frequency = 8 MHz
for a detailed example.

8.4.1.5 PLL Engaged External (PEE)

The PLL engaged external (PEE) mode is entered when all the following conditions occur:
• CLKS bits are written to 00
• IREFS bit is written to 0
• PLLS bit is written to 1
• RDIV bits are written to divide reference clock to be within the range of 1 MHz to 2 MHz
In PLL engaged external mode, the MCGOUT clock is derived from the PLL clock which is controlled by
the external reference clock. The external reference clock which is enabled can be an external
crystal/resonator or it can be another external clock source The PLL clock frequency locks to a

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 Chapter 8 Multi-Purpose Clock Generator (S08MCGV1)

multiplication factor, as selected by the VDIV bits, times the reference frequency, as selected by the RDIV
bits. If BDM is enabled then the MCGLCLK is derived from the DCO (open-loop mode) divided by two.
If BDM is not enabled then the FLL is disabled in a low power state.

8.4.1.6 PLL Bypassed External (PBE)

In PLL bypassed external (PBE) mode, the MCGOUT clock is derived from the external reference clock
and the PLL is operational but its output clock is not used. This mode is useful to allow the PLL to acquire
its target frequency while the MCGOUT clock is driven from the external reference clock.
The PLL bypassed external mode is entered when all the following conditions occur:
• CLKS bits are written to 10
• IREFS bit is written to 0
• PLLS bit is written to 1
• RDIV bits are written to divide reference clock to be within the range of 1 MHz to 2 MHz
• LP bit is written to 0
In PLL bypassed external mode, the MCGOUT clock is derived from the external reference clock. The
external reference clock which is enabled can be an external crystal/resonator or it can be another external
clock source. The PLL clock frequency locks to a multiplication factor, as selected by the VDIV bits, times
the reference frequency, as selected by the RDIV bits. If BDM is enabled then the MCGLCLK is derived
from the DCO (open-loop mode) divided by two. If BDM is not enabled then the FLL is disabled in a low
power state.

8.4.1.7 Bypassed Low Power Internal (BLPI)

The bypassed low power internal (BLPI) mode is entered when all the following conditions occur:
• CLKS bits are written to 01
• IREFS bit is written to 1
• PLLS bit is written to 0 or 1
• LP bit is written to 1
• BDM mode is not active
In bypassed low power internal mode, the MCGOUT clock is derived from the internal reference clock.
The PLL and the FLL are disabled at all times in BLPI mode and the MCGLCLK will not be available for
BDC communications If the BDM becomes active the mode will switch to one of the bypassed internal
modes as determined by the state of the PLLS bit.

8.4.1.8 Bypassed Low Power External (BLPE)

The bypassed low power external (BLPE) mode is entered when all the following conditions occur:
• CLKS bits are written to 10
• IREFS bit is written to 0
• PLLS bit is written to 0 or 1

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• LP bit is written to 1
• BDM mode is not active
In bypassed low power external mode, the MCGOUT clock is derived from the external reference clock.
The external reference clock which is enabled can be an external crystal/resonator or it can be another
external clock source.
The PLL and the FLL are disabled at all times in BLPE mode and the MCGLCLK will not be available
for BDC communications. If the BDM becomes active the mode will switch to one of the bypassed
external modes as determined by the state of the PLLS bit.

8.4.1.9 Stop
Stop mode is entered whenever the MCU enters a STOP state. In this mode, the FLL and PLL are disabled
and all MCG clock signals are static except in the following cases:
MCGIRCLK will be active in stop mode when all the following conditions occur:
• IRCLKEN = 1
• IREFSTEN = 1
MCGERCLK will be active in stop mode when all the following conditions occur:
• ERCLKEN = 1
• EREFSTEN = 1

8.4.2 Mode Switching

When switching between engaged internal and engaged external modes the IREFS bit can be changed at
anytime, but the RDIV bits must be changed simultaneously so that the reference frequency stays in the
range required by the state of the PLLS bit (31.25 kHz to 39.0625 kHz if the FLL is selected, or 1 MHz to
2 MHz if the PLL is selected). After a change in the IREFS value the FLL or PLL will begin locking again
after the switch is completed. The completion of the switch is shown by the IREFST bit .
For the special case of entering stop mode immediately after switching to FBE mode, if the external clock
and the internal clock are disabled in stop mode, (EREFSTEN = 0 and IREFSTEN = 0), it is necessary to
allow 100us after the IREFST bit is cleared to allow the internal reference to shutdown. For most cases the
delay due to instruction execution times will be sufficient.
The CLKS bits can also be changed at anytime, but in order for the MCGLCLK to be configured correctly
the RDIV bits must be changed simultaneously so that the reference frequency stays in the range required
by the state of the PLLS bit (31.25 kHz to 39.0625 kHz if the FLL is selected, or 1 MHz to 2MHz if the
PLL is selected). The actual switch to the newly selected clock will be shown by the CLKST bits. If the
newly selected clock is not available, the previous clock will remain selected.
For details see Figure 8-8.

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8.4.3 Bus Frequency Divider

The BDIV bits can be changed at anytime and the actual switch to the new frequency will occur
immediately.

8.4.4 Low Power Bit Usage

The low power bit (LP) is provided to allow the FLL or PLL to be disabled and thus conserve power when
these systems are not being used. However, in some applications it may be desirable to enable the FLL or
PLL and allow it to lock for maximum accuracy before switching to an engaged mode. Do this by writing
the LP bit to 0.

8.4.5 Internal Reference Clock

When IRCLKEN is set the internal reference clock signal will be presented as MCGIRCLK, which can be
used as an additional clock source. The MCGIRCLK frequency can be re-targeted by trimming the period
of the internal reference clock. This can be done by writing a new value to the TRIM bits in the MCGTRM
register. Writing a larger value will decrease the MCGIRCLK frequency, and writing a smaller value to
the MCGTRM register will increase the MCGIRCLK frequency. The TRIM bits will effect the MCGOUT
frequency if the MCG is in FLL engaged internal (FEI), FLL bypassed internal (FBI), or bypassed low
power internal (BLPI) mode. The TRIM and FTRIM value is initialized by POR but is not affected by other
resets.
Until MCGIRCLK is trimmed, programming low reference divider (RDIV) factors may result in
MCGOUT frequencies that exceed the maximum chip-level frequency and violate the chip-level clock
timing specifications (see the Device Overview chapter).
If IREFSTEN and IRCLKEN bits are both set, the internal reference clock will keep running during stop
mode in order to provide a fast recovery upon exiting stop.

8.4.6 External Reference Clock

The MCG module can support an external reference clock with frequencies between 31.25 kHz to 5 MHz
in FEE and FBE modes, 1 MHz to 16 MHz in PEE and PBE modes, and 0 to 40 MHz in BLPE mode.
When ERCLKEN is set, the external reference clock signal will be presented as MCGERCLK, which can
be used as an additional clock source. When IREFS = 1, the external reference clock will not be used by
the FLL or PLL and will only be used as MCGERCLK. In these modes, the frequency can be equal to the
maximum frequency the chip-level timing specifications will support (see the Device Overview chapter).
If EREFSTEN and ERCLKEN bits are both set or the MCG is in FEE, FBE, PEE, PBE or BLPE mode,
the external reference clock will keep running during stop mode in order to provide a fast recovery upon
exiting stop.
If CME bit is written to 1, the clock monitor is enabled. If the external reference falls below a certain
frequency (floc_high or floc_low depending on the RANGE bit in the MCGC2), the MCU will reset. The LOC
bit in the System Reset Status (SRS) register will be set to indicate the error.

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8.4.7 Fixed Frequency Clock

The MCG presents the divided reference clock as MCGFFCLK for use as an additional clock source. The
MCGFFCLK frequency must be no more than 1/4 of the MCGOUT frequency to be valid. Because of this
requirement, the MCGFFCLK is not valid in bypass modes for the following combinations of BDIV and
RDIV values:
• BDIV=00 (divide by 1), RDIV < 010
BDIV=01 (divide by 2), RDIV < 011

8.5 Initialization / Application Information

This section describes how to initialize and configure the MCG module in application. The following
sections include examples on how to initialize the MCG and properly switch between the various available
modes.

8.5.1 MCG Module Initialization Sequence

The MCG comes out of reset configured for FEI mode with the BDIV set for divide-by-2. The internal
reference will stabilize in tirefst microseconds before the FLL can acquire lock. As soon as the internal
reference is stable, the FLL will acquire lock in tfll_lock milliseconds.
Upon POR, the internal reference will require trimming to guarantee an accurate clock. Freescale
recommends using Flash location 0xFFAE for storing the fine trim bit, FTRIM in the MCGSC register,
and 0xFFAF for storing the 8-bit trim value in the MCGTRM register. The MCU will not automatically
copy the values in these Flash locations to the respective registers. Therefore, user code must copy these
values from Flash to the registers.
NOTE
The BDIV value should not be changed to divide-by-1 without first
trimming the internal reference. Failure to do so could result in the MCU
running out of specification.

8.5.1.1 Initializing the MCG

Because the MCG comes out of reset in FEI mode, the only MCG modes which can be directly switched
to upon reset are FEE, FBE, and FBI modes (see Figure 8-8). Reaching any of the other modes requires
first configuring the MCG for one of these three initial modes. Care must be taken to check relevant status
bits in the MCGSC register reflecting all configuration changes within each mode.
To change from FEI mode to FEE or FBE modes, follow this procedure:
1. Enable the external clock source by setting the appropriate bits in MCGC2.
2. Write to MCGC1 to select the clock mode.
— If entering FEE, set RDIV appropriately, clear the IREFS bit to switch to the external reference,
and leave the CLKS bits at %00 so that the output of the FLL is selected as the system clock
source.

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 Chapter 8 Multi-Purpose Clock Generator (S08MCGV1)

— If entering FBE, clear the IREFS bit to switch to the external reference and change the CLKS
bits to %10 so that the external reference clock is selected as the system clock source. The
RDIV bits should also be set appropriately here according to the external reference frequency
because although the FLL is bypassed, it is still on in FBE mode.
— The internal reference can optionally be kept running by setting the IRCLKEN bit. This is
useful if the application will switch back and forth between internal and external modes. For
minimum power consumption, leave the internal reference disabled while in an external clock
mode.
3. After the proper configuration bits have been set, wait for the affected bits in the MCGSC register
to be changed appropriately, reflecting that the MCG has moved into the proper mode.
— If ERCLKEN was set in step 1 or the MCG is in FEE, FBE, PEE, PBE, or BLPE mode, and
EREFS was also set in step 1, wait here for the OSCINIT bit to become set indicating that the
external clock source has finished its initialization cycles and stabilized. Typical crystal startup
times are given in Appendix A, “Electrical Characteristics”.
— If in FEE mode, check to make sure the IREFST bit is cleared and the LOCK bit is set before
moving on.
— If in FBE mode, check to make sure the IREFST bit is cleared, the LOCK bit is set, and the
CLKST bits have changed to %10 indicating the external reference clock has been
appropriately selected. Although the FLL is bypassed in FBE mode, it is still on and will lock
in FBE mode.
To change from FEI clock mode to FBI clock mode, follow this procedure:
1. Change the CLKS bits to %01 so that the internal reference clock is selected as the system clock
source.
2. Wait for the CLKST bits in the MCGSC register to change to %01, indicating that the internal
reference clock has been appropriately selected.

8.5.2 MCG Mode Switching

When switching between operational modes of the MCG, certain configuration bits must be changed in
order to properly move from one mode to another. Each time any of these bits are changed (PLLS, IREFS,
CLKS, or EREFS), the corresponding bits in the MCGSC register (PLLST, IREFST, CLKST, or
OSCINIT) must be checked before moving on in the application software.
Additionally, care must be taken to ensure that the reference clock divider (RDIV) is set properly for the
mode being switched to. For instance, in PEE mode, if using a 4 MHz crystal, RDIV must be set to %001
(divide-by-2) or %010 (divide -by-4) in order to divide the external reference down to the required
frequency between 1 and 2 MHz.
The RDIV and IREFS bits should always be set properly before changing the PLLS bit so that the FLL or
PLL clock has an appropriate reference clock frequency to switch to.

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The table below shows MCGOUT frequency calculations using RDIV, BDIV, and VDIV settings for each
clock mode. The bus frequency is equal to MCGOUT divided by 2.
Table 8-6. MCGOUT Frequency Calculation Options

Clock Mode fMCGOUT1 Note

FEI (FLL engaged internal) (fint * 1024 ) / B Typical fMCGOUT = 16 MHz

immediately after reset. RDIV
bits set to %000.

FEE (FLL engaged external) (fext / R *1024) / B fext / R must be in the range of
31.25 kHz to 39.0625 kHz

FBE (FLL bypassed external) fext / B fext / R must be in the range of

31.25 kHz to 39.0625 kHz

FBI (FLL bypassed internal) fint / B Typical fint = 32 kHz

PEE (PLL engaged external) [(fext / R) * M] / B fext / R must be in the range of 1

MHz to 2 MHz

PBE (PLL bypassed external) fext / B fext / R must be in the range of 1

MHz to 2 MHz

BLPI (Bypassed low power internal) fint / B

BLPE (Bypassed low power external) fext / B

1
R is the reference divider selected by the RDIV bits, B is the bus frequency divider selected by the BDIV bits,
and M is the multiplier selected by the VDIV bits.

This section will include 3 mode switching examples using a 4 MHz external crystal. If using an external
clock source less than 1 MHz, the MCG should not be configured for any of the PLL modes (PEE and
PBE).

8.5.2.1 Example # 1: Moving from FEI to PEE Mode: External Crystal = 4 MHz,
Bus Frequency = 8 MHz
In this example, the MCG will move through the proper operational modes from FEI to PEE mode until
the 4 MHz crystal reference frequency is set to achieve a bus frequency of 8 MHz. Because the MCG is in
FEI mode out of reset, this example also shows how to initialize the MCG for PEE mode out of reset. First,
the code sequence will be described. Then a flowchart will be included which illustrates the sequence.
1. First, FEI must transition to FBE mode:
a) MCGC2 = 0x36 (%00110110)
– BDIV (bits 7 and 6) set to %00, or divide-by-1
– RANGE (bit 5) set to 1 because the frequency of 4 MHz is within the high frequency range
– HGO (bit 4) set to 1 to configure external oscillator for high gain operation
– EREFS (bit 2) set to 1, because a crystal is being used
– ERCLKEN (bit 1) set to 1 to ensure the external reference clock is active
b) Loop until OSCINIT (bit 1) in MCGSC is 1, indicating the crystal selected by the EREFS bit
has been initialized.

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 Chapter 8 Multi-Purpose Clock Generator (S08MCGV1)

c) MCGC1 = 0xB8 (%10111000)

– CLKS (bits 7 and 6) set to %10 in order to select external reference clock as system clock
source
– RDIV (bits 5-3) set to %111, or divide-by-128 because 4 MHz / 128 = 31.25 kHz which is
in the 31.25 kHz to 39.0625 kHz range required by the FLL
– IREFS (bit 2) cleared to 0, selecting the external reference clock
d) Loop until IREFST (bit 4) in MCGSC is 0, indicating the external reference is the current
source for the reference clock
e) Loop until CLKST (bits 3 and 2) in MCGSC are %10, indicating that the external reference
clock is selected to feed MCGOUT
2. Then, FBE must transition either directly to PBE mode or first through BLPE mode and then to
PBE mode:
a) BLPE: If a transition through BLPE mode is desired, first set LP (bit 3) in MCGC2 to 1.
b) BLPE/PBE: MCGC1 = 0x90 (%10010000)
– RDIV (bits 5-3) set to %010, or divide-by-4 because 4 MHz / 4 = 1 MHz which is in the 1
MHz to 2 MHz range required by the PLL. In BLPE mode, the configuration of the RDIV
does not matter because both the FLL and PLL are disabled. Changing them only sets up the
the dividers for PLL usage in PBE mode
c) BLPE/PBE: MCGC3 = 0x44 (%01000100)
– PLLS (bit 6) set to 1, selects the PLL. In BLPE mode, changing this bit only prepares the
MCG for PLL usage in PBE mode
– VDIV (bits 3-0) set to %0100, or multiply-by-16 because 1 MHz reference * 16 = 16 MHz.
In BLPE mode, the configuration of the VDIV bits does not matter because the PLL is
disabled. Changing them only sets up the multiply value for PLL usage in PBE mode
d) BLPE: If transitioning through BLPE mode, clear LP (bit 3) in MCGC2 to 0 here to switch to
PBE mode
e) PBE: Loop until PLLST (bit 5) in MCGSC is set, indicating that the current source for the
PLLS clock is the PLL
f) PBE: Then loop until LOCK (bit 6) in MCGSC is set, indicating that the PLL has acquired lock
3. Last, PBE mode transitions into PEE mode:
a) MCGC1 = 0x10 (%00010000)
– CLKS (bits7 and 6) in MCGSC1 set to %00 in order to select the output of the PLL as the
system clock source
– Loop until CLKST (bits 3 and 2) in MCGSC are %11, indicating that the PLL output is
selected to feed MCGOUT in the current clock mode
b) Now, With an RDIV of divide-by-4, a BDIV of divide-by-1, and a VDIV of multiply-by-16,
MCGOUT = [(4 MHz / 4) * 16] / 1 = 16 MHz, and the bus frequency is MCGOUT / 2, or 8 MHz

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Chapter 8 Multi-Purpose Clock Generator (S08MCGV1)

START
IN FEI MODE

MCGC2 = $36

IN
BLPE MODE ? NO
(LP=1)

CHECK NO
OSCINIT = 1 ? YES

MCGC2 = $36
YES (LP = 0)

MCGC1 = $B8

CHECK NO
PLLST = 1?
CHECK NO
IREFST = 0? YES

YES
CHECK NO
LOCK = 1?
CHECK NO
CLKST = %10?
YES

YES MCGC1 = $10

ENTER NO
BLPE MODE ?
CHECK NO
CLKST = %11?
YES

YES
MCGC2 = $3E
(LP = 1)

CONTINUE
IN PEE MODE
MCGC1 = $90
MCGC3 = $44

Figure 8-9. Flowchart of FEI to PEE Mode Transition using a 4 MHz crystal

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142 Freescale Semiconductor
 Chapter 8 Multi-Purpose Clock Generator (S08MCGV1)

8.5.2.2 Example # 2: Moving from PEE to BLPI Mode: External Crystal = 4 MHz,
Bus Frequency =16 kHz
In this example, the MCG will move through the proper operational modes from PEE mode with a 4 MHz
crystal configured for an 8 MHz bus frequency (see previous example) to BLPI mode with a 16 kHz bus
frequency.First, the code sequence will be described. Then a flowchart will be included which illustrates
the sequence.
1. First, PEE must transition to PBE mode:
a) MCGC1 = 0x90 (%10010000)
– CLKS (bits 7 and 6) set to %10 in order to switch the system clock source to the external
reference clock
b) Loop until CLKST (bits 3 and 2) in MCGSC are %10, indicating that the external reference
clock is selected to feed MCGOUT
2. Then, PBE must transition either directly to FBE mode or first through BLPE mode and then to
FBE mode:
a) BLPE: If a transition through BLPE mode is desired, first set LP (bit 3) in MCGC2 to 1
b) BLPE/FBE: MCGC1 = 0xB8 (%10111000)
– RDIV (bits 5-3) set to %111, or divide-by-128 because 4 MHz / 128 = 31.25 kHz which is
in the 31.25 kHz to 39.0625 kHz range required by the FLL. In BLPE mode, the
configuration of the RDIV does not matter because both the FLL and PLL are disabled.
Changing them only sets up the dividers for FLL usage in FBE mode
c) BLPE/FBE: MCGC3 = 0x04 (%00000100)
– PLLS (bit 6) clear to 0 to select the FLL. In BLPE mode, changing this bit only prepares the
MCG for FLL usage in FBE mode. With PLLS = 0, the VDIV value does not matter.
d) BLPE: If transitioning through BLPE mode, clear LP (bit 3) in MCGC2 to 0 here to switch to
FBE mode
e) FBE: Loop until PLLST (bit 5) in MCGSC is clear, indicating that the current source for the
PLLS clock is the FLL
f) FBE: Optionally, loop until LOCK (bit 6) in the MCGSC is set, indicating that the FLL has
acquired lock. Although the FLL is bypassed in FBE mode, it is still enabled and running.
3. Next, FBE mode transitions into FBI mode:
a) MCGC1 = 0x44 (%01000100)
– CLKS (bits7 and 6) in MCGSC1 set to %01 in order to switch the system clock to the
internal reference clock
– IREFS (bit 2) set to 1 to select the internal reference clock as the reference clock source
– RDIV (bits 5-3) set to %000, or divide-by-1 because the trimmed internal reference should
be within the 31.25 kHz to 39.0625 kHz range required by the FLL
b) Loop until IREFST (bit 4) in MCGSC is 1, indicating the internal reference clock has been
selected as the reference clock source
c) Loop until CLKST (bits 3 and 2) in MCGSC are %01, indicating that the internal reference
clock is selected to feed MCGOUT

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4. Lastly, FBI transitions into FBILP mode.

a) MCGC2 = 0x08 (%00001000)
– LP (bit 3) in MCGSC is 1

START
IN PEE MODE

MCGC1 = $90

CHECK NO
PLLST = 0?

CHECK NO
YES
CLKST = %10 ?

YES
OPTIONAL: NO
CHECK LOCK
= 1?
ENTER NO
BLPE MODE ?
YES

MCGC1 = $44
YES

MCGC2 = $3E

CHECK NO
IREFST = 0?
MCGC1 = $B8
MCGC3 = $04 YES

IN CHECK NO
NO
BLPE MODE ? CLKST = %01?
(LP=1)

YES
YES

MCGC2 = $08
MCGC2 = $36
(LP = 0)

CONTINUE
IN BLPI MODE

Figure 8-10. Flowchart of PEE to BLPI Mode Transition using a 4 MHz crystal

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 Chapter 8 Multi-Purpose Clock Generator (S08MCGV1)

8.5.2.3 Example #3: Moving from BLPI to FEE Mode: External Crystal = 4 MHz,
Bus Frequency = 16 MHz
In this example, the MCG will move through the proper operational modes from BLPI mode at a 16 kHz
bus frequency running off of the internal reference clock (see previous example) to FEE mode using a 4
MHz crystal configured for a 16 MHz bus frequency. First, the code sequence will be described. Then a
flowchart will be included which illustrates the sequence.
1. First, BLPI must transition to FBI mode.
a) MCGC2 = 0x00 (%00000000)
– LP (bit 3) in MCGSC is 0
b) Optionally, loop until LOCK (bit 6) in the MCGSC is set, indicating that the FLL has acquired
lock. Although the FLL is bypassed in FBI mode, it is still enabled and running.
2. Next, FBI will transition to FEE mode.
a) MCGC2 = 0x36 (%00110110)
– RANGE (bit 5) set to 1 because the frequency of 4 MHz is within the high frequency range
– HGO (bit 4) set to 1 to configure external oscillator for high gain operation
– EREFS (bit 2) set to 1, because a crystal is being used
– ERCLKEN (bit 1) set to 1 to ensure the external reference clock is active
b) Loop until OSCINIT (bit 1) in MCGSC is 1, indicating the crystal selected by the EREFS bit
has been initialized.
c) MCGC1 = 0x38 (%00111000)
– CLKS (bits 7 and 6) set to %00 in order to select the output of the FLL as system clock
source
– RDIV (bits 5-3) set to %111, or divide-by-128 because 4 MHz / 128 = 31.25 kHz which is
in the 31.25 kHz to 39.0625 kHz range required by the FLL
– IREFS (bit 1) cleared to 0, selecting the external reference clock
d) Loop until IREFST (bit 4) in MCGSC is 0, indicating the external reference clock is the current
source for the reference clock
e) Optionally, loop until LOCK (bit 6) in the MCGSC is set, indicating that the FLL has
reacquired lock.
f) Loop until CLKST (bits 3 and 2) in MCGSC are %00, indicating that the output of the FLL is
selected to feed MCGOUT

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START
IN BLPI MODE
CHECK NO
IREFST = 0?
MCGC2 = $00
YES

OPTIONAL: NO OPTIONAL: NO
CHECK LOCK CHECK LOCK
= 1? = 1?

YES
YES

MCGC2 = $36
CHECK NO
CLKST = %00?

CHECK NO YES
OSCINIT = 1 ?
CONTINUE
YES IN FEE MODE

MCGC1 = $38

Figure 8-11. Flowchart of BLPI to FEE Mode Transition using a 4 MHz crystal

8.5.2.4 Example # 4: Moving from FEI to PEE Mode: External Crystal = 8 MHz,
Bus Frequency = 8 MHz
In this example, the MCG will move through the proper operational modes from FEI to PEE mode until
the 8 MHz crystal reference frequency is set to achieve a bus frequency of 8 MHz.
This example is similar to example number one except that in this case the frequency of the external crystal
is 8 MHz instead of 4 MHz. Special consideration must be taken with this case since there is a period of
time along the way from FEI mode to PEE mode where the FLL operates based on a reference clock with
a frequency that is greater than the maximum allowed for the FLL. This occurs because with an 8 MHz

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 Chapter 8 Multi-Purpose Clock Generator (S08MCGV1)

external crystal and a maximum reference divider factor of 128, the resulting frequency of the reference
clock for the FLL is 62.5 kHz (greater than the 39.0625 kHz maximum allowed).
Care must be taken in the software to minimize the amount of time spent in this state where the FLL is
operating in this condition.
The following code sequence describes how to move from FEI mode to PEE mode until the 8 MHz crystal
reference frequency is set to achieve a bus frequency of 8 MHz. Because the MCG is in FEI mode out of
reset, this example also shows how to initialize the MCG for PEE mode out of reset. First, the code
sequence will be described. Then a flowchart will be included which illustrates the sequence.
1. First, FEI must transition to FBE mode:
a) MCGC2 = 0x36 (%00110110)
– BDIV (bits 7 and 6) set to %00, or divide-by-1
– RANGE (bit 5) set to 1 because the frequency of 8 MHz is within the high frequency range
– HGO (bit 4) set to 1 to configure external oscillator for high gain operation
– EREFS (bit 2) set to 1, because a crystal is being used
– ERCLKEN (bit 1) set to 1 to ensure the external reference clock is active
b) Loop until OSCINIT (bit 1) in MCGSC is 1, indicating the crystal selected by the EREFS bit
has been initialized.
c) Block Interrupts (If applicable by setting the interrupt bit in the CCR).
d) MCGC1 = 0xB8 (%10111000)
– CLKS (bits 7 and 6) set to %10 in order to select external reference clock as system clock
source
– RDIV (bits 5-3) set to %111, or divide-by-128.
NOTE
8 MHz / 128 = 62.5 kHz which is greater than the 31.25 kHz to 39.0625 kHz
range required by the FLL. Therefore after the transition to FBE is
complete, software must progress through to BLPE mode immediately by
setting the LP bit in MCGC2.
– IREFS (bit 2) cleared to 0, selecting the external reference clock
e) Loop until IREFST (bit 4) in MCGSC is 0, indicating the external reference is the current
source for the reference clock
f) Loop until CLKST (bits 3 and 2) in MCGSC are %10, indicating that the external reference
clock is selected to feed MCGOUT
2. Then, FBE mode transitions into BLPE mode:
a) MCGC2 = 0x3E (%00111110)
– LP (bit 3) in MCGC2 to 1 (BLPE mode entered)
NOTE
There must be no extra steps (including interrupts) between steps 1d and 2a.
b) Enable Interrupts (if applicable by clearing the interrupt bit in the CCR).

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c) MCGC1 = 0x98 (%10011000)

– RDIV (bits 5-3) set to %011, or divide-by-8 because 8 MHz / 8= 1 MHz which is in the 1
MHz to 2 MHz range required by the PLL. In BLPE mode, the configuration of the RDIV
does not matter because both the FLL and PLL are disabled. Changing them only sets up the
the dividers for PLL usage in PBE mode
d) MCGC3 = 0x44 (%01000100)
– PLLS (bit 6) set to 1, selects the PLL. In BLPE mode, changing this bit only prepares the
MCG for PLL usage in PBE mode
– VDIV (bits 3-0) set to %0100, or multiply-by-16 because 1 MHz reference * 16 = 16 MHz.
In BLPE mode, the configuration of the VDIV bits does not matter because the PLL is
disabled. Changing them only sets up the multiply value for PLL usage in PBE mode
e) Loop until PLLST (bit 5) in MCGSC is set, indicating that the current source for the PLLS
clock is the PLL
3. Then, BLPE mode transitions into PBE mode:
a) Clear LP (bit 3) in MCGC2 to 0 here to switch to PBE mode
b) Then loop until LOCK (bit 6) in MCGSC is set, indicating that the PLL has acquired lock
4. Last, PBE mode transitions into PEE mode:
a) MCGC1 = 0x18 (%00011000)
– CLKS (bits7 and 6) in MCGSC1 set to %00 in order to select the output of the PLL as the
system clock source
– Loop until CLKST (bits 3 and 2) in MCGSC are %11, indicating that the PLL output is
selected to feed MCGOUT in the current clock mode
b) Now, With an RDIV of divide-by-8, a BDIV of divide-by-1, and a VDIV of multiply-by-16,
MCGOUT = [(8 MHz / 8) * 16] / 1 = 16 MHz, and the bus frequency is MCGOUT / 2, or 8 MHz

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 Chapter 8 Multi-Purpose Clock Generator (S08MCGV1)

START
IN FEI MODE

MCGC2 = $36

CHECK NO
CHECK NO PLLST = 1?
OSCINIT = 1 ?
YES

YES
MCGC2 = $36
(LP = 0)
MCGC1 = $B8

CHECK NO
IREFST = 0? CHECK NO
LOCK = 1?
YES

YES

CHECK NO
CLKST = %10? MCGC1 = $18

YES
CHECK NO
MCGC2 = $3E CLKST = %11?
(LP = 1)

YES
MCGC1 = $98
MCGC3 = $44
CONTINUE
IN PEE MODE

Figure 8-12. Flowchart of FEI to PEE Mode Transition using a 8 MHz crystal

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8.5.3 Calibrating the Internal Reference Clock (IRC)

The IRC is calibrated by writing to the MCGTRM register first, then using the FTRIM bit to “fine tune”
the frequency. We will refer to this total 9-bit value as the trim value, ranging from 0x000 to 0x1FF, where
the FTRIM bit is the LSB.
The trim value after a POR is always 0x100 (MCGTRM = 0x80 and FTRIM = 0). Writing a larger value
will decrease the frequency and smaller values will increase the frequency. The trim value is linear with
the period, except that slight variations in wafer fab processing produce slight non-linearities between trim
value and period. These non-linearities are why an iterative trimming approach to search for the best trim
value is recommended. In example #4 later in this section, this approach will be demonstrated.
After a trim value has been found for a device, this value can be stored in Flash memory to save the value.
If power is removed from the device, the IRC can easily be re-trimmed by copying the saved value from
Flash to the MCG registers. Freescale identifies recommended Flash locations for storing the trim value
for each MCU. Consult the memory map in the data sheet for these locations. On devices that are factory
trimmed, the factory trim value will be stored in these locations.

8.5.3.1 Example #5: Internal Reference Clock Trim

For applications that require a tight frequency tolerance, a trimming procedure is provided that will allow
a very accurate internal clock source. This section outlines one example of trimming the internal oscillator.
Many other possible trimming procedures are valid and can be used.
In the example below, the MCG trim will be calibrated for the 9-bit MCGTRM and FTRIM collective
value. This value will be referred to as TRMVAL.

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 Chapter 8 Multi-Purpose Clock Generator (S08MCGV1)

Initial conditions:
1) Clock supplied from ATE has 500 μs duty period
2) MCG configured for internal reference with 8MHz bus
START TRIM PROCEDURE
TRMVAL = $100
n=1

MEASURE
INCOMING CLOCK WIDTH
(COUNT = # OF BUS CLOCKS / 8)

COUNT < EXPECTED = 500

(RUNNING TOO SLOW)
. COUNT = EXPECTED = 500
CASE STATEMENT

COUNT > EXPECTED = 500

(RUNNING TOO FAST)
TRMVAL = TRMVAL = STORE MCGTRM AND
TRMVAL - 256/ (2**n) TRMVAL + 256/ (2**n) FTRIM VALUES IN
(DECREASING TRMVAL (INCREASING TRMVAL
NON-VOLATILE MEMORY
INCREASES THE FREQUENCY) DECREASES THE FREQUENCY)

CONTINUE
n = n+1

YES
IS n > 9?

NO

Figure 8-13. Trim Procedure

In this particular case, the MCU has been attached to a PCB and the entire assembly is undergoing final
test with automated test equipment. A separate signal or message is provided to the MCU operating under
user provided software control. The MCU initiates a trim procedure as outlined in Figure 8-13 while the
tester supplies a precision reference signal.
If the intended bus frequency is near the maximum allowed for the device, it is recommended to trim using
a reference divider value (RDIV setting) of twice the final value. After the trim procedure is complete, the
reference divider can be restored. This will prevent accidental overshoot of the maximum clock frequency.

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152 Freescale Semiconductor
Chapter 9
Analog Comparator (S08ACMPV3)
9.1 Introduction
The analog comparator module (ACMP) provides a circuit for comparing two analog input voltages or for
comparing one analog input voltage to an internal reference voltage. The comparator circuit is designed to
operate across the full range of the supply voltage (rail-to-rail operation).
All MC9S08EN32 Series MCUs have one analog comparator, ACMP1, in all available packages.
NOTE
MC9S08EN32 Series devices operate at a higher voltage range (2.7 V to
5.5 V) and do not include stop1 mode. Please ignore references to stop1.

9.1.1 ACMP Configuration Information

When using the bandgap reference voltage for input to ACMP+, the user must enable the bandgap buffer
by setting BGBE =1 in SPMSC1 see Section 5.8.7, “System Power Management Status and Control 1
Register (SPMSC1).” For value of bandgap voltage reference see Section A.6, “DC Characteristics.”

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Chapter 9 Analog Comparator (S08ACMPV3)

HCS08 CORE PTA7/PIA7/ADP7/IRQ

PTA6/PIA6/ADP6
PTA5/PIA5/ADP5
CPU

PORT A
PTA4/PIA4/ADP4
ACMP1O
ANALOG COMPARATOR PTA3/PIA3/ADP3/ACMP1O
BKGD/MS ACMP1-
(ACMP1) PTA2/PIA2/ADP2/ACMP1-
BDC BKP ACMP1+
PTA1/PIA1/ADP1/ACMP1+
PTA0/PIA0/ADP0/MCLK
HCS08 SYSTEM CONTROL
PTB7/PIB7
RESETS AND INTERRUPTS PTB6/PIB6
RESET
MODES OF OPERATION PTB5/PIB5

PORT B
POWER MANAGEMENT PTB4/PIB4
PTB3/PIB3/ADP11
8 PTB2/PIB2/ADP10
COP LVD PTB1/PIB1/ADP9
IRQ

ADP7-ADP0 PTB0/PIB0/ADP8
INT IRQ
12-CHANNEL,10-BIT
ADP11-ADP8
ANALOG-TO-DIGITAL
VREFH
CONVERTER (ADC)
VREFL
VDDA
VSSA

TPM1CH3–TPM1CH0
PTD7/PID7
USER FLASH 4-CHANNEL TIMER/PWM 6 PTD6/PID6
MODULE (TPM1) TPM1CLK
MC9S08EN32 = 32K PTD5/PID5/TPM1CH3
MC9S08EN16 = 16K

PORT D
PTD4/PID4/TPM1CH2
PTD3/PID3/TPM1CH1
PTD2/PID2/TPM1CH0
PTD1/PID1
PTD0/PID0
PTE7
PTE6
MISO
USER RAM PTE5/MISO
MOSI
PORT E

MC9S08EN32 = 1 KBYTE SERIAL PERIPHERAL PTE4/MOSI

SPSCK
MC9S08EN16 = 512 BYTES INTERFACE MODULE (SPI) PTE3/SPSCK
SS
PTE2/SS
RxD1
PTE1/RxD1
DEBUG MODULE (DBG) SERIAL COMMUNICATIONS TxD1
PTE0/TxD1
INTERFACE (SCI1)

REAL TIME COUNTER (RTC) PTF5

PORT F

PTF4
VDD PTF3
VDD VOLTAGE PTF2/TPM1CLK
VSS REGULATOR PTF1
VSS PTF0

MULTI-PURPOSE
CLOCK GENERATOR
PORT G

(MCG)
XTAL
PTG1/XTAL
OSCILLATOR (XOSC) EXTAL
PTG0/EXTAL
- VREFH/VREFL internally connected to VDDA/VSSA
- VDD and VSS pins are each internally connected to two pads in 32-pin package - Pin not connected in 32-pin package

Figure 9-1. MC9S08EN32 Block Diagram

MC9S08EN32 Series Data Sheet, Rev. 2

154 Freescale Semiconductor
 Chapter 9 Analog Comparator (S08ACMPV3)

9.1.2 Features
The ACMP has the following features:
• Full rail to rail supply operation.
• Selectable interrupt on rising edge, falling edge, or either rising or falling edges of comparator
output.
• Option to compare to fixed internal bandgap reference voltage.
• Option to allow comparator output to be visible on a pin, ACMP1O.

9.1.3 Modes of Operation

This section defines the ACMP operation in wait, stop, and background debug modes.

9.1.3.1 ACMP in Wait Mode

The ACMP continues to run in wait mode if enabled before executing the appropriate instruction.
Therefore, the ACMP can be used to bring the MCU out of wait mode if the ACMP interrupt is enabled
(ACIE is set). For lowest possible current consumption, the ACMP should be disabled by software if not
required as an interrupt source during wait mode.

9.1.3.2 ACMP in Stop Modes

The ACMP is disabled in all stop modes, regardless of the settings before executing the stop instruction..
Therefore, the ACMP cannot be used as a wake up source from stop modes..
During stop2 mode, the ACMP module is fully powered down. Upon wake-up from stop2 mode, the
ACMP module is in the reset state.
During stop3 mode, clocks to the ACMP module are halted. No registers are affected. In addition, the
ACMP comparator circuit enters a low-power state. No compare operation occurs while in stop3.
If stop3 is exited with a reset, the ACMP is put into its reset state. If stop3 is exited with an interrupt, the
ACMP continues from the state it was in when stop3 was entered.

9.1.3.3 ACMP in Active Background Mode

When the microcontroller is in active background mode, the ACMP continues to operate normally.

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 155
Chapter 9 Analog Comparator (S08ACMPV3)

9.1.4 Block Diagram

The block diagram for the analog comparator module is shown Figure 9-2.

Internal Bus
Internal
Reference ACMP1
INTERRUPT
ACIE REQUEST
ACBGS
Status & Control ACF
ACME
Register
ACOPE

ACMOD

set ACF
ACMP1+

+
Interrupt
Control
-

ACMP1- Comparator

ACMP1O

Figure 9-2. Analog Comparator (ACMP) Block Diagram

9.2 External Signal Description

The ACMP has two analog input pins, ACMP1+ and ACMP1− and one digital output pin ACMP1O. Each
of these pins can accept an input voltage that varies across the full operating voltage range of the MCU.
As shown in Figure 9-2, the ACMP1- pin is connected to the inverting input of the comparator, and the
ACMP1+ pin is connected to the comparator non-inverting input if ACBGS is a 0. As shown in Figure 9-2,
the ACMP1O pin can be enabled to drive an external pin.
The signal properties of ACMP are shown in Table 9-1.
Table 9-1. Signal Properties

Signal Function I/O

ACMP1- Inverting analog input to the ACMP. I

(Minus input)

ACMP1+ Non-inverting analog input to the ACMP. I

(Positive input)

ACMP1O Digital output of the ACMP. O

MC9S08EN32 Series Data Sheet, Rev. 2

156 Freescale Semiconductor
 Chapter 9 Analog Comparator (S08ACMPV3)

9.3 Memory Map/Register Definition

The ACMP includes one register:
• An 8-bit status and control register
Refer to the direct-page register summary in the memory section of this document for the absolute address
assignments for the ACMP register.This section refers to register and control bits only by their names and
relative address offsets.
Some MCUs may have more than one ACMP, so register names include placeholder characters (x) to
identify which ACMP is being referenced.
Table 9-2. ACMP Register Summary

Name 7 6 5 4 3 2 1 0

R ACO
ACMP1SC ACME ACBGS ACF ACIE ACOPE ACMOD
W

9.3.1 ACMP1 Status and Control Register (ACMP1SC)

ACMP1SC contains the status flag and control bits used to enable and configure the ACMP.

7 6 5 4 3 2 1 0

R ACO
ACME ACBGS ACF ACIE ACOPE ACMOD
W

Reset: 0 0 0 0 0 0 0 0

Figure 9-3. ACMP1 Status and Control Register (ACMP1SC)

Table 9-3. ACMP1SC Field Descriptions

Field Description

7 Analog Comparator Module Enable. Enables the ACMP module.

ACME 0 ACMP not enabled
1 ACMP is enabled

6 Analog Comparator Bandgap Select. Selects between the bandgap reference voltage or the ACMP1+ pin as the
ACBGS input to the non-inverting input of the analog comparator.
0 External pin ACMP1+ selected as non-inverting input to comparator
1 Internal reference select as non-inverting input to comparator

5 Analog Comparator Flag. ACF is set when a compare event occurs. Compare events are defined by ACMOD.
ACF ACF is cleared by writing a one to it.
0 Compare event has not occured
1 Compare event has occured

4 Analog Comparator Interrupt Enable. Enables the interrupt from the ACMP. When ACIE is set, an interupt is
ACIE asserted when ACF is set.
0 Interrupt disabled
1 Interrupt enabled

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 157
Chapter 9 Analog Comparator (S08ACMPV3)

Table 9-3. ACMP1SC Field Descriptions (continued)

Field Description

3 Analog Comparator Output. Reading ACO returns the current value of the analog comparator output. ACO is
ACO reset to a 0 and reads as a 0 when the ACMP is disabled (ACME = 0).

2 Analog Comparator Output Pin Enable. Enables the comparator output to be placed onto the external pin,
ACOPE ACMP1O.
0 Analog comparator output not available on ACMP1O
1 Analog comparator output is driven out on ACMP1O

1:0 Analog Comparator Mode. ACMOD selects the type of compare event which sets ACF.
ACMOD 00 Encoding 0 — Comparator output falling edge
01 Encoding 1 — Comparator output rising edge
10 Encoding 2 — Comparator output falling edge
11 Encoding 3 — Comparator output rising or falling edge

9.4 Functional Description

The analog comparator can compare two analog input voltages applied to ACMP1+ and ACMP1−, or it
can compare an analog input voltage applied to ACMP1− with an internal bandgap reference voltage.
ACBGS selects between the bandgap reference voltage or the ACMP1+ pin as the input to the
non-inverting input of the analog comparator. The comparator output is high when the non-inverting input
is greater than the inverting input, and is low when the non-inverting input is less than the inverting input.
ACMOD selects the condition that causes ACF to be set. ACF can be set on a rising edge of the comparator
output, a falling edge of the comparator output, or a rising or a falling edge (toggle). The comparator output
can be read directly through ACO. The comparator output can be driven onto the ACMP1O pin using
ACOPE.

MC9S08EN32 Series Data Sheet, Rev. 2

158 Freescale Semiconductor
Chapter 10
Analog-to-Digital Converter (S08ADC12V1)
10.1 Introduction
The 12-bit analog-to-digital converter (ADC) is a successive approximation ADC designed for operation
within an integrated microcontroller system-on-chip.
NOTE
MC9S08EN32 Series devices operate at a higher voltage range (2.7 V to
5.5 V) and do not include stop1 mode. Please ignore references to stop1.

10.1.1 Analog Power and Ground Signal Names

References to VDDAD and VSSAD in this chapter correspond to signals VDDA and VSSA, respectively.

10.1.2 Channel Assignments

NOTE
The ADC channel assignments for the MC9S08EN32 Series devices are
shown in Table 10-1. Reserved channels convert to an unknown value.
This chapter shows bits for all S08ADC12V1 channels. MC9S08EN32
Series MCUs do not use all of these channels. All bits corresponding to
channels that are not available on a device are reserved.

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 159
Chapter 10 Analog-to-Digital Converter (S08ADC12V1)

Table 10-1. ADC Channel Assignment

ADCH Channel Input ADCH Channel Input

00000 AD0 PTA0/ADP0/MCLK 01010 AD10 PTB2/ADP10

00001 AD1 PTA1/ADP1/ACMP1+ 01011 AD11 PTB3/ADP11
00010 AD2 PTA2/ADP2/ACMP1P- 01100– AD12 through AD25 Reserved
00011 AD3 PTA3/ADP3/ACMP1O 11001
00100 AD4 PTA4/ADP4 11010 AD26 Temperature Sensor1
00101 AD5 PTA5/ADP5 11011 AD27 Internal Bandgap2
00110 AD6 PTA6/ADP6 11100 Reserved Reserved
00111 AD7 PTA7/ADP7 11101 VREFH VREFH
01000 AD8 PTB0/ADP8 11110 VREFL VREFL
01001 AD9 PTB1/ADP9 11111 Module Disabled None

Notes:
1 For information, see Section 10.1.5, “Temperature Sensor”.
2 Requires BGBE =1 in SPMSC1 see Section 5.8.8, “System Power Management Status and Control 2 Register
(SPMSC2)”. For value of bandgap voltage reference see A.6, “DC Characteristics”.

10.1.3 Alternate Clock

The ADC module is capable of performing conversions using the MCU bus clock, the bus clock divided
by two, the local asynchronous clock (ADACK) within the module, or the alternate clock, ALTCLK. The
alternate clock for the MC9S08EN32 Series MCU devices is the external reference clock (MCGERCLK).
The selected clock source must run at a frequency such that the ADC conversion clock (ADCK) runs at a
frequency within its specified range (fADCK) after being divided down from the ALTCLK input as
determined by the ADIV bits.
ALTCLK is active while the MCU is in wait mode provided the conditions described above are met. This
allows ALTCLK to be used as the conversion clock source for the ADC while the MCU is in wait mode.
ALTCLK cannot be used as the ADC conversion clock source while the MCU is in either stop2 or stop3.

10.1.4 Hardware Trigger

The ADC hardware trigger, ADHWT, is the output from the real time counter (RTC). The RTC counter
can be clocked by either MCGERCLK or a nominal 1 kHz clock source.

MC9S08EN32 Series Data Sheet, Rev. 2

160 Freescale Semiconductor
 Chapter 10 Analog-to-Digital Converter (S08ADC12V1)

The period of the RTC is determined by the input clock frequency, the RTCPS bits, and the RTCMOD
register. When the ADC hardware trigger is enabled, a conversion is initiated upon an RTC counter
overflow.
The RTC can be configured to cause a hardware trigger in MCU run, wait, and stop3.

10.1.5 Temperature Sensor

To use the on-chip temperature sensor, the user must perform the following:
• Configure ADC for long sample with a maximum of 1 MHz clock
• Convert the bandgap voltage reference channel (AD27)
— By converting the digital value of the bandgap voltage reference channel using the value of
VBG the user can determine VDD. For value of bandgap voltage, see Section A.6, “DC
Characteristics”.
• Convert the temperature sensor channel (AD26)
— By using the calculated value of VDD, convert the digital value of AD26 into a voltage, VTEMP
Equation 10-1 provides an approximate transfer function of the temperature sensor.

Temp = 25 - ((VTEMP -VTEMP25) ÷ m) Eqn. 10-1

where:
— VTEMP is the voltage of the temperature sensor channel at the ambient temperature.
— VTEMP25 is the voltage of the temperature sensor channel at 25°C.
— m is the hot or cold voltage versus temperature slope in V/°C.
For temperature calculations, use the VTEMP25 and m values from the ADC Electricals table.
In application code, the user reads the temperature sensor channel, calculates VTEMP, and compares to
VTEMP25 . If VTEMP is greater than VTEMP25 the cold slope value is applied in Equation 10-1. If VTEMP is
less than VTEMP25 the hot slope value is applied in Equation 10-1. To improve accuracy the user should
calibrate the bandgap voltage reference and temperature sensor.
Calibrating at 25°C will improve accuracy to ± 4.5°C.
Calibration at three points, -40°C, 25°C, and 125°C will improve accuracy to ± 2.5°C. Once calibration
has been completed, the user will need to calculate the slope for both hot and cold. In application code, the
user would then calculate the temperature using Equation 10-1 as detailed above and then determine if the
temperature is above or below 25°C. Once determined if the temperature is above or below 25°C, the user
can recalculate the temperature using the hot or cold slope value obtained during calibration.

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 161
Chapter 10 Analog-to-Digital Converter (S08ADC12V1)

HCS08 CORE PTA7/PIA7/ADP7/IRQ

PTA6/PIA6/ADP6
PTA5/PIA5/ADP5
CPU

PORT A
PTA4/PIA4/ADP4
ACMP1O
ANALOG COMPARATOR PTA3/PIA3/ADP3/ACMP1O
BKGD/MS ACMP1-
(ACMP1) PTA2/PIA2/ADP2/ACMP1-
BDC BKP ACMP1+
PTA1/PIA1/ADP1/ACMP1+
PTA0/PIA0/ADP0/MCLK
HCS08 SYSTEM CONTROL
PTB7/PIB7
RESETS AND INTERRUPTS PTB6/PIB6
RESET
MODES OF OPERATION PTB5/PIB5

PORT B
POWER MANAGEMENT PTB4/PIB4
PTB3/PIB3/ADP11
8 PTB2/PIB2/ADP10
COP LVD PTB1/PIB1/ADP9
IRQ

ADP7-ADP0 PTB0/PIB0/ADP8
INT IRQ
12-CHANNEL,10-BIT
ADP11-ADP8
ANALOG-TO-DIGITAL
VREFH
CONVERTER (ADC)
VREFL
VDDA
VSSA

TPM1CH3–TPM1CH0
PTD7/PID7
USER FLASH 4-CHANNEL TIMER/PWM 6 PTD6/PID6
MODULE (TPM1) TPM1CLK
MC9S08EN32 = 32K PTD5/PID5/TPM1CH3
MC9S08EN16 = 16K

PORT D
PTD4/PID4/TPM1CH2
PTD3/PID3/TPM1CH1
PTD2/PID2/TPM1CH0
PTD1/PID1
PTD0/PID0
PTE7
PTE6
MISO
USER RAM PTE5/MISO
MOSI
PORT E

MC9S08EN32 = 1 KBYTE SERIAL PERIPHERAL PTE4/MOSI

SPSCK
MC9S08EN16 = 512 BYTES INTERFACE MODULE (SPI) PTE3/SPSCK
SS
PTE2/SS
RxD1
PTE1/RxD1
DEBUG MODULE (DBG) SERIAL COMMUNICATIONS TxD1
PTE0/TxD1
INTERFACE (SCI1)

REAL TIME COUNTER (RTC) PTF5

PORT F

PTF4
VDD PTF3
VDD VOLTAGE PTF2/TPM1CLK
VSS REGULATOR PTF1
VSS PTF0

MULTI-PURPOSE
CLOCK GENERATOR
PORT G

(MCG)
XTAL
PTG1/XTAL
OSCILLATOR (XOSC) EXTAL
PTG0/EXTAL
- VREFH/VREFL internally connected to VDDA/VSSA
- VDD and VSS pins are each internally connected to two pads in 32-pin package - Pin not connected in 32-pin package

Figure 10-1. MC9S08EN32 Block Diagram Emphasizing the ADC Module and Pins

MC9S08EN32 Series Data Sheet, Rev. 2

162 Freescale Semiconductor
 Chapter 10 Analog-to-Digital Converter (S08ADC12V1)

10.1.6 Features
Features of the ADC module include:
• Linear successive approximation algorithm with 12 bits resolution.
• Up to 28 analog inputs.
• Output formatted in 12-, 10- or 8-bit right-justified format.
• Single or continuous conversion (automatic return to idle after single conversion).
• Configurable sample time and conversion speed/power.
• Conversion complete flag and interrupt.
• Input clock selectable from up to four sources.
• Operation in wait or stop3 modes for lower noise operation.
• Asynchronous clock source for lower noise operation.
• Selectable asynchronous hardware conversion trigger.
• Automatic compare with interrupt for less-than, or greater-than or equal-to, programmable value.

10.1.7 Block Diagram

Figure 10-2 provides a block diagram of the ADC module

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 163
Chapter 10 Analog-to-Digital Converter (S08ADC12V1)

Compare true
3 ADCSC1 ADCCFG

COCO
AIEN

ADLSMP
complete

ADICLK
ADTRG

ADLPC
MODE
ADCO
ADCH

ADIV
Async
1 2 Clock Gen

ADACK

MCU STOP ADCK

Bus Clock
Clock
ADHWT Control Sequencer Divide
÷2
ALTCLK

initialize
sample

convert
transfer
abort
AD0
AIEN 1
•••

Interrupt
ADVIN COCO 2
SAR Converter
AD27

VREFH Data Registers

VREFL
Sum

Compare true
3
Compare
Logic
Value

ACFGT

Compare Value Registers ADCSC2

Figure 10-2. ADC Block Diagram

10.2 External Signal Description

The ADC module supports up to 28 separate analog inputs. It also requires four supply/reference/ground
connections.

Table 10-2. Signal Properties

Name Function

AD27–AD0 Analog Channel inputs

VREFH High reference voltage
VREFL Low reference voltage
VDDAD Analog power supply
VSSAD Analog ground

MC9S08EN32 Series Data Sheet, Rev. 2

164 Freescale Semiconductor
 Chapter 10 Analog-to-Digital Converter (S08ADC12V1)

10.2.1 Analog Power (VDDAD)

The ADC analog portion uses VDDAD as its power connection. In some packages, VDDAD is connected
internally to VDD. If externally available, connect the VDDAD pin to the same voltage potential as VDD.
External filtering may be necessary to ensure clean VDDAD for good results.

10.2.2 Analog Ground (VSSAD)

The ADC analog portion uses VSSAD as its ground connection. In some packages, VSSAD is connected
internally to VSS. If externally available, connect the VSSAD pin to the same voltage potential as VSS.

10.2.3 Voltage Reference High (VREFH)

VREFH is the high reference voltage for the converter. In some packages, VREFH is connected internally to
VDDAD. If externally available, VREFH may be connected to the same potential as VDDAD, or may be
driven by an external source that is between the minimum VDDAD spec and the VDDAD potential (VREFH
must never exceed VDDAD).

10.2.4 Voltage Reference Low (VREFL)

VREFL is the low reference voltage for the converter. In some packages, VREFL is connected internally to
VSSAD. If externally available, connect the VREFL pin to the same voltage potential as VSSAD.

10.2.5 Analog Channel Inputs (ADx)

The ADC module supports up to 28 separate analog inputs. An input is selected for conversion through the
ADCH channel select bits.

10.3 Register Definition

These memory mapped registers control and monitor operation of the ADC:
• Status and control register, ADCSC1
• Status and control register, ADCSC2
• Data result registers, ADCRH and ADCRL
• Compare value registers, ADCCVH and ADCCVL
• Configuration register, ADCCFG
• Pin enable registers, APCTL1, APCTL2, APCTL3

10.3.1 Status and Control Register 1 (ADCSC1)

This section describes the function of the ADC status and control register (ADCSC1). Writing ADCSC1
aborts the current conversion and initiates a new conversion (if the ADCH bits are equal to a value other
than all 1s).

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 165
Chapter 10 Analog-to-Digital Converter (S08ADC12V1)

7 6 5 4 3 2 1 0

R COCO
AIEN ADCO ADCH
W

Reset: 0 0 0 1 1 1 1 1

= Unimplemented or Reserved

Figure 10-3. Status and Control Register (ADCSC1)

Table 10-3. ADCSC1 Register Field Descriptions

Field Description

7 Conversion Complete Flag — The COCO flag is a read-only bit which is set each time a conversion is
COCO completed when the compare function is disabled (ACFE = 0). When the compare function is enabled (ACFE =
1) the COCO flag is set upon completion of a conversion only if the compare result is true. This bit is cleared
whenever ADCSC1 is written or whenever ADCRL is read.
0 Conversion not completed
1 Conversion completed

6 Interrupt Enable — AIEN is used to enable conversion complete interrupts. When COCO becomes set while
AIEN AIEN is high, an interrupt is asserted.
0 Conversion complete interrupt disabled
1 Conversion complete interrupt enabled

5 Continuous Conversion Enable — ADCO is used to enable continuous conversions.

ADCO 0 One conversion following a write to the ADCSC1 when software triggered operation is selected, or one
conversion following assertion of ADHWT when hardware triggered operation is selected.
1 Continuous conversions initiated following a write to ADCSC1 when software triggered operation is selected.
Continuous conversions are initiated by an ADHWT event when hardware triggered operation is selected.

4:0 Input Channel Select — The ADCH bits form a 5-bit field which is used to select one of the input channels. The
ADCH input channels are detailed in Figure 10-4.
The successive approximation converter subsystem is turned off when the channel select bits are all set to 1.
This feature allows for explicit disabling of the ADC and isolation of the input channel from all sources.
Terminating continuous conversions this way will prevent an additional, single conversion from being performed.
It is not necessary to set the channel select bits to all 1s to place the ADC in a low-power state when continuous
conversions are not enabled because the module automatically enters a low-power state when a conversion
completes.

Figure 10-4. Input Channel Select

ADCH Input Select ADCH Input Select

00000 AD0 10000 AD16

00001 AD1 10001 AD17
00010 AD2 10010 AD18
00011 AD3 10011 AD19
00100 AD4 10100 AD20
00101 AD5 10101 AD21
00110 AD6 10110 AD22
00111 AD7 10111 AD23

MC9S08EN32 Series Data Sheet, Rev. 2

166 Freescale Semiconductor
 Chapter 10 Analog-to-Digital Converter (S08ADC12V1)

Figure 10-4. Input Channel Select (continued)

ADCH Input Select ADCH Input Select

01000 AD8 11000 AD24

01001 AD9 11001 AD25
01010 AD10 11010 AD26
01011 AD11 11011 AD27
01100 AD12 11100 Reserved
01101 AD13 11101 VREFH
01110 AD14 11110 VREFL
01111 AD15 11111 Module disabled

10.3.2 Status and Control Register 2 (ADCSC2)

The ADCSC2 register is used to control the compare function, conversion trigger and conversion active of
the ADC module.

7 6 5 4 3 2 1 0

R ADACT 0 0
ADTRG ACFE ACFGT R1 R1
W

Reset: 0 0 0 0 0 0 0 0

= Unimplemented or Reserved

1
Bits 1 and 0 are reserved bits that must always be written to 0.

Figure 10-5. Status and Control Register 2 (ADCSC2)

Table 10-4. ADCSC2 Register Field Descriptions

Field Description

7 Conversion Active — ADACT indicates that a conversion is in progress. ADACT is set when a conversion is
ADACT initiated and cleared when a conversion is completed or aborted.
0 Conversion not in progress
1 Conversion in progress

6 Conversion Trigger Select — ADTRG is used to select the type of trigger to be used for initiating a conversion.
ADTRG Two types of trigger are selectable: software trigger and hardware trigger. When software trigger is selected, a
conversion is initiated following a write to ADCSC1. When hardware trigger is selected, a conversion is initiated
following the assertion of the ADHWT input.
0 Software trigger selected
1 Hardware trigger selected

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Freescale Semiconductor 167
Chapter 10 Analog-to-Digital Converter (S08ADC12V1)

Table 10-4. ADCSC2 Register Field Descriptions (continued)

Field Description

5 Compare Function Enable — ACFE is used to enable the compare function.

ACFE 0 Compare function disabled
1 Compare function enabled

4 Compare Function Greater Than Enable — ACFGT is used to configure the compare function to trigger when
ACFGT the result of the conversion of the input being monitored is greater than or equal to the compare value. The
compare function defaults to triggering when the result of the compare of the input being monitored is less than
the compare value.
0 Compare triggers when input is less than compare level
1 Compare triggers when input is greater than or equal to compare level

10.3.3 Data Result High Register (ADCRH)

In 12-bit operation, ADCRH contains the upper four bits of the result of a 12-bit conversion.

7 6 5 4 3 2 1 0

R 0 0 0 0 ADR11 ADR10 ADR9 ADR8

Reset: 0 0 0 0 0 0 0 0

= Unimplemented or Reserved

Figure 10-6. Data Result High Register (ADCRH)

In 10-bit mode, ADCRH contains the upper two bits of the result of a 10-bit conversion. When configured
for 10-bit mode, ADR11 – ADR10 are equal to zero. When configured for 8-bit mode, ADR11 – ADR8
are equal to zero.
In both 12-bit and 10-bit mode, ADCRH is updated each time a conversion completes except when
automatic compare is enabled and the compare condition is not met. In 12-bit and 10-bit mode, reading
ADCRH prevents the ADC from transferring subsequent conversion results into the result registers until
ADCRL is read. If ADCRL is not read until after the next conversion is completed, then the intermediate
conversion result is lost. In 8-bit mode there is no interlocking with ADCRL.

In the case that the MODE bits are changed, any data in ADCRH becomes invalid.

10.3.4 Data Result Low Register (ADCRL)

ADCRL contains the lower eight bits of the result of a 12-bit or 10-bit conversion, and all eight bits of an
8-bit conversion. This register is updated each time a conversion completes except when automatic
compare is enabled and the compare condition is not met. In 12-bit and 10-bit mode, reading ADCRH
prevents the ADC from transferring subsequent conversion results into the result registers until ADCRL is
read. If ADCRL is not read until the after next conversion is completed, then the intermediate conversion
results will be lost. In 8-bit mode, there is no interlocking with ADCRH. In the case that the MODE bits
are changed, any data in ADCRL becomes invalid.

MC9S08EN32 Series Data Sheet, Rev. 2

168 Freescale Semiconductor
 Chapter 10 Analog-to-Digital Converter (S08ADC12V1)

7 6 5 4 3 2 1 0

R ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0

Reset: 0 0 0 0 0 0 0 0

= Unimplemented or Reserved

Figure 10-7. Data Result Low Register (ADCRL)

10.3.5 Compare Value High Register (ADCCVH)

In 12-bit mode, the ADCCVH register holds the upper four bits of the 12-bit compare value. These bits are
compared to the upper four bits of the result following a conversion in 12-bit mode when the compare
function is enabled.

7 6 5 4 3 2 1 0

R 0 0 0 0
ADCV11 ADCV10 ADCV9 ADCV8
W

Reset: 0 0 0 0 0 0 0 0

= Unimplemented or Reserved

Figure 10-8. Compare Value High Register (ADCCVH)

In 10-bit mode, the ADCCVH register holds the upper two bits of the 10-bit compare value (ADCV9 –
ADCV8). These bits are compared to the upper two bits of the result following a conversion in 10-bit mode
when the compare function is enabled.
In 8-bit mode, ADCCVH is not used during compare.

10.3.6 Compare Value Low Register (ADCCVL)

This register holds the lower 8 bits of the 12-bit or 10-bit compare value, or all 8 bits of the 8-bit compare
value. Bits ADCV7:ADCV0 are compared to the lower 8 bits of the result following a conversion in 12-bit,
10-bit or 8-bit mode.

7 6 5 4 3 2 1 0

R
ADCV7 ADCV6 ADCV5 ADCV4 ADCV3 ADCV2 ADCV1 ADCV0
W

Reset: 0 0 0 0 0 0 0 0

Figure 10-9. Compare Value Low Register(ADCCVL)

10.3.7 Configuration Register (ADCCFG)

ADCCFG is used to select the mode of operation, clock source, clock divide, and configure for low power
or long sample time.

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7 6 5 4 3 2 1 0

R
ADLPC ADIV ADLSMP MODE ADICLK
W

Reset: 0 0 0 0 0 0 0 0

Figure 10-10. Configuration Register (ADCCFG)

Table 10-5. ADCCFG Register Field Descriptions

Field Description

7 Low Power Configuration — ADLPC controls the speed and power configuration of the successive
ADLPC approximation converter. This is used to optimize power consumption when higher sample rates are not required.
0 High speed configuration
1 Low power configuration: {FC31}The power is reduced at the expense of maximum clock speed.

6:5 Clock Divide Select — ADIV select the divide ratio used by the ADC to generate the internal clock ADCK.
ADIV Table 10-6 shows the available clock configurations.

4 Long Sample Time Configuration — ADLSMP selects between long and short sample time. This adjusts the
ADLSMP sample period to allow higher impedance inputs to be accurately sampled or to maximize conversion speed for
lower impedance inputs. Longer sample times can also be used to lower overall power consumption when
continuous conversions are enabled if high conversion rates are not required.
0 Short sample time
1 Long sample time

3:2 Conversion Mode Selection — MODE bits are used to select between 12-, 10- or 8-bit operation. See
MODE Table 10-7.

1:0 Input Clock Select — ADICLK bits select the input clock source to generate the internal clock ADCK. See
ADICLK Table 10-8.

Table 10-6. Clock Divide Select

ADIV Divide Ratio Clock Rate

00 1 Input clock
01 2 Input clock ÷ 2
10 4 Input clock ÷ 4
11 8 Input clock ÷ 8

Table 10-7. Conversion Modes

MODE Mode Description

00 8-bit conversion (N=8)
01 12-bit conversion (N=12)
10 10-bit conversion (N=10)
11 Reserved

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Table 10-8. Input Clock Select

ADICLK Selected Clock Source

00 Bus clock
01 Bus clock divided by 2
10 Alternate clock (ALTCLK)
11 Asynchronous clock (ADACK)

10.3.8 Pin Control 1 Register (APCTL1)

The pin control registers are used to disable the I/O port control of MCU pins used as analog inputs.
APCTL1 is used to control the pins associated with channels 0–7 of the ADC module.
7 6 5 4 3 2 1 0

R
ADPC7 ADPC6 ADPC5 ADPC4 ADPC3 ADPC2 ADPC1 ADPC0
W

Reset: 0 0 0 0 0 0 0 0

Figure 10-11. Pin Control 1 Register (APCTL1)

Table 10-9. APCTL1 Register Field Descriptions

Field Description

7 ADC Pin Control 7 — ADPC7 is used to control the pin associated with channel AD7.
ADPC7 0 AD7 pin I/O control enabled
1 AD7 pin I/O control disabled

6 ADC Pin Control 6 — ADPC6 is used to control the pin associated with channel AD6.
ADPC6 0 AD6 pin I/O control enabled
1 AD6 pin I/O control disabled

5 ADC Pin Control 5 — ADPC5 is used to control the pin associated with channel AD5.
ADPC5 0 AD5 pin I/O control enabled
1 AD5 pin I/O control disabled

4 ADC Pin Control 4 — ADPC4 is used to control the pin associated with channel AD4.
ADPC4 0 AD4 pin I/O control enabled
1 AD4 pin I/O control disabled

3 ADC Pin Control 3 — ADPC3 is used to control the pin associated with channel AD3.
ADPC3 0 AD3 pin I/O control enabled
1 AD3 pin I/O control disabled

2 ADC Pin Control 2 — ADPC2 is used to control the pin associated with channel AD2.
ADPC2 0 AD2 pin I/O control enabled
1 AD2 pin I/O control disabled

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Table 10-9. APCTL1 Register Field Descriptions (continued)

Field Description

1 ADC Pin Control 1 — ADPC1 is used to control the pin associated with channel AD1.
ADPC1 0 AD1 pin I/O control enabled
1 AD1 pin I/O control disabled

0 ADC Pin Control 0 — ADPC0 is used to control the pin associated with channel AD0.
ADPC0 0 AD0 pin I/O control enabled
1 AD0 pin I/O control disabled

10.3.9 Pin Control 2 Register (APCTL2)

APCTL2 is used to control channels 8–15 of the ADC module.

7 6 5 4 3 2 1 0

R
ADPC15 ADPC14 ADPC13 ADPC12 ADPC11 ADPC10 ADPC9 ADPC8
W

Reset: 0 0 0 0 0 0 0 0

Figure 10-12. Pin Control 2 Register (APCTL2)

Table 10-10. APCTL2 Register Field Descriptions

Field Description

7 ADC Pin Control 15 — ADPC15 is used to control the pin associated with channel AD15.
ADPC15 0 AD15 pin I/O control enabled
1 AD15 pin I/O control disabled

6 ADC Pin Control 14 — ADPC14 is used to control the pin associated with channel AD14.
ADPC14 0 AD14 pin I/O control enabled
1 AD14 pin I/O control disabled

5 ADC Pin Control 13 — ADPC13 is used to control the pin associated with channel AD13.
ADPC13 0 AD13 pin I/O control enabled
1 AD13 pin I/O control disabled

4 ADC Pin Control 12 — ADPC12 is used to control the pin associated with channel AD12.
ADPC12 0 AD12 pin I/O control enabled
1 AD12 pin I/O control disabled

3 ADC Pin Control 11 — ADPC11 is used to control the pin associated with channel AD11.
ADPC11 0 AD11 pin I/O control enabled
1 AD11 pin I/O control disabled

2 ADC Pin Control 10 — ADPC10 is used to control the pin associated with channel AD10.
ADPC10 0 AD10 pin I/O control enabled
1 AD10 pin I/O control disabled

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Table 10-10. APCTL2 Register Field Descriptions (continued)

Field Description

1 ADC Pin Control 9 — ADPC9 is used to control the pin associated with channel AD9.
ADPC9 0 AD9 pin I/O control enabled
1 AD9 pin I/O control disabled

0 ADC Pin Control 8 — ADPC8 is used to control the pin associated with channel AD8.
ADPC8 0 AD8 pin I/O control enabled
1 AD8 pin I/O control disabled

10.3.10 Pin Control 3 Register (APCTL3)

APCTL3 is used to control channels 16–23 of the ADC module.

7 6 5 4 3 2 1 0

R
ADPC23 ADPC22 ADPC21 ADPC20 ADPC19 ADPC18 ADPC17 ADPC16
W

Reset: 0 0 0 0 0 0 0 0

Figure 10-13. Pin Control 3 Register (APCTL3)

Table 10-11. APCTL3 Register Field Descriptions

Field Description

7 ADC Pin Control 23 — ADPC23 is used to control the pin associated with channel AD23.
ADPC23 0 AD23 pin I/O control enabled
1 AD23 pin I/O control disabled

6 ADC Pin Control 22 — ADPC22 is used to control the pin associated with channel AD22.
ADPC22 0 AD22 pin I/O control enabled
1 AD22 pin I/O control disabled

5 ADC Pin Control 21 — ADPC21 is used to control the pin associated with channel AD21.
ADPC21 0 AD21 pin I/O control enabled
1 AD21 pin I/O control disabled

4 ADC Pin Control 20 — ADPC20 is used to control the pin associated with channel AD20.
ADPC20 0 AD20 pin I/O control enabled
1 AD20 pin I/O control disabled

3 ADC Pin Control 19 — ADPC19 is used to control the pin associated with channel AD19.
ADPC19 0 AD19 pin I/O control enabled
1 AD19 pin I/O control disabled

2 ADC Pin Control 18 — ADPC18 is used to control the pin associated with channel AD18.
ADPC18 0 AD18 pin I/O control enabled
1 AD18 pin I/O control disabled

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Table 10-11. APCTL3 Register Field Descriptions (continued)

Field Description

1 ADC Pin Control 17 — ADPC17 is used to control the pin associated with channel AD17.
ADPC17 0 AD17 pin I/O control enabled
1 AD17 pin I/O control disabled

0 ADC Pin Control 16 — ADPC16 is used to control the pin associated with channel AD16.
ADPC16 0 AD16 pin I/O control enabled
1 AD16 pin I/O control disabled

10.4 Functional Description

The ADC module is disabled during reset or when the ADCH bits are all high. The module is idle when a
conversion has completed and another conversion has not been initiated. When idle, the module is in its
lowest power state.
The ADC can perform an analog-to-digital conversion on any of the software selectable channels. In 12-bit
and 10-bit mode, the selected channel voltage is converted by a successive approximation algorithm into
a 12-bit digital result. In 8-bit mode, the selected channel voltage is converted by a successive
approximation algorithm into a 9-bit digital result.
When the conversion is completed, the result is placed in the data registers (ADCRH and ADCRL). In
10-bit mode, the result is rounded to 10 bits and placed in the data registers (ADCRH and ADCRL). In
8-bit mode, the result is rounded to 8 bits and placed in ADCRL. The conversion complete flag (COCO)
is then set and an interrupt is generated if the conversion complete interrupt has been enabled (AIEN = 1).
The ADC module has the capability of automatically comparing the result of a conversion with the
contents of its compare registers. The compare function is enabled by setting the ACFE bit and operates
in conjunction with any of the conversion modes and configurations.

10.4.1 Clock Select and Divide Control

One of four clock sources can be selected as the clock source for the ADC module. This clock source is
then divided by a configurable value to generate the input clock to the converter (ADCK). The clock is
selected from one of the following sources by means of the ADICLK bits.
• The bus clock, which is equal to the frequency at which software is executed. This is the default
selection following reset.
• The bus clock divided by 2. For higher bus clock rates, this allows a maximum divide by 16 of the
bus clock.
• ALTCLK, as defined for this MCU (See module section introduction).
• The asynchronous clock (ADACK) – This clock is generated from a clock source within the ADC
module. When selected as the clock source this clock remains active while the MCU is in wait or
stop3 mode and allows conversions in these modes for lower noise operation.
Whichever clock is selected, its frequency must fall within the specified frequency range for ADCK. If the
available clocks are too slow, the ADC will not perform according to specifications. If the available clocks

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are too fast, then the clock must be divided to the appropriate frequency. This divider is specified by the
ADIV bits and can be divide-by 1, 2, 4, or 8.

10.4.2 Input Select and Pin Control

The pin control registers (APCTL3, APCTL2, and APCTL1) are used to disable the I/O port control of the
pins used as analog inputs.When a pin control register bit is set, the following conditions are forced for the
associated MCU pin:
• The output buffer is forced to its high impedance state.
• The input buffer is disabled. A read of the I/O port returns a zero for any pin with its input buffer
disabled.
• The pullup is disabled.

10.4.3 Hardware Trigger

The ADC module has a selectable asynchronous hardware conversion trigger, ADHWT, that is enabled
when the ADTRG bit is set. This source is not available on all MCUs. Consult the module introduction for
information on the ADHWT source specific to this MCU.
When ADHWT source is available and hardware trigger is enabled (ADTRG=1), a conversion is initiated
on the rising edge of ADHWT. If a conversion is in progress when a rising edge occurs, the rising edge is
ignored. In continuous convert configuration, only the initial rising edge to launch continuous conversions
is observed. The hardware trigger function operates in conjunction with any of the conversion modes and
configurations.

10.4.4 Conversion Control

Conversions can be performed in 12-bit mode, 10-bit mode or 8-bit mode as determined by the MODE
bits. Conversions can be initiated by either a software or hardware trigger. In addition, the ADC module
can be configured for low power operation, long sample time, continuous conversion, and automatic
compare of the conversion result to a software determined compare value.

10.4.4.1 Initiating Conversions

A conversion is initiated:
• Following a write to ADCSC1 (with ADCH bits not all 1s) if software triggered operation is
selected.
• Following a hardware trigger (ADHWT) event if hardware triggered operation is selected.
• Following the transfer of the result to the data registers when continuous conversion is enabled.
If continuous conversions are enabled a new conversion is automatically initiated after the completion of
the current conversion. In software triggered operation, continuous conversions begin after ADCSC1 is
written and continue until aborted. In hardware triggered operation, continuous conversions begin after a
hardware trigger event and continue until aborted.

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10.4.4.2 Completing Conversions

A conversion is completed when the result of the conversion is transferred into the data result registers,
ADCRH and ADCRL. This is indicated by the setting of COCO. An interrupt is generated if AIEN is high
at the time that COCO is set.
A blocking mechanism prevents a new result from overwriting previous data in ADCRH and ADCRL if
the previous data is in the process of being read while in 12-bit or 10-bit MODE (the ADCRH register has
been read but the ADCRL register has not). When blocking is active, the data transfer is blocked, COCO
is not set, and the new result is lost. In the case of single conversions with the compare function enabled
and the compare condition false, blocking has no effect and ADC operation is terminated. In all other cases
of operation, when a data transfer is blocked, another conversion is initiated regardless of the state of
ADCO (single or continuous conversions enabled).
If single conversions are enabled, the blocking mechanism could result in several discarded conversions
and excess power consumption. To avoid this issue, the data registers must not be read after initiating a
single conversion until the conversion completes.

10.4.4.3 Aborting Conversions

Any conversion in progress will be aborted when:
• A write to ADCSC1 occurs (the current conversion will be aborted and a new conversion will be
initiated, if ADCH are not all 1s).
• A write to ADCSC2, ADCCFG, ADCCVH, or ADCCVL occurs. This indicates a mode of
operation change has occurred and the current conversion is therefore invalid.
• The MCU is reset.
• The MCU enters stop mode with ADACK not enabled.
When a conversion is aborted, the contents of the data registers, ADCRH and ADCRL, are not altered but
continue to be the values transferred after the completion of the last successful conversion. In the case that
the conversion was aborted by a reset, ADCRH and ADCRL return to their reset states.

10.4.4.4 Power Control

The ADC module remains in its idle state until a conversion is initiated. If ADACK is selected as the
conversion clock source, the ADACK clock generator is also enabled.
Power consumption when active can be reduced by setting ADLPC. This results in a lower maximum value
for fADCK (see the electrical specifications).

10.4.4.5 Sample Time and Total Conversion Time

The total conversion time depends on the sample time (as determined by ADLSMP), the MCU bus
frequency, the conversion mode (8-bit, 10-bit or 12-bit), and the frequency of the conversion clock (fADCK).
After the module becomes active, sampling of the input begins. ADLSMP is used to select between short
(3.5 ADCK cycles) and long (23.5 ADCK cycles) sample times.When sampling is complete, the converter
is isolated from the input channel and a successive approximation algorithm is performed to determine the

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digital value of the analog signal. The result of the conversion is transferred to ADCRH and ADCRL upon
completion of the conversion algorithm.
If the bus frequency is less than the fADCK frequency, precise sample time for continuous conversions
cannot be guaranteed when short sample is enabled (ADLSMP=0). If the bus frequency is less than 1/11th
of the fADCK frequency, precise sample time for continuous conversions cannot be guaranteed when long
sample is enabled (ADLSMP=1).
The maximum total conversion time for different conditions is summarized in Table 10-12.

Table 10-12. Total Conversion Time vs. Control Conditions

Conversion Type ADICLK ADLSMP Max Total Conversion Time

Single or first continuous 8-bit 0x, 10 0 20 ADCK cycles + 5 bus clock cycles
Single or first continuous 10-bit or 12-bit 0x, 10 0 23 ADCK cycles + 5 bus clock cycles
Single or first continuous 8-bit 0x, 10 1 40 ADCK cycles + 5 bus clock cycles
Single or first continuous 10-bit or 12-bit 0x, 10 1 43 ADCK cycles + 5 bus clock cycles
Single or first continuous 8-bit 11 0 5 μs + 20 ADCK + 5 bus clock cycles
Single or first continuous 10-bit or 12-bit 11 0 5 μs + 23 ADCK + 5 bus clock cycles
Single or first continuous 8-bit 11 1 5 μs + 40 ADCK + 5 bus clock cycles
Single or first continuous 10-bit or 12-bit 11 1 5 μs + 43 ADCK + 5 bus clock cycles
Subsequent continuous 8-bit; xx 0 17 ADCK cycles
fBUS > fADCK
Subsequent continuous 10-bit or 12-bit; xx 0 20 ADCK cycles
fBUS > fADCK
Subsequent continuous 8-bit; xx 1 37 ADCK cycles
fBUS > fADCK/11
Subsequent continuous 10-bit or 12-bit; xx 1 40 ADCK cycles
fBUS > fADCK/11

The maximum total conversion time is determined by the clock source chosen and the divide ratio selected.
The clock source is selectable by the ADICLK bits, and the divide ratio is specified by the ADIV bits. For
example, in 10-bit mode, with the bus clock selected as the input clock source, the input clock divide-by-1
ratio selected, and a bus frequency of 8 MHz, then the conversion time for a single conversion is:

23 ADCK cyc 5 bus cyc

Conversion time = + = 3.5 μs
8 MHz/1 8 MHz

Number of bus cycles = 3.5 μs x 8 MHz = 28 cycles

NOTE
The ADCK frequency must be between fADCK minimum and fADCK
maximum to meet ADC specifications.

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10.4.5 Automatic Compare Function

The compare function can be configured to check for either an upper limit or lower limit. After the input
is sampled and converted, the result is added to the two’s complement of the compare value (ADCCVH
and ADCCVL). When comparing to an upper limit (ACFGT = 1), if the result is greater-than or equal-to
the compare value, COCO is set. When comparing to a lower limit (ACFGT = 0), if the result is less than
the compare value, COCO is set. The value generated by the addition of the conversion result and the two’s
complement of the compare value is transferred to ADCRH and ADCRL.
Upon completion of a conversion while the compare function is enabled, if the compare condition is not
true, COCO is not set and no data is transferred to the result registers. An ADC interrupt is generated upon
the setting of COCO if the ADC interrupt is enabled (AIEN = 1).
NOTE
The compare function can be used to monitor the voltage on a channel while
the MCU is in either wait or stop3 mode. The ADC interrupt will wake the
MCU when the compare condition is met.

10.4.6 MCU Wait Mode Operation

The WAIT instruction puts the MCU in a lower power-consumption standby mode from which recovery
is very fast because the clock sources remain active. If a conversion is in progress when the MCU enters
wait mode, it continues until completion. Conversions can be initiated while the MCU is in wait mode by
means of the hardware trigger or if continuous conversions are enabled.
The bus clock, bus clock divided by two, and ADACK are available as conversion clock sources while in
wait mode. The use of ALTCLK as the conversion clock source in wait is dependent on the definition of
ALTCLK for this MCU. Consult the module introduction for information on ALTCLK specific to this
MCU.
A conversion complete event sets the COCO and generates an ADC interrupt to wake the MCU from wait
mode if the ADC interrupt is enabled (AIEN = 1).

10.4.7 MCU Stop3 Mode Operation

The STOP instruction is used to put the MCU in a low power-consumption standby mode during which
most or all clock sources on the MCU are disabled.

10.4.7.1 Stop3 Mode With ADACK Disabled

If the asynchronous clock, ADACK, is not selected as the conversion clock, executing a STOP instruction
aborts the current conversion and places the ADC in its idle state. The contents of ADCRH and ADCRL
are unaffected by stop3 mode. After exiting from stop3 mode, a software or hardware trigger is required
to resume conversions.

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10.4.7.2 Stop3 Mode With ADACK Enabled

If ADACK is selected as the conversion clock, the ADC continues operation during stop3 mode. For
guaranteed ADC operation, the MCU’s voltage regulator must remain active during stop3 mode. Consult
the module introduction for configuration information for this MCU.
If a conversion is in progress when the MCU enters stop3 mode, it continues until completion. Conversions
can be initiated while the MCU is in stop3 mode by means of the hardware trigger or if continuous
conversions are enabled.
A conversion complete event sets the COCO and generates an ADC interrupt to wake the MCU from stop3
mode if the ADC interrupt is enabled (AIEN = 1).
NOTE
It is possible for the ADC module to wake the system from low power stop
and cause the MCU to begin consuming run-level currents without
generating a system level interrupt. To prevent this scenario, software
should ensure that the data transfer blocking mechanism (discussed in
Section 10.4.4.2, “Completing Conversions) is cleared when entering stop3
and continuing ADC conversions.

10.4.8 MCU Stop1 and Stop2 Mode Operation

The ADC module is automatically disabled when the MCU enters either stop1 or stop2 mode. All module
registers contain their reset values following exit from stop1 or stop2. Therefore the module must be
re-enabled and re-configured following exit from stop1 or stop2.

10.5 Initialization Information

This section gives an example which provides some basic direction on how a user would initialize and
configure the ADC module. The user has the flexibility of choosing between configuring the module for
8-, 10-, or 12-bit resolution, single or continuous conversion, and a polled or interrupt approach, among
many other options. Refer to Table 10-6, Table 10-7, and Table 10-8 for information used in this example.
NOTE
Hexadecimal values designated by a preceding 0x, binary values designated
by a preceding %, and decimal values have no preceding character.

10.5.1 ADC Module Initialization Example

10.5.1.1 Initialization Sequence

Before the ADC module can be used to complete conversions, an initialization procedure must be
performed. A typical sequence is as follows:
1. Update the configuration register (ADCCFG) to select the input clock source and the divide ratio
used to generate the internal clock, ADCK. This register is also used for selecting sample time and
low-power configuration.

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2. Update status and control register 2 (ADCSC2) to select the conversion trigger (hardware or
software) and compare function options, if enabled.
3. Update status and control register 1 (ADCSC1) to select whether conversions will be continuous
or completed only once, and to enable or disable conversion complete interrupts. The input channel
on which conversions will be performed is also selected here.

10.5.1.2 Pseudo — Code Example

In this example, the ADC module will be set up with interrupts enabled to perform a single 10-bit
conversion at low power with a long sample time on input channel 1, where the internal ADCK clock will
be derived from the bus clock divided by 1.
ADCCFG = 0x98 (%10011000)
Bit 7 ADLPC 1 Configures for low power (lowers maximum clock speed)
Bit 6:5 ADIV 00 Sets the ADCK to the input clock ÷ 1
Bit 4 ADLSMP 1 Configures for long sample time
Bit 3:2 MODE 10 Sets mode at 10-bit conversions
Bit 1:0 ADICLK 00 Selects bus clock as input clock source
ADCSC2 = 0x00 (%00000000)
Bit 7 ADACT 0 Flag indicates if a conversion is in progress
Bit 6 ADTRG 0 Software trigger selected
Bit 5 ACFE 0 Compare function disabled
Bit 4 ACFGT 0 Not used in this example
Bit 3:2 00 Unimplemented or reserved, always reads zero
Bit 1:0 00 Reserved for Freescale’s internal use; always write zero
ADCSC1 = 0x41 (%01000001)
Bit 7 COCO 0 Read-only flag which is set when a conversion completes
Bit 6 AIEN 1 Conversion complete interrupt enabled
Bit 5 ADCO 0 One conversion only (continuous conversions disabled)
Bit 4:0 ADCH 00001 Input channel 1 selected as ADC input channel
ADCRH/L = 0xxx
Holds results of conversion. Read high byte (ADCRH) before low byte (ADCRL) so that conversion
data cannot be overwritten with data from the next conversion.
ADCCVH/L = 0xxx
Holds compare value when compare function enabled
APCTL1=0x02
AD1 pin I/O control disabled. All other AD pins remain general purpose I/O pins
APCTL2=0x00
All other AD pins remain general purpose I/O pins

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 Chapter 10 Analog-to-Digital Converter (S08ADC12V1)

RESET

INITIALIZE ADC
ADCCFG = $98
ADCSC2 = $00
ADCSC1 = $41

CHECK NO
COCO=1?

YES

READ ADCRH
THEN ADCRL TO
CLEAR COCO BIT

CONTINUE

Figure 10-14. Initialization Flowchart for Example

10.6 Application Information

This section contains information for using the ADC module in applications. The ADC has been designed
to be integrated into a microcontroller for use in embedded control applications requiring an A/D
converter.

10.6.1 External Pins and Routing

The following sections discuss the external pins associated with the ADC module and how they should be
used for best results.

10.6.1.1 Analog Supply Pins

The ADC module has analog power and ground supplies (VDDAD and VSSAD) which are available as
separate pins on some devices. On other devices, VSSAD is shared on the same pin as the MCU digital VSS,
and on others, both VSSAD and VDDAD are shared with the MCU digital supply pins. In these cases, there
are separate pads for the analog supplies which are bonded to the same pin as the corresponding digital
supply so that some degree of isolation between the supplies is maintained.
When available on a separate pin, both VDDAD and VSSAD must be connected to the same voltage potential
as their corresponding MCU digital supply (VDD and VSS) and must be routed carefully for maximum
noise immunity and bypass capacitors placed as near as possible to the package.

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In cases where separate power supplies are used for analog and digital power, the ground connection
between these supplies must be at the VSSAD pin. This should be the only ground connection between these
supplies if possible. The VSSAD pin makes a good single point ground location.

10.6.1.2 Analog Reference Pins

In addition to the analog supplies, the ADC module has connections for two reference voltage inputs. The
high reference is VREFH, which may be shared on the same pin as VDDAD on some devices. The low
reference is VREFL, which may be shared on the same pin as VSSAD on some devices.
When available on a separate pin, VREFH may be connected to the same potential as VDDAD, or may be
driven by an external source that is between the minimum VDDAD spec and the VDDAD potential (VREFH
must never exceed VDDAD). When available on a separate pin, VREFL must be connected to the same
voltage potential as VSSAD. Both VREFH and VREFL must be routed carefully for maximum noise
immunity and bypass capacitors placed as near as possible to the package.
AC current in the form of current spikes required to supply charge to the capacitor array at each successive
approximation step is drawn through the VREFH and VREFL loop. The best external component to meet this
current demand is a 0.1 μF capacitor with good high frequency characteristics. This capacitor is connected
between VREFH and VREFL and must be placed as near as possible to the package pins. Resistance in the
path is not recommended because the current will cause a voltage drop which could result in conversion
errors. Inductance in this path must be minimum (parasitic only).

10.6.1.3 Analog Input Pins

The external analog inputs are typically shared with digital I/O pins on MCU devices. The pin I/O control
is disabled by setting the appropriate control bit in one of the pin control registers. Conversions can be
performed on inputs without the associated pin control register bit set. It is recommended that the pin
control register bit always be set when using a pin as an analog input. This avoids problems with contention
because the output buffer will be in its high impedance state and the pullup is disabled. Also, the input
buffer draws DC current when its input is not at either VDD or VSS. Setting the pin control register bits for
all pins used as analog inputs should be done to achieve lowest operating current.
Empirical data shows that capacitors on the analog inputs improve performance in the presence of noise
or when the source impedance is high. Use of 0.01 μF capacitors with good high-frequency characteristics
is sufficient. These capacitors are not necessary in all cases, but when used they must be placed as near as
possible to the package pins and be referenced to VSSA.
For proper conversion, the input voltage must fall between VREFH and VREFL. If the input is equal to or
exceeds VREFH, the converter circuit converts the signal to $FFF (full scale 12-bit representation), $3FF
(full scale 10-bit representation) or $FF (full scale 8-bit representation). If the input is equal to or less than
VREFL, the converter circuit converts it to $000. Input voltages between VREFH and VREFL are straight-line
linear conversions. There will be a brief current associated with VREFL when the sampling capacitor is
charging. The input is sampled for 3.5 cycles of the ADCK source when ADLSMP is low, or 23.5 cycles
when ADLSMP is high.
For minimal loss of accuracy due to current injection, pins adjacent to the analog input pins should not be
transitioning during conversions.

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182 Freescale Semiconductor
 Chapter 10 Analog-to-Digital Converter (S08ADC12V1)

10.6.2 Sources of Error

Several sources of error exist for A/D conversions. These are discussed in the following sections.

10.6.2.1 Sampling Error

For proper conversions, the input must be sampled long enough to achieve the proper accuracy. Given the
maximum input resistance of approximately 7kΩ and input capacitance of approximately 5.5 pF, sampling
to within 1/4LSB (at 12-bit resolution) can be achieved within the minimum sample window (3.5 cycles @
8 MHz maximum ADCK frequency) provided the resistance of the external analog source (RAS) is kept
below 2 kΩ.
Higher source resistances or higher-accuracy sampling is possible by setting ADLSMP (to increase the
sample window to 23.5 cycles) or decreasing ADCK frequency to increase sample time.

10.6.2.2 Pin Leakage Error

Leakage on the I/O pins can cause conversion error if the external analog source resistance (RAS) is high.
If this error cannot be tolerated by the application, keep RAS lower than VDDAD / (2N*ILEAK) for less than
1/4LSB leakage error (N = 8 in 8-bit, 10 in 10-bit or 12 in 12-bit mode).

10.6.2.3 Noise-Induced Errors

System noise which occurs during the sample or conversion process can affect the accuracy of the
conversion. The ADC accuracy numbers are guaranteed as specified only if the following conditions are
met:
• There is a 0.1 μF low-ESR capacitor from VREFH to VREFL.
• There is a 0.1 μF low-ESR capacitor from VDDAD to VSSAD.
• If inductive isolation is used from the primary supply, an additional 1 μF capacitor is placed from
VDDAD to VSSAD.
• VSSAD (and VREFL, if connected) is connected to VSS at a quiet point in the ground plane.
• Operate the MCU in wait or stop3 mode before initiating (hardware triggered conversions) or
immediately after initiating (hardware or software triggered conversions) the ADC conversion.
— For software triggered conversions, immediately follow the write to the ADCSC1 with a WAIT
instruction or STOP instruction.
— For stop3 mode operation, select ADACK as the clock source. Operation in stop3 reduces VDD
noise but increases effective conversion time due to stop recovery.
• There is no I/O switching, input or output, on the MCU during the conversion.
There are some situations where external system activity causes radiated or conducted noise emissions or
excessive VDD noise is coupled into the ADC. In these situations, or when the MCU cannot be placed in
wait or stop3 or I/O activity cannot be halted, these recommended actions may reduce the effect of noise
on the accuracy:
• Place a 0.01 μF capacitor (CAS) on the selected input channel to VREFL or VSSAD (this will
improve noise issues but will affect sample rate based on the external analog source resistance).

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• Average the result by converting the analog input many times in succession and dividing the sum
of the results. Four samples are required to eliminate the effect of a 1LSB, one-time error.
• Reduce the effect of synchronous noise by operating off the asynchronous clock (ADACK) and
averaging. Noise that is synchronous to ADCK cannot be averaged out.

10.6.2.4 Code Width and Quantization Error

The ADC quantizes the ideal straight-line transfer function into 4096 steps (in 12-bit mode). Each step
ideally has the same height (1 code) and width. The width is defined as the delta between the transition
points to one code and the next. The ideal code width for an N bit converter (in this case N can be 8, 10 or
12), defined as 1LSB, is:

1LSB = (VREFH - VREFL) / 2N Eqn. 10-2

There is an inherent quantization error due to the digitization of the result. For 8-bit or 10-bit conversions
the code will transition when the voltage is at the midpoint between the points where the straight line
transfer function is exactly represented by the actual transfer function. Therefore, the quantization error
will be ± 1/2LSB in 8- or 10-bit mode. As a consequence, however, the code width of the first ($000)
conversion is only 1/2LSB and the code width of the last ($FF or $3FF) is 1.5LSB.
For 12-bit conversions the code transitions only after the full code width is present, so the quantization
error is -1LSB to 0LSB and the code width of each step is 1LSB.

10.6.2.5 Linearity Errors

The ADC may also exhibit non-linearity of several forms. Every effort has been made to reduce these
errors but the system should be aware of them because they affect overall accuracy. These errors are:
• Zero-scale error (EZS) (sometimes called offset) — This error is defined as the difference between
the actual code width of the first conversion and the ideal code width (1/2LSB in 8-bit or 10-bit
modes and 1LSB in 12-bit mode). Note, if the first conversion is $001, then the difference between
the actual $001 code width and its ideal (1LSB) is used.
• Full-scale error (EFS) — This error is defined as the difference between the actual code width of
the last conversion and the ideal code width (1.5LSB in 8-bit or 10-bit modes and 1LSB in 12-bit
mode). Note, if the last conversion is $3FE, then the difference between the actual $3FE code width
and its ideal (1LSB) is used.
• Differential non-linearity (DNL) — This error is defined as the worst-case difference between the
actual code width and the ideal code width for all conversions.
• Integral non-linearity (INL) — This error is defined as the highest-value the (absolute value of the)
running sum of DNL achieves. More simply, this is the worst-case difference of the actual
transition voltage to a given code and its corresponding ideal transition voltage, for all codes.
• Total unadjusted error (TUE) — This error is defined as the difference between the actual transfer
function and the ideal straight-line transfer function, and therefore includes all forms of error.

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 Chapter 10 Analog-to-Digital Converter (S08ADC12V1)

10.6.2.6 Code Jitter, Non-Monotonicity and Missing Codes

Analog-to-digital converters are susceptible to three special forms of error. These are code jitter,
non-monotonicity, and missing codes.
Code jitter is when, at certain points, a given input voltage converts to one of two values when sampled
repeatedly. Ideally, when the input voltage is infinitesimally smaller than the transition voltage, the
converter yields the lower code (and vice-versa). However, even very small amounts of system noise can
cause the converter to be indeterminate (between two codes) for a range of input voltages around the
transition voltage. This range is normally around 1/2LSB in 8-bit or 10-bit mode, or around 2 LSB in 12-bit
mode, and will increase with noise.
This error may be reduced by repeatedly sampling the input and averaging the result. Additionally the
techniques discussed in Section 10.6.2.3 will reduce this error.
Non-monotonicity is defined as when, except for code jitter, the converter converts to a lower code for a
higher input voltage. Missing codes are those values which are never converted for any input value.
In 8-bit or 10-bit mode, the ADC is guaranteed to be monotonic and to have no missing codes.

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Freescale Semiconductor 185
Chapter 10 Analog-to-Digital Converter (S08ADC12V1)

MC9S08EN32 Series Data Sheet, Rev. 2

186 Freescale Semiconductor
Chapter 11
Serial Peripheral Interface (S08SPIV3)
11.1 Introduction
The serial peripheral interface (SPI) module provides for full-duplex, synchronous, serial communication
between the MCU and peripheral devices. These peripheral devices can include other microcontrollers,
analog-to-digital converters, shift registers, sensors, memories, etc.
The SPI runs at a baud rate up to the bus clock divided by two in master mode and bus clock divided by
four in slave mode.
All devices in the MC9S08EN32 Series MCUs contain one SPI module, as shown in the following block
diagram.
NOTE
Ensure that the SPI should not be disabled (SPE=0) at the same time as a bit
change to the CPHA bit. These changes should be performed as separate
operations or unexpected behavior may occur.

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Freescale Semiconductor 187
Chapter 11 Serial Peripheral Interface (S08SPIV3)

HCS08 CORE PTA7/PIA7/ADP7/IRQ

PTA6/PIA6/ADP6
PTA5/PIA5/ADP5
CPU

PORT A
PTA4/PIA4/ADP4
ACMP1O
ANALOG COMPARATOR PTA3/PIA3/ADP3/ACMP1O
BKGD/MS ACMP1-
(ACMP1) PTA2/PIA2/ADP2/ACMP1-
BDC BKP ACMP1+
PTA1/PIA1/ADP1/ACMP1+
PTA0/PIA0/ADP0/MCLK
HCS08 SYSTEM CONTROL
PTB7/PIB7
RESETS AND INTERRUPTS PTB6/PIB6
RESET
MODES OF OPERATION PTB5/PIB5

PORT B
POWER MANAGEMENT PTB4/PIB4
PTB3/PIB3/ADP11
8 PTB2/PIB2/ADP10
COP LVD PTB1/PIB1/ADP9
IRQ

ADP7-ADP0 PTB0/PIB0/ADP8
INT IRQ
12-CHANNEL,10-BIT
ADP11-ADP8
ANALOG-TO-DIGITAL
VREFH
CONVERTER (ADC)
VREFL
VDDA
VSSA

TPM1CH3–TPM1CH0
PTD7/PID7
USER FLASH 4-CHANNEL TIMER/PWM 6 PTD6/PID6
MODULE (TPM1) TPM1CLK
MC9S08EN32 = 32K PTD5/PID5/TPM1CH3
MC9S08EN16 = 16K

PORT D
PTD4/PID4/TPM1CH2
PTD3/PID3/TPM1CH1
PTD2/PID2/TPM1CH0
PTD1/PID1
PTD0/PID0
PTE7
PTE6
MISO
USER RAM PTE5/MISO
MOSI
PORT E

MC9S08EN32 = 1 KBYTE SERIAL PERIPHERAL PTE4/MOSI

SPSCK
MC9S08EN16 = 512 BYTES INTERFACE MODULE (SPI) PTE3/SPSCK
SS
PTE2/SS
RxD1
PTE1/RxD1
DEBUG MODULE (DBG) SERIAL COMMUNICATIONS TxD1
PTE0/TxD1
INTERFACE (SCI1)

REAL TIME COUNTER (RTC) PTF5

PORT F

PTF4
VDD PTF3
VDD VOLTAGE PTF2/TPM1CLK
VSS REGULATOR PTF1
VSS PTF0

MULTI-PURPOSE
CLOCK GENERATOR
PORT G

(MCG)
XTAL
PTG1/XTAL
OSCILLATOR (XOSC) EXTAL
PTG0/EXTAL
- VREFH/VREFL internally connected to VDDA/VSSA
- VDD and VSS pins are each internally connected to two pads in 32-pin package - Pin not connected in 32-pin package

Figure 11-1. MC9S08EN32 Block Diagram

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188 Freescale Semiconductor
 Chapter 11 Serial Peripheral Interface (S08SPIV3)

11.1.1 Features
Features of the SPI module include:
• Master or slave mode operation
• Full-duplex or single-wire bidirectional option
• Programmable transmit bit rate
• Double-buffered transmit and receive
• Serial clock phase and polarity options
• Slave select output
• Selectable MSB-first or LSB-first shifting

11.1.2 Block Diagrams

This section includes block diagrams showing SPI system connections, the internal organization of the SPI
module, and the SPI clock dividers that control the master mode bit rate.

11.1.2.1 SPI System Block Diagram

Figure 11-2 shows the SPI modules of two MCUs connected in a master-slave arrangement. The master
device initiates all SPI data transfers. During a transfer, the master shifts data out (on the MOSI pin) to the
slave while simultaneously shifting data in (on the MISO pin) from the slave. The transfer effectively
exchanges the data that was in the SPI shift registers of the two SPI systems. The SPSCK signal is a clock
output from the master and an input to the slave. The slave device must be selected by a low level on the
slave select input (SS pin). In this system, the master device has configured its SS pin as an optional slave
select output.

MASTER SLAVE

MOSI MOSI

SPI SHIFTER SPI SHIFTER

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
MISO MISO

SPSCK SPSCK

CLOCK
GENERATOR
SS SS

Figure 11-2. SPI System Connections

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Freescale Semiconductor 189
Chapter 11 Serial Peripheral Interface (S08SPIV3)

The most common uses of the SPI system include connecting simple shift registers for adding input or
output ports or connecting small peripheral devices such as serial A/D or D/A converters. Although
Figure 11-2 shows a system where data is exchanged between two MCUs, many practical systems involve
simpler connections where data is unidirectionally transferred from the master MCU to a slave or from a
slave to the master MCU.

11.1.2.2 SPI Module Block Diagram

Figure 11-3 is a block diagram of the SPI module. The central element of the SPI is the SPI shift register.
Data is written to the double-buffered transmitter (write to SPID) and gets transferred to the SPI shift
register at the start of a data transfer. After shifting in a byte of data, the data is transferred into the
double-buffered receiver where it can be read (read from SPID). Pin multiplexing logic controls
connections between MCU pins and the SPI module.
When the SPI is configured as a master, the clock output is routed to the SPSCK pin, the shifter output is
routed to MOSI, and the shifter input is routed from the MISO pin.
When the SPI is configured as a slave, the SPSCK pin is routed to the clock input of the SPI, the shifter
output is routed to MISO, and the shifter input is routed from the MOSI pin.
In the external SPI system, simply connect all SPSCK pins to each other, all MISO pins together, and all
MOSI pins together. Peripheral devices often use slightly different names for these pins.

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 Chapter 11 Serial Peripheral Interface (S08SPIV3)

PIN CONTROL

M
MOSI
SPE
S (MOMI)
Tx BUFFER (WRITE SPID)

ENABLE
SPI SYSTEM M MISO
SHIFT SHIFT (SISO)
SPI SHIFT REGISTER S
OUT IN

SPC0
Rx BUFFER (READ SPID)
BIDIROE
SHIFT SHIFT Rx BUFFER Tx BUFFER
LSBFE
DIRECTION CLOCK FULL EMPTY

MASTER CLOCK
M
BUS RATE SPIBR CLOCK
SPSCK
CLOCK CLOCK GENERATOR LOGIC SLAVE CLOCK
S
MASTER/SLAVE MASTER/
MSTR
MODE SELECT SLAVE
MODFEN

MODE FAULT SSOE

SS
DETECTION

SPRF SPTEF
SPTIE
SPI
INTERRUPT
MODF REQUEST
SPIE
Figure 11-3. SPI Module Block Diagram

11.1.3 SPI Baud Rate Generation

As shown in Figure 11-4, the clock source for the SPI baud rate generator is the bus clock. The three
prescale bits (SPPR2:SPPR1:SPPR0) choose a prescale divisor of 1, 2, 3, 4, 5, 6, 7, or 8. The three rate
select bits (SPR2:SPR1:SPR0) divide the output of the prescaler stage by 2, 4, 8, 16, 32, 64, 128, or 256
to get the internal SPI master mode bit-rate clock.

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Chapter 11 Serial Peripheral Interface (S08SPIV3)

PRESCALER CLOCK RATE DIVIDER

DIVIDE BY DIVIDE BY MASTER

BUS CLOCK SPI
1, 2, 3, 4, 5, 6, 7, or 8 2, 4, 8, 16, 32, 64, 128, or 256 BIT RATE

SPPR2:SPPR1:SPPR0 SPR2:SPR1:SPR0
Figure 11-4. SPI Baud Rate Generation

11.2 External Signal Description

The SPI optionally shares four port pins. The function of these pins depends on the settings of SPI control
bits. When the SPI is disabled (SPE = 0), these four pins revert to being general-purpose port I/O pins that
are not controlled by the SPI.

11.2.1 SPSCK — SPI Serial Clock

When the SPI is enabled as a slave, this pin is the serial clock input. When the SPI is enabled as a master,
this pin is the serial clock output.

11.2.2 MOSI — Master Data Out, Slave Data In

When the SPI is enabled as a master and SPI pin control zero (SPC0) is 0 (not bidirectional mode), this
pin is the serial data output. When the SPI is enabled as a slave and SPC0 = 0, this pin is the serial data
input. If SPC0 = 1 to select single-wire bidirectional mode, and master mode is selected, this pin becomes
the bidirectional data I/O pin (MOMI). Also, the bidirectional mode output enable bit determines whether
the pin acts as an input (BIDIROE = 0) or an output (BIDIROE = 1). If SPC0 = 1 and slave mode is
selected, this pin is not used by the SPI and reverts to being a general-purpose port I/O pin.

11.2.3 MISO — Master Data In, Slave Data Out

When the SPI is enabled as a master and SPI pin control zero (SPC0) is 0 (not bidirectional mode), this
pin is the serial data input. When the SPI is enabled as a slave and SPC0 = 0, this pin is the serial data
output. If SPC0 = 1 to select single-wire bidirectional mode, and slave mode is selected, this pin becomes
the bidirectional data I/O pin (SISO) and the bidirectional mode output enable bit determines whether the
pin acts as an input (BIDIROE = 0) or an output (BIDIROE = 1). If SPC0 = 1 and master mode is selected,
this pin is not used by the SPI and reverts to being a general-purpose port I/O pin.

11.2.4 SS — Slave Select

When the SPI is enabled as a slave, this pin is the low-true slave select input. When the SPI is enabled as
a master and mode fault enable is off (MODFEN = 0), this pin is not used by the SPI and reverts to being
a general-purpose port I/O pin. When the SPI is enabled as a master and MODFEN = 1, the slave select
output enable bit determines whether this pin acts as the mode fault input (SSOE = 0) or as the slave select
output (SSOE = 1).

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 Chapter 11 Serial Peripheral Interface (S08SPIV3)

11.3 Modes of Operation

11.3.1 SPI in Stop Modes

The SPI is disabled in all stop modes, regardless of the settings before executing the STOP instruction.
During either stop1 or stop2 mode, the SPI module will be fully powered down. Upon wake-up from stop1
or stop2 mode, the SPI module will be in the reset state. During stop3 mode, clocks to the SPI module are
halted. No registers are affected. If stop3 is exited with a reset, the SPI will be put into its reset state. If
stop3 is exited with an interrupt, the SPI continues from the state it was in when stop3 was entered.

11.4 Register Definition

The SPI has five 8-bit registers to select SPI options, control baud rate, report SPI status, and for
transmit/receive data.
Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address
assignments for all SPI registers. This section refers to registers and control bits only by their names, and
a Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.

11.4.1 SPI Control Register 1 (SPIC1)

This read/write register includes the SPI enable control, interrupt enables, and configuration options.

7 6 5 4 3 2 1 0

R
SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE
W

Reset 0 0 0 0 0 1 0 0

Figure 11-5. SPI Control Register 1 (SPIC1)

Table 11-1. SPIC1 Field Descriptions

Field Description

7 SPI Interrupt Enable (for SPRF and MODF) — This is the interrupt enable for SPI receive buffer full (SPRF)
SPIE and mode fault (MODF) events.
0 Interrupts from SPRF and MODF inhibited (use polling)
1 When SPRF or MODF is 1, request a hardware interrupt

6 SPI System Enable — Disabling the SPI halts any transfer that is in progress, clears data buffers, and initializes
SPE internal state machines. SPRF is cleared and SPTEF is set to indicate the SPI transmit data buffer is empty.
0 SPI system inactive
1 SPI system enabled

5 SPI Transmit Interrupt Enable — This is the interrupt enable bit for SPI transmit buffer empty (SPTEF).
SPTIE 0 Interrupts from SPTEF inhibited (use polling)
1 When SPTEF is 1, hardware interrupt requested

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Chapter 11 Serial Peripheral Interface (S08SPIV3)

Table 11-1. SPIC1 Field Descriptions (continued)

Field Description

4 Master/Slave Mode Select

MSTR 0 SPI module configured as a slave SPI device
1 SPI module configured as a master SPI device

3 Clock Polarity — This bit effectively places an inverter in series with the clock signal from a master SPI or to a
CPOL slave SPI device. Refer to Section 11.5.1, “SPI Clock Formats” for more details.
0 Active-high SPI clock (idles low)
1 Active-low SPI clock (idles high)

2 Clock Phase — This bit selects one of two clock formats for different kinds of synchronous serial peripheral
CPHA devices. Refer to Section 11.5.1, “SPI Clock Formats” for more details.
0 First edge on SPSCK occurs at the middle of the first cycle of an 8-cycle data transfer
1 First edge on SPSCK occurs at the start of the first cycle of an 8-cycle data transfer

1 Slave Select Output Enable — This bit is used in combination with the mode fault enable (MODFEN) bit in
SSOE SPCR2 and the master/slave (MSTR) control bit to determine the function of the SS pin as shown in Table 11-2.

0 LSB First (Shifter Direction)

LSBFE 0 SPI serial data transfers start with most significant bit
1 SPI serial data transfers start with least significant bit

Table 11-2. SS Pin Function

MODFEN SSOE Master Mode Slave Mode

0 0 General-purpose I/O (not SPI) Slave select input
0 1 General-purpose I/O (not SPI) Slave select input
1 0 SS input for mode fault Slave select input
1 1 Automatic SS output Slave select input

NOTE
Ensure that the SPI should not be disabled (SPE=0) at the same time as a bit change to the CPHA bit. These
changes should be performed as separate operations or unexpected behavior may occur.

11.4.2 SPI Control Register 2 (SPIC2)

This read/write register is used to control optional features of the SPI system. Bits 7, 6, 5, and 2 are not
implemented and always read 0.

7 6 5 4 3 2 1 0

R 0 0 0 0
MODFEN BIDIROE SPISWAI SPC0
W

Reset 0 0 0 0 0 0 0 0

= Unimplemented or Reserved

Figure 11-6. SPI Control Register 2 (SPIC2)

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 Chapter 11 Serial Peripheral Interface (S08SPIV3)

Table 11-3. SPIC2 Register Field Descriptions

Field Description

4 Master Mode-Fault Function Enable — When the SPI is configured for slave mode, this bit has no meaning or
MODFEN effect. (The SS pin is the slave select input.) In master mode, this bit determines how the SS pin is used (refer
to Table 11-2 for more details).
0 Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI
1 Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output

3 Bidirectional Mode Output Enable — When bidirectional mode is enabled by SPI pin control 0 (SPC0) = 1,
BIDIROE BIDIROE determines whether the SPI data output driver is enabled to the single bidirectional SPI I/O pin.
Depending on whether the SPI is configured as a master or a slave, it uses either the MOSI (MOMI) or MISO
(SISO) pin, respectively, as the single SPI data I/O pin. When SPC0 = 0, BIDIROE has no meaning or effect.
0 Output driver disabled so SPI data I/O pin acts as an input
1 SPI I/O pin enabled as an output

1 SPI Stop in Wait Mode

SPISWAI 0 SPI clocks continue to operate in wait mode
1 SPI clocks stop when the MCU enters wait mode

0 SPI Pin Control 0 — The SPC0 bit chooses single-wire bidirectional mode. If MSTR = 0 (slave mode), the SPI
SPC0 uses the MISO (SISO) pin for bidirectional SPI data transfers. If MSTR = 1 (master mode), the SPI uses the
MOSI (MOMI) pin for bidirectional SPI data transfers. When SPC0 = 1, BIDIROE is used to enable or disable the
output driver for the single bidirectional SPI I/O pin.
0 SPI uses separate pins for data input and data output
1 SPI configured for single-wire bidirectional operation

11.4.3 SPI Baud Rate Register (SPIBR)

This register is used to set the prescaler and bit rate divisor for an SPI master. This register may be read or
written at any time.
7 6 5 4 3 2 1 0

R 0 0
SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0
W

Reset 0 0 0 0 0 0 0 0

= Unimplemented or Reserved

Figure 11-7. SPI Baud Rate Register (SPIBR)

Table 11-4. SPIBR Register Field Descriptions

Field Description

6:4 SPI Baud Rate Prescale Divisor — This 3-bit field selects one of eight divisors for the SPI baud rate prescaler
SPPR[2:0] as shown in Table 11-5. The input to this prescaler is the bus rate clock (BUSCLK). The output of this prescaler
drives the input of the SPI baud rate divider (see Figure 11-4).
2:0 SPI Baud Rate Divisor — This 3-bit field selects one of eight divisors for the SPI baud rate divider as shown in
SPR[2:0] Table 11-6. The input to this divider comes from the SPI baud rate prescaler (see Figure 11-4). The output of this
divider is the SPI bit rate clock for master mode.

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Chapter 11 Serial Peripheral Interface (S08SPIV3)

Table 11-5. SPI Baud Rate Prescaler Divisor

SPPR2:SPPR1:SPPR0 Prescaler Divisor

0:0:0 1
0:0:1 2
0:1:0 3
0:1:1 4
1:0:0 5
1:0:1 6
1:1:0 7
1:1:1 8

Table 11-6. SPI Baud Rate Divisor

SPR2:SPR1:SPR0 Rate Divisor

0:0:0 2
0:0:1 4
0:1:0 8
0:1:1 16
1:0:0 32
1:0:1 64
1:1:0 128
1:1:1 256

11.4.4 SPI Status Register (SPIS)

This register has three read-only status bits. Bits 6, 3, 2, 1, and 0 are not implemented and always read 0.
Writes have no meaning or effect.
7 6 5 4 3 2 1 0

R SPRF 0 SPTEF MODF 0 0 0 0

Reset 0 0 1 0 0 0 0 0

= Unimplemented or Reserved

Figure 11-8. SPI Status Register (SPIS)

MC9S08EN32 Series Data Sheet, Rev. 2

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Table 11-7. SPIS Register Field Descriptions

Field Description

7 SPI Read Buffer Full Flag — SPRF is set at the completion of an SPI transfer to indicate that received data may
SPRF be read from the SPI data register (SPID). SPRF is cleared by reading SPRF while it is set, then reading the SPI
data register.
0 No data available in the receive data buffer
1 Data available in the receive data buffer

5 SPI Transmit Buffer Empty Flag — This bit is set when there is room in the transmit data buffer. It is cleared by
SPTEF reading SPIS with SPTEF set, followed by writing a data value to the transmit buffer at SPID. SPIS must be read
with SPTEF = 1 before writing data to SPID or the SPID write will be ignored. SPTEF generates an SPTEF CPU
interrupt request if the SPTIE bit in the SPIC1 is also set. SPTEF is automatically set when a data byte transfers
from the transmit buffer into the transmit shift register. For an idle SPI (no data in the transmit buffer or the shift
register and no transfer in progress), data written to SPID is transferred to the shifter almost immediately so
SPTEF is set within two bus cycles allowing a second 8-bit data value to be queued into the transmit buffer. After
completion of the transfer of the value in the shift register, the queued value from the transmit buffer will
automatically move to the shifter and SPTEF will be set to indicate there is room for new data in the transmit
buffer. If no new data is waiting in the transmit buffer, SPTEF simply remains set and no data moves from the
buffer to the shifter.
0 SPI transmit buffer not empty
1 SPI transmit buffer empty

4 Master Mode Fault Flag — MODF is set if the SPI is configured as a master and the slave select input goes
MODF low, indicating some other SPI device is also configured as a master. The SS pin acts as a mode fault error input
only when MSTR = 1, MODFEN = 1, and SSOE = 0; otherwise, MODF will never be set. MODF is cleared by
reading MODF while it is 1, then writing to SPI control register 1 (SPIC1).
0 No mode fault error
1 Mode fault error detected

11.4.5 SPI Data Register (SPID)

7 6 5 4 3 2 1 0

R
Bit 7 6 5 4 3 2 1 Bit 0
W

Reset 0 0 0 0 0 0 0 0

Figure 11-9. SPI Data Register (SPID)

Reads of this register return the data read from the receive data buffer. Writes to this register write data to
the transmit data buffer. When the SPI is configured as a master, writing data to the transmit data buffer
initiates an SPI transfer.
Data should not be written to the transmit data buffer unless the SPI transmit buffer empty flag (SPTEF)
is set, indicating there is room in the transmit buffer to queue a new transmit byte.
Data may be read from SPID any time after SPRF is set and before another transfer is finished. Failure to
read the data out of the receive data buffer before a new transfer ends causes a receive overrun condition
and the data from the new transfer is lost.

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11.5 Functional Description

An SPI transfer is initiated by checking for the SPI transmit buffer empty flag (SPTEF = 1) and then
writing a byte of data to the SPI data register (SPID) in the master SPI device. When the SPI shift register
is available, this byte of data is moved from the transmit data buffer to the shifter, SPTEF is set to indicate
there is room in the buffer to queue another transmit character if desired, and the SPI serial transfer starts.
During the SPI transfer, data is sampled (read) on the MISO pin at one SPSCK edge and shifted, changing
the bit value on the MOSI pin, one-half SPSCK cycle later. After eight SPSCK cycles, the data that was in
the shift register of the master has been shifted out the MOSI pin to the slave while eight bits of data were
shifted in the MISO pin into the master’s shift register. At the end of this transfer, the received data byte is
moved from the shifter into the receive data buffer and SPRF is set to indicate the data can be read by
reading SPID. If another byte of data is waiting in the transmit buffer at the end of a transfer, it is moved
into the shifter, SPTEF is set, and a new transfer is started.
Normally, SPI data is transferred most significant bit (MSB) first. If the least significant bit first enable
(LSBFE) bit is set, SPI data is shifted LSB first.
When the SPI is configured as a slave, its SS pin must be driven low before a transfer starts and SS must
stay low throughout the transfer. If a clock format where CPHA = 0 is selected, SS must be driven to a
logic 1 between successive transfers. If CPHA = 1, SS may remain low between successive transfers. See
Section 11.5.1, “SPI Clock Formats” for more details.
Because the transmitter and receiver are double buffered, a second byte, in addition to the byte currently
being shifted out, can be queued into the transmit data buffer, and a previously received character can be
in the receive data buffer while a new character is being shifted in. The SPTEF flag indicates when the
transmit buffer has room for a new character. The SPRF flag indicates when a received character is
available in the receive data buffer. The received character must be read out of the receive buffer (read
SPID) before the next transfer is finished or a receive overrun error results.
In the case of a receive overrun, the new data is lost because the receive buffer still held the previous
character and was not ready to accept the new data. There is no indication for such an overrun condition
so the application system designer must ensure that previous data has been read from the receive buffer
before a new transfer is initiated.

11.5.1 SPI Clock Formats

To accommodate a wide variety of synchronous serial peripherals from different manufacturers, the SPI
system has a clock polarity (CPOL) bit and a clock phase (CPHA) control bit to select one of four clock
formats for data transfers. CPOL selectively inserts an inverter in series with the clock. CPHA chooses
between two different clock phase relationships between the clock and data.
Figure 11-10 shows the clock formats when CPHA = 1. At the top of the figure, the eight bit times are
shown for reference with bit 1 starting at the first SPSCK edge and bit 8 ending one-half SPSCK cycle after
the sixteenth SPSCK edge. The MSB first and LSB first lines show the order of SPI data bits depending
on the setting in LSBFE. Both variations of SPSCK polarity are shown, but only one of these waveforms
applies for a specific transfer, depending on the value in CPOL. The SAMPLE IN waveform applies to the
MOSI input of a slave or the MISO input of a master. The MOSI waveform applies to the MOSI output

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pin from a master and the MISO waveform applies to the MISO output from a slave. The SS OUT
waveform applies to the slave select output from a master (provided MODFEN and SSOE = 1). The master
SS output goes to active low one-half SPSCK cycle before the start of the transfer and goes back high at
the end of the eighth bit time of the transfer. The SS IN waveform applies to the slave select input of a
slave.

BIT TIME #
(REFERENCE) 1 2 ... 6 7 8

SPSCK
(CPOL = 0)

SPSCK
(CPOL = 1)

SAMPLE IN
(MISO OR MOSI)

MOSI
(MASTER OUT)

MSB FIRST BIT 7 BIT 6 ... BIT 2 BIT 1 BIT 0

LSB FIRST BIT 0 BIT 1 ... BIT 5 BIT 6 BIT 7

MISO
(SLAVE OUT)

SS OUT
(MASTER)

SS IN
(SLAVE)

Figure 11-10. SPI Clock Formats (CPHA = 1)

When CPHA = 1, the slave begins to drive its MISO output when SS goes to active low, but the data is not
defined until the first SPSCK edge. The first SPSCK edge shifts the first bit of data from the shifter onto
the MOSI output of the master and the MISO output of the slave. The next SPSCK edge causes both the
master and the slave to sample the data bit values on their MISO and MOSI inputs, respectively. At the
third SPSCK edge, the SPI shifter shifts one bit position which shifts in the bit value that was just sampled,
and shifts the second data bit value out the other end of the shifter to the MOSI and MISO outputs of the
master and slave, respectively. When CHPA = 1, the slave’s SS input is not required to go to its inactive
high level between transfers.
Figure 11-11 shows the clock formats when CPHA = 0. At the top of the figure, the eight bit times are
shown for reference with bit 1 starting as the slave is selected (SS IN goes low), and bit 8 ends at the last
SPSCK edge. The MSB first and LSB first lines show the order of SPI data bits depending on the setting

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in LSBFE. Both variations of SPSCK polarity are shown, but only one of these waveforms applies for a
specific transfer, depending on the value in CPOL. The SAMPLE IN waveform applies to the MOSI input
of a slave or the MISO input of a master. The MOSI waveform applies to the MOSI output pin from a
master and the MISO waveform applies to the MISO output from a slave. The SS OUT waveform applies
to the slave select output from a master (provided MODFEN and SSOE = 1). The master SS output goes
to active low at the start of the first bit time of the transfer and goes back high one-half SPSCK cycle after
the end of the eighth bit time of the transfer. The SS IN waveform applies to the slave select input of a
slave.

BIT TIME #
(REFERENCE) 1 2 ... 6 7 8

SPSCK
(CPOL = 0)

SPSCK
(CPOL = 1)

SAMPLE IN
(MISO OR MOSI)

MOSI
(MASTER OUT)
MSB FIRST BIT 7 BIT 6 ... BIT 2 BIT 1 BIT 0
LSB FIRST BIT 0 BIT 1 ... BIT 5 BIT 6 BIT 7
MISO
(SLAVE OUT)

SS OUT
(MASTER)

SS IN
(SLAVE)

Figure 11-11. SPI Clock Formats (CPHA = 0)

When CPHA = 0, the slave begins to drive its MISO output with the first data bit value (MSB or LSB
depending on LSBFE) when SS goes to active low. The first SPSCK edge causes both the master and the
slave to sample the data bit values on their MISO and MOSI inputs, respectively. At the second SPSCK
edge, the SPI shifter shifts one bit position which shifts in the bit value that was just sampled and shifts the
second data bit value out the other end of the shifter to the MOSI and MISO outputs of the master and
slave, respectively. When CPHA = 0, the slave’s SS input must go to its inactive high level between
transfers.

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11.5.2 SPI Interrupts

There are three flag bits, two interrupt mask bits, and one interrupt vector associated with the SPI system.
The SPI interrupt enable mask (SPIE) enables interrupts from the SPI receiver full flag (SPRF) and mode
fault flag (MODF). The SPI transmit interrupt enable mask (SPTIE) enables interrupts from the SPI
transmit buffer empty flag (SPTEF). When one of the flag bits is set, and the associated interrupt mask bit
is set, a hardware interrupt request is sent to the CPU. If the interrupt mask bits are cleared, software can
poll the associated flag bits instead of using interrupts. The SPI interrupt service routine (ISR) should
check the flag bits to determine what event caused the interrupt. The service routine should also clear the
flag bit(s) before returning from the ISR (usually near the beginning of the ISR).

11.5.3 Mode Fault Detection

A mode fault occurs and the mode fault flag (MODF) becomes set when a master SPI device detects an
error on the SS pin (provided the SS pin is configured as the mode fault input signal). The SS pin is
configured to be the mode fault input signal when MSTR = 1, mode fault enable is set (MODFEN = 1),
and slave select output enable is clear (SSOE = 0).
The mode fault detection feature can be used in a system where more than one SPI device might become
a master at the same time. The error is detected when a master’s SS pin is low, indicating that some other
SPI device is trying to address this master as if it were a slave. This could indicate a harmful output driver
conflict, so the mode fault logic is designed to disable all SPI output drivers when such an error is detected.
When a mode fault is detected, MODF is set and MSTR is cleared to change the SPI configuration back
to slave mode. The output drivers on the SPSCK, MOSI, and MISO (if not bidirectional mode) are
disabled.
MODF is cleared by reading it while it is set, then writing to the SPI control register 1 (SPIC1). User
software should verify the error condition has been corrected before changing the SPI back to master
mode.

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Chapter 12
Serial Communications Interface (S08SCIV4)
12.1 Introduction
All MCUs in the MC9S08EN32 Series include SCI1.
NOTE
MC9S08EN32 Series devices operate at a higher voltage range (2.7 V to
5.5 V) and do not include stop1 mode. Please ignore references to stop1.

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 203
Chapter 12 Serial Communications Interface (S08SCIV4)

HCS08 CORE PTA7/PIA7/ADP7/IRQ

PTA6/PIA6/ADP6
PTA5/PIA5/ADP5
CPU

PORT A
PTA4/PIA4/ADP4
ACMP1O
ANALOG COMPARATOR PTA3/PIA3/ADP3/ACMP1O
BKGD/MS ACMP1-
(ACMP1) PTA2/PIA2/ADP2/ACMP1-
BDC BKP ACMP1+
PTA1/PIA1/ADP1/ACMP1+
PTA0/PIA0/ADP0/MCLK
HCS08 SYSTEM CONTROL
PTB7/PIB7
RESETS AND INTERRUPTS PTB6/PIB6
RESET
MODES OF OPERATION PTB5/PIB5

PORT B
POWER MANAGEMENT PTB4/PIB4
PTB3/PIB3/ADP11
8 PTB2/PIB2/ADP10
COP LVD PTB1/PIB1/ADP9
IRQ

ADP7-ADP0 PTB0/PIB0/ADP8
INT IRQ
12-CHANNEL,10-BIT
ADP11-ADP8
ANALOG-TO-DIGITAL
VREFH
CONVERTER (ADC)
VREFL
VDDA
VSSA

TPM1CH3–TPM1CH0
PTD7/PID7
USER FLASH 4-CHANNEL TIMER/PWM 6 PTD6/PID6
MODULE (TPM1) TPM1CLK
MC9S08EN32 = 32K PTD5/PID5/TPM1CH3
MC9S08EN16 = 16K

PORT D
PTD4/PID4/TPM1CH2
PTD3/PID3/TPM1CH1
PTD2/PID2/TPM1CH0
PTD1/PID1
PTD0/PID0
PTE7
PTE6
MISO
USER RAM PTE5/MISO
MOSI
PORT E

MC9S08EN32 = 1 KBYTE SERIAL PERIPHERAL PTE4/MOSI

SPSCK
MC9S08EN16 = 512 BYTES INTERFACE MODULE (SPI) PTE3/SPSCK
SS
PTE2/SS
RxD1
PTE1/RxD1
DEBUG MODULE (DBG) SERIAL COMMUNICATIONS TxD1
PTE0/TxD1
INTERFACE (SCI1)

REAL TIME COUNTER (RTC) PTF5

PORT F

PTF4
VDD PTF3
VDD VOLTAGE PTF2/TPM1CLK
VSS REGULATOR PTF1
VSS PTF0

MULTI-PURPOSE
CLOCK GENERATOR
PORT G

(MCG)
XTAL
PTG1/XTAL
OSCILLATOR (XOSC) EXTAL
PTG0/EXTAL
- VREFH/VREFL internally connected to VDDA/VSSA
- VDD and VSS pins are each internally connected to two pads in 32-pin package - Pin not connected in 32-pin package

Figure 12-1. MC9S08EN32 Block Diagram

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 Chapter 12 Serial Communications Interface (S08SCIV4)

12.1.1 Features
Features of SCI module include:
• Full-duplex, standard non-return-to-zero (NRZ) format
• Double-buffered transmitter and receiver with separate enables
• Programmable baud rates (13-bit modulo divider)
• Interrupt-driven or polled operation:
— Transmit data register empty and transmission complete
— Receive data register full
— Receive overrun, parity error, framing error, and noise error
— Idle receiver detect
— Active edge on receive pin
— Break detect supporting LIN
• Hardware parity generation and checking
• Programmable 8-bit or 9-bit character length
• Receiver wakeup by idle-line or address-mark
• Optional 13-bit break character generation / 11-bit break character detection
• Selectable transmitter output polarity

12.1.2 Modes of Operation

See Section 12.3, “Functional Description,” For details concerning SCI operation in these modes:
• 8- and 9-bit data modes
• Stop mode operation
• Loop mode
• Single-wire mode

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12.1.3 Block Diagram

Figure 12-2 shows the transmitter portion of the SCI.
INTERNAL BUS

(WRITE-ONLY)
LOOPS
SCID – Tx BUFFER RSRC

LOOP TO RECEIVE
11-BIT TRANSMIT SHIFT REGISTER CONTROL
M DATA IN

START
STOP
TO TxD PIN
1 × BAUD H 8 7 6 5 4 3 2 1 0 L
RATE CLOCK

LSB
SHIFT DIRECTION

TXINV

PREAMBLE (ALL 1s)

LOAD FROM SCI1D

BREAK (ALL 0s)

T8 SHIFT ENABLE

PE PARITY
GENERATION
PT

SCI CONTROLS TxD

TE
SBK TO TxD
TRANSMIT CONTROL
TxD DIRECTION PIN LOGIC
TXDIR
BRK13

TDRE

TIE

Tx INTERRUPT
TC
REQUEST
TCIE

Figure 12-2. SCI Transmitter Block Diagram

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 Chapter 12 Serial Communications Interface (S08SCIV4)

Figure 12-3 shows the receiver portion of the SCI.

INTERNAL BUS

(READ-ONLY)
16 × BAUD DIVIDE
RATE CLOCK SCID – Rx BUFFER
BY 16
FROM
TRANSMITTER
11-BIT RECEIVE SHIFT REGISTER

START
LOOPS

STOP
SINGLE-WIRE

LSB
M
LOOP CONTROL
RSRC
LBKDE H 8 7 6 5 4 3 2 1 0 L
FROM RxD PIN

ALL 1s

MSB
RXINV DATA RECOVERY SHIFT DIRECTION

WAKE WAKEUP
RWU RWUID
LOGIC
ILT

ACTIVE EDGE
DETECT

RDRF
RIE

IDLE
ILIE
Rx INTERRUPT
REQUEST
LBKDIF

LBKDIE

RXEDGIF
RXEDGIE

OR
ORIE

FE
FEIE
ERROR INTERRUPT
REQUEST
NF

NEIE
PE PARITY
PF
CHECKING
PT
PEIE

Figure 12-3. SCI Receiver Block Diagram

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12.2 Register Definition

The SCI has eight 8-bit registers to control baud rate, select SCI options, report SCI status, and for
transmit/receive data.
Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address
assignments for all SCI registers. This section refers to registers and control bits only by their names. A
Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.

12.2.1 SCI Baud Rate Registers (SCI1BDH, SCI1BDL)

This pair of registers controls the prescale divisor for SCI baud rate generation. To update the 13-bit baud
rate setting [SBR12:SBR0], first write to SCI1BDH to buffer the high half of the new value and then write
to SCI1BDL. The working value in SCI1BDH does not change until SCI1BDL is written.
SCI1BDL is reset to a non-zero value, so after reset the baud rate generator remains disabled until the first
time the receiver or transmitter is enabled (RE or TE bits in SCI1C2 are written to 1).

7 6 5 4 3 2 1 0

R 0
LBKDIE RXEDGIE SBR12 SBR11 SBR10 SBR9 SBR8
W

Reset 0 0 0 0 0 0 0 0

= Unimplemented or Reserved

Figure 12-4. SCI Baud Rate Register (SCI1BDH)

Table 12-1. SCI1BDH Field Descriptions

Field Description

7 LIN Break Detect Interrupt Enable (for LBKDIF)

LBKDIE 0 Hardware interrupts from LBKDIF disabled (use polling).
1 Hardware interrupt requested when LBKDIF flag is 1.

6 RxD Input Active Edge Interrupt Enable (for RXEDGIF)

RXEDGIE 0 Hardware interrupts from RXEDGIF disabled (use polling).
1 Hardware interrupt requested when RXEDGIF flag is 1.

4:0 Baud Rate Modulo Divisor — The 13 bits in SBR[12:0] are referred to collectively as BR, and they set the
SBR[12:8] modulo divide rate for the SCI baud rate generator. When BR = 0, the SCI baud rate generator is disabled to
reduce supply current. When BR = 1 to 8191, the SCI baud rate = BUSCLK/(16×BR). See also BR bits in
Table 12-2.

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7 6 5 4 3 2 1 0

R
SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0
W

Reset 0 0 0 0 0 1 0 0

Figure 12-5. SCI Baud Rate Register (SCI1BDL)

Table 12-2. SCI1BDL Field Descriptions

Field Description

7:0 Baud Rate Modulo Divisor — These 13 bits in SBR[12:0] are referred to collectively as BR, and they set the
SBR[7:0] modulo divide rate for the SCI baud rate generator. When BR = 0, the SCI baud rate generator is disabled to
reduce supply current. When BR = 1 to 8191, the SCI baud rate = BUSCLK/(16×BR). See also BR bits in
Table 12-1.

12.2.2 SCI Control Register 1 (SCI1C1)

This read/write register is used to control various optional features of the SCI system.

7 6 5 4 3 2 1 0

R
LOOPS SCISWAI RSRC M WAKE ILT PE PT
W

Reset 0 0 0 0 0 0 0 0

Figure 12-6. SCI Control Register 1 (SCI1C1)

Table 12-3. SCI1C1 Field Descriptions

Field Description

7 Loop Mode Select — Selects between loop back modes and normal 2-pin full-duplex modes. When
LOOPS LOOPS = 1, the transmitter output is internally connected to the receiver input.
0 Normal operation — RxD and TxD use separate pins.
1 Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input. (See
RSRC bit.) RxD pin is not used by SCI.
6 SCI Stops in Wait Mode
SCISWAI 0 SCI clocks continue to run in wait mode so the SCI can be the source of an interrupt that wakes up the CPU.
1 SCI clocks freeze while CPU is in wait mode.
5 Receiver Source Select — This bit has no meaning or effect unless the LOOPS bit is set to 1. When
RSRC LOOPS = 1, the receiver input is internally connected to the TxD pin and RSRC determines whether this
connection is also connected to the transmitter output.
0 Provided LOOPS = 1, RSRC = 0 selects internal loop back mode and the SCI does not use the RxD pins.
1 Single-wire SCI mode where the TxD pin is connected to the transmitter output and receiver input.
4 9-Bit or 8-Bit Mode Select
M 0 Normal — start + 8 data bits (LSB first) + stop.
1 Receiver and transmitter use 9-bit data characters
start + 8 data bits (LSB first) + 9th data bit + stop.

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Table 12-3. SCI1C1 Field Descriptions (continued)

Field Description

3 Receiver Wakeup Method Select — Refer to Section 12.3.3.2, “Receiver Wakeup Operation” for more
WAKE information.
0 Idle-line wakeup.
1 Address-mark wakeup.
2 Idle Line Type Select — Setting this bit to 1 ensures that the stop bit and logic 1 bits at the end of a character
ILT do not count toward the 10 or 11 bit times of logic high level needed by the idle line detection logic. Refer to
Section 12.3.3.2.1, “Idle-Line Wakeup” for more information.
0 Idle character bit count starts after start bit.
1 Idle character bit count starts after stop bit.
1 Parity Enable — Enables hardware parity generation and checking. When parity is enabled, the most significant
PE bit (MSB) of the data character (eighth or ninth data bit) is treated as the parity bit.
0 No hardware parity generation or checking.
1 Parity enabled.
0 Parity Type — Provided parity is enabled (PE = 1), this bit selects even or odd parity. Odd parity means the total
PT number of 1s in the data character, including the parity bit, is odd. Even parity means the total number of 1s in
the data character, including the parity bit, is even.
0 Even parity.
1 Odd parity.

12.2.3 SCI Control Register 2 (SCI1C2)

This register can be read or written at any time.

7 6 5 4 3 2 1 0

R
TIE TCIE RIE ILIE TE RE RWU SBK
W

Reset 0 0 0 0 0 0 0 0

Figure 12-7. SCI Control Register 2 (SCI1C2)

Table 12-4. SCI1C2 Field Descriptions

Field Description

7 Transmit Interrupt Enable (for TDRE)

TIE 0 Hardware interrupts from TDRE disabled (use polling).
1 Hardware interrupt requested when TDRE flag is 1.
6 Transmission Complete Interrupt Enable (for TC)
TCIE 0 Hardware interrupts from TC disabled (use polling).
1 Hardware interrupt requested when TC flag is 1.
5 Receiver Interrupt Enable (for RDRF)
RIE 0 Hardware interrupts from RDRF disabled (use polling).
1 Hardware interrupt requested when RDRF flag is 1.
4 Idle Line Interrupt Enable (for IDLE)
ILIE 0 Hardware interrupts from IDLE disabled (use polling).
1 Hardware interrupt requested when IDLE flag is 1.

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Table 12-4. SCI1C2 Field Descriptions (continued)

Field Description

3 Transmitter Enable
TE 0 Transmitter off.
1 Transmitter on.
TE must be 1 in order to use the SCI transmitter. When TE = 1, the SCI forces the TxD pin to act as an output
for the SCI system.
When the SCI is configured for single-wire operation (LOOPS = RSRC = 1), TXDIR controls the direction of
traffic on the single SCI communication line (TxD pin).
TE also can be used to queue an idle character by writing TE = 0 then TE = 1 while a transmission is in progress.
Refer to Section 12.3.2.1, “Send Break and Queued Idle” for more details.
When TE is written to 0, the transmitter keeps control of the port TxD pin until any data, queued idle, or queued
break character finishes transmitting before allowing the pin to revert to a general-purpose I/O pin.
2 Receiver Enable — When the SCI receiver is off, the RxD pin reverts to being a general-purpose port I/O pin.
RE If LOOPS = 1 the RxD pin reverts to being a general-purpose I/O pin even if RE = 1.
0 Receiver off.
1 Receiver on.
1 Receiver Wakeup Control — This bit can be written to 1 to place the SCI receiver in a standby state where it
RWU waits for automatic hardware detection of a selected wakeup condition. The wakeup condition is either an idle
line between messages (WAKE = 0, idle-line wakeup), or a logic 1 in the most significant data bit in a character
(WAKE = 1, address-mark wakeup). Application software sets RWU and (normally) a selected hardware
condition automatically clears RWU. Refer to Section 12.3.3.2, “Receiver Wakeup Operation” for more details.
0 Normal SCI receiver operation.
1 SCI receiver in standby waiting for wakeup condition.
0 Send Break — Writing a 1 and then a 0 to SBK queues a break character in the transmit data stream. Additional
SBK break characters of 10 or 11 (13 or 14 if BRK13 = 1) bit times of logic 0 are queued as long as SBK = 1.
Depending on the timing of the set and clear of SBK relative to the information currently being transmitted, a
second break character may be queued before software clears SBK. Refer to Section 12.3.2.1, “Send Break and
Queued Idle” for more details.
0 Normal transmitter operation.
1 Queue break character(s) to be sent.

12.2.4 SCI Status Register 1 (SCI1S1)

This register has eight read-only status flags. Writes have no effect. Special software sequences (which do
not involve writing to this register) are used to clear these status flags.

7 6 5 4 3 2 1 0

R TDRE TC RDRF IDLE OR NF FE PF

Reset 1 1 0 0 0 0 0 0

= Unimplemented or Reserved

Figure 12-8. SCI Status Register 1 (SCI1S1)

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Table 12-5. SCI1S1 Field Descriptions

Field Description

7 Transmit Data Register Empty Flag — TDRE is set out of reset and when a transmit data value transfers from
TDRE the transmit data buffer to the transmit shifter, leaving room for a new character in the buffer. To clear TDRE, read
SCI1S1 with TDRE = 1 and then write to the SCI data register (SCI1D).
0 Transmit data register (buffer) full.
1 Transmit data register (buffer) empty.
6 Transmission Complete Flag — TC is set out of reset and when TDRE = 1 and no data, preamble, or break
TC character is being transmitted.
0 Transmitter active (sending data, a preamble, or a break).
1 Transmitter idle (transmission activity complete).
TC is cleared automatically by reading SCI1S1 with TC = 1 and then doing one of the following three things:
• Write to the SCI data register (SCI1D) to transmit new data
• Queue a preamble by changing TE from 0 to 1
• Queue a break character by writing 1 to SBK in SCI1C2
5 Receive Data Register Full Flag — RDRF becomes set when a character transfers from the receive shifter into
RDRF the receive data register (SCI1D). To clear RDRF, read SCI1S1 with RDRF = 1 and then read the SCI data
register (SCI1D).
0 Receive data register empty.
1 Receive data register full.
4 Idle Line Flag — IDLE is set when the SCI receive line becomes idle for a full character time after a period of
IDLE activity. When ILT = 0, the receiver starts counting idle bit times after the start bit. So if the receive character is
all 1s, these bit times and the stop bit time count toward the full character time of logic high (10 or 11 bit times
depending on the M control bit) needed for the receiver to detect an idle line. When ILT = 1, the receiver doesn’t
start counting idle bit times until after the stop bit. So the stop bit and any logic high bit times at the end of the
previous character do not count toward the full character time of logic high needed for the receiver to detect an
idle line.
To clear IDLE, read SCI1S1 with IDLE = 1 and then read the SCI data register (SCI1D). After IDLE has been
cleared, it cannot become set again until after a new character has been received and RDRF has been set. IDLE
will get set only once even if the receive line remains idle for an extended period.
0 No idle line detected.
1 Idle line was detected.
3 Receiver Overrun Flag — OR is set when a new serial character is ready to be transferred to the receive data
OR register (buffer), but the previously received character has not been read from SCI1D yet. In this case, the new
character (and all associated error information) is lost because there is no room to move it into SCI1D. To clear
OR, read SCI1S1 with OR = 1 and then read the SCI data register (SCI1D).
0 No overrun.
1 Receive overrun (new SCI data lost).
2 Noise Flag — The advanced sampling technique used in the receiver takes seven samples during the start bit
NF and three samples in each data bit and the stop bit. If any of these samples disagrees with the rest of the samples
within any bit time in the frame, the flag NF will be set at the same time as the flag RDRF gets set for the
character. To clear NF, read SCI1S1 and then read the SCI data register (SCI1D).
0 No noise detected.
1 Noise detected in the received character in SCI1D.

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Table 12-5. SCI1S1 Field Descriptions (continued)

Field Description

1 Framing Error Flag — FE is set at the same time as RDRF when the receiver detects a logic 0 where the stop
FE bit was expected. This suggests the receiver was not properly aligned to a character frame. To clear FE, read
SCI1S1 with FE = 1 and then read the SCI data register (SCI1D).
0 No framing error detected. This does not guarantee the framing is correct.
1 Framing error.
0 Parity Error Flag — PF is set at the same time as RDRF when parity is enabled (PE = 1) and the parity bit in
PF the received character does not agree with the expected parity value. To clear PF, read SCI1S1 and then read
the SCI data register (SCI1D).
0 No parity error.
1 Parity error.

12.2.5 SCI Status Register 2 (SCI1S2)

This register has one read-only status flag.

7 6 5 4 3 2 1 0

R 0 RAF
LBKDIF RXEDGIF RXINV RWUID BRK13 LBKDE
W

Reset 0 0 0 0 0 0 0 0

= Unimplemented or Reserved

Figure 12-9. SCI Status Register 2 (SCI1S2)

Table 12-6. SCI1S2 Field Descriptions

Field Description

7 LIN Break Detect Interrupt Flag — LBKDIF is set when the LIN break detect circuitry is enabled and a LIN break
LBKDIF character is detected. LBKDIF is cleared by writing a “1” to it.
0 No LIN break character has been detected.
1 LIN break character has been detected.

6 RxD Pin Active Edge Interrupt Flag — RXEDGIF is set when an active edge (falling if RXINV = 0, rising if
RXEDGIF RXINV=1) on the RxD pin occurs. RXEDGIF is cleared by writing a “1” to it.
0 No active edge on the receive pin has occurred.
1 An active edge on the receive pin has occurred.

4 Receive Data Inversion — Setting this bit reverses the polarity of the received data input.
RXINV1 0 Receive data not inverted
1 Receive data inverted

3 Receive Wake Up Idle Detect— RWUID controls whether the idle character that wakes up the receiver sets the
RWUID IDLE bit.
0 During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character.
1 During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character.

2 Break Character Generation Length — BRK13 is used to select a longer transmitted break character length.
BRK13 Detection of a framing error is not affected by the state of this bit.
0 Break character is transmitted with length of 10 bit times (11 if M = 1)
1 Break character is transmitted with length of 13 bit times (14 if M = 1)

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Table 12-6. SCI1S2 Field Descriptions (continued)

Field Description

1 LIN Break Detection Enable— LBKDE is used to select a longer break character detection length. While
LBKDE LBKDE is set, framing error (FE) and receive data register full (RDRF) flags are prevented from setting.
0 Break character is detected at length of 10 bit times (11 if M = 1).
1 Break character is detected at length of 11 bit times (12 if M = 1).

0 Receiver Active Flag — RAF is set when the SCI receiver detects the beginning of a valid start bit, and RAF is
RAF cleared automatically when the receiver detects an idle line. This status flag can be used to check whether an
SCI character is being received before instructing the MCU to go to stop mode.
0 SCI receiver idle waiting for a start bit.
1 SCI receiver active (RxD input not idle).
1
Setting RXINV inverts the RxD input for all cases: data bits, start and stop bits, break, and idle.

When using an internal oscillator in a LIN system, it is necessary to raise the break detection threshold by
one bit time. Under the worst case timing conditions allowed in LIN, it is possible that a 0x00 data
character can appear to be 10.26 bit times long at a slave which is running 14% faster than the master. This
would trigger normal break detection circuitry which is designed to detect a 10 bit break symbol. When
the LBKDE bit is set, framing errors are inhibited and the break detection threshold changes from 10 bits
to 11 bits, preventing false detection of a 0x00 data character as a LIN break symbol.

12.2.6 SCI Control Register 3 (SCI1C3)

7 6 5 4 3 2 1 0

R R8
T8 TXDIR TXINV ORIE NEIE FEIE PEIE
W

Reset 0 0 0 0 0 0 0 0

= Unimplemented or Reserved

Figure 12-10. SCI Control Register 3 (SCI1C3)

Table 12-7. SCI1C3 Field Descriptions

Field Description

7 Ninth Data Bit for Receiver — When the SCI is configured for 9-bit data (M = 1), R8 can be thought of as a
R8 ninth receive data bit to the left of the MSB of the buffered data in the SCI1D register. When reading 9-bit data,
read R8 before reading SCI1D because reading SCI1D completes automatic flag clearing sequences which
could allow R8 and SCI1D to be overwritten with new data.

6 Ninth Data Bit for Transmitter — When the SCI is configured for 9-bit data (M = 1), T8 may be thought of as a
T8 ninth transmit data bit to the left of the MSB of the data in the SCI1D register. When writing 9-bit data, the entire
9-bit value is transferred to the SCI shift register after SCI1D is written so T8 should be written (if it needs to
change from its previous value) before SCI1D is written. If T8 does not need to change in the new value (such
as when it is used to generate mark or space parity), it need not be written each time SCI1D is written.

5 TxD Pin Direction in Single-Wire Mode — When the SCI is configured for single-wire half-duplex operation
TXDIR (LOOPS = RSRC = 1), this bit determines the direction of data at the TxD pin.
0 TxD pin is an input in single-wire mode.
1 TxD pin is an output in single-wire mode.

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Table 12-7. SCI1C3 Field Descriptions (continued)

Field Description

4 Transmit Data Inversion — Setting this bit reverses the polarity of the transmitted data output.
TXINV1 0 Transmit data not inverted
1 Transmit data inverted

3 Overrun Interrupt Enable — This bit enables the overrun flag (OR) to generate hardware interrupt requests.
ORIE 0 OR interrupts disabled (use polling).
1 Hardware interrupt requested when OR = 1.

2 Noise Error Interrupt Enable — This bit enables the noise flag (NF) to generate hardware interrupt requests.
NEIE 0 NF interrupts disabled (use polling).
1 Hardware interrupt requested when NF = 1.

1 Framing Error Interrupt Enable — This bit enables the framing error flag (FE) to generate hardware interrupt
FEIE requests.
0 FE interrupts disabled (use polling).
1 Hardware interrupt requested when FE = 1.

0 Parity Error Interrupt Enable — This bit enables the parity error flag (PF) to generate hardware interrupt
PEIE requests.
0 PF interrupts disabled (use polling).
1 Hardware interrupt requested when PF = 1.
1
Setting TXINV inverts the TxD output for all cases: data bits, start and stop bits, break, and idle.

12.2.7 SCI Data Register (SCI1D)

This register is actually two separate registers. Reads return the contents of the read-only receive data
buffer and writes go to the write-only transmit data buffer. Reads and writes of this register are also
involved in the automatic flag clearing mechanisms for the SCI status flags.

7 6 5 4 3 2 1 0

R R7 R6 R5 R4 R3 R2 R1 R0

W T7 T6 T5 T4 T3 T2 T1 T0

Reset 0 0 0 0 0 0 0 0

Figure 12-11. SCI Data Register (SCI1D)

12.3 Functional Description

The SCI allows full-duplex, asynchronous, NRZ serial communication among the MCU and remote
devices, including other MCUs. The SCI comprises a baud rate generator, transmitter, and receiver block.
The transmitter and receiver operate independently, although they use the same baud rate generator. During
normal operation, the MCU monitors the status of the SCI, writes the data to be transmitted, and processes
received data. The following describes each of the blocks of the SCI.

12.3.1 Baud Rate Generation

As shown in Figure 12-12, the clock source for the SCI baud rate generator is the bus-rate clock.

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MODULO DIVIDE BY
(1 THROUGH 8191)

DIVIDE BY
16 Tx BAUD RATE
BUSCLK SBR12:SBR0

BAUD RATE GENERATOR Rx SAMPLING CLOCK

OFF IF [SBR12:SBR0] = 0 (16 × BAUD RATE)
BUSCLK
BAUD RATE =
[SBR12:SBR0] × 16
Figure 12-12. SCI Baud Rate Generation

SCI communications require the transmitter and receiver (which typically derive baud rates from
independent clock sources) to use the same baud rate. Allowed tolerance on this baud frequency depends
on the details of how the receiver synchronizes to the leading edge of the start bit and how bit sampling is
performed.
The MCU resynchronizes to bit boundaries on every high-to-low transition, but in the worst case, there are
no such transitions in the full 10- or 11-bit time character frame so any mismatch in baud rate is
accumulated for the whole character time. For a Freescale Semiconductor SCI system whose bus
frequency is driven by a crystal, the allowed baud rate mismatch is about 4.5percent for 8-bit data format
and about 4 percent for 9-bit data format. Although baud rate modulo divider settings do not always
produce baud rates that exactly match standard rates, it is normally possible to get within a few percent,
which is acceptable for reliable communications.

12.3.2 Transmitter Functional Description

This section describes the overall block diagram for the SCI transmitter, as well as specialized functions
for sending break and idle characters. The transmitter block diagram is shown in Figure 12-2.
The transmitter output (TxD) idle state defaults to logic high (TXINV = 0 following reset). The transmitter
output is inverted by setting TXINV = 1. The transmitter is enabled by setting the TE bit in SCI1C2. This
queues a preamble character that is one full character frame of the idle state. The transmitter then remains
idle until data is available in the transmit data buffer. Programs store data into the transmit data buffer by
writing to the SCI data register (SCI1D).
The central element of the SCI transmitter is the transmit shift register that is either 10 or 11 bits long
depending on the setting in the M control bit. For the remainder of this section, we will assume M = 0,
selecting the normal 8-bit data mode. In 8-bit data mode, the shift register holds a start bit, eight data bits,
and a stop bit. When the transmit shift register is available for a new SCI character, the value waiting in
the transmit data register is transferred to the shift register (synchronized with the baud rate clock) and the
transmit data register empty (TDRE) status flag is set to indicate another character may be written to the
transmit data buffer at SCI1D.
If no new character is waiting in the transmit data buffer after a stop bit is shifted out the TxD pin, the
transmitter sets the transmit complete flag and enters an idle mode, with TxD high, waiting for more
characters to transmit.

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Writing 0 to TE does not immediately release the pin to be a general-purpose I/O pin. Any transmit activity
that is in progress must first be completed. This includes data characters in progress, queued idle
characters, and queued break characters.

12.3.2.1 Send Break and Queued Idle

The SBK control bit in SCI1C2 is used to send break characters which were originally used to gain the
attention of old teletype receivers. Break characters are a full character time of logic 0 (10 bit times
including the start and stop bits). A longer break of 13 bit times can be enabled by setting BRK13 = 1.
Normally, a program would wait for TDRE to become set to indicate the last character of a message has
moved to the transmit shifter, then write 1 and then write 0 to the SBK bit. This action queues a break
character to be sent as soon as the shifter is available. If SBK is still 1 when the queued break moves into
the shifter (synchronized to the baud rate clock), an additional break character is queued. If the receiving
device is another Freescale Semiconductor SCI, the break characters will be received as 0s in all eight data
bits and a framing error (FE = 1) occurs.
When idle-line wakeup is used, a full character time of idle (logic 1) is needed between messages to wake
up any sleeping receivers. Normally, a program would wait for TDRE to become set to indicate the last
character of a message has moved to the transmit shifter, then write 0 and then write 1 to the TE bit. This
action queues an idle character to be sent as soon as the shifter is available. As long as the character in the
shifter does not finish while TE = 0, the SCI transmitter never actually releases control of the TxD pin. If
there is a possibility of the shifter finishing while TE = 0, set the general-purpose I/O controls so the pin
that is shared with TxD is an output driving a logic 1. This ensures that the TxD line will look like a normal
idle line even if the SCI loses control of the port pin between writing 0 and then 1 to TE.
The length of the break character is affected by the BRK13 and M bits as shown below.
Table 12-8. Break Character Length

BRK13 M Break Character Length

0 0 10 bit times
0 1 11 bit times
1 0 13 bit times
1 1 14 bit times

12.3.3 Receiver Functional Description

In this section, the receiver block diagram (Figure 12-3) is used as a guide for the overall receiver
functional description. Next, the data sampling technique used to reconstruct receiver data is described in
more detail. Finally, two variations of the receiver wakeup function are explained.
The receiver input is inverted by setting RXINV = 1. The receiver is enabled by setting the RE bit in
SCI1C2. Character frames consist of a start bit of logic 0, eight (or nine) data bits (LSB first), and a stop
bit of logic 1. For information about 9-bit data mode, refer to Section 12.3.5.1, “8- and 9-Bit Data Modes.”
For the remainder of this discussion, we assume the SCI is configured for normal 8-bit data mode.
After receiving the stop bit into the receive shifter, and provided the receive data register is not already full,
the data character is transferred to the receive data register and the receive data register full (RDRF) status

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flag is set. If RDRF was already set indicating the receive data register (buffer) was already full, the overrun
(OR) status flag is set and the new data is lost. Because the SCI receiver is double-buffered, the program
has one full character time after RDRF is set before the data in the receive data buffer must be read to avoid
a receiver overrun.
When a program detects that the receive data register is full (RDRF = 1), it gets the data from the receive
data register by reading SCI1D. The RDRF flag is cleared automatically by a 2-step sequence which is
normally satisfied in the course of the user’s program that handles receive data. Refer to Section 12.3.4,
“Interrupts and Status Flags” for more details about flag clearing.

12.3.3.1 Data Sampling Technique

The SCI receiver uses a 16× baud rate clock for sampling. The receiver starts by taking logic level samples
at 16 times the baud rate to search for a falling edge on the RxD serial data input pin. A falling edge is
defined as a logic 0 sample after three consecutive logic 1 samples. The 16× baud rate clock is used to
divide the bit time into 16 segments labeled RT1 through RT16. When a falling edge is located, three more
samples are taken at RT3, RT5, and RT7 to make sure this was a real start bit and not merely noise. If at
least two of these three samples are 0, the receiver assumes it is synchronized to a receive character.
The receiver then samples each bit time, including the start and stop bits, at RT8, RT9, and RT10 to
determine the logic level for that bit. The logic level is interpreted to be that of the majority of the samples
taken during the bit time. In the case of the start bit, the bit is assumed to be 0 if at least two of the samples
at RT3, RT5, and RT7 are 0 even if one or all of the samples taken at RT8, RT9, and RT10 are 1s. If any
sample in any bit time (including the start and stop bits) in a character frame fails to agree with the logic
level for that bit, the noise flag (NF) will be set when the received character is transferred to the receive
data buffer.
The falling edge detection logic continuously looks for falling edges, and if an edge is detected, the sample
clock is resynchronized to bit times. This improves the reliability of the receiver in the presence of noise
or mismatched baud rates. It does not improve worst case analysis because some characters do not have
any extra falling edges anywhere in the character frame.
In the case of a framing error, provided the received character was not a break character, the sampling logic
that searches for a falling edge is filled with three logic 1 samples so that a new start bit can be detected
almost immediately.
In the case of a framing error, the receiver is inhibited from receiving any new characters until the framing
error flag is cleared. The receive shift register continues to function, but a complete character cannot
transfer to the receive data buffer if FE is still set.

12.3.3.2 Receiver Wakeup Operation

Receiver wakeup is a hardware mechanism that allows an SCI receiver to ignore the characters in a
message that is intended for a different SCI receiver. In such a system, all receivers evaluate the first
character(s) of each message, and as soon as they determine the message is intended for a different
receiver, they write logic 1 to the receiver wake up (RWU) control bit in SCI1C2. When RWU bit is set,
the status flags associated with the receiver (with the exception of the idle bit, IDLE, when RWUID bit is
set) are inhibited from setting, thus eliminating the software overhead for handling the unimportant

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message characters. At the end of a message, or at the beginning of the next message, all receivers
automatically force RWU to 0 so all receivers wake up in time to look at the first character(s) of the next
message.

12.3.3.2.1 Idle-Line Wakeup

When WAKE = 0, the receiver is configured for idle-line wakeup. In this mode, RWU is cleared
automatically when the receiver detects a full character time of the idle-line level. The M control bit selects
8-bit or 9-bit data mode that determines how many bit times of idle are needed to constitute a full character
time (10 or 11 bit times because of the start and stop bits).
When RWU is one and RWUID is zero, the idle condition that wakes up the receiver does not set the IDLE
flag. The receiver wakes up and waits for the first data character of the next message which will set the
RDRF flag and generate an interrupt if enabled. When RWUID is one, any idle condition sets the IDLE
flag and generates an interrupt if enabled, regardless of whether RWU is zero or one.
The idle-line type (ILT) control bit selects one of two ways to detect an idle line. When ILT = 0, the idle
bit counter starts after the start bit so the stop bit and any logic 1s at the end of a character count toward
the full character time of idle. When ILT = 1, the idle bit counter does not start until after a stop bit time,
so the idle detection is not affected by the data in the last character of the previous message.

12.3.3.2.2 Address-Mark Wakeup

When WAKE = 1, the receiver is configured for address-mark wakeup. In this mode, RWU is cleared
automatically when the receiver detects a logic 1 in the most significant bit of a received character (eighth
bit in M = 0 mode and ninth bit in M = 1 mode).
Address-mark wakeup allows messages to contain idle characters but requires that the MSB be reserved
for use in address frames. The logic 1 MSB of an address frame clears the RWU bit before the stop bit is
received and sets the RDRF flag. In this case the character with the MSB set is received even though the
receiver was sleeping during most of this character time.

12.3.4 Interrupts and Status Flags

The SCI system has three separate interrupt vectors to reduce the amount of software needed to isolate the
cause of the interrupt. One interrupt vector is associated with the transmitter for TDRE and TC events.
Another interrupt vector is associated with the receiver for RDRF, IDLE, RXEDGIF and LBKDIF events,
and a third vector is used for OR, NF, FE, and PF error conditions. Each of these ten interrupt sources can
be separately masked by local interrupt enable masks. The flags can still be polled by software when the
local masks are cleared to disable generation of hardware interrupt requests.
The SCI transmitter has two status flags that optionally can generate hardware interrupt requests. Transmit
data register empty (TDRE) indicates when there is room in the transmit data buffer to write another
transmit character to SCI1D. If the transmit interrupt enable (TIE) bit is set, a hardware interrupt will be
requested whenever TDRE = 1. Transmit complete (TC) indicates that the transmitter is finished
transmitting all data, preamble, and break characters and is idle with TxD at the inactive level. This flag is
often used in systems with modems to determine when it is safe to turn off the modem. If the transmit
complete interrupt enable (TCIE) bit is set, a hardware interrupt will be requested whenever TC = 1.

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Instead of hardware interrupts, software polling may be used to monitor the TDRE and TC status flags if
the corresponding TIE or TCIE local interrupt masks are 0s.
When a program detects that the receive data register is full (RDRF = 1), it gets the data from the receive
data register by reading SCI1D. The RDRF flag is cleared by reading SCI1S1 while RDRF = 1 and then
reading SCI1D.
When polling is used, this sequence is naturally satisfied in the normal course of the user program. If
hardware interrupts are used, SCI1S1 must be read in the interrupt service routine (ISR). Normally, this is
done in the ISR anyway to check for receive errors, so the sequence is automatically satisfied.
The IDLE status flag includes logic that prevents it from getting set repeatedly when the RxD line remains
idle for an extended period of time. IDLE is cleared by reading SCI1S1 while IDLE = 1 and then reading
SCI1D. After IDLE has been cleared, it cannot become set again until the receiver has received at least one
new character and has set RDRF.
If the associated error was detected in the received character that caused RDRF to be set, the error flags —
noise flag (NF), framing error (FE), and parity error flag (PF) — get set at the same time as RDRF. These
flags are not set in overrun cases.
If RDRF was already set when a new character is ready to be transferred from the receive shifter to the
receive data buffer, the overrun (OR) flag gets set instead the data along with any associated NF, FE, or PF
condition is lost.
At any time, an active edge on the RxD serial data input pin causes the RXEDGIF flag to set. The
RXEDGIF flag is cleared by writing a “1” to it. This function does depend on the receiver being enabled
(RE = 1).

12.3.5 Additional SCI Functions

The following sections describe additional SCI functions.

12.3.5.1 8- and 9-Bit Data Modes

The SCI system (transmitter and receiver) can be configured to operate in 9-bit data mode by setting the
M control bit in SCI1C1. In 9-bit mode, there is a ninth data bit to the left of the MSB of the SCI data
register. For the transmit data buffer, this bit is stored in T8 in SCI1C3. For the receiver, the ninth bit is
held in R8 in SCI1C3.
For coherent writes to the transmit data buffer, write to the T8 bit before writing to SCI1D.
If the bit value to be transmitted as the ninth bit of a new character is the same as for the previous character,
it is not necessary to write to T8 again. When data is transferred from the transmit data buffer to the
transmit shifter, the value in T8 is copied at the same time data is transferred from SCI1D to the shifter.
9-bit data mode typically is used in conjunction with parity to allow eight bits of data plus the parity in the
ninth bit. Or it is used with address-mark wakeup so the ninth data bit can serve as the wakeup bit. In
custom protocols, the ninth bit can also serve as a software-controlled marker.

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12.3.5.2 Stop Mode Operation

During all stop modes, clocks to the SCI module are halted.
In stop1 and stop2 modes, all SCI register data is lost and must be re-initialized upon recovery from these
two stop modes. No SCI module registers are affected in stop3 mode.
The receive input active edge detect circuit is still active in stop3 mode, but not in stop2. . An active edge
on the receive input brings the CPU out of stop3 mode if the interrupt is not masked (RXEDGIE = 1).
Note, because the clocks are halted, the SCI module will resume operation upon exit from stop (only in
stop3 mode). Software should ensure stop mode is not entered while there is a character being transmitted
out of or received into the SCI module.

12.3.5.3 Loop Mode

When LOOPS = 1, the RSRC bit in the same register chooses between loop mode (RSRC = 0) or
single-wire mode (RSRC = 1). Loop mode is sometimes used to check software, independent of
connections in the external system, to help isolate system problems. In this mode, the transmitter output is
internally connected to the receiver input and the RxD pin is not used by the SCI, so it reverts to a
general-purpose port I/O pin.

12.3.5.4 Single-Wire Operation

When LOOPS = 1, the RSRC bit in the same register chooses between loop mode (RSRC = 0) or
single-wire mode (RSRC = 1). Single-wire mode is used to implement a half-duplex serial connection.
The receiver is internally connected to the transmitter output and to the TxD pin. The RxD pin is not used
and reverts to a general-purpose port I/O pin.
In single-wire mode, the TXDIR bit in SCI1C3 controls the direction of serial data on the TxD pin. When
TXDIR = 0, the TxD pin is an input to the SCI receiver and the transmitter is temporarily disconnected
from the TxD pin so an external device can send serial data to the receiver. When TXDIR = 1, the TxD pin
is an output driven by the transmitter. In single-wire mode, the internal loop back connection from the
transmitter to the receiver causes the receiver to receive characters that are sent out by the transmitter.

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Chapter 13
Real-Time Counter (S08RTCV1)
13.1 Introduction
The RTC module consists of one 8-bit counter, one 8-bit comparator, several binary-based and
decimal-based prescaler dividers, three clock sources, and one programmable periodic interrupt. This
module can be used for time-of-day, calendar or any task scheduling functions. It can also serve as a cyclic
wake up from low power modes without the need of external components.
All devices in the MC9S08EN32 Series feature the RTC.

13.1.1 RTC Clock Signal Names

References to ERCLK and IRCLK in this chapter correspond to signals MCGERCLK and MCGIRCLK,
respectively.

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 223
Chapter 13 Real-Time Counter (S08RTCV1)

HCS08 CORE PTA7/PIA7/ADP7/IRQ

PTA6/PIA6/ADP6
PTA5/PIA5/ADP5
CPU

PORT A
PTA4/PIA4/ADP4
ACMP1O
ANALOG COMPARATOR PTA3/PIA3/ADP3/ACMP1O
BKGD/MS ACMP1-
(ACMP1) PTA2/PIA2/ADP2/ACMP1-
BDC BKP ACMP1+
PTA1/PIA1/ADP1/ACMP1+
PTA0/PIA0/ADP0/MCLK
HCS08 SYSTEM CONTROL
PTB7/PIB7
RESETS AND INTERRUPTS PTB6/PIB6
RESET
MODES OF OPERATION PTB5/PIB5

PORT B
POWER MANAGEMENT PTB4/PIB4
PTB3/PIB3/ADP11
8 PTB2/PIB2/ADP10
COP LVD PTB1/PIB1/ADP9
IRQ

ADP7-ADP0 PTB0/PIB0/ADP8
INT IRQ
12-CHANNEL,10-BIT
ADP11-ADP8
ANALOG-TO-DIGITAL
VREFH
CONVERTER (ADC)
VREFL
VDDA
VSSA

TPM1CH3–TPM1CH0
PTD7/PID7
USER FLASH 4-CHANNEL TIMER/PWM 6 PTD6/PID6
MODULE (TPM1) TPM1CLK
MC9S08EN32 = 32K PTD5/PID5/TPM1CH3
MC9S08EN16 = 16K

PORT D
PTD4/PID4/TPM1CH2
PTD3/PID3/TPM1CH1
PTD2/PID2/TPM1CH0
PTD1/PID1
PTD0/PID0
PTE7
PTE6
MISO
USER RAM PTE5/MISO
MOSI
PORT E

MC9S08EN32 = 1 KBYTE SERIAL PERIPHERAL PTE4/MOSI

SPSCK
MC9S08EN16 = 512 BYTES INTERFACE MODULE (SPI) PTE3/SPSCK
SS
PTE2/SS
RxD1
PTE1/RxD1
DEBUG MODULE (DBG) SERIAL COMMUNICATIONS TxD1
PTE0/TxD1
INTERFACE (SCI1)

REAL-TIME COUNTER (RTC) PTF5

PORT F

PTF4
VDD PTF3
VDD VOLTAGE PTF2/TPM1CLK
VSS REGULATOR PTF1
VSS PTF0

MULTI-PURPOSE
CLOCK GENERATOR
PORT G

(MCG)
XTAL
PTG1/XTAL
OSCILLATOR (XOSC) EXTAL
PTG0/EXTAL
- VREFH/VREFL internally connected to VDDA/VSSA
- VDD and VSS pins are each internally connected to two pads in 32-pin package - Pin not connected in 32-pin package

Figure 13-1. MC9S08EN32 Block Diagram

MC9S08EN32 Series Data Sheet, Rev. 2

224 Freescale Semiconductor
 Chapter 13 Real-Time Counter (S08RTCV1)

13.1.2 Features
Features of the RTC module include:
• 8-bit up-counter
— 8-bit modulo match limit
— Software controllable periodic interrupt on match
• Three software selectable clock sources for input to prescaler with selectable binary-based and
decimal-based divider values
— 1-kHz internal Low Power Oscillator (LPO)
— External clock (ERCLK)
— 32-kHz internal clock (IRCLK)

13.1.3 Modes of Operation

This section defines the operation in stop, wait and background debug modes.
Wait Mode
The RTC continues to run in wait mode if enabled before executing the WAIT instruction. Therefore, the
RTC can be used to bring the MCU out of wait mode if the real-time interrupt is enabled. For lowest
possible current consumption, the RTC should be stopped by software if not needed as an interrupt source
during wait mode.
Stop Modes
The RTC continues to run in stop2 or stop3 mode if the RTC is enabled before executing the STOP
instruction. Therefore, the RTC can be used to bring the MCU out of stop modes with no external
components, if the real-time interrupt is enabled.
The LPO clock can be used in both stop2 and stop3 modes. ERCLK and IRCLK clocks are only available
in stop3 mode.
Power consumption is lower when all clock sources are disabled, but in that case the real-time interrupt
cannot wake up the MCU from stop modes.

Active Background Mode

The RTC suspends all counting during active background mode until the microcontroller returns to normal
user operating mode. Counting resumes from the suspended value as long as the RTCMOD register is not
written and the RTCPS and RTCLKS bits are not altered.

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 225
Chapter 13 Real-Time Counter (S08RTCV1)

13.1.4 Block Diagram

The block diagram for the RTC module is shown in Figure 13-2.

LPO CLOCK
ERCLK SOURCE
SELECT
IRCLK

VDD
8-BIT MODULO
RTCLKS (RTCMOD)
BACKGROUND D Q RTIF RTC
MODE INTERRUPT
REQUEST
RTCPS E
RTCLKS[0] 8-BIT COMPARATOR
R

RTIE
RTC Write 1 to
PRESCALER CLOCK 8-BIT COUNTER RTIF
DIVIDE-BY (RTCCNT)

Figure 13-2. Real-Time Counter (RTC) Block Diagram

13.2 External Signal Description

The RTC does not include any off-chip signals.

13.3 Register Definition

The RTC includes a status and control register, an 8-bit counter register, and an 8-bit modulo register.
Refer to the direct-page register summary in the memory section of this data sheet for the absolute address
assignments for all RTC registers.This section refers to registers and control bits only by their names and
relative address offsets.
Table 13-1 is a summary of RTC registers.
Table 13-1. RTC Register Summary

Name 7 6 5 4 3 2 1 0

R
RTCSC RTIF RTCLKS RTIE RTCPS
W

R RTCCNT
RTCCNT
W

R
RTCMOD RTCMOD
W

MC9S08EN32 Series Data Sheet, Rev. 2

226 Freescale Semiconductor
 Chapter 13 Real-Time Counter (S08RTCV1)

13.3.1 RTC Status and Control Register (RTCSC)

RTCSC contains the real-time interrupt status flag (RTIF), the clock select bits (RTCLKS), the real-time
interrupt enable bit (RTIE), and the prescaler select bits (RTCPS).

7 6 5 4 3 2 1 0

R
RTIF RTCLKS RTIE RTCPS
W

Reset: 0 0 0 0 0 0 0 0

Figure 13-3. RTC Status and Control Register (RTCSC)

Table 13-2. RTCSC Field Descriptions

Field Description

7 Real-Time Interrupt Flag — This status bit indicates the RTC counter register reached the value in the RTC
RTIF modulo register. Writing a logic 0 has no effect. Writing a logic 1 clears the bit and the real-time interrupt request.
Reset clears RTIF to 0.
0 RTC counter has not reached the value in the RTC modulo register.
1 RTC counter has reached the value in the RTC modulo register.

6:5 Real-Time Clock Source Select — These two read/write bits select the clock source input to the RTC
RTCLKS prescaler. Changing the clock source clears the prescaler and RTCCNT counters. When selecting a clock
source, ensure that the clock source is properly enabled (if applicable) to ensure correct operation of the RTC.
Reset clears RTCLKS to 00.
00 Real-time clock source is the 1-kHz low power oscillator (LPO)
01 Real-time clock source is the external clock (ERCLK)
1x Real-time clock source is the internal clock (IRCLK)

4 Real-Time Interrupt Enable — This read/write bit enables real-time interrupts. If RTIE is set, then an interrupt
RTIE is generated when RTIF is set. Reset clears RTIE to 0.
0 Real-time interrupt requests are disabled. Use software polling.
1 Real-time interrupt requests are enabled.

3:0 Real-Time Clock Prescaler Select — These four read/write bits select binary-based or decimal-based
RTCPS divide-by values for the clock source. See Table 13-3. Changing the prescaler value clears the prescaler and
RTCCNT counters. Reset clears RTCPS to 0000.

Table 13-3. RTC Prescaler Divide-by values

RTCPS
RTCLKS[0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0 OFF 23 25 26 27 28 29 210 1 2 22 10 24 102 5x102 103

1 OFF 210 211 212 213 214 215 216 103 2x103 5x103 104 2x104 5x104 105 2x105

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 227
Chapter 13 Real-Time Counter (S08RTCV1)

13.3.2 RTC Counter Register (RTCCNT)

RTCCNT is the read-only value of the current RTC count of the 8-bit counter.

7 6 5 4 3 2 1 0

R RTCCNT

Reset: 0 0 0 0 0 0 0 0

Figure 13-4. RTC Counter Register (RTCCNT)

Table 13-4. RTCCNT Field Description

Field Description

7:0 RTC Count— These eight read-only bits contain the current value of the 8-bit counter. Writes have no effect to this
RTCCNT register. Reset, writing to RTCMOD, or writing different values to RTCLKS and RTCPS clear the count to 0x00.

13.3.3 RTC Modulo Register (RTCMOD)

7 6 5 4 3 2 1 0

R
RTCMOD
W

Reset: 0 0 0 0 0 0 0 0

Figure 13-5. RTC Modulo Register (RTCMOD)

Table 13-5. RTCMOD Field Descriptions

Field Description

7:0 RTC Modulo — These eight read/write bits contain the modulo value used to reset the count to 0x00 upon a
RTCMOD compare match and set the RTIF status bit. A value of 0x00 sets the RTIF bit on each rising edge of the prescaler
output. Writing to RTCMOD resets the prescaler and the RTCCNT counters to 0x00. Reset sets the modulo to
0x00.

MC9S08EN32 Series Data Sheet, Rev. 2

228 Freescale Semiconductor
 Chapter 13 Real-Time Counter (S08RTCV1)

13.4 Functional Description

The RTC is composed of a main 8-bit up-counter with an 8-bit modulo register, a clock source selector,
and a prescaler block with binary-based and decimal-based selectable values. The module also contains
software selectable interrupt logic.
After any MCU reset, the counter is stopped and reset to 0x00, the modulus register is set to 0x00, and the
prescaler is off. The 1-kHz internal oscillator clock is selected as the default clock source. To start the
prescaler, write any value other than zero to the prescaler select bits (RTCPS).
Three clock sources are software selectable: the low power oscillator clock (LPO), the external clock
(ERCLK) and the internal clock (IRCLK). The RTC clock select bits (RTCLKS) are used to select the
desired clock source. If a different value is written to RTCLKS, the prescaler and RTCCNT counters are
reset to 0x00.
RTCPS and the RTCLKS[0] bit select the desired divide-by value. If a different value is written to RTCPS,
the prescaler and RTCCNT counters are reset to 0x00. Table 13-6 shows different prescaler period values.
Table 13-6. Prescaler Period

1-kHz internal clock 1-MHz external clock 32-kHz internal clock 32-kHz internal clock
RTCPS source prescaler period source prescaler period source prescaler period source prescaler period
(RTCLKS = 00) (RTCLKS = 01) (RTCLKS = 10) (RTCLKS = 11)

0000 Off Off Off Off

0001 8 ms 1.024 ms 250 μs 32 ms

0010 32 ms 2.048 ms 1 ms 64 ms

0011 64 ms 4.096 ms 2 ms 128 ms

0100 128 ms 8.192 ms 4 ms 256 ms

0101 256 ms 16.4 ms 8 ms 512 ms

0110 512 ms 32.8 ms 16 ms 1.024 s

0111 1.024 s 65.5 ms 32 ms 2.048 s

1000 1 ms 1 ms 31.25 μs 31.25 ms

1001 2 ms 2 ms 62.5 μs 62.5 ms

1010 4 ms 5 ms 125 μs 156.25 ms

1011 10 ms 10 ms 312.5 μs 312.5 ms

1100 16 ms 20 ms 0.5 ms 0.625 s

1101 0.1 s 50 ms 3.125 ms 1.5625 s

1110 0.5 s 0.1 s 15.625 ms 3.125 s

1111 1s 0.2 s 31.25 ms 6.25 s

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 229
Chapter 13 Real-Time Counter (S08RTCV1)

The RTC modulo register (RTCMOD) allows the compare value to be set to any value from 0x00 to 0xFF.
When the counter is active, the counter increments at the selected rate until the count matches the modulo
value. When these values match, the counter resets to 0x00 and continues counting. The real-time interrupt
flag (RTIF) is set whenever a match occurs. The flag sets on the transition from the modulo value to 0x00.
Writing to RTCMOD resets the prescaler and the RTCCNT counters to 0x00.
The RTC allows for an interrupt to be generated whenever RTIF is set. To enable the real-time interrupt,
set the real-time interrupt enable bit (RTIE) in RTCSC. RTIF is cleared by writing a 1 to RTIF.

13.4.1 RTC Operation Example

This section shows an example of the RTC operation as the counter reaches a matching value from the
modulo register.

Internal
1-kHz

RTC clock
(RTCPS=%0010)

RTCCNT 0x52 0x53 0x54 0x55 0x00 0x01

RTIF

RTCMOD 0x55

Figure 13-6. RTC counter overflow example

In the example of Figure 13-6, the selected clock source is the internal clock source. The prescaler is set
to RTCPS = %0010 or divide-by-4. The modulo value in the RTCMOD register is set to 0x55. When the
counter, RTCCNT, reaches the modulo value of 0x55, the counter overflows to 0x00 and continues
counting. The real-time interrupt flag, RTIF, sets when the counter value changes from 0x55 to 0x00. A
real-time interrupt is generated when RTIF is set, if RTIE = 1.’b00the clock ofthe clock of flip-flop is

13.5 Initialization/Application Information

This section provides example code to give some basic direction to a user on how to initialize and configure
the RTC module. The example software is implemented in C language.
The example below shows how to implement time of day with the RTC using the 1-kHz clock source to
achieve the lowest possible power consumption. Since the 1-kHz clock source is not as accurate as a
crystal, software can be added for any adjustments. For accuracy without adjustments at the expense of
additional power consumption, the external clock (ERCLK) or the internal clock (IRCLK) can be selected
with appropriate prescaler and modulo values.

MC9S08EN32 Series Data Sheet, Rev. 2

230 Freescale Semiconductor
 Chapter 13 Real-Time Counter (S08RTCV1)

/* Initialize the elapsed time counters */

Seconds = 0;
Minutes = 0;
Hours = 0;
Days=0;

/* Configure RTC to interrupt every 1 second from 1-kHz clock source */

RTCMOD.byte = 0x00;
RTCSC.byte = 0x1F;

/**********************************************************************
Function Name : RTC_ISR
Notes : Interrupt service routine for RTC module.
**********************************************************************/
#pragma TRAP_PROC
void RTC_ISR(void)
{
/* Clear the interrupt flag */
RTCSC.byte = RTCSC.byte | 0x80;

/* RTC interrupts every 1 Second */

Seconds++;

/* 60 seconds in a minute */
if (Seconds > 59){
Minutes++;
Seconds = 0;
}

/* 60 minutes in an hour */
if (Minutes > 59){
Hours++;
Minutes = 0;
}

/* 24 hours in a day */
if (Hours > 23){
Days ++;
Hours = 0;
}
}

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 231
Chapter 13 Real-Time Counter (S08RTCV1)

MC9S08EN32 Series Data Sheet, Rev. 2

232 Freescale Semiconductor
Chapter 14
Timer Pulse-Width Modulator (S08TPMV3)
NOTE
This chapter refers to S08TPM version 3, which applies to the 0M74K and
newer mask sets of this device. 3M05C and older mask set devices use
S08TPM version 2. If your device uses mask 3M05C or older, please refer
to Appendix B, “Timer Pulse-Width Modulator (TPMV2) on page 303 for
information pertaining to that module.

14.1 Introduction
The TPM uses one input/output (I/O) pin per channel, TPM1CHn, where n is the channel number (for
example, 0–3). The TPM shares its I/O pins with general-purpose I/O port pins (refer to the Pins and
Connections chapter for more information).
MC9S08EN32 Series MCUs have one TPM module, TPM1. In all available packages, TPM1 is 4-channel,
as shown in the following block diagram.

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 233
Chapter 14 Timer Pulse-Width Modulator (S08TPMV3)

HCS08 CORE PTA7/PIA7/ADP7/IRQ

PTA6/PIA6/ADP6
PTA5/PIA5/ADP5
CPU

PORT A
PTA4/PIA4/ADP4
ACMP1O
ANALOG COMPARATOR PTA3/PIA3/ADP3/ACMP1O
BKGD/MS ACMP1-
(ACMP1) PTA2/PIA2/ADP2/ACMP1-
BDC BKP ACMP1+
PTA1/PIA1/ADP1/ACMP1+
PTA0/PIA0/ADP0/MCLK
HCS08 SYSTEM CONTROL
PTB7/PIB7
RESETS AND INTERRUPTS PTB6/PIB6
RESET
MODES OF OPERATION PTB5/PIB5

PORT B
POWER MANAGEMENT PTB4/PIB4
PTB3/PIB3/ADP11
8 PTB2/PIB2/ADP10
COP LVD PTB1/PIB1/ADP9
IRQ

ADP7-ADP0 PTB0/PIB0/ADP8
INT IRQ
12-CHANNEL,10-BIT
ADP11-ADP8
ANALOG-TO-DIGITAL
VREFH
CONVERTER (ADC)
VREFL
VDDA
VSSA

TPM1CH3–TPM1CH0
PTD7/PID7
USER FLASH 4-CHANNEL TIMER/PWM 4 PTD6/PID6
MODULE (TPM1) TPM1CLK
MC9S08EN32 = 32K PTD5/PID5/TPM1CH3
MC9S08EN16 = 16K

PORT D
PTD4/PID4/TPM1CH2
PTD3/PID3/TPM1CH1
PTD2/PID2/TPM1CH0
PTD1/PID1
PTD0/PID0
PTE7
PTE6
MISO
USER RAM PTE5/MISO
MOSI
PORT E

MC9S08EN32 = 1 KBYTE SERIAL PERIPHERAL PTE4/MOSI

SPSCK
MC9S08EN16 = 512 BYTES INTERFACE MODULE (SPI) PTE3/SPSCK
SS
PTE2/SS
RxD1
PTE1/RxD1
DEBUG MODULE (DBG) SERIAL COMMUNICATIONS TxD1
PTE0/TxD1
INTERFACE (SCI1)

REAL TIME COUNTER (RTC) PTF5

PORT F

PTF4
VDD PTF3
VDD VOLTAGE PTF2/TPM1CLK
VSS REGULATOR PTF1
VSS PTF0

MULTI-PURPOSE
CLOCK GENERATOR
PORT G

(MCG)
XTAL
PTG1/XTAL
OSCILLATOR (XOSC) EXTAL
PTG0/EXTAL
- VREFH/VREFL internally connected to VDDA/VSSA
- VDD and VSS pins are each internally connected to two pads in 32-pin package - Pin not connected in 32-pin package

Figure 14-1. MC9S08EN32 Block Diagram

MC9S08EN32 Series Data Sheet, Rev. 2

234 Freescale Semiconductor
 Chapter 14 Timer/PWM Module (S08TPMV3)

14.1.1 Features
The TPM includes these distinctive features:
• One to eight channels:
— Each channel may be input capture, output compare, or edge-aligned PWM
— Rising-Edge, falling-edge, or any-edge input capture trigger
— Set, clear, or toggle output compare action
— Selectable polarity on PWM outputs
• Module may be configured for buffered, center-aligned pulse-width-modulation (CPWM) on all
channels
• Timer clock source selectable as prescaled bus clock, fixed system clock, or an external clock pin
— Prescale taps for divide-by 1, 2, 4, 8, 16, 32, 64, or 128
— Fixed system clock source are synchronized to the bus clock by an on-chip synchronization
circuit
— External clock pin may be shared with any timer channel pin or a separated input pin
• 16-bit free-running or modulo up/down count operation
• Timer system enable
• One interrupt per channel plus terminal count interrupt

14.1.2 Modes of Operation

In general, TPM channels may be independently configured to operate in input capture, output compare,
or edge-aligned PWM modes. A control bit allows the whole TPM (all channels) to switch to
center-aligned PWM mode. When center-aligned PWM mode is selected, input capture, output compare,
and edge-aligned PWM functions are not available on any channels of this TPM module.
When the microcontroller is in active BDM background or BDM foreground mode, the TPM temporarily
suspends all counting until the microcontroller returns to normal user operating mode. During stop mode,
all system clocks, including the main oscillator, are stopped; therefore, the TPM is effectively disabled
until clocks resume. During wait mode, the TPM continues to operate normally. Provided the TPM does
not need to produce a real time reference or provide the interrupt source(s) needed to wake the MCU from
wait mode, the user can save power by disabling TPM functions before entering wait mode.
• Input capture mode
When a selected edge event occurs on the associated MCU pin, the current value of the 16-bit timer
counter is captured into the channel value register and an interrupt flag bit is set. Rising edges,
falling edges, any edge, or no edge (disable channel) may be selected as the active edge which
triggers the input capture.
• Output compare mode
When the value in the timer counter register matches the channel value register, an interrupt flag
bit is set, and a selected output action is forced on the associated MCU pin. The output compare
action may be selected to force the pin to zero, force the pin to one, toggle the pin, or ignore the
pin (used for software timing functions).

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 235
Chapter 14 Timer/PWM Module (S08TPMV3)

• Edge-aligned PWM mode

The value of a 16-bit modulo register plus 1 sets the period of the PWM output signal. The channel
value register sets the duty cycle of the PWM output signal. The user may also choose the polarity
of the PWM output signal. Interrupts are available at the end of the period and at the duty-cycle
transition point. This type of PWM signal is called edge-aligned because the leading edges of all
PWM signals are aligned with the beginning of the period, which is the same for all channels within
a TPM.
• Center-aligned PWM mode
Twice the value of a 16-bit modulo register sets the period of the PWM output, and the
channel-value register sets the half-duty-cycle duration. The timer counter counts up until it
reaches the modulo value and then counts down until it reaches zero. As the count matches the
channel value register while counting down, the PWM output becomes active. When the count
matches the channel value register while counting up, the PWM output becomes inactive. This type
of PWM signal is called center-aligned because the centers of the active duty cycle periods for all
channels are aligned with a count value of zero. This type of PWM is required for types of motors
used in small appliances.
This is a high-level description only. Detailed descriptions of operating modes are in later sections.

14.1.3 Block Diagram

The TPM uses one input/output (I/O) pin per channel, TPM1CHn (timer channel n) where n is the channel
number (1-8). The TPM shares its I/O pins with general purpose I/O port pins (refer to I/O pin descriptions
in full-chip specification for the specific chip implementation).
Figure 14-2 shows the TPM structure. The central component of the TPM is the 16-bit counter that can
operate as a free-running counter or a modulo up/down counter. The TPM counter (when operating in
normal up-counting mode) provides the timing reference for the input capture, output compare, and
edge-aligned PWM functions. The timer counter modulo registers, TPM1MODH:TPM1MODL, control
the modulo value of the counter (the values 0x0000 or 0xFFFF effectively make the counter free running).
Software can read the counter value at any time without affecting the counting sequence. Any write to
either half of the TPM1CNT counter resets the counter, regardless of the data value written.

MC9S08EN32 Series Data Sheet, Rev. 2

236 Freescale Semiconductor
 Chapter 14 Timer/PWM Module (S08TPMV3)

BUS CLOCK CLOCK SOURCE

PRESCALE AND SELECT
SELECT
1, 2, 4, 8, 16, 32, 64,
FIXED SYSTEM CLOCK OFF, BUS, FIXED
SYNC or 128
EXTERNAL CLOCK SYSTEM CLOCK, EXT

CLKSB:CLKSA PS2:PS1:PS0
CPWMS

16-BIT COUNTER TOF INTER-

COUNTER RESET RUPT
TOIE LOGIC
16-BIT COMPARATOR

TPM1MODH:TPM1MODL

CHANNEL 0 ELS0B ELS0A PORT

LOGIC TPM1CH0
16-BIT COMPARATOR
TPM1C0VH:TPM1C0VL CH0F
INTER-
16-BIT LATCH RUPT
LOGIC
MS0B MS0A CH0IE

CHANNEL 1 ELS1B ELS1A PORT TPM1CH1

INTERNAL BUS

LOGIC
16-BIT COMPARATOR
TPM1C1VH:TPM1C1VL CH1F
INTER-
16-BIT LATCH RUPT
LOGIC
CH1IE
MS1B MS1A

Up to 8 channels

CHANNEL 7 ELS7B ELS7A PORT

TPM1CH7
LOGIC
16-BIT COMPARATOR
TPM1C7VH:TPM1C7VL CH7F
INTER-
16-BIT LATCH RUPT
LOGIC
MS7B MS7A CH7IE

Figure 14-2. TPM Block Diagram

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 237
Chapter 14 Timer/PWM Module (S08TPMV3)

The TPM channels are programmable independently as input capture, output compare, or edge-aligned
PWM channels. Alternately, the TPM can be configured to produce CPWM outputs on all channels. When
the TPM is configured for CPWMs, the counter operates as an up/down counter; input capture, output
compare, and EPWM functions are not practical.
If a channel is configured as input capture, an internal pullup device may be enabled for that channel. The
details of how a module interacts with pin controls depends upon the chip implementation because the I/O
pins and associated general purpose I/O controls are not part of the module. Refer to the discussion of the
I/O port logic in a full-chip specification.
Because center-aligned PWMs are usually used to drive 3-phase AC-induction motors and brushless DC
motors, they are typically used in sets of three or six channels.

14.2 Signal Description

Table 14-1 shows the user-accessible signals for the TPM. The number of channels may be varied from
one to eight. When an external clock is included, it can be shared with the same pin as any TPM channel;
however, it could be connected to a separate input pin. Refer to the I/O pin descriptions in full-chip
specification for the specific chip implementation.

Table 14-1. Signal Properties

Name Function

EXTCLK1 External clock source which may be selected to drive the TPM counter.
2
TPM1CHn I/O pin associated with TPM channel n
1
When preset, this signal can share any channel pin; however depending upon full-chip
implementation, this signal could be connected to a separate external pin.
2 n=channel number (1 to 8)

Refer to documentation for the full-chip for details about reset states, port connections, and whether there
is any pullup device on these pins.
TPM channel pins can be associated with general purpose I/O pins and have passive pullup devices which
can be enabled with a control bit when the TPM or general purpose I/O controls have configured the
associated pin as an input. When no TPM function is enabled to use a corresponding pin, the pin reverts
to being controlled by general purpose I/O controls, including the port-data and data-direction registers.
Immediately after reset, no TPM functions are enabled, so all associated pins revert to general purpose I/O
control.

14.2.1 Detailed Signal Descriptions

This section describes each user-accessible pin signal in detail. Although Table 14-1 grouped all channel
pins together, any TPM pin can be shared with the external clock source signal. Since I/O pin logic is not
part of the TPM, refer to full-chip documentation for a specific derivative for more details about the
interaction of TPM pin functions and general purpose I/O controls including port data, data direction, and
pullup controls.

MC9S08EN32 Series Data Sheet, Rev. 2

238 Freescale Semiconductor
 Chapter 14 Timer/PWM Module (S08TPMV3)

14.2.1.1 EXTCLK — External Clock Source

Control bits in the timer status and control register allow the user to select nothing (timer disable), the
bus-rate clock (the normal default source), a crystal-related clock, or an external clock as the clock which
drives the TPM prescaler and subsequently the 16-bit TPM counter. The external clock source is
synchronized in the TPM. The bus clock clocks the synchronizer; the frequency of the external source must
be no more than one-fourth the frequency of the bus-rate clock, to meet Nyquist criteria and allowing for
jitter.
The external clock signal shares the same pin as a channel I/O pin, so the channel pin will not be usable
for channel I/O function when selected as the external clock source. It is the user’s responsibility to avoid
such settings. If this pin is used as an external clock source (CLKSB:CLKSA = 1:1), the channel can still
be used in output compare mode as a software timer (ELSnB:ELSnA = 0:0).

14.2.1.2 TPM1CHn — TPM Channel n I/O Pin(s)

Each TPM channel is associated with an I/O pin on the MCU. The function of this pin depends on the
channel configuration. The TPM pins share with general purpose I/O pins, where each pin has a port data
register bit, and a data direction control bit, and the port has optional passive pullups which may be enabled
whenever a port pin is acting as an input.
The TPM channel does not control the I/O pin when (ELSnB:ELSnA = 0:0) or when (CLKSB:CLKSA =
0:0) so it normally reverts to general purpose I/O control. When CPWMS = 1 (and ELSnB:ELSnA not =
0:0), all channels within the TPM are configured for center-aligned PWM and the TPM1CHn pins are all
controlled by the TPM system. When CPWMS=0, the MSnB:MSnA control bits determine whether the
channel is configured for input capture, output compare, or edge-aligned PWM.
When a channel is configured for input capture (CPWMS=0, MSnB:MSnA = 0:0 and ELSnB:ELSnA not
= 0:0), the TPM1CHn pin is forced to act as an edge-sensitive input to the TPM. ELSnB:ELSnA control
bits determine what polarity edge or edges will trigger input-capture events. A synchronizer based on the
bus clock is used to synchronize input edges to the bus clock. This implies the minimum pulse width—that
can be reliably detected—on an input capture pin is four bus clock periods (with ideal clock pulses as near
as two bus clocks can be detected). TPM uses this pin as an input capture input to override the port data
and data direction controls for the same pin.
When a channel is configured for output compare (CPWMS=0, MSnB:MSnA = 0:1 and ELSnB:ELSnA
not = 0:0), the associated data direction control is overridden, the TPM1CHn pin is considered an output
controlled by the TPM, and the ELSnB:ELSnA control bits determine how the pin is controlled. The
remaining three combinations of ELSnB:ELSnA determine whether the TPM1CHn pin is toggled, cleared,
or set each time the 16-bit channel value register matches the timer counter.
When the output compare toggle mode is initially selected, the previous value on the pin is driven out until
the next output compare event—then the pin is toggled.

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When a channel is configured for edge-aligned PWM (CPWMS=0, MSnB=1 and ELSnB:ELSnA not =
0:0), the data direction is overridden, the TPM1CHn pin is forced to be an output controlled by the TPM,
and ELSnA controls the polarity of the PWM output signal on the pin. When ELSnB:ELSnA=1:0, the
TPM1CHn pin is forced high at the start of each new period (TPM1CNT=0x0000), and the pin is forced
low when the channel value register matches the timer counter. When ELSnA=1, the TPM1CHn pin is
forced low at the start of each new period (TPM1CNT=0x0000), and the pin is forced high when the
channel value register matches the timer counter.
TPM1MODH:TPM1MODL = 0x0008
TPM1MODH:TPM1MODL = 0x0005

TPM1CNTH:TPM1CNTL ... 0 1 2 3 4 5 6 7 8 0 1 2 ...

TPM1CHn
CHnF BIT

TOF BIT

Figure 14-3. High-True Pulse of an Edge-Aligned PWM

TPM1MODH:TPM1MODL = 0x0008
TPM1MODH:TPM1MODL = 0x0005

TPM1CNTH:TPM1CNTL ... 0 1 2 3 4 5 6 7 8 0 1 2 ...

TPM1CHn

CHnF BIT

TOF BIT

Figure 14-4. Low-True Pulse of an Edge-Aligned PWM

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When the TPM is configured for center-aligned PWM (and ELSnB:ELSnA not = 0:0), the data direction
for all channels in this TPM are overridden, the TPM1CHn pins are forced to be outputs controlled by the
TPM, and the ELSnA bits control the polarity of each TPM1CHn output. If ELSnB:ELSnA=1:0, the
corresponding TPM1CHn pin is cleared when the timer counter is counting up, and the channel value
register matches the timer counter; the TPM1CHn pin is set when the timer counter is counting down, and
the channel value register matches the timer counter. If ELSnA=1, the corresponding TPM1CHn pin is set
when the timer counter is counting up and the channel value register matches the timer counter; the
TPM1CHn pin is cleared when the timer counter is counting down and the channel value register matches
the timer counter.
TPM1MODH:TPM1MODL = 0x0008
TPM1MODH:TPM1MODL = 0x0005

TPM1CNTH:TPM1CNTL ... 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 ...

TPM1CHn
CHnF BIT

TOF BIT

Figure 14-5. High-True Pulse of a Center-Aligned PWM

TPM1MODH:TPM1MODL = 0x0008
TPM1MODH:TPM1MODL = 0x0005

TPM1CNTH:TPM1CNTL ... 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 ...

TPM1CHn

CHnF BIT

TOF BIT

Figure 14-6. Low-True Pulse of a Center-Aligned PWM

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Chapter 14 Timer/PWM Module (S08TPMV3)

14.3 Register Definition

This section consists of register descriptions in address order.

14.3.1 TPM Status and Control Register (TPM1SC)

TPM1SC contains the overflow status flag and control bits used to configure the interrupt enable, TPM
configuration, clock source, and prescale factor. These controls relate to all channels within this timer
module.

7 6 5 4 3 2 1 0

R TOF
TOIE CPWMS CLKSB CLKSA PS2 PS1 PS0
W 0
Reset 0 0 0 0 0 0 0 0

Figure 14-7. TPM Status and Control Register (TPM1SC)

Table 14-2. TPM1SC Field Descriptions

Field Description

7 Timer overflow flag. This read/write flag is set when the TPM counter resets to 0x0000 after reaching the modulo
TOF value programmed in the TPM counter modulo registers. Clear TOF by reading the TPM status and control
register when TOF is set and then writing a logic 0 to TOF. If another TPM overflow occurs before the clearing
sequence is complete, the sequence is reset so TOF would remain set after the clear sequence was completed
for the earlier TOF. This is done so a TOF interrupt request cannot be lost during the clearing sequence for a
previous TOF. Reset clears TOF. Writing a logic 1 to TOF has no effect.
0 TPM counter has not reached modulo value or overflow
1 TPM counter has overflowed
6 Timer overflow interrupt enable. This read/write bit enables TPM overflow interrupts. If TOIE is set, an interrupt is
TOIE generated when TOF equals one. Reset clears TOIE.
0 TOF interrupts inhibited (use for software polling)
1 TOF interrupts enabled
5 Center-aligned PWM select. When present, this read/write bit selects CPWM operating mode. By default, the
CPWMS TPM operates in up-counting mode for input capture, output compare, and edge-aligned PWM functions. Setting
CPWMS reconfigures the TPM to operate in up/down counting mode for CPWM functions. Reset clears CPWMS.
0 All channels operate as input capture, output compare, or edge-aligned PWM mode as selected by the
MSnB:MSnA control bits in each channel’s status and control register.
1 All channels operate in center-aligned PWM mode.
4–3 Clock source selects. As shown in Table 14-3, this 2-bit field is used to disable the TPM system or select one of
CLKS[B:A] three clock sources to drive the counter prescaler. The fixed system clock source is only meaningful in systems
with a PLL-based system clock. When there is no PLL, the fixed-system clock source is the same as the bus rate
clock. The external source is synchronized to the bus clock by TPM module, and the fixed system clock source
(when a PLL is present) is synchronized to the bus clock by an on-chip synchronization circuit. When a PLL is
present but not enabled, the fixed-system clock source is the same as the bus-rate clock.
2–0 Prescale factor select. This 3-bit field selects one of 8 division factors for the TPM clock input as shown in
PS[2:0] Table 14-4. This prescaler is located after any clock source synchronization or clock source selection so it affects
the clock source selected to drive the TPM system. The new prescale factor will affect the clock source on the
next system clock cycle after the new value is updated into the register bits.

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Table 14-3. TPM-Clock-Source Selection

CLKSB:CLKSA TPM Clock Source to Prescaler Input

00 No clock selected (TPM counter disable)

01 Bus rate clock
10 Fixed system clock
11 External source

Table 14-4. Prescale Factor Selection

PS2:PS1:PS0 TPM Clock Source Divided-by

000 1
001 2
010 4
011 8
100 16
101 32
110 64
111 128

14.3.2 TPM-Counter Registers (TPM1CNTH:TPM1CNTL)

The two read-only TPM counter registers contain the high and low bytes of the value in the TPM counter.
Reading either byte (TPM1CNTH or TPM1CNTL) latches the contents of both bytes into a buffer where
they remain latched until the other half is read. This allows coherent 16-bit reads in either big-endian or
little-endian order which makes this more friendly to various compiler implementations. The coherency
mechanism is automatically restarted by an MCU reset or any write to the timer status/control register
(TPM1SC).
Reset clears the TPM counter registers. Writing any value to TPM1CNTH or TPM1CNTL also clears the
TPM counter (TPM1CNTH:TPM1CNTL) and resets the coherency mechanism, regardless of the data
involved in the write.

7 6 5 4 3 2 1 0

R Bit 15 14 13 12 11 10 9 Bit 8
W Any write to TPM1CNTH clears the 16-bit counter
Reset 0 0 0 0 0 0 0 0

Figure 14-8. TPM Counter Register High (TPM1CNTH)

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7 6 5 4 3 2 1 0

R Bit 7 6 5 4 3 2 1 Bit 0
W Any write to TPM1CNTL clears the 16-bit counter
Reset 0 0 0 0 0 0 0 0

Figure 14-9. TPM Counter Register Low (TPM1CNTL)

When BDM is active, the timer counter is frozen (this is the value that will be read by user); the coherency
mechanism is frozen such that the buffer latches remain in the state they were in when the BDM became
active, even if one or both counter halves are read while BDM is active. This assures that if the user was
in the middle of reading a 16-bit register when BDM became active, it will read the appropriate value from
the other half of the 16-bit value after returning to normal execution.
In BDM mode, writing any value to TPM1SC, TPM1CNTH or TPM1CNTL registers resets the read
coherency mechanism of the TPM1CNTH:L registers, regardless of the data involved in the write.

14.3.3 TPM Counter Modulo Registers (TPM1MODH:TPM1MODL)

The read/write TPM modulo registers contain the modulo value for the TPM counter. After the TPM
counter reaches the modulo value, the TPM counter resumes counting from 0x0000 at the next clock, and
the overflow flag (TOF) becomes set. Writing to TPM1MODH or TPM1MODL inhibits the TOF bit and
overflow interrupts until the other byte is written. Reset sets the TPM counter modulo registers to 0x0000
which results in a free running timer counter (modulo disabled).
Writing to either byte (TPM1MODH or TPM1MODL) latches the value into a buffer and the registers are
updated with the value of their write buffer according to the value of CLKSB:CLKSA bits, so:
• If (CLKSB:CLKSA = 0:0), then the registers are updated when the second byte is written
• If (CLKSB:CLKSA not = 0:0), then the registers are updated after both bytes were written, and the
TPM counter changes from (TPM1MODH:TPM1MODL - 1) to (TPM1MODH:TPM1MODL). If
the TPM counter is a free-running counter, the update is made when the TPM counter changes from
0xFFFE to 0xFFFF
The latching mechanism may be manually reset by writing to the TPM1SC address (whether BDM is
active or not).
When BDM is active, the coherency mechanism is frozen (unless reset by writing to TPM1SC register)
such that the buffer latches remain in the state they were in when the BDM became active, even if one or
both halves of the modulo register are written while BDM is active. Any write to the modulo registers
bypasses the buffer latches and directly writes to the modulo register while BDM is active.

7 6 5 4 3 2 1 0

R
Bit 15 14 13 12 11 10 9 Bit 8
W
Reset 0 0 0 0 0 0 0 0

Figure 14-10. TPM Counter Modulo Register High (TPM1MODH)

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7 6 5 4 3 2 1 0

R
Bit 7 6 5 4 3 2 1 Bit 0
W
Reset 0 0 0 0 0 0 0 0

Reset the TPM counter before writing to the TPM modulo registers to avoid confusion about when the first
counter overflow will occur.

14.3.4 TPM Channel n Status and Control Register (TPM1CnSC)

TPM1CnSC contains the channel-interrupt-status flag and control bits used to configure the interrupt
enable, channel configuration, and pin function.

7 6 5 4 3 2 1 0

R CHnF 0 0
CHnIE MSnB MSnA ELSnB ELSnA
W 0
Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved

Figure 14-12. TPM Channel n Status and Control Register (TPM1CnSC)

Table 14-5. TPM1CnSC Field Descriptions

Field Description

7 Channel n flag. When channel n is an input-capture channel, this read/write bit is set when an active edge occurs
CHnF on the channel n pin. When channel n is an output compare or edge-aligned/center-aligned PWM channel, CHnF
is set when the value in the TPM counter registers matches the value in the TPM channel n value registers. When
channel n is an edge-aligned/center-aligned PWM channel and the duty cycle is set to 0% or 100%, CHnF will
not be set even when the value in the TPM counter registers matches the value in the TPM channel n value
registers.
A corresponding interrupt is requested when CHnF is set and interrupts are enabled (CHnIE = 1). Clear CHnF by
reading TPM1CnSC while CHnF is set and then writing a logic 0 to CHnF. If another interrupt request occurs
before the clearing sequence is complete, the sequence is reset so CHnF remains set after the clear sequence
completed for the earlier CHnF. This is done so a CHnF interrupt request cannot be lost due to clearing a previous
CHnF.
Reset clears the CHnF bit. Writing a logic 1 to CHnF has no effect.
0 No input capture or output compare event occurred on channel n
1 Input capture or output compare event on channel n
6 Channel n interrupt enable. This read/write bit enables interrupts from channel n. Reset clears CHnIE.
CHnIE 0 Channel n interrupt requests disabled (use for software polling)
1 Channel n interrupt requests enabled
5 Mode select B for TPM channel n. When CPWMS=0, MSnB=1 configures TPM channel n for edge-aligned PWM
MSnB mode. Refer to the summary of channel mode and setup controls in Table 14-6.

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Table 14-5. TPM1CnSC Field Descriptions (continued)

Field Description

4 Mode select A for TPM channel n. When CPWMS=0 and MSnB=0, MSnA configures TPM channel n for
MSnA input-capture mode or output compare mode. Refer to Table 14-6 for a summary of channel mode and setup
controls.
Note: If the associated port pin is not stable for at least two bus clock cycles before changing to input capture
mode, it is possible to get an unexpected indication of an edge trigger.
3–2 Edge/level select bits. Depending upon the operating mode for the timer channel as set by CPWMS:MSnB:MSnA
ELSnB and shown in Table 14-6, these bits select the polarity of the input edge that triggers an input capture event, select
ELSnA the level that will be driven in response to an output compare match, or select the polarity of the PWM output.
Setting ELSnB:ELSnA to 0:0 configures the related timer pin as a general purpose I/O pin not related to any timer
functions. This function is typically used to temporarily disable an input capture channel or to make the timer pin
available as a general purpose I/O pin when the associated timer channel is set up as a software timer that does
not require the use of a pin.

Table 14-6. Mode, Edge, and Level Selection

CPWMS MSnB:MSnA ELSnB:ELSnA Mode Configuration

X XX 00 Pin not used for TPM - revert to general

purpose I/O or other peripheral control
0 00 01 Input capture Capture on rising edge
only
10 Capture on falling edge
only
11 Capture on rising or
falling edge
01 01 Output compare Toggle output on
compare
10 Clear output on
compare
11 Set output on compare
1X 10 Edge-aligned High-true pulses (clear
PWM output on compare)
X1 Low-true pulses (set
output on compare)
1 XX 10 Center-aligned High-true pulses (clear
PWM output on compare-up)
X1 Low-true pulses (set
output on compare-up)

14.3.5 TPM Channel Value Registers (TPM1CnVH:TPM1CnVL)

These read/write registers contain the captured TPM counter value of the input capture function or the
output compare value for the output compare or PWM functions. The channel registers are cleared by
reset.

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7 6 5 4 3 2 1 0

R
Bit 15 14 13 12 11 10 9 Bit 8
W
Reset 0 0 0 0 0 0 0 0

Figure 14-13. TPM Channel Value Register High (TPM1CnVH)

7 6 5 4 3 2 1 0

R
Bit 7 6 5 4 3 2 1 Bit 0
W
Reset 0 0 0 0 0 0 0 0

Figure 14-14. TPM Channel Value Register Low (TPM1CnVL)

In input capture mode, reading either byte (TPM1CnVH or TPM1CnVL) latches the contents of both bytes
into a buffer where they remain latched until the other half is read. This latching mechanism also resets
(becomes unlatched) when the TPM1CnSC register is written (whether BDM mode is active or not). Any
write to the channel registers will be ignored during the input capture mode.
When BDM is active, the coherency mechanism is frozen (unless reset by writing to TPM1CnSC register)
such that the buffer latches remain in the state they were in when the BDM became active, even if one or
both halves of the channel register are read while BDM is active. This assures that if the user was in the
middle of reading a 16-bit register when BDM became active, it will read the appropriate value from the
other half of the 16-bit value after returning to normal execution. The value read from the TPM1CnVH
and TPM1CnVL registers in BDM mode is the value of these registers and not the value of their read
buffer.
In output compare or PWM modes, writing to either byte (TPM1CnVH or TPM1CnVL) latches the value
into a buffer. After both bytes are written, they are transferred as a coherent 16-bit value into the
timer-channel registers according to the value of CLKSB:CLKSA bits and the selected mode, so:
• If (CLKSB:CLKSA = 0:0), then the registers are updated when the second byte is written.
• If (CLKSB:CLKSA not = 0:0 and in output compare mode) then the registers are updated after the
second byte is written and on the next change of the TPM counter (end of the prescaler counting).
• If (CLKSB:CLKSA not = 0:0 and in EPWM or CPWM modes), then the registers are updated after
the both bytes were written, and the TPM counter changes from (TPM1MODH:TPM1MODL - 1)
to (TPM1MODH:TPM1MODL). If the TPM counter is a free-running counter then the update is
made when the TPM counter changes from 0xFFFE to 0xFFFF.
The latching mechanism may be manually reset by writing to the TPM1CnSC register (whether BDM
mode is active or not). This latching mechanism allows coherent 16-bit writes in either big-endian or
little-endian order which is friendly to various compiler implementations.
When BDM is active, the coherency mechanism is frozen such that the buffer latches remain in the state
they were in when the BDM became active even if one or both halves of the channel register are written
while BDM is active. Any write to the channel registers bypasses the buffer latches and directly write to
the channel register while BDM is active. The values written to the channel register while BDM is active

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are used for PWM & output compare operation once normal execution resumes. Writes to the channel
registers while BDM is active do not interfere with partial completion of a coherency sequence. After the
coherency mechanism has been fully exercised, the channel registers are updated using the buffered values
written (while BDM was not active) by the user.

14.4 Functional Description

All TPM functions are associated with a central 16-bit counter which allows flexible selection of the clock
source and prescale factor. There is also a 16-bit modulo register associated with the main counter.
The CPWMS control bit chooses between center-aligned PWM operation for all channels in the TPM
(CPWMS=1) or general purpose timing functions (CPWMS=0) where each channel can independently be
configured to operate in input capture, output compare, or edge-aligned PWM mode. The CPWMS control
bit is located in the main TPM status and control register because it affects all channels within the TPM
and influences the way the main counter operates. (In CPWM mode, the counter changes to an up/down
mode rather than the up-counting mode used for general purpose timer functions.)
The following sections describe the main counter and each of the timer operating modes (input capture,
output compare, edge-aligned PWM, and center-aligned PWM). Because details of pin operation and
interrupt activity depend upon the operating mode, these topics will be covered in the associated mode
explanation sections.

14.4.1 Counter
All timer functions are based on the main 16-bit counter (TPM1CNTH:TPM1CNTL). This section
discusses selection of the clock source, end-of-count overflow, up-counting vs. up/down counting, and
manual counter reset.

14.4.1.1 Counter Clock Source

The 2-bit field, CLKSB:CLKSA, in the timer status and control register (TPM1SC) selects one of three
possible clock sources or OFF (which effectively disables the TPM). See Table 14-3. After any MCU reset,
CLKSB:CLKSA=0:0 so no clock source is selected, and the TPM is in a very low power state. These
control bits may be read or written at any time and disabling the timer (writing 00 to the CLKSB:CLKSA
field) does not affect the values in the counter or other timer registers.

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Table 14-7. TPM Clock Source Selection

CLKSB:CLKSA TPM Clock Source to Prescaler Input

00 No clock selected (TPM counter disabled)

01 Bus rate clock
10 Fixed system clock
11 External source

The bus rate clock is the main system bus clock for the MCU. This clock source requires no
synchronization because it is the clock that is used for all internal MCU activities including operation of
the CPU and buses.
In MCUs that have no PLL or the PLL is not engaged, the fixed system clock source is the same as the
bus-rate-clock source, and it does not go through a synchronizer. When a PLL is present and engaged, a
synchronizer is required between the crystal divided-by two clock source and the timer counter so counter
transitions will be properly aligned to bus-clock transitions. A synchronizer will be used at chip level to
synchronize the crystal-related source clock to the bus clock.
The external clock source may be connected to any TPM channel pin. This clock source always has to pass
through a synchronizer to assure that counter transitions are properly aligned to bus clock transitions. The
bus-rate clock drives the synchronizer; therefore, to meet Nyquist criteria even with jitter, the frequency of
the external clock source must not be faster than the bus rate divided-by four. With ideal clocks the external
clock can be as fast as bus clock divided by four.
When the external clock source shares the TPM channel pin, this pin should not be used for other channel
timing functions. For example, it would be ambiguous to configure channel 0 for input capture when the
TPM channel 0 pin was also being used as the timer external clock source. (It is the user’s responsibility
to avoid such settings.) The TPM channel could still be used in output compare mode for software timing
functions (pin controls set not to affect the TPM channel pin).

14.4.1.2 Counter Overflow and Modulo Reset

An interrupt flag and enable are associated with the 16-bit main counter. The flag (TOF) is a
software-accessible indication that the timer counter has overflowed. The enable signal selects between
software polling (TOIE=0) where no hardware interrupt is generated, or interrupt-driven operation
(TOIE=1) where a static hardware interrupt is generated whenever the TOF flag is equal to one.
The conditions causing TOF to become set depend on whether the TPM is configured for center-aligned
PWM (CPWMS=1). In the simplest mode, there is no modulus limit and the TPM is not in CPWMS=1
mode. In this case, the 16-bit timer counter counts from 0x0000 through 0xFFFF and overflows to 0x0000
on the next counting clock. TOF becomes set at the transition from 0xFFFF to 0x0000. When a modulus
limit is set, TOF becomes set at the transition from the value set in the modulus register to 0x0000. When
the TPM is in center-aligned PWM mode (CPWMS=1), the TOF flag gets set as the counter changes
direction at the end of the count value set in the modulus register (that is, at the transition from the value
set in the modulus register to the next lower count value). This corresponds to the end of a PWM period
(the 0x0000 count value corresponds to the center of a period).

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14.4.1.3 Counting Modes

The main timer counter has two counting modes. When center-aligned PWM is selected (CPWMS=1), the
counter operates in up/down counting mode. Otherwise, the counter operates as a simple up counter. As
an up counter, the timer counter counts from 0x0000 through its terminal count and then continues with
0x0000. The terminal count is 0xFFFF or a modulus value in TPM1MODH:TPM1MODL.
When center-aligned PWM operation is specified, the counter counts up from 0x0000 through its terminal
count and then down to 0x0000 where it changes back to up counting. Both 0x0000 and the terminal count
value are normal length counts (one timer clock period long). In this mode, the timer overflow flag (TOF)
becomes set at the end of the terminal-count period (as the count changes to the next lower count value).

14.4.1.4 Manual Counter Reset

The main timer counter can be manually reset at any time by writing any value to either half of
TPM1CNTH or TPM1CNTL. Resetting the counter in this manner also resets the coherency mechanism
in case only half of the counter was read before resetting the count.

14.4.2 Channel Mode Selection

Provided CPWMS=0, the MSnB and MSnA control bits in the channel n status and control registers
determine the basic mode of operation for the corresponding channel. Choices include input capture,
output compare, and edge-aligned PWM.

14.4.2.1 Input Capture Mode

With the input-capture function, the TPM can capture the time at which an external event occurs. When an
active edge occurs on the pin of an input-capture channel, the TPM latches the contents of the TPM counter
into the channel-value registers (TPM1CnVH:TPM1CnVL). Rising edges, falling edges, or any edge may
be chosen as the active edge that triggers an input capture.
In input capture mode, the TPM1CnVH and TPM1CnVL registers are read only.
When either half of the 16-bit capture register is read, the other half is latched into a buffer to support
coherent 16-bit accesses in big-endian or little-endian order. The coherency sequence can be manually
reset by writing to the channel status/control register (TPM1CnSC).
An input capture event sets a flag bit (CHnF) which may optionally generate a CPU interrupt request.
While in BDM, the input capture function works as configured by the user. When an external event occurs,
the TPM latches the contents of the TPM counter (which is frozen because of the BDM mode) into the
channel value registers and sets the flag bit.

14.4.2.2 Output Compare Mode

With the output-compare function, the TPM can generate timed pulses with programmable position,
polarity, duration, and frequency. When the counter reaches the value in the channel-value registers of an
output-compare channel, the TPM can set, clear, or toggle the channel pin.

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In output compare mode, values are transferred to the corresponding timer channel registers only after both
8-bit halves of a 16-bit register have been written and according to the value of CLKSB:CLKSA bits, so:
• If (CLKSB:CLKSA = 0:0), the registers are updated when the second byte is written
• If (CLKSB:CLKSA not = 0:0), the registers are updated at the next change of the TPM counter
(end of the prescaler counting) after the second byte is written.
The coherency sequence can be manually reset by writing to the channel status/control register
(TPM1CnSC).
An output compare event sets a flag bit (CHnF) which may optionally generate a CPU-interrupt request.

14.4.2.3 Edge-Aligned PWM Mode

This type of PWM output uses the normal up-counting mode of the timer counter (CPWMS=0) and can
be used when other channels in the same TPM are configured for input capture or output compare
functions. The period of this PWM signal is determined by the value of the modulus register
(TPM1MODH:TPM1MODL) plus 1. The duty cycle is determined by the setting in the timer channel
register (TPM1CnVH:TPM1CnVL). The polarity of this PWM signal is determined by the setting in the
ELSnA control bit. 0% and 100% duty cycle cases are possible.
The output compare value in the TPM channel registers determines the pulse width (duty cycle) of the
PWM signal (Figure 14-15). The time between the modulus overflow and the output compare is the pulse
width. If ELSnA=0, the counter overflow forces the PWM signal high, and the output compare forces the
PWM signal low. If ELSnA=1, the counter overflow forces the PWM signal low, and the output compare
forces the PWM signal high.

OVERFLOW OVERFLOW OVERFLOW

PERIOD
PULSE
WIDTH

TPM1CHn

OUTPUT OUTPUT OUTPUT

COMPARE COMPARE COMPARE

Figure 14-15. PWM Period and Pulse Width (ELSnA=0)

When the channel value register is set to 0x0000, the duty cycle is 0%. 100% duty cycle can be achieved
by setting the timer-channel register (TPM1CnVH:TPM1CnVL) to a value greater than the modulus
setting. This implies that the modulus setting must be less than 0xFFFF in order to get 100% duty cycle.
Because the TPM may be used in an 8-bit MCU, the settings in the timer channel registers are buffered to
ensure coherent 16-bit updates and to avoid unexpected PWM pulse widths. Writes to any of the registers
TPM1CnVH and TPM1CnVL, actually write to buffer registers. In edge-aligned PWM mode, values are
transferred to the corresponding timer-channel registers according to the value of CLKSB:CLKSA bits, so:
• If (CLKSB:CLKSA = 0:0), the registers are updated when the second byte is written
• If (CLKSB:CLKSA not = 0:0), the registers are updated after the both bytes were written, and the
TPM counter changes from (TPM1MODH:TPM1MODL - 1) to (TPM1MODH:TPM1MODL). If

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the TPM counter is a free-running counter then the update is made when the TPM counter changes
from 0xFFFE to 0xFFFF.

14.4.2.4 Center-Aligned PWM Mode

This type of PWM output uses the up/down counting mode of the timer counter (CPWMS=1). The output
compare value in TPM1CnVH:TPM1CnVL determines the pulse width (duty cycle) of the PWM signal
while the period is determined by the value in TPM1MODH:TPM1MODL. TPM1MODH:TPM1MODL
should be kept in the range of 0x0001 to 0x7FFF because values outside this range can produce ambiguous
results. ELSnA will determine the polarity of the CPWM output.
pulse width = 2 x (TPM1CnVH:TPM1CnVL)
period = 2 x (TPM1MODH:TPM1MODL); TPM1MODH:TPM1MODL=0x0001-0x7FFF
If the channel-value register TPM1CnVH:TPM1CnVL is zero or negative (bit 15 set), the duty cycle will
be 0%. If TPM1CnVH:TPM1CnVL is a positive value (bit 15 clear) and is greater than the (non-zero)
modulus setting, the duty cycle will be 100% because the duty cycle compare will never occur. This
implies the usable range of periods set by the modulus register is 0x0001 through 0x7FFE (0x7FFF if you
do not need to generate 100% duty cycle). This is not a significant limitation. The resulting period would
be much longer than required for normal applications.
TPM1MODH:TPM1MODL=0x0000 is a special case that should not be used with center-aligned PWM
mode. When CPWMS=0, this case corresponds to the counter running free from 0x0000 through 0xFFFF,
but when CPWMS=1 the counter needs a valid match to the modulus register somewhere other than at
0x0000 in order to change directions from up-counting to down-counting.
The output compare value in the TPM channel registers (times 2) determines the pulse width (duty cycle)
of the CPWM signal (Figure 14-16). If ELSnA=0, a compare occurred while counting up forces the
CPWM output signal low and a compare occurred while counting down forces the output high. The
counter counts up until it reaches the modulo setting in TPM1MODH:TPM1MODL, then counts down
until it reaches zero. This sets the period equal to two times TPM1MODH:TPM1MODL.

OUTPUT COUNT= 0 OUTPUT

COUNT= COMPARE COMPARE COUNT=
TPM1MODH:TPM1MODL (COUNT DOWN) (COUNT UP) TPM1MODH:TPM1MODL

TPM1CHn
PULSE WIDTH
2 x TPM1CnVH:TPM1CnVL
PERIOD
2 x TPM1MODH:TPM1MODL
Figure 14-16. CPWM Period and Pulse Width (ELSnA=0)

Center-aligned PWM outputs typically produce less noise than edge-aligned PWMs because fewer I/O pin
transitions are lined up at the same system clock edge. This type of PWM is also required for some types
of motor drives.

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Input capture, output compare, and edge-aligned PWM functions do not make sense when the counter is
operating in up/down counting mode so this implies that all active channels within a TPM must be used in
CPWM mode when CPWMS=1.
The TPM may be used in an 8-bit MCU. The settings in the timer channel registers are buffered to ensure
coherent 16-bit updates and to avoid unexpected PWM pulse widths. Writes to any of the registers
TPM1MODH, TPM1MODL, TPM1CnVH, and TPM1CnVL, actually write to buffer registers.
In center-aligned PWM mode, the TPM1CnVH:L registers are updated with the value of their write buffer
according to the value of CLKSB:CLKSA bits, so:
• If (CLKSB:CLKSA = 0:0), the registers are updated when the second byte is written
• If (CLKSB:CLKSA not = 0:0), the registers are updated after the both bytes were written, and the
TPM counter changes from (TPM1MODH:TPM1MODL - 1) to (TPM1MODH:TPM1MODL). If
the TPM counter is a free-running counter, the update is made when the TPM counter changes from
0xFFFE to 0xFFFF.
When TPM1CNTH:TPM1CNTL=TPM1MODH:TPM1MODL, the TPM can optionally generate a TOF
interrupt (at the end of this count).
Writing to TPM1SC cancels any values written to TPM1MODH and/or TPM1MODL and resets the
coherency mechanism for the modulo registers. Writing to TPM1CnSC cancels any values written to the
channel value registers and resets the coherency mechanism for TPM1CnVH:TPM1CnVL.

14.5 Reset Overview

14.5.1 General
The TPM is reset whenever any MCU reset occurs.

14.5.2 Description of Reset Operation

Reset clears the TPM1SC register which disables clocks to the TPM and disables timer overflow interrupts
(TOIE=0). CPWMS, MSnB, MSnA, ELSnB, and ELSnA are all cleared which configures all TPM
channels for input-capture operation with the associated pins disconnected from I/O pin logic (so all MCU
pins related to the TPM revert to general purpose I/O pins).

14.6 Interrupts

14.6.1 General
The TPM generates an optional interrupt for the main counter overflow and an interrupt for each channel.
The meaning of channel interrupts depends on each channel’s mode of operation. If the channel is
configured for input capture, the interrupt flag is set each time the selected input capture edge is
recognized. If the channel is configured for output compare or PWM modes, the interrupt flag is set each
time the main timer counter matches the value in the 16-bit channel value register.

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All TPM interrupts are listed in Table 14-8 which shows the interrupt name, the name of any local enable
that can block the interrupt request from leaving the TPM and getting recognized by the separate interrupt
processing logic.

Table 14-8. Interrupt Summary

Local
Interrupt Source Description
Enable

TOF TOIE Counter overflow Set each time the timer counter reaches its terminal
count (at transition to next count value which is
usually 0x0000)
CHnF CHnIE Channel event An input capture or output compare event took
place on channel n

The TPM module will provide a high-true interrupt signal. Vectors and priorities are determined at chip
integration time in the interrupt module so refer to the user’s guide for the interrupt module or to the chip’s
complete documentation for details.

14.6.2 Description of Interrupt Operation

For each interrupt source in the TPM, a flag bit is set upon recognition of the interrupt condition such as
timer overflow, channel-input capture, or output-compare events. This flag may be read (polled) by
software to determine that the action has occurred, or an associated enable bit (TOIE or CHnIE) can be set
to enable hardware interrupt generation. While the interrupt enable bit is set, a static interrupt will generate
whenever the associated interrupt flag equals one. The user’s software must perform a sequence of steps
to clear the interrupt flag before returning from the interrupt-service routine.
TPM interrupt flags are cleared by a two-step process including a read of the flag bit while it is set (1)
followed by a write of zero (0) to the bit. If a new event is detected between these two steps, the sequence
is reset and the interrupt flag remains set after the second step to avoid the possibility of missing the new
event.

14.6.2.1 Timer Overflow Interrupt (TOF) Description

The meaning and details of operation for TOF interrupts varies slightly depending upon the mode of
operation of the TPM system (general purpose timing functions versus center-aligned PWM operation).
The flag is cleared by the two step sequence described above.

14.6.2.1.1 Normal Case

Normally TOF is set when the timer counter changes from 0xFFFF to 0x0000. When the TPM is not
configured for center-aligned PWM (CPWMS=0), TOF gets set when the timer counter changes from the
terminal count (the value in the modulo register) to 0x0000. This case corresponds to the normal meaning
of counter overflow.

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14.6.2.1.2 Center-Aligned PWM Case

When CPWMS=1, TOF gets set when the timer counter changes direction from up-counting to
down-counting at the end of the terminal count (the value in the modulo register). In this case the TOF
corresponds to the end of a PWM period.

14.6.2.2 Channel Event Interrupt Description

The meaning of channel interrupts depends on the channel’s current mode (input-capture, output-compare,
edge-aligned PWM, or center-aligned PWM).

14.6.2.2.1 Input Capture Events

When a channel is configured as an input capture channel, the ELSnB:ELSnA control bits select no edge
(off), rising edges, falling edges or any edge as the edge which triggers an input capture event. When the
selected edge is detected, the interrupt flag is set. The flag is cleared by the two-step sequence described
in Section 14.6.2, “Description of Interrupt Operation.”

14.6.2.2.2 Output Compare Events

When a channel is configured as an output compare channel, the interrupt flag is set each time the main
timer counter matches the 16-bit value in the channel value register. The flag is cleared by the two-step
sequence described Section 14.6.2, “Description of Interrupt Operation.”

14.6.2.2.3 PWM End-of-Duty-Cycle Events

For channels configured for PWM operation there are two possibilities. When the channel is configured
for edge-aligned PWM, the channel flag gets set when the timer counter matches the channel value register
which marks the end of the active duty cycle period. When the channel is configured for center-aligned
PWM, the timer count matches the channel value register twice during each PWM cycle. In this CPWM
case, the channel flag is set at the start and at the end of the active duty cycle period which are the times
when the timer counter matches the channel value register. The flag is cleared by the two-step sequence
described Section 14.6.2, “Description of Interrupt Operation.”

14.7 The differences from TPM v2 to TPM v3

1. Write to TPMxCnTH:L registers (Section 14.3.2, “TPM-Counter Registers
(TPM1CNTH:TPM1CNTL)) [SE110-TPM case 7]
Any write to TPMxCNTH or TPMxCNTL registers in TPM v3 clears the TPM counter
(TPMxCNTH:L) and the prescaler counter. Instead, in the TPM v2 only the TPM counter is cleared
in this case.
2. Read of TPMxCNTH:L registers (Section 14.3.2, “TPM-Counter Registers
(TPM1CNTH:TPM1CNTL))
— In TPM v3, any read of TPMxCNTH:L registers during BDM mode returns the value of the
TPM counter that is frozen. In TPM v2, if only one byte of the TPMxCNTH:L registers was
read before the BDM mode became active, then any read of TPMxCNTH:L registers during

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BDM mode returns the latched value of TPMxCNTH:L from the read buffer instead of the
frozen TPM counter value.
— This read coherency mechanism is cleared in TPM v3 in BDM mode if there is a write to
TPMxSC, TPMxCNTH or TPMxCNTL. Instead, in these conditions the TPM v2 does not clear
this read coherency mechanism.
3. Read of TPMxCnVH:L registers (Section 14.3.5, “TPM Channel Value Registers
(TPM1CnVH:TPM1CnVL))
— In TPM v3, any read of TPMxCnVH:L registers during BDM mode returns the value of the
TPMxCnVH:L register. In TPM v2, if only one byte of the TPMxCnVH:L registers was read
before the BDM mode became active, then any read of TPMxCnVH:L registers during BDM
mode returns the latched value of TPMxCNTH:L from the read buffer instead of the value in
the TPMxCnVH:L registers.
— This read coherency mechanism is cleared in TPM v3 in BDM mode if there is a write to
TPMxCnSC. Instead, in this condition the TPM v2 does not clear this read coherency
mechanism.
4. Write to TPMxCnVH:L registers
— Input Capture Mode (Section 14.4.2.1, “Input Capture Mode)
In this mode the TPM v3 does not allow the writes to TPMxCnVH:L registers. Instead, the
TPM v2 allows these writes.
— Output Compare Mode (Section 14.4.2.2, “Output Compare Mode)
In this mode and if (CLKSB:CLKSA not = 0:0), the TPM v3 updates the TPMxCnVH:L
registers with the value of their write buffer at the next change of the TPM counter (end of the
prescaler counting) after the second byte is written. Instead, the TPM v2 always updates these
registers when their second byte is written.
— Edge-Aligned PWM (Section 14.4.2.3, “Edge-Aligned PWM Mode)
In this mode and if (CLKSB:CLKSA not = 00), the TPM v3 updates the TPMxCnVH:L
registers with the value of their write buffer after that the both bytes were written and when the
TPM counter changes from (TPMxMODH:L - 1) to (TPMxMODH:L). If the TPM counter is
a free-running counter, then this update is made when the TPM counter changes from $FFFE
to $FFFF. Instead, the TPM v2 makes this update after that the both bytes were written and
when the TPM counter changes from TPMxMODH:L to $0000.
— Center-Aligned PWM (Section 14.4.2.4, “Center-Aligned PWM Mode)
In this mode and if (CLKSB:CLKSA not = 00), the TPM v3 updates the TPMxCnVH:L
registers with the value of their write buffer after that the both bytes were written and when the
TPM counter changes from (TPMxMODH:L - 1) to (TPMxMODH:L). If the TPM counter is
a free-running counter, then this update is made when the TPM counter changes from $FFFE
to $FFFF. Instead, the TPM v2 makes this update after that the both bytes were written and
when the TPM counter changes from TPMxMODH:L to (TPMxMODH:L - 1).
5. Center-Aligned PWM (Section 14.4.2.4, “Center-Aligned PWM Mode)
— TPMxCnVH:L = TPMxMODH:L [SE110-TPM case 1]
In this case, the TPM v3 produces 100% duty cycle. Instead, the TPM v2 produces 0% duty
cycle.

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— TPMxCnVH:L = (TPMxMODH:L - 1) [SE110-TPM case 2]

In this case, the TPM v3 produces almost 100% duty cycle. Instead, the TPM v2 produces 0%
duty cycle.
— TPMxCnVH:L is changed from 0x0000 to a non-zero value [SE110-TPM case 3 and 5]
In this case, the TPM v3 waits for the start of a new PWM period to begin using the new duty
cycle setting. Instead, the TPM v2 changes the channel output at the middle of the current
PWM period (when the count reaches 0x0000).
— TPMxCnVH:L is changed from a non-zero value to 0x0000 [SE110-TPM case 4]
In this case, the TPM v3 finishes the current PWM period using the old duty cycle setting.
Instead, the TPM v2 finishes the current PWM period using the new duty cycle setting.
6. Write to TPMxMODH:L registers in BDM mode (Section 14.3.3, “TPM Counter Modulo
Registers (TPM1MODH:TPM1MODL))
In the TPM v3 a write to TPMxSC register in BDM mode clears the write coherency mechanism
of TPMxMODH:L registers. Instead, in the TPM v2 this coherency mechanism is not cleared when
there is a write to TPMxSC register.

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Chapter 15
Development Support
15.1 Introduction
Development support systems in the HCS08 include the background debug controller (BDC) and the
on-chip debug module (DBG). The BDC provides a single-wire debug interface to the target MCU that
provides a convenient interface for programming the on-chip Flash and other nonvolatile memories. The
BDC is also the primary debug interface for development and allows non-intrusive access to memory data
and traditional debug features such as CPU register modify, breakpoints, and single instruction trace
commands.
In the HCS08 Family, address and data bus signals are not available on external pins (not even in test
modes). Debug is done through commands fed into the target MCU via the single-wire background debug
interface. The debug module provides a means to selectively trigger and capture bus information so an
external development system can reconstruct what happened inside the MCU on a cycle-by-cycle basis
without having external access to the address and data signals.

15.1.1 Forcing Active Background

The method for forcing active background mode depends on the specific HCS08 derivative. For the
MC9S08EN32, you can force active background after a power-on reset by holding the BKGD pin low as
the device exits the reset condition. You can also force active background by driving BKGD low
immediately after a serial background command that writes a one to the BDFR bit in the SBDFR register.
If no debug pod is connected to the BKGD pin, the MCU will always reset into normal operating mode.

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15.1.2 Features
Features of the BDC module include:
• Single pin for mode selection and background communications
• BDC registers are not located in the memory map
• SYNC command to determine target communications rate
• Non-intrusive commands for memory access
• Active background mode commands for CPU register access
• GO and TRACE1 commands
• BACKGROUND command can wake CPU from stop or wait modes
• One hardware address breakpoint built into BDC
• Oscillator runs in stop mode, if BDC enabled
• COP watchdog disabled while in active background mode
Features of the ICE system include:
• Two trigger comparators: Two address + read/write (R/W) or one full address + data + R/W
• Flexible 8-word by 16-bit FIFO (first-in, first-out) buffer for capture information:
— Change-of-flow addresses or
— Event-only data
• Two types of breakpoints:
— Tag breakpoints for instruction opcodes
— Force breakpoints for any address access
• Nine trigger modes:
— Basic: A-only, A OR B
— Sequence: A then B
— Full: A AND B data, A AND NOT B data
— Event (store data): Event-only B, A then event-only B
— Range: Inside range (A ≤ address ≤ B), outside range (address < A or address > B)

15.2 Background Debug Controller (BDC)

All MCUs in the HCS08 Family contain a single-wire background debug interface that supports in-circuit
programming of on-chip nonvolatile memory and sophisticated non-intrusive debug capabilities. Unlike
debug interfaces on earlier 8-bit MCUs, this system does not interfere with normal application resources.
It does not use any user memory or locations in the memory map and does not share any on-chip
peripherals.
BDC commands are divided into two groups:
• Active background mode commands require that the target MCU is in active background mode (the
user program is not running). Active background mode commands allow the CPU registers to be
read or written, and allow the user to trace one user instruction at a time, or GO to the user program
from active background mode.

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• Non-intrusive commands can be executed at any time even while the user’s program is running.
Non-intrusive commands allow a user to read or write MCU memory locations or access status and
control registers within the background debug controller.
Typically, a relatively simple interface pod is used to translate commands from a host computer into
commands for the custom serial interface to the single-wire background debug system. Depending on the
development tool vendor, this interface pod may use a standard RS-232 serial port, a parallel printer port,
or some other type of communications such as a universal serial bus (USB) to communicate between the
host PC and the pod. The pod typically connects to the target system with ground, the BKGD pin, RESET,
and sometimes VDD. An open-drain connection to reset allows the host to force a target system reset,
which is useful to regain control of a lost target system or to control startup of a target system before the
on-chip nonvolatile memory has been programmed. Sometimes VDD can be used to allow the pod to use
power from the target system to avoid the need for a separate power supply. However, if the pod is powered
separately, it can be connected to a running target system without forcing a target system reset or otherwise
disturbing the running application program.

BKGD 1 2 GND
NO CONNECT 3 4 RESET
NO CONNECT 5 6 VDD

Figure 15-1. BDM Tool Connector

15.2.1 BKGD Pin Description

BKGD is the single-wire background debug interface pin. The primary function of this pin is for
bidirectional serial communication of active background mode commands and data. During reset, this pin
is used to select between starting in active background mode or starting the user’s application program.
This pin is also used to request a timed sync response pulse to allow a host development tool to determine
the correct clock frequency for background debug serial communications.
BDC serial communications use a custom serial protocol first introduced on the M68HC12 Family of
microcontrollers. This protocol assumes the host knows the communication clock rate that is determined
by the target BDC clock rate. All communication is initiated and controlled by the host that drives a
high-to-low edge to signal the beginning of each bit time. Commands and data are sent most significant bit
first (MSB first). For a detailed description of the communications protocol, refer to Section 15.2.2,
“Communication Details.”
If a host is attempting to communicate with a target MCU that has an unknown BDC clock rate, a SYNC
command may be sent to the target MCU to request a timed sync response signal from which the host can
determine the correct communication speed.
BKGD is a pseudo-open-drain pin and there is an on-chip pullup so no external pullup resistor is required.
Unlike typical open-drain pins, the external RC time constant on this pin, which is influenced by external
capacitance, plays almost no role in signal rise time. The custom protocol provides for brief, actively
driven speedup pulses to force rapid rise times on this pin without risking harmful drive level conflicts.
Refer to Section 15.2.2, “Communication Details,” for more detail.

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When no debugger pod is connected to the 6-pin BDM interface connector, the internal pullup on BKGD
chooses normal operating mode. When a debug pod is connected to BKGD it is possible to force the MCU
into active background mode after reset. The specific conditions for forcing active background depend
upon the HCS08 derivative (refer to the introduction to this Development Support section). It is not
necessary to reset the target MCU to communicate with it through the background debug interface.

15.2.2 Communication Details

The BDC serial interface requires the external controller to generate a falling edge on the BKGD pin to
indicate the start of each bit time. The external controller provides this falling edge whether data is
transmitted or received.
BKGD is a pseudo-open-drain pin that can be driven either by an external controller or by the MCU. Data
is transferred MSB first at 16 BDC clock cycles per bit (nominal speed). The interface times out if
512 BDC clock cycles occur between falling edges from the host. Any BDC command that was in progress
when this timeout occurs is aborted without affecting the memory or operating mode of the target MCU
system.
The custom serial protocol requires the debug pod to know the target BDC communication clock speed.
The clock switch (CLKSW) control bit in the BDC status and control register allows the user to select the
BDC clock source. The BDC clock source can either be the bus or the alternate BDC clock source.
The BKGD pin can receive a high or low level or transmit a high or low level. The following diagrams
show timing for each of these cases. Interface timing is synchronous to clocks in the target BDC, but
asynchronous to the external host. The internal BDC clock signal is shown for reference in counting cycles.

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Figure 15-2 shows an external host transmitting a logic 1 or 0 to the BKGD pin of a target HCS08 MCU.
The host is asynchronous to the target so there is a 0-to-1 cycle delay from the host-generated falling edge
to where the target perceives the beginning of the bit time. Ten target BDC clock cycles later, the target
senses the bit level on the BKGD pin. Typically, the host actively drives the pseudo-open-drain BKGD pin
during host-to-target transmissions to speed up rising edges. Because the target does not drive the BKGD
pin during the host-to-target transmission period, there is no need to treat the line as an open-drain signal
during this period.

BDC CLOCK
(TARGET MCU)

HOST
TRANSMIT 1

HOST
TRANSMIT 0

10 CYCLES
EARLIEST START
OF NEXT BIT
SYNCHRONIZATION TARGET SENSES BIT LEVEL
UNCERTAINTY
PERCEIVED START
OF BIT TIME
Figure 15-2. BDC Host-to-Target Serial Bit Timing

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Figure 15-3 shows the host receiving a logic 1 from the target HCS08 MCU. Because the host is
asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on
BKGD to the perceived start of the bit time in the target MCU. The host holds the BKGD pin low long
enough for the target to recognize it (at least two target BDC cycles). The host must release the low drive
before the target MCU drives a brief active-high speedup pulse seven cycles after the perceived start of the
bit time. The host should sample the bit level about 10 cycles after it started the bit time.

BDC CLOCK
(TARGET MCU)

HOST DRIVE
TO BKGD PIN HIGH-IMPEDANCE

TARGET MCU
SPEEDUP PULSE
HIGH-IMPEDANCE HIGH-IMPEDANCE

PERCEIVED START
OF BIT TIME

R-C RISE
BKGD PIN

10 CYCLES
EARLIEST START
OF NEXT BIT
10 CYCLES

HOST SAMPLES BKGD PIN

Figure 15-3. BDC Target-to-Host Serial Bit Timing (Logic 1)

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Figure 15-4 shows the host receiving a logic 0 from the target HCS08 MCU. Because the host is
asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on
BKGD to the start of the bit time as perceived by the target MCU. The host initiates the bit time but the
target HCS08 finishes it. Because the target wants the host to receive a logic 0, it drives the BKGD pin low
for 13 BDC clock cycles, then briefly drives it high to speed up the rising edge. The host samples the bit
level about 10 cycles after starting the bit time.

BDC CLOCK
(TARGET MCU)

HOST DRIVE
TO BKGD PIN HIGH-IMPEDANCE

SPEEDUP
TARGET MCU PULSE
DRIVE AND
SPEED-UP PULSE

PERCEIVED START
OF BIT TIME

BKGD PIN

10 CYCLES
EARLIEST START
10 CYCLES OF NEXT BIT

HOST SAMPLES BKGD PIN

Figure 15-4. BDM Target-to-Host Serial Bit Timing (Logic 0)

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15.2.3 BDC Commands

BDC commands are sent serially from a host computer to the BKGD pin of the target HCS08 MCU. All
commands and data are sent MSB-first using a custom BDC communications protocol. Active background
mode commands require that the target MCU is currently in the active background mode while
non-intrusive commands may be issued at any time whether the target MCU is in active background mode
or running a user application program.
Table 15-1 shows all HCS08 BDC commands, a shorthand description of their coding structure, and the
meaning of each command.
Coding Structure Nomenclature
This nomenclature is used in Table 15-1 to describe the coding structure of the BDC commands.
Commands begin with an 8-bit hexadecimal command code in the host-to-target
direction (most significant bit first)
/ = separates parts of the command
d = delay 16 target BDC clock cycles
AAAA = a 16-bit address in the host-to-target direction
RD = 8 bits of read data in the target-to-host direction
WD = 8 bits of write data in the host-to-target direction
RD16 = 16 bits of read data in the target-to-host direction
WD16 = 16 bits of write data in the host-to-target direction
SS = the contents of BDCSCR in the target-to-host direction (STATUS)
CC = 8 bits of write data for BDCSCR in the host-to-target direction (CONTROL)
RBKP = 16 bits of read data in the target-to-host direction (from BDCBKPT breakpoint
register)
WBKP = 16 bits of write data in the host-to-target direction (for BDCBKPT breakpoint register)

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Table 15-1. BDC Command Summary

Command Active BDM/ Coding

Description
Mnemonic Non-intrusive Structure
Request a timed reference pulse to determine
SYNC Non-intrusive n/a1 target BDC communication speed
Enable acknowledge protocol. Refer to
ACK_ENABLE Non-intrusive D5/d
Freescale document order no. HCS08RMv1/D.
Disable acknowledge protocol. Refer to
ACK_DISABLE Non-intrusive D6/d
Freescale document order no. HCS08RMv1/D.
Enter active background mode if enabled
BACKGROUND Non-intrusive 90/d
(ignore if ENBDM bit equals 0)
READ_STATUS Non-intrusive E4/SS Read BDC status from BDCSCR
WRITE_CONTROL Non-intrusive C4/CC Write BDC controls in BDCSCR
READ_BYTE Non-intrusive E0/AAAA/d/RD Read a byte from target memory
READ_BYTE_WS Non-intrusive E1/AAAA/d/SS/RD Read a byte and report status
Re-read byte from address just read and
READ_LAST Non-intrusive E8/SS/RD
report status
WRITE_BYTE Non-intrusive C0/AAAA/WD/d Write a byte to target memory
WRITE_BYTE_WS Non-intrusive C1/AAAA/WD/d/SS Write a byte and report status
READ_BKPT Non-intrusive E2/RBKP Read BDCBKPT breakpoint register
WRITE_BKPT Non-intrusive C2/WBKP Write BDCBKPT breakpoint register
Go to execute the user application program
GO Active BDM 08/d
starting at the address currently in the PC
Trace 1 user instruction at the address in the
TRACE1 Active BDM 10/d
PC, then return to active background mode
Same as GO but enable external tagging
TAGGO Active BDM 18/d
(HCS08 devices have no external tagging pin)
READ_A Active BDM 68/d/RD Read accumulator (A)
READ_CCR Active BDM 69/d/RD Read condition code register (CCR)
READ_PC Active BDM 6B/d/RD16 Read program counter (PC)
READ_HX Active BDM 6C/d/RD16 Read H and X register pair (H:X)
READ_SP Active BDM 6F/d/RD16 Read stack pointer (SP)
Increment H:X by one then read memory byte
READ_NEXT Active BDM 70/d/RD
located at H:X
Increment H:X by one then read memory byte
READ_NEXT_WS Active BDM 71/d/SS/RD
located at H:X. Report status and data.
WRITE_A Active BDM 48/WD/d Write accumulator (A)
WRITE_CCR Active BDM 49/WD/d Write condition code register (CCR)
WRITE_PC Active BDM 4B/WD16/d Write program counter (PC)
WRITE_HX Active BDM 4C/WD16/d Write H and X register pair (H:X)
WRITE_SP Active BDM 4F/WD16/d Write stack pointer (SP)
Increment H:X by one, then write memory byte
WRITE_NEXT Active BDM 50/WD/d
located at H:X
Increment H:X by one, then write memory byte
WRITE_NEXT_WS Active BDM 51/WD/d/SS
located at H:X. Also report status.

1 The SYNC command is a special operation that does not have a command code.

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The SYNC command is unlike other BDC commands because the host does not necessarily know the
correct communications speed to use for BDC communications until after it has analyzed the response to
the SYNC command.
To issue a SYNC command, the host:
• Drives the BKGD pin low for at least 128 cycles of the slowest possible BDC clock (The slowest
clock is normally the reference oscillator/64 or the self-clocked rate/64.)
• Drives BKGD high for a brief speedup pulse to get a fast rise time (This speedup pulse is typically
one cycle of the fastest clock in the system.)
• Removes all drive to the BKGD pin so it reverts to high impedance
• Monitors the BKGD pin for the sync response pulse
The target, upon detecting the SYNC request from the host (which is a much longer low time than would
ever occur during normal BDC communications):
• Waits for BKGD to return to a logic high
• Delays 16 cycles to allow the host to stop driving the high speedup pulse
• Drives BKGD low for 128 BDC clock cycles
• Drives a 1-cycle high speedup pulse to force a fast rise time on BKGD
• Removes all drive to the BKGD pin so it reverts to high impedance
The host measures the low time of this 128-cycle sync response pulse and determines the correct speed for
subsequent BDC communications. Typically, the host can determine the correct communication speed
within a few percent of the actual target speed and the communication protocol can easily tolerate speed
errors of several percent.

15.2.4 BDC Hardware Breakpoint

The BDC includes one relatively simple hardware breakpoint that compares the CPU address bus to a
16-bit match value in the BDCBKPT register. This breakpoint can generate a forced breakpoint or a tagged
breakpoint. A forced breakpoint causes the CPU to enter active background mode at the first instruction
boundary following any access to the breakpoint address. The tagged breakpoint causes the instruction
opcode at the breakpoint address to be tagged so that the CPU will enter active background mode rather
than executing that instruction if and when it reaches the end of the instruction queue. This implies that
tagged breakpoints can only be placed at the address of an instruction opcode while forced breakpoints can
be set at any address.
The breakpoint enable (BKPTEN) control bit in the BDC status and control register (BDCSCR) is used to
enable the breakpoint logic (BKPTEN = 1). When BKPTEN = 0, its default value after reset, the
breakpoint logic is disabled and no BDC breakpoints are requested regardless of the values in other BDC
breakpoint registers and control bits. The force/tag select (FTS) control bit in BDCSCR is used to select
forced (FTS = 1) or tagged (FTS = 0) type breakpoints.
The on-chip debug module (DBG) includes circuitry for two additional hardware breakpoints that are more
flexible than the simple breakpoint in the BDC module.

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15.3 On-Chip Debug System (DBG)

Because HCS08 devices do not have external address and data buses, the most important functions of an
in-circuit emulator have been built onto the chip with the MCU. The debug system consists of an 8-stage
FIFO that can store address or data bus information, and a flexible trigger system to decide when to capture
bus information and what information to capture. The system relies on the single-wire background debug
system to access debug control registers and to read results out of the eight stage FIFO.
The debug module includes control and status registers that are accessible in the user’s memory map.
These registers are located in the high register space to avoid using valuable direct page memory space.
Most of the debug module’s functions are used during development, and user programs rarely access any
of the control and status registers for the debug module. The one exception is that the debug system can
provide the means to implement a form of ROM patching. This topic is discussed in greater detail in
Section 15.3.6, “Hardware Breakpoints.”

15.3.1 Comparators A and B

Two 16-bit comparators (A and B) can optionally be qualified with the R/W signal and an opcode tracking
circuit. Separate control bits allow you to ignore R/W for each comparator. The opcode tracking circuitry
optionally allows you to specify that a trigger will occur only if the opcode at the specified address is
actually executed as opposed to only being read from memory into the instruction queue. The comparators
are also capable of magnitude comparisons to support the inside range and outside range trigger modes.
Comparators are disabled temporarily during all BDC accesses.
The A comparator is always associated with the 16-bit CPU address. The B comparator compares to the
CPU address or the 8-bit CPU data bus, depending on the trigger mode selected. Because the CPU data
bus is separated into a read data bus and a write data bus, the RWAEN and RWA control bits have an
additional purpose, in full address plus data comparisons they are used to decide which of these buses to
use in the comparator B data bus comparisons. If RWAEN = 1 (enabled) and RWA = 0 (write), the CPU’s
write data bus is used. Otherwise, the CPU’s read data bus is used.
The currently selected trigger mode determines what the debugger logic does when a comparator detects
a qualified match condition. A match can cause:
• Generation of a breakpoint to the CPU
• Storage of data bus values into the FIFO
• Starting to store change-of-flow addresses into the FIFO (begin type trace)
• Stopping the storage of change-of-flow addresses into the FIFO (end type trace)

15.3.2 Bus Capture Information and FIFO Operation

The usual way to use the FIFO is to setup the trigger mode and other control options, then arm the
debugger. When the FIFO has filled or the debugger has stopped storing data into the FIFO, you would
read the information out of it in the order it was stored into the FIFO. Status bits indicate the number of
words of valid information that are in the FIFO as data is stored into it. If a trace run is manually halted by
writing 0 to ARM before the FIFO is full (CNT = 1:0:0:0), the information is shifted by one position and

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the host must perform ((8 – CNT) – 1) dummy reads of the FIFO to advance it to the first significant entry
in the FIFO.
In most trigger modes, the information stored in the FIFO consists of 16-bit change-of-flow addresses. In
these cases, read DBGFH then DBGFL to get one coherent word of information out of the FIFO. Reading
DBGFL (the low-order byte of the FIFO data port) causes the FIFO to shift so the next word of information
is available at the FIFO data port. In the event-only trigger modes (see Section 15.3.5, “Trigger Modes”),
8-bit data information is stored into the FIFO. In these cases, the high-order half of the FIFO (DBGFH) is
not used and data is read out of the FIFO by simply reading DBGFL. Each time DBGFL is read, the FIFO
is shifted so the next data value is available through the FIFO data port at DBGFL.
In trigger modes where the FIFO is storing change-of-flow addresses, there is a delay between CPU
addresses and the input side of the FIFO. Because of this delay, if the trigger event itself is a change-of-flow
address or a change-of-flow address appears during the next two bus cycles after a trigger event starts the
FIFO, it will not be saved into the FIFO. In the case of an end-trace, if the trigger event is a change-of-flow,
it will be saved as the last change-of-flow entry for that debug run.
The FIFO can also be used to generate a profile of executed instruction addresses when the debugger is not
armed. When ARM = 0, reading DBGFL causes the address of the most-recently fetched opcode to be
saved in the FIFO. To use the profiling feature, a host debugger would read addresses out of the FIFO by
reading DBGFH then DBGFL at regular periodic intervals. The first eight values would be discarded
because they correspond to the eight DBGFL reads needed to initially fill the FIFO. Additional periodic
reads of DBGFH and DBGFL return delayed information about executed instructions so the host debugger
can develop a profile of executed instruction addresses.

15.3.3 Change-of-Flow Information

To minimize the amount of information stored in the FIFO, only information related to instructions that
cause a change to the normal sequential execution of instructions is stored. With knowledge of the source
and object code program stored in the target system, an external debugger system can reconstruct the path
of execution through many instructions from the change-of-flow information stored in the FIFO.
For conditional branch instructions where the branch is taken (branch condition was true), the source
address is stored (the address of the conditional branch opcode). Because BRA and BRN instructions are
not conditional, these events do not cause change-of-flow information to be stored in the FIFO.
Indirect JMP and JSR instructions use the current contents of the H:X index register pair to determine the
destination address, so the debug system stores the run-time destination address for any indirect JMP or
JSR. For interrupts, RTI, or RTS, the destination address is stored in the FIFO as change-of-flow
information.

15.3.4 Tag vs. Force Breakpoints and Triggers

Tagging is a term that refers to identifying an instruction opcode as it is fetched into the instruction queue,
but not taking any other action until and unless that instruction is actually executed by the CPU. This
distinction is important because any change-of-flow from a jump, branch, subroutine call, or interrupt
causes some instructions that have been fetched into the instruction queue to be thrown away without being
executed.

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A force-type breakpoint waits for the current instruction to finish and then acts upon the breakpoint
request. The usual action in response to a breakpoint is to go to active background mode rather than
continuing to the next instruction in the user application program.
The tag vs. force terminology is used in two contexts within the debug module. The first context refers to
breakpoint requests from the debug module to the CPU. The second refers to match signals from the
comparators to the debugger control logic. When a tag-type break request is sent to the CPU, a signal is
entered into the instruction queue along with the opcode so that if/when this opcode ever executes, the CPU
will effectively replace the tagged opcode with a BGND opcode so the CPU goes to active background
mode rather than executing the tagged instruction. When the TRGSEL control bit in the DBGT register is
set to select tag-type operation, the output from comparator A or B is qualified by a block of logic in the
debug module that tracks opcodes and only produces a trigger to the debugger if the opcode at the compare
address is actually executed. There is separate opcode tracking logic for each comparator so more than one
compare event can be tracked through the instruction queue at a time.

15.3.5 Trigger Modes

The trigger mode controls the overall behavior of a debug run. The 4-bit TRG field in the DBGT register
selects one of nine trigger modes. When TRGSEL = 1 in the DBGT register, the output of the comparator
must propagate through an opcode tracking circuit before triggering FIFO actions. The BEGIN bit in
DBGT chooses whether the FIFO begins storing data when the qualified trigger is detected (begin trace),
or the FIFO stores data in a circular fashion from the time it is armed until the qualified trigger is detected
(end trigger).
A debug run is started by writing a 1 to the ARM bit in the DBGC register, which sets the ARMF flag and
clears the AF and BF flags and the CNT bits in DBGS. A begin-trace debug run ends when the FIFO gets
full. An end-trace run ends when the selected trigger event occurs. Any debug run can be stopped manually
by writing a 0 to ARM or DBGEN in DBGC.
In all trigger modes except event-only modes, the FIFO stores change-of-flow addresses. In event-only
trigger modes, the FIFO stores data in the low-order eight bits of the FIFO.
The BEGIN control bit is ignored in event-only trigger modes and all such debug runs are begin type
traces. When TRGSEL = 1 to select opcode fetch triggers, it is not necessary to use R/W in comparisons
because opcode tags would only apply to opcode fetches that are always read cycles. It would also be
unusual to specify TRGSEL = 1 while using a full mode trigger because the opcode value is normally
known at a particular address.
The following trigger mode descriptions only state the primary comparator conditions that lead to a trigger.
Either comparator can usually be further qualified with R/W by setting RWAEN (RWBEN) and the
corresponding RWA (RWB) value to be matched against R/W. The signal from the comparator with
optional R/W qualification is used to request a CPU breakpoint if BRKEN = 1 and TAG determines
whether the CPU request will be a tag request or a force request.

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A-Only — Trigger when the address matches the value in comparator A

A OR B — Trigger when the address matches either the value in comparator A or the value in
comparator B
A Then B — Trigger when the address matches the value in comparator B but only after the address for
another cycle matched the value in comparator A. There can be any number of cycles after the A match
and before the B match.
A AND B Data (Full Mode) — This is called a full mode because address, data, and R/W (optionally)
must match within the same bus cycle to cause a trigger event. Comparator A checks address, the low byte
of comparator B checks data, and R/W is checked against RWA if RWAEN = 1. The high-order half of
comparator B is not used.
In full trigger modes it is not useful to specify a tag-type CPU breakpoint (BRKEN = TAG = 1), but if you
do, the comparator B data match is ignored for the purpose of issuing the tag request to the CPU and the
CPU breakpoint is issued when the comparator A address matches.
A AND NOT B Data (Full Mode) — Address must match comparator A, data must not match the low
half of comparator B, and R/W must match RWA if RWAEN = 1. All three conditions must be met within
the same bus cycle to cause a trigger.
In full trigger modes it is not useful to specify a tag-type CPU breakpoint (BRKEN = TAG = 1), but if you
do, the comparator B data match is ignored for the purpose of issuing the tag request to the CPU and the
CPU breakpoint is issued when the comparator A address matches.
Event-Only B (Store Data) — Trigger events occur each time the address matches the value in
comparator B. Trigger events cause the data to be captured into the FIFO. The debug run ends when the
FIFO becomes full.
A Then Event-Only B (Store Data) — After the address has matched the value in comparator A, a trigger
event occurs each time the address matches the value in comparator B. Trigger events cause the data to be
captured into the FIFO. The debug run ends when the FIFO becomes full.
Inside Range (A ≤ Address ≤ B) — A trigger occurs when the address is greater than or equal to the value
in comparator A and less than or equal to the value in comparator B at the same time.
Outside Range (Address < A or Address > B) — A trigger occurs when the address is either less than
the value in comparator A or greater than the value in comparator B.

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15.3.6 Hardware Breakpoints

The BRKEN control bit in the DBGC register may be set to 1 to allow any of the trigger conditions
described in Section 15.3.5, “Trigger Modes,” to be used to generate a hardware breakpoint request to the
CPU. TAG in DBGC controls whether the breakpoint request will be treated as a tag-type breakpoint or a
force-type breakpoint. A tag breakpoint causes the current opcode to be marked as it enters the instruction
queue. If a tagged opcode reaches the end of the pipe, the CPU executes a BGND instruction to go to active
background mode rather than executing the tagged opcode. A force-type breakpoint causes the CPU to
finish the current instruction and then go to active background mode.
If the background mode has not been enabled (ENBDM = 1) by a serial WRITE_CONTROL command
through the BKGD pin, the CPU will execute an SWI instruction instead of going to active background
mode.

15.4 Register Definition

This section contains the descriptions of the BDC and DBG registers and control bits.
Refer to the high-page register summary in the device overview chapter of this data sheet for the absolute
address assignments for all DBG registers. This section refers to registers and control bits only by their
names. A Freescale-provided equate or header file is used to translate these names into the appropriate
absolute addresses.

15.4.1 BDC Registers and Control Bits

The BDC has two registers:
• The BDC status and control register (BDCSCR) is an 8-bit register containing control and status
bits for the background debug controller.
• The BDC breakpoint match register (BDCBKPT) holds a 16-bit breakpoint match address.
These registers are accessed with dedicated serial BDC commands and are not located in the memory
space of the target MCU (so they do not have addresses and cannot be accessed by user programs).
Some of the bits in the BDCSCR have write limitations; otherwise, these registers may be read or written
at any time. For example, the ENBDM control bit may not be written while the MCU is in active
background mode. (This prevents the ambiguous condition of the control bit forbidding active background
mode while the MCU is already in active background mode.) Also, the four status bits (BDMACT, WS,
WSF, and DVF) are read-only status indicators and can never be written by the WRITE_CONTROL serial
BDC command. The clock switch (CLKSW) control bit may be read or written at any time.

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15.4.1.1 BDC Status and Control Register (BDCSCR)

This register can be read or written by serial BDC commands (READ_STATUS and WRITE_CONTROL)
but is not accessible to user programs because it is not located in the normal memory map of the MCU.

7 6 5 4 3 2 1 0

R BDMACT WS WSF DVF

ENBDM BKPTEN FTS CLKSW
W

Normal 0 0 0 0 0 0 0 0
Reset

Reset in 1 1 0 0 1 0 0 0
Active BDM:

= Unimplemented or Reserved

Figure 15-5. BDC Status and Control Register (BDCSCR)

Table 15-2. BDCSCR Register Field Descriptions

Field Description

7 Enable BDM (Permit Active Background Mode) — Typically, this bit is written to 1 by the debug host shortly
ENBDM after the beginning of a debug session or whenever the debug host resets the target and remains 1 until a normal
reset clears it.
0 BDM cannot be made active (non-intrusive commands still allowed)
1 BDM can be made active to allow active background mode commands
6 Background Mode Active Status — This is a read-only status bit.
BDMACT 0 BDM not active (user application program running)
1 BDM active and waiting for serial commands
5 BDC Breakpoint Enable — If this bit is clear, the BDC breakpoint is disabled and the FTS (force tag select)
BKPTEN control bit and BDCBKPT match register are ignored.
0 BDC breakpoint disabled
1 BDC breakpoint enabled
4 Force/Tag Select — When FTS = 1, a breakpoint is requested whenever the CPU address bus matches the
FTS BDCBKPT match register. When FTS = 0, a match between the CPU address bus and the BDCBKPT register
causes the fetched opcode to be tagged. If this tagged opcode ever reaches the end of the instruction queue,
the CPU enters active background mode rather than executing the tagged opcode.
0 Tag opcode at breakpoint address and enter active background mode if CPU attempts to execute that
instruction
1 Breakpoint match forces active background mode at next instruction boundary (address need not be an
opcode)
3 Select Source for BDC Communications Clock — CLKSW defaults to 0, which selects the alternate BDC
CLKSW clock source.
0 Alternate BDC clock source
1 MCU bus clock

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Table 15-2. BDCSCR Register Field Descriptions (continued)

Field Description

2 Wait or Stop Status — When the target CPU is in wait or stop mode, most BDC commands cannot function.
WS However, the BACKGROUND command can be used to force the target CPU out of wait or stop and into active
background mode where all BDC commands work. Whenever the host forces the target MCU into active
background mode, the host should issue a READ_STATUS command to check that BDMACT = 1 before
attempting other BDC commands.
0 Target CPU is running user application code or in active background mode (was not in wait or stop mode when
background became active)
1 Target CPU is in wait or stop mode, or a BACKGROUND command was used to change from wait or stop to
active background mode
1 Wait or Stop Failure Status — This status bit is set if a memory access command failed due to the target CPU
WSF executing a wait or stop instruction at or about the same time. The usual recovery strategy is to issue a
BACKGROUND command to get out of wait or stop mode into active background mode, repeat the command
that failed, then return to the user program. (Typically, the host would restore CPU registers and stack values and
re-execute the wait or stop instruction.)
0 Memory access did not conflict with a wait or stop instruction
1 Memory access command failed because the CPU entered wait or stop mode
0 Data Valid Failure Status — This status bit is not used in the MC9S08EN32 Series because it does not have
DVF any slow access memory.
0 Memory access did not conflict with a slow memory access
1 Memory access command failed because CPU was not finished with a slow memory access

15.4.1.2 BDC Breakpoint Match Register (BDCBKPT)

This 16-bit register holds the address for the hardware breakpoint in the BDC. The BKPTEN and FTS
control bits in BDCSCR are used to enable and configure the breakpoint logic. Dedicated serial BDC
commands (READ_BKPT and WRITE_BKPT) are used to read and write the BDCBKPT register but is
not accessible to user programs because it is not located in the normal memory map of the MCU.
Breakpoints are normally set while the target MCU is in active background mode before running the user
application program. For additional information about setup and use of the hardware breakpoint logic in
the BDC, refer to Section 15.2.4, “BDC Hardware Breakpoint.”

15.4.2 System Background Debug Force Reset Register (SBDFR)

This register contains a single write-only control bit. A serial background mode command such as
WRITE_BYTE must be used to write to SBDFR. Attempts to write this register from a user program are
ignored. Reads always return 0x00.

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7 6 5 4 3 2 1 0

R 0 0 0 0 0 0 0 0

W BDFR1

Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved

1
BDFR is writable only through serial background mode debug commands, not from user programs.

Figure 15-6. System Background Debug Force Reset Register (SBDFR)

Table 15-3. SBDFR Register Field Description

Field Description

0 Background Debug Force Reset — A serial active background mode command such as WRITE_BYTE allows
BDFR an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot
be written from a user program.

15.4.3 DBG Registers and Control Bits

The debug module includes nine bytes of register space for three 16-bit registers and three 8-bit control
and status registers. These registers are located in the high register space of the normal memory map so
they are accessible to normal application programs. These registers are rarely if ever accessed by normal
user application programs with the possible exception of a ROM patching mechanism that uses the
breakpoint logic.

15.4.3.1 Debug Comparator A High Register (DBGCAH)

This register contains compare value bits for the high-order eight bits of comparator A. This register is
forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1.

15.4.3.2 Debug Comparator A Low Register (DBGCAL)

This register contains compare value bits for the low-order eight bits of comparator A. This register is
forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1.

15.4.3.3 Debug Comparator B High Register (DBGCBH)

This register contains compare value bits for the high-order eight bits of comparator B. This register is
forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1.

15.4.3.4 Debug Comparator B Low Register (DBGCBL)

This register contains compare value bits for the low-order eight bits of comparator B. This register is
forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1.

MC9S08EN32 Series Data Sheet, Rev. 2

276 Freescale Semiconductor
 Chapter 15 Development Support

15.4.3.5 Debug FIFO High Register (DBGFH)

This register provides read-only access to the high-order eight bits of the FIFO. Writes to this register have
no meaning or effect. In the event-only trigger modes, the FIFO only stores data into the low-order byte of
each FIFO word, so this register is not used and will read 0x00.
Reading DBGFH does not cause the FIFO to shift to the next word. When reading 16-bit words out of the
FIFO, read DBGFH before reading DBGFL because reading DBGFL causes the FIFO to advance to the
next word of information.

15.4.3.6 Debug FIFO Low Register (DBGFL)

This register provides read-only access to the low-order eight bits of the FIFO. Writes to this register have
no meaning or effect.
Reading DBGFL causes the FIFO to shift to the next available word of information. When the debug
module is operating in event-only modes, only 8-bit data is stored into the FIFO (high-order half of each
FIFO word is unused). When reading 8-bit words out of the FIFO, simply read DBGFL repeatedly to get
successive bytes of data from the FIFO. It isn’t necessary to read DBGFH in this case.
Do not attempt to read data from the FIFO while it is still armed (after arming but before the FIFO is filled
or ARMF is cleared) because the FIFO is prevented from advancing during reads of DBGFL. This can
interfere with normal sequencing of reads from the FIFO.
Reading DBGFL while the debugger is not armed causes the address of the most-recently fetched opcode
to be stored to the last location in the FIFO. By reading DBGFH then DBGFL periodically, external host
software can develop a profile of program execution. After eight reads from the FIFO, the ninth read will
return the information that was stored as a result of the first read. To use the profiling feature, read the FIFO
eight times without using the data to prime the sequence and then begin using the data to get a delayed
picture of what addresses were being executed. The information stored into the FIFO on reads of DBGFL
(while the FIFO is not armed) is the address of the most-recently fetched opcode.

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 277
Chapter 15 Development Support

15.4.3.7 Debug Control Register (DBGC)

This register can be read or written at any time.

7 6 5 4 3 2 1 0

R
DBGEN ARM TAG BRKEN RWA RWAEN RWB RWBEN
W

Reset 0 0 0 0 0 0 0 0

Figure 15-7. Debug Control Register (DBGC)

Table 15-4. DBGC Register Field Descriptions

Field Description

7 Debug Module Enable — Used to enable the debug module. DBGEN cannot be set to 1 if the MCU is secure.
DBGEN 0 DBG disabled
1 DBG enabled

6 Arm Control — Controls whether the debugger is comparing and storing information in the FIFO. A write is used
ARM to set this bit (and ARMF) and completion of a debug run automatically clears it. Any debug run can be manually
stopped by writing 0 to ARM or to DBGEN.
0 Debugger not armed
1 Debugger armed

5 Tag/Force Select — Controls whether break requests to the CPU will be tag or force type requests. If
TAG BRKEN = 0, this bit has no meaning or effect.
0 CPU breaks requested as force type requests
1 CPU breaks requested as tag type requests

4 Break Enable — Controls whether a trigger event will generate a break request to the CPU. Trigger events can
BRKEN cause information to be stored in the FIFO without generating a break request to the CPU. For an end trace, CPU
break requests are issued to the CPU when the comparator(s) and R/W meet the trigger requirements. For a
begin trace, CPU break requests are issued when the FIFO becomes full. TRGSEL does not affect the timing of
CPU break requests.
0 CPU break requests not enabled
1 Triggers cause a break request to the CPU

3 R/W Comparison Value for Comparator A — When RWAEN = 1, this bit determines whether a read or a write
RWA access qualifies comparator A. When RWAEN = 0, RWA and the R/W signal do not affect comparator A.
0 Comparator A can only match on a write cycle
1 Comparator A can only match on a read cycle

2 Enable R/W for Comparator A — Controls whether the level of R/W is considered for a comparator A match.
RWAEN 0 R/W is not used in comparison A
1 R/W is used in comparison A

1 R/W Comparison Value for Comparator B — When RWBEN = 1, this bit determines whether a read or a write
RWB access qualifies comparator B. When RWBEN = 0, RWB and the R/W signal do not affect comparator B.
0 Comparator B can match only on a write cycle
1 Comparator B can match only on a read cycle

0 Enable R/W for Comparator B — Controls whether the level of R/W is considered for a comparator B match.
RWBEN 0 R/W is not used in comparison B
1 R/W is used in comparison B

MC9S08EN32 Series Data Sheet, Rev. 2

278 Freescale Semiconductor
 Chapter 15 Development Support

15.4.3.8 Debug Trigger Register (DBGT)

This register can be read any time, but may be written only if ARM = 0, except bits 4 and 5 are hard-wired
to 0s.

7 6 5 4 3 2 1 0

R 0 0
TRGSEL BEGIN TRG3 TRG2 TRG1 TRG0
W

Reset 0 0 0 0 0 0 0 0

= Unimplemented or Reserved

Figure 15-8. Debug Trigger Register (DBGT)

Table 15-5. DBGT Register Field Descriptions

Field Description

7 Trigger Type — Controls whether the match outputs from comparators A and B are qualified with the opcode
TRGSEL tracking logic in the debug module. If TRGSEL is set, a match signal from comparator A or B must propagate
through the opcode tracking logic and a trigger event is only signalled to the FIFO logic if the opcode at the match
address is actually executed.
0 Trigger on access to compare address (force)
1 Trigger if opcode at compare address is executed (tag)

6 Begin/End Trigger Select — Controls whether the FIFO starts filling at a trigger or fills in a circular manner until
BEGIN a trigger ends the capture of information. In event-only trigger modes, this bit is ignored and all debug runs are
assumed to be begin traces.
0 Data stored in FIFO until trigger (end trace)
1 Trigger initiates data storage (begin trace)

3:0 Select Trigger Mode — Selects one of nine triggering modes, as described below.
TRG[3:0] 0000 A-only
0001 A OR B
0010 A Then B
0011 Event-only B (store data)
0100 A then event-only B (store data)
0101 A AND B data (full mode)
0110 A AND NOT B data (full mode)
0111 Inside range: A ≤ address ≤ B
1000 Outside range: address < A or address > B
1001 – 1111 (No trigger)

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 279
Chapter 15 Development Support

15.4.3.9 Debug Status Register (DBGS)

This is a read-only status register.

7 6 5 4 3 2 1 0

R AF BF ARMF 0 CNT3 CNT2 CNT1 CNT0

Reset 0 0 0 0 0 0 0 0

= Unimplemented or Reserved

Figure 15-9. Debug Status Register (DBGS)

Table 15-6. DBGS Register Field Descriptions

Field Description

7 Trigger Match A Flag — AF is cleared at the start of a debug run and indicates whether a trigger match A
AF condition was met since arming.
0 Comparator A has not matched
1 Comparator A match

6 Trigger Match B Flag — BF is cleared at the start of a debug run and indicates whether a trigger match B
BF condition was met since arming.
0 Comparator B has not matched
1 Comparator B match

5 Arm Flag — While DBGEN = 1, this status bit is a read-only image of ARM in DBGC. This bit is set by writing 1
ARMF to the ARM control bit in DBGC (while DBGEN = 1) and is automatically cleared at the end of a debug run. A
debug run is completed when the FIFO is full (begin trace) or when a trigger event is detected (end trace). A
debug run can also be ended manually by writing 0 to ARM or DBGEN in DBGC.
0 Debugger not armed
1 Debugger armed

3:0 FIFO Valid Count — These bits are cleared at the start of a debug run and indicate the number of words of valid
CNT[3:0] data in the FIFO at the end of a debug run. The value in CNT does not decrement as data is read out of the FIFO.
The external debug host is responsible for keeping track of the count as information is read out of the FIFO.
0000 Number of valid words in FIFO = No valid data
0001 Number of valid words in FIFO = 1
0010 Number of valid words in FIFO = 2
0011 Number of valid words in FIFO = 3
0100 Number of valid words in FIFO = 4
0101 Number of valid words in FIFO = 5
0110 Number of valid words in FIFO = 6
0111 Number of valid words in FIFO = 7
1000 Number of valid words in FIFO = 8

MC9S08EN32 Series Data Sheet, Rev. 2

280 Freescale Semiconductor
Appendix A
Electrical Characteristics

A.1 Introduction
This section contains the most accurate electrical and timing information for the MC9S08EN32 Series of
microcontrollers available at the time of publication.

A.2 Parameter Classification

The electrical parameters shown in this supplement are guaranteed by various methods. To give the
customer a better understanding the following classification is used and the parameters are tagged
accordingly in the tables where appropriate:

Table A-1. Parameter Classifications

P Those parameters are guaranteed during production testing on each individual device.
Those parameters are achieved by the design characterization by measuring a
C
statistically relevant sample size across process variations.
Those parameters are achieved by design characterization on a small sample size from
T typical devices under typical conditions unless otherwise noted. All values shown in
the typical column are within this category.
D Those parameters are derived mainly from simulations.

NOTE
The classification is shown in the column labeled “C” in the parameter
tables where appropriate.

A.3 Absolute Maximum Ratings

Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not
guaranteed. Stress beyond the limits specified in Table A-2 may affect device reliability or cause
permanent damage to the device. For functional operating conditions, refer to the remaining tables in this
section.

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 281
Appendix A Electrical Characteristics

This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD).
Table A-2. Absolute Maximum Ratings

Num Rating Symbol Value Unit

1 Supply voltage VDD –0.3 to + 5.8 V
2 Input voltage VIn – 0.3 to VDD + 0.3 V
Instantaneous maximum current Single pin limit
3 ID ± 25 mA
(applies to all port pins)1, 2, 3
4 Maximum current into VDD IDD 120 mA
5 Storage temperature Tstg –55 to +150 °C
1
Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp
voltages, then use the larger of the two resistance values.
2 All functional non-supply pins are internally clamped to V
SS and VDD.
3 Power supply must maintain regulation within operating V
DD range during instantaneous and operating
maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection
current may flow out of VDD and could result in external power supply going out of regulation. Ensure
external VDD load will shunt current greater than maximum injection current. This will be the greatest
risk when the MCU is not consuming power. Examples are: if no system clock is present, or if the clock
rate is very low which would reduce overall power consumption.

A.4 Thermal Characteristics

This section provides information about operating temperature range, power dissipation, and package
thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in
on-chip logic and it is user-determined rather than being controlled by the MCU design. In order to take
PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or
VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy
loads), the difference between pin voltage and VSS or VDD will be very small.

MC9S08EN32 Series Data Sheet, Rev. 2

282 Freescale Semiconductor
 Appendix A Electrical Characteristics

Table A-3. Thermal Characteristics

Temp.
Num C Rating Symbol Value Unit
Code

1 D –40 to 125 M
Operating temperature range (packaged) TA –40 to 105 °C V
–40 to 85 C

2 T Maximum Junction Temperature1 TJ 135 °C —

3 D Thermal resistance2

Single-layer board

48-pin LQFP θJA 75 °C/W

32-pin LQFP θJA 80 °C/W

Four-Layer board

48-pin LQFP θJA 51 °C/W

32-pin LQFP θJA 52 °C/W

1 Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
2 Junction to Ambient Natural Convection

The average chip-junction temperature (TJ) in °C can be obtained from:

TJ = TA + (PD × θJA) Eqn. A-1

where:
TA = Ambient temperature, °C
θJA = Package thermal resistance, junction-to-ambient, °C/W
PD = Pint + PI/O
Pint = IDD × VDD, Watts — chip internal power
PI/O = Power dissipation on input and output pins — user determined
For most applications, PI/O << Pint and can be neglected. An approximate relationship between PD and TJ
(if PI/O is neglected) is:

PD = K ÷ (TJ + 273°C) Eqn. A-2

Solving equations 1 and 2 for K gives:

K = PD × (TA + 273°C) + θJA × (PD)2 Eqn. A-3

where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring
PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by
solving equations 1 and 2 iteratively for any value of TA.

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 283
Appendix A Electrical Characteristics

A.5 ESD Protection and Latch-Up Immunity

Although damage from electrostatic discharge (ESD) is much less common on these devices than on early
CMOS circuits, normal handling precautions should be used to avoid exposure to static discharge.
Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels
of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade
Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body
Model (HBM) and the Charge Device Model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
Table A-4. ESD and Latch-up Test Conditions

Model Description Symbol Value Unit

Series Resistance R1 1500 Ω

Human Body Storage Capacitance C 100 pF
Number of Pulse per pin – 3
Minimum input voltage limit –2.5 V
Latch-up
Maximum input voltage limit 7.5 V

Table A-5. ESD and Latch-Up Protection Characteristics

Num Rating Symbol Min Max Unit

1 Human Body Model (HBM) VHBM +/- 2000 – V

2 Charge Device Model (CDM) VCDM +/- 500 – V

3 Latch-up Current at TA = 125°C ILAT +/- 100 – mA

MC9S08EN32 Series Data Sheet, Rev. 2

284 Freescale Semiconductor
 Appendix A Electrical Characteristics

A.6 DC Characteristics
This section includes information about power supply requirements, I/O pin characteristics, and power
supply current in various operating modes.
Table A-6. DC Characteristics

Num C Characteristic Symbol Condition Min Typ1 Max Unit

1 — Operating Voltage VDD 2.7 — 5.5 V
P All I/O pins, low-drive strength 5 V, ILoad = –2 mA VDD – 1.5 — —

C 3 V, ILoad = –0.6 mA VDD – 1.5 — —

C Output high 5 V, ILoad = –0.4 mA VDD – 0.8 — —

2 C voltage VOH 3 V, ILoad = –0.24 mA VDD – 0.8 — — V
P All I/O pins, high-drive strength 5 V, ILoad = –10 mA VDD – 1.5 — —
C 3 V, ILoad = –3 mA VDD – 1.5 — —
C 5 V, ILoad = –2 mA VDD – 0.8 — —
C 3 V, ILoad = –0.4 mA VDD – 0.8 — —
3 C Output Max total IOH for all ports IOHT 5V 0 — -100 mA
high current 3V 0 — -60

P All I/O pins, low-drive strength 5 V, ILoad = 2 mA — — 1.5

C 3 V, ILoad = 0.6 mA — — 1.5

C Output low 5 V, ILoad = 0.4 mA — — 0.8

4 C voltage VOL 3 V, ILoad = 0.24 mA — — 0.8 V
P All I/O pins, high-drive strength 5 V, ILoad = 10 mA — — 1.5
C 3 V, ILoad = 3 mA — — 1.5
C 5 V, ILoad = 2 mA — — 0.8
C 3 V, ILoad = 0.4 mA — — 0.8
5 C Output Max total IOL for all ports IOLT 5V 0 — 100 mA
low current 3V 0 — 60
6 C Input high voltage; all digital inputs VIH 5V 0.65 x VDD — —
7 C Input low voltage; all digital inputs VIL 5V — — 0.35 x VDD V

8 C Input hysteresis Vhys 0.06 x VDD mV

Input leakage VIn = VDD or VSS — 0.1 1 μA
9 P current (Per pin) |IIn|
all input only pins
Hi-Z (off-state) leakage VIn = VDD or VSS — 0.1 1 μA
10 P
current (per pin) |IOZ|
all input/output

Pullup resistors (or Pulldown2 resistors RPU, 5V 20 45 65

P
11 when enabled) RPD kΩ
C 3V 20 45 65
Input Capacitance, all pins
12 T
CIn — — 8 pF
13 D RAM retention voltage VRAM 0.9 1.4 2.0 V

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 285
Appendix A Electrical Characteristics

Table A-6. DC Characteristics (continued)

Num C Characteristic Symbol Condition Min Typ1 Max Unit

3
14 D POR re-arm voltage VPOR 0.9 1.4 2.0 V
4
15 D POR re-arm time tPOR 10 — — μs
Low-voltage detection threshold —
high range VLVD1
16 P
VDD falling 3.9 4.0 4.1 V
VDD rising 4.0 4.1 4.2
Low-voltage detection threshold —
low range VLVD0
17 P
VDD falling 2.48 2.56 2.64 V
VDD rising 2.54 2.62 2.70
Low-voltage warning threshold —
high range 1 VLVW3
18 C
VDD falling 4.5 4.6 4.7 V
VDD rising 4.6 4.7 4.8
Low-voltage warning threshold —
high range 0 VLVW2
19 P
VDD falling 4.2 4.3 4.4 V
VDD rising 4.3 4.4 4.5
Low-voltage warning threshold
low range 1 VLVW1
20 P
VDD falling 2.84 2.92 3.00 V
VDD rising 2.90 2.98 3.06
Low-voltage warning threshold —
low range 0 VLVW0
21 C
VDD falling 2.66 2.74 2.82 V
VDD rising 2.72 2.80 2.88
Low-voltage inhibit reset/recover Vhys 5V — 100 —
22 T hysteresis mV
3V — 60 —
dc injection current 5, 6, 7, 8
Single pin limit VIN > VDD 0 — 2
D IIC VIN < VSS 0 — –0.2 mA
23
Total MCU limit, includes VIN > VDD 0 — 25
sum of all stressed pins
VIN < VSS 0 — –5
Bandgap Voltage Reference VBG
24 C Factory trimmed at 1.19 1.20 1.21 V
VDD = 3.0 V, Temp = 25°C
1
Typical values are measured at 25°C. Characterized, not tested
2
When a pin interrupt is configured to detect rising edges, pulldown resistors are used in place of pullup resistors.
3
Maximum is highest voltage that POR is guaranteed.
4
Simulated, not tested
5
Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current
conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result
in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or
if clock rate is very low which (would reduce overall power consumption).
6
All functional non-supply pins are internally clamped to VSS and VDD.

MC9S08EN32 Series Data Sheet, Rev. 2

286 Freescale Semiconductor
 Appendix A Electrical Characteristics

7
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values for positive and negative clamp voltages, then use the larger of the two values.
8
PTE1 does not have a clamp diode to VDD. Do not drive PTE1 above VDD.

A.7 Supply Current Characteristics

Table A-7. Supply Current Characteristics

Num C Parameter Symbol VDD (V) Typical1 Max2 Unit

C Run supply current3 measured at 5 3 7.5

1 (CPU clock = 2 MHz, fBus = 1 MHz) RIDD mA
C 3 2.8 7.4
3
P Run supply current measured at 5 7.7 11.4
2 (CPU clock = 16 MHz, fBus = 8 MHz) RIDD mA
C 3 7.4 11.2

P Run supply current3 measured at 5 15 24

3 (CPU clock = 40 MHz, fBus = 20 MHz) RIDD mA
C 3 14 23

Stop3 mode
P4 supply
current –40 °C (C, V, & M suffix) 0.9 —

P4 25 °C (All parts) 5 1.0 —

P 105 °C (V suffix only) 26 39

4 P 125 °C (M suffix only) S3IDD 62 90 μA

C –40 °C (C, V, & M suffix) 0.8 —

C 25 °C (All parts) 3 0.9 —

C 105 °C (V suffix only) 21 32

C 125 °C (M suffix only) 52 80

Stop2 mode
P4 supply
current –40 °C (C, V, & M suffix) 0.8 —

P4 25 °C (All parts) 5 0.9 —

P 105 °C (V suffix only) 25 37

5 P 125 °C (M suffix only) S2IDD 46 70 μA

C –40 °C (C, V, & M suffix) 0.7 —

C 25 °C (All parts) 3 0.8 —

C 105 °C (V suffix only) 20 30

C 125 °C (M suffix only) 40 60

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 287
Appendix A Electrical Characteristics

Table A-7. Supply Current Characteristics (continued)

Num C Parameter Symbol VDD (V) Typical1 Max2 Unit

RTC adder to stop2 or stop35, 25°C 5 300 — nA

6 C
3 300 — nA

LVD adder to stop3 (LVDE = LVDSE = 1) 5 110 — μA

7 C
3 90 — μA

Adder to stop3 for oscillator enabled6 5 5 — μA

8 C (IRCLKEN = 1 and IREFSTEN = 1 or
ERCLKEN = 1 and EREFSTEN = 1) 3 5 — μA
1
Typicals are measured at 25°C, unless otherwise noted.
2
Maximum values in this column apply for the full operating temperature range of the device unless otherwise noted.
3
All modules except ADC active, MCG configured for FBE, and does not include any dc loads on port pins
4
Stop currents are tested in production for 25°C on all parts. Tests at other temperatures depend upon the part number
suffix and maturity of the product. Freescale may eliminate a test insertion at a particular temperature from the
production test flow once sufficient data has been collected and is approved.
5
Most customers are expected to find that auto-wakeup from stop2 or stop3 can be used instead of the higher current
wait mode.
6
Values given under the following conditions: low range operation (RANGE = 0), low power mode (HGO = 0).

A.8 Analog Comparator (ACMP) Electricals

Table A-8. Analog Comparator Electrical Specifications

Num C Rating Symbol Min Typical Max Unit

1 — Supply voltage VDD 2.7 — 5.5 V

2 D Supply current (active) IDDAC — 20 35 μA
3 D Analog input voltage VAIN VSS – 0.3 — VDD V
4 D Analog input offset voltage VAIO 20 40 mV
5 D Analog Comparator hysteresis VH 3.0 6.0 20.0 mV

6 D Analog input leakage current IALKG -- -- 1.0 μA

7 D Analog Comparator initialization delay tAINIT — — 1.0 μs

A.9 ADC Characteristics

Table A-9. 12-bit ADC Operating Conditions

Characteristic Conditions Symb Min Typ1 Max Unit Comment

Supply voltage Absolute VDDAD 2.7 — 5.5 V

Delta to VDD (VDD-VDDAD)2 ΔVDDAD -100 0 +100 mV

Ground voltage Delta to VSS (VSS-VSSAD)2 ΔVSSAD -100 0 +100 mV

MC9S08EN32 Series Data Sheet, Rev. 2

288 Freescale Semiconductor
 Appendix A Electrical Characteristics

Table A-9. 12-bit ADC Operating Conditions (continued)

Characteristic Conditions Symb Min Typ1 Max Unit Comment

Ref Voltage VREFH 2.7 VDDAD VDDAD V Applicable in only

High 64-pin packages
{VREFH < VDDAD
characterized but
not production test}

Ref Voltage VREFL VSSAD VSSAD VSSAD V Not Applicable in

Low 64-pin packages
(only 32- and
48-pin packages)

Input Voltage VADIN VREFL — VREFH V

Input CADIN — 4.5 5.5 pF

Capacitance

Input RADIN — 3 5 kΩ
Resistance

Analog Source 12 bit mode RAS kΩ External to MCU

Resistance fADCK > 4MHz — — 2
fADCK < 4MHz — — 5

10 bit mode
fADCK > 4MHz — — 5
fADCK < 4MHz — — 10

8 bit mode (all valid fADCK) — — 10

ADC High Speed (ADLPC=0) fADCK 0.4 — 8.0 MHz

Conversion
Clock Freq. Low Power (ADLPC=1) 0.4 — 4.0
1
Typical values assume VDDAD = 5.0V, Temp = 25°C, fADCK=1.0MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
2 DC potential difference.

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 289
Appendix A Electrical Characteristics

SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT ZADIN
SIMPLIFIED
Pad
ZAS leakage CHANNEL SELECT
due to CIRCUIT
ADC SAR
input ENGINE
RAS RADIN
protection
+
VADIN
–
CAS
VAS +
–

RADIN

INPUT PIN
RADIN

INPUT PIN
RADIN

INPUT PIN CADIN

Figure A-1. ADC Input Impedance Equivalency Diagram

Table A-10. 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD)

Characteristic Conditions C Symb Min Typ1 Max Unit Comment

Supply Current ADLPC=1 T IDD + — 133 — μA ADC current

ADLSMP=1 IDDAD only
ADCO=1

Supply Current ADLPC=1 T IDD + — 218 — μA ADC current

ADLSMP=0 IDDAD only
ADCO=1

Supply Current ADLPC=0 T IDD + — 327 — μA ADC current

ADLSMP=1 IDDAD only
ADCO=1

Supply Current ADLPC=0 D IDD + — 0.582 1 mA ADC current

ADLSMP=0 IDDAD only
ADCO=1

Supply Current Stop, Reset, Module Off IDD + — 0.011 1 μA ADC current
IDDAD only

ADC High Speed (ADLPC=0) P fADACK 2 3.3 5 MHz tADACK =

Asynchronous 1/fADACK
Clock Source Low Power (ADLPC=1) 1.25 2 3.3

MC9S08EN32 Series Data Sheet, Rev. 2

290 Freescale Semiconductor
 Appendix A Electrical Characteristics

Table A-10. 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) (continued)

Characteristic Conditions C Symb Min Typ1 Max Unit Comment

Conversion Short Sample (ADLSMP=0) D tADC — 20 — ADCK See

Time (Including cycles Table 10-12
sample time) Long Sample (ADLSMP=1) — 40 — for conversion
time variances
Sample Time Short Sample (ADLSMP=0) D tADS — 3.5 — ADCK
cycles
Long Sample (ADLSMP=1) — 23.5 —

Total 12 bit mode T ETUE — ±3.0 ±10 LSB2 Includes

Unadjusted quantization
Error 10 bit mode P — ±1 ±2.5

8 bit mode T — ±0.5 ±1.0

Differential 12 bit mode T DNL — ±1.75 ±4.0 LSB2

Non-Linearity
10 bit mode3 P — ±0.5 ±1.0

8 bit mode3 T — ±0.3 ±0.5

Integral 12 bit mode T INL — ±1.5 ±4.0 LSB2

Non-Linearity
10 bit mode T — ±0.5 ±1.0

8 bit mode T — ±0.3 ±0.5

Zero-Scale 12 bit mode T EZS — ±1.5 ±6.0 LSB2 VADIN = VSSAD

Error
10 bit mode P — ±0.5 ±1.5

8 bit mode T — ±0.5 ±0.5

Full-Scale Error 12 bit mode T EFS — ±1 ±4.0 LSB2 VADIN = VDDAD

10 bit mode T — ±0.5 ±1

8 bit mode T — ±0.5 ±0.5

Quantization 12 bit mode D EQ — -1 to 0 -1 to 0 LSB2

Error
10 bit mode — — ±0.5

8 bit mode — — ±0.5

Input Leakage 12 bit mode D EIL — ±1 ±10.0 LSB2 Pad leakage4 *

Error RAS
10 bit mode — ±0.2 ±2.5

8 bit mode — ±0.1 ±1

Temp Sensor -40°C– 25°C D m — 3.266 — mV/°C

Slope
25°C– 125°C — 3.638 —

Temp Sensor 25°C D VTEMP25 — 1.396 — V

Voltage
1
Typical values assume VDDAD = 5.0V, Temp = 25°C, fADCK=1.0MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
2 1 LSB = (V N
REFH - VREFL)/2

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 291
Appendix A Electrical Characteristics

3
Monotonicity and No-Missing-Codes guaranteed in 10 bit and 8 bit modes
4
Based on input pad leakage current. Refer to pad electricals.

A.10 External Oscillator (XOSC) Characteristics

Table A-11. Oscillator Electrical Specifications (Temperature Range = –40 to 125°C Ambient)

Num C Rating Symbol Min Typ1 Max Unit

Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1
Low range (RANGE = 0) flo 32 — 38.4 kHz
2
C High range (RANGE = 1) FEE or FBE mode fhi-fll 1 — 5 MHz
1 3
High range (RANGE = 1) PEE or PBE mode fhi-pll 1 — 16 MHz
High range (RANGE = 1, HGO = 1) BLPE mode fhi-hgo 1 — 16 MHz
High range (RANGE = 1, HGO = 0) BLPE mode fhi-lp 1 — 8 MHz
C1 See crystal or resonator
2 — Load capacitors
C2 manufacturer’s recommendation.
Feedback resistor
3 — Low range (32 kHz to 100 kHz) RF — 10 — MΩ
High range (1 MHz to 16 MHz) — 1 — MΩ
Series resistor
Low range, low gain (RANGE = 0, HGO = 0) — 0 —
Low range, high gain (RANGE = 0, HGO = 1) — 100 —
4 — High range, low gain (RANGE = 1, HGO = 0) RS — 0 — kΩ
High range, high gain (RANGE = 1, HGO = 1) ≥ 8 MHz — 0 0
4 MHz — 0 10
1 MHz — 0 20
4
Crystal start-up time
Low range, low gain (RANGE = 0, HGO = 0) t — 200 —
CSTL-LP

T Low range, high gain (RANGE = 0, HGO = 1) t — 400 —

5 CSTL-HGO
t
High range, low gain (RANGE = 1, HGO = 0)5 CSTH-LP — 5 — ms
t
High range, high gain (RANGE = 1, HGO = 1)4 CSTH-HGO — 15 —
Square wave input clock frequency (EREFS = 0, ERCLKEN = 1)
T FEE or FBE mode 2 0.03125 — 5
6
3 fextal 1 — 16 MHz
PEE or PBE mode
BLPE mode 0 — 40
1
Typical data was characterized at 3.0 V, 25°C or is recommended value.
2 When MCG is configured for FEE or FBE mode, the input clock source must be divisible using RDIV to within the range of
31.25 kHz to 39.0625 kHz.
3
When MCG is configured for PEE or PBE mode, input clock source must be divisible using RDIV to within the range of 1 MHz
to 2 MHz.
4
This parameter is characterized and not tested on each device. Proper PC board layout procedures must be followed to
achieve specifications.
5 4 MHz crystal.

MC9S08EN32 Series Data Sheet, Rev. 2

292 Freescale Semiconductor
 Appendix A Electrical Characteristics

MCU
EXTAL XTAL

RS
RF

C1 Crystal or Resonator C2

A.11 MCG Specifications

Table A-12. MCG Frequency Specifications (Temperature Range = –40 to 125°C Ambient)

Num C Rating Symbol Min Typical Max Unit

Internal reference frequency - factory trimmed at
1 P fint_ft — 31.25 — kHz
VDD = 5 V and temperature = 25 °C
2 P Average internal reference frequency - untrimmed 1 fint_ut 25 32.7 41.66 kHz
3 P Average internal reference frequency - user trimmed fint_t 31.25 — 39.0625 kHz
4 D Internal reference startup time tirefst — 60 100 us
DCO output frequency range - untrimmed 1
5 — fdco_ut 25.6 33.48 42.66 MHz
value provided for reference: fdco_ut = 1024 X fint_ut
6 P DCO output frequency range - trimmed fdco_t 32 — 40 MHz
Resolution of trimmed DCO output frequency at fixed
7 C Δfdco_res_t — ± 0.1 ± 0.2 %fdco
voltage and temperature (using FTRIM)
Resolution of trimmed DCO output frequency at fixed
8 C Δfdco_res_t — ± 0.2 ± 0.4 %fdco
voltage and temperature (not using FTRIM)
Total deviation of trimmed DCO output frequency over + 0.5
9 P Δfdco_t — ±2 %fdco
voltage and temperature -1.0
Total deviation of trimmed DCO output frequency over
10 C Δfdco_t — ± 0.5 ±1 %fdco
fixed voltage and temperature range of 0 - 70 °C
11 C FLL acquisition time 2 tfll_acquire — — 1 ms
12 D PLL acquisition time 3 tpll_acquire — — 1 ms
Long term Jitter of DCO output clock (averaged over
13 C CJitter — 0.02 0.2 %fdco
2ms interval) 4
14 D VCO operating frequency fvco 7.0 — 55.0 MHz
15 D PLL reference frequency range fpll_ref 1.0 — 2.0 MHz
Long term accuracy of PLL output clock (averaged over
16 T
2 ms)
fpll_jitter_2ms — 0.5905 — %fpll

17 T Jitter of PLL output clock measured over 625 ns6 fpll_jitter_625ns — 0.5665 — %fpll
18 D Lock entry frequency tolerance 7 Dlock ± 1.49 — ± 2.98 %
19 D Lock exit frequency tolerance 8 Dunl ± 4.47 — ± 5.97 %

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 293
 Appendix A Electrical Characteristics

Table A-12. MCG Frequency Specifications (Temperature Range = –40 to 125°C Ambient) (continued)

Num C Rating Symbol Min Typical Max Unit

tfll_acquire+
20 D Lock time - FLL tfll_lock — — s
1075(1/fint_t)
tpll_acquire+
21 D Lock time - PLL tpll_lock — — s
1075(1/fpll_ref)
Loss of external clock minimum frequency - RANGE =
22 D 0 floc_low (3/5) x fint — — kHz

Loss of external clock minimum frequency - RANGE =

23 D 1 floc_high (16/5) x fint — — kHz

1
TRIM register at default value (0x80) and FTRIM control bit at default value (0x0).
2
This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing
from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this
specification assumes it is already running.
3
This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE,
BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already
running.
4
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBUS.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected
into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a given
interval.
5
Jitter measurements are based upon a 48 MHz MCGOUT clock frequency.
6
625 ns represents 5 time quanta for CAN applications, under worst case conditions of 8 MHz CAN bus clock, 1 Mbps CAN bus
speed, and 8 time quanta per bit for bit time settings. 5 time quanta is the minimum time between a synchronization edge and the
sample point of a bit using 8 time quanta per bit.
7
Below Dlock minimum, the MCG is guaranteed to enter lock. Above Dlock maximum, the MCG will not enter lock. But if the MCG
is already in lock, then the MCG may stay in lock.
8
Below Dunl minimum, the MCG will not exit lock if already in lock. Above Dunl maximum, the MCG is guaranteed to exit lock.

MC9S08EN32 Series Data Sheet, Rev. 2

294 Freescale Semiconductor
 Appendix A Electrical Characteristics

A.12 AC Characteristics
This section describes ac timing characteristics for each peripheral system.

A.12.1 Control Timing

Table A-13. Control Timing

Nu
C Rating Symbol Min Typical Max Unit
m

1 Bus frequency (tcyc = 1/fBus) fBus dc — 20 MHz

2 Internal low-power oscillator period tLPO 700 1300 μs

3 External reset pulse width1 textrst 1.5 x tcyc — ns

4 Reset low drive2 trstdrv 34 x tcyc — ns

5 Active background debug mode latch setup time tMSSU 25 — ns

6 Active background debug mode latch hold time tMSH 25 — ns
IRQ/PIAx/ PIBx/PIDx pulse width
7 Asynchronous path2 tILIH, tIHIL 100 — — ns
Synchronous path3 1.5 tcyc
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)3 tRise, tFall ns
Slew rate control disabled (PTxSE = 0) — 40
Slew rate control enabled (PTxSE = 1) — 75
8 T
Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)3 tRise, tFall ns
Slew rate control disabled (PTxSE = 0) — 11
Slew rate control enabled (PTxSE = 1) — 35
1 This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to
override reset requests from internal sources.
2
When any reset is initiated, internal circuitry drives the RESET pin low for about 34 cycles of tcyc. After POR reset, the bus
clock frequency changes to the untrimmed DCO frequency (freset = (fdco_ut)/4) because TRIM is reset to 0x80 and FTRIM is
reset to 0; and there is an extra divide-by-two because BDIV is reset to 0:1. After other resets, trim stays at the pre-reset value.
3 Timing is shown with respect to 20% V
DD and 80% VDD levels. Temperature range –40°C to 125°C.

textrst

RESET PIN

Figure A-2. Reset Timing

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 295
Appendix A Electrical Characteristics

BKGD/MS

RESET

tMSH

tMSSU

Figure A-3. Active Background Debug Mode Latch Timing

tIHIL

PIAx/PIBx/PIDx

IRQ/PIAx/PIBx/PIDx

tILIH

Figure A-4. Pin Interrupt Timing

A.12.2 Timer/PWM
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that
can be used as the optional external source to the timer counter. These synchronizers operate from the
current bus rate clock.
Table A-14. TPM Input Timing

Num C Rating Symbol Min Max Unit

1 — External clock frequency fTCLK dc fBus/4 MHz

2 — External clock period tTCLK 4 — tcyc

3 D External clock high time tclkh 1.5 — tcyc

4 D External clock low time tclkl 1.5 — tcyc

5 D Input capture pulse width tICPW 1.5 — tcyc

MC9S08EN32 Series Data Sheet, Rev. 2

296 Freescale Semiconductor
 Appendix A Electrical Characteristics

tTCLK
tclkh

TPMxCHn

tclkl

Figure A-5. Timer External Clock

tICPW

TPMxCHn

TPMxCHn

tICPW

Figure A-6. Timer Input Capture Pulse

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 297
Appendix A Electrical Characteristics

A.12.3 SPI
Table A-15 and Figure A-7 through Figure A-10 describe the timing requirements for the SPI system.
Table A-15. SPI Electrical Characteristic

Num1 C Rating2 Symbol Min Max Unit

Cycle time
1 D Master tSCK 2 2048 tcyc
Slave tSCK 4 — tcyc
Enable lead time
Master — 1/2 tSCK
2 D tLead
Slave 1/2 — tSCK
tLead
Enable lag time
Master — 1/2 tSCK
3 D tLag
Slave 1/2 — tSCK
tLag
Clock (SPSCK) high time
4 D
Master and Slave tSCKH (1/2 tSCK )– 25 — ns

Clock (SPSCK) low time

5 D Master and Slave tSCKL (1/2 tSCK) – 25 — ns

Data setup time (inputs)

6 D Master tSI(M) 30 — ns
Slave tSI(S) 30 — ns

Data hold time (inputs)

7 D Master tHI(M) 30 — ns
Slave tHI(S) 30 — ns

8 D Access time, slave3 tA 0 40 ns

9 D Disable time, slave4 tdis — 40 ns

Data setup time (outputs)

10 D Master tSO 25 — ns
Slave tSO 25 — ns

Data hold time (outputs)

11 D Master tHO –10 — ns
Slave tHO –10 — ns

Operating frequency5
12 D Master fop fBus/2048 5 MHz
Slave fop dc fBus/4
1
Refer to Figure A-7 through Figure A-10.
2 All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI
pins. All timing assumes slew rate control disabled and high drive strength enabled for SPI output
pins.
3
Time to data active from high-impedance state.
4 Hold time to high-impedance state.
5 Maximum baud rate must be limited to 5 MHz due to pad input characteristics.

MC9S08EN32 Series Data Sheet, Rev. 2

298 Freescale Semiconductor
 Appendix A Electrical Characteristics

SS1
(OUTPUT)

2 1 3
SCK 5
(CPOL = 0)
(OUTPUT) 4

SCK 5
(CPOL = 1)
(OUTPUT) 4

6 7

MISO
(INPUT) MSB IN2 BIT 6 . . . 1 LSB IN

10 10 11

MOSI
(OUTPUT) MSB OUT2 BIT 6 . . . 1 LSB OUT

NOTES:
1. SS output mode (MODFEN = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure A-7. SPI Master Timing (CPHA = 0)

SS(1)
(OUTPUT)

1
2 3
SCK
(CPOL = 0) 5
(OUTPUT) 4

SCK 5
(CPOL = 1)
4
(OUTPUT)
6 7
MISO
(INPUT) MSB IN(2) BIT 6 . . . 1 LSB IN

10 11
MOSI
(OUTPUT) MSB OUT(2) BIT 6 . . . 1 LSB OUT

NOTES:
1. SS output mode (MODFEN = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure A-8. SPI Master Timing (CPHA = 1)

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 299
Appendix A Electrical Characteristics

SS
(INPUT)

1 3
SCK
(CPOL = 0) 5
(INPUT) 4
2
SCK
(CPOL = 1) 5
(INPUT) 4 9
8 10 11

MISO SEE
(OUTPUT) SLAVE MSB OUT BIT 6 . . . 1 SLAVE LSB OUT NOTE

6 7

MOSI
(INPUT) MSB IN BIT 6 . . . 1 LSB IN

NOTE:
1. Not defined but normally MSB of character just received
Figure A-9. SPI Slave Timing (CPHA = 0)

SS
(INPUT)

1 3
2
SCK
(CPOL = 0) 5
(INPUT) 4

SCK 5
(CPOL = 1) 4
(INPUT)
10 11 9
MISO SEE
(OUTPUT) NOTE SLAVE MSB OUT BIT 6 . . . 1 SLAVE LSB OUT

8 6 7
MOSI
(INPUT) MSB IN BIT 6 . . . 1 LSB IN

NOTE:
1. Not defined but normally LSB of character just received
Figure A-10. SPI Slave Timing (CPHA = 1)

MC9S08EN32 Series Data Sheet, Rev. 2

300 Freescale Semiconductor
 Appendix A Electrical Characteristics

A.13 Flash
This section provides details about program/erase times and program-erase endurance for the Flash
memory.
Program and erase operations do not require any special power sources other than the normal VDD supply.
For more detailed information about program/erase operations, see Chapter 4, “Memory.”

Table A-16. Flash Characteristics

Num C Rating Symbol Min Typical Max Unit

1 — Supply voltage for program/erase Vprog/erase 2.7 5.5 V

Supply voltage for read operation

2 — 0 < fBus < 8 MHz VRead 2.7 5.5 V
0 < fBus < 20 MHz

3 — Internal FCLK frequency1 fFCLK 150 200 kHz

4 — Internal FCLK period (1/FCLK) tFcyc 5 6.67 μs

5 — Byte program time (random location)(2) tprog 9 tFcyc

6 — Byte program time (burst mode)(2) tBurst 4 tFcyc

7 — Page erase time2 tPage 4000 tFcyc

8 — Mass erase time(2) tMass 20,000 tFcyc

Flash Program/erase endurance3

9 C TL to TH = –40°C to + 125°C nFLPE — — cycles
10,000
T = 25°C 100,000 —
—

10 C Data retention4 tD_ret 15 100 — years

1
The frequency of this clock is controlled by a software setting.
2 These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for
calculating approximate time to program and erase.
3 Typical endurance for Flash is based on the intrinsic bit cell performance. For additional information on how Freescale

Semiconductor defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile
Memory.
4 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated

to 25°C using the Arrhenius equation. For additional information on how Freescale Semiconductor defines typical data
retention, please refer to Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory.

A.14 EMC Performance

Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the
MCU resides. Board design and layout, circuit topology choices, location and characteristics of external
components as well as MCU software operation all play a significant role in EMC performance. The
system designer should consult Freescale applications notes such as AN2321, AN1050, AN1263,
AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC performance.

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 301
Appendix A Electrical Characteristics

A.14.1 Radiated Emissions

Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell
method in accordance with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed
with the microcontroller installed on a custom EMC evaluation board while running specialized EMC test
software. The radiated emissions from the microcontroller are measured in a TEM cell in two package
orientations (North and East). For more detailed information concerning the evaluation results, conditions
and setup, please refer to the EMC Evaluation Report for this device.
The maximum radiated RF emissions of the tested configuration in all orientations are less than or equal
to the reported emissions levels.
Table A-17. Radiated Emissions for 3M05C Mask Set

Level1
Parameter Symbol Conditions Frequency fosc/fCPU Unit
(Max)

VRE_TEM VDD = 5 0.15 – 50 MHz 18 dBμV

TA = +25oC
50 – 150 MHz 18
Radiated emissions, 150 – 500 MHz 16 MHz 13
electric field — Conditions - Crystal
TBD 500 – 1000 MHz 20 MHz Bus 7

IEC Level L —

SAE Level 2 —

1 Data based on qualification test results.

MC9S08EN32 Series Data Sheet, Rev. 2

302 Freescale Semiconductor
Appendix B
Timer Pulse-Width Modulator (TPMV2)
NOTE

This chapter refers to S08TPM version 2, which applies to the 3M05C and
older mask sets of this device. 0M74K and newer mask set devices use
S08TPM version 3. If your device uses mask 0M74K or newer, please refer
to Chapter 14, “Timer Pulse-Width Modulator (S08TPMV3) on page 233
for information pertaining to that module.

B.1 Introduction
The TPM uses one input/output (I/O) pin per channel, TPM1CHn where x is the TPM number (for
example, 1 or 2) and n is the channel number (for example, 0–4). The TPM shares its I/O pins with
general-purpose I/O port pins (refer to the Pins and Connections chapter for more information).

B.2 Features
The TPM has the following features:
• Each TPM may be configured for buffered, center-aligned pulse-width modulation (CPWM) on all
channels
• Clock sources independently selectable per TPM (multiple TPMs device)
• Selectable clock sources (device dependent): bus clock, fixed system clock, external pin
• Clock prescaler taps for divide by 1, 2, 4, 8, 16, 32, 64, or 128
• 16-bit free-running or up/down (CPWM) count operation
• 16-bit modulus register to control counter range
• Timer system enable
• One interrupt per channel plus a terminal count interrupt for each TPM module (multiple TPMs
device)
• Channel features:
— Each channel may be input capture, output compare, or buffered edge-aligned PWM
— Rising-edge, falling-edge, or any-edge input capture trigger
— Set, clear, or toggle output compare action
— Selectable polarity on PWM outputs

B.3 Block Diagram

Figure B-1 shows the structure of a TPM. Some MCUs include more than one TPM, with various numbers
of channels.

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 303
Appendix B Timer Pulse-Width Modulator (TPMV2)

BUSCLK CLOCK SOURCE PRESCALE AND SELECT

SELECT DIVIDE BY
XCLK SYNC OFF, BUS, XCLK, EXT 1, 2, 4, 8, 16, 32, 64, or 128
TPMxCLK

CLKSB CLKSA PS2 PS1 PS0

CPWMS

MAIN 16-BIT COUNTER TOF

COUNTER RESET INTERRUPT
TOIE LOGIC
16-BIT COMPARATOR
TPM1MODH:TPM1MODL

ELS0B ELS0A
CHANNEL 0
PORT TPM1CH0
16-BIT COMPARATOR LOGIC
TPM1C0VH:TPM1C0VL CH0F
16-BIT LATCH INTERRUPT
LOGIC
MS0B MS0A CH0IE

CHANNEL 1 ELS1B ELS1A

PORT TPM1CH1
INTERNAL BUS

16-BIT COMPARATOR LOGIC

TPM1C1VH:TPM1C1VL CH1F

16-BIT LATCH INTERRUPT

LOGIC
MS1B MS1A CH1IE
...

...
...

ELSnB ELSnA
CHANNEL n TPM1CHn
PORT
16-BIT COMPARATOR LOGIC
TPM1CnVH:TPM1CnVL CHnF
16-BIT LATCH INTERRUPT
LOGIC
MSnA CHnIE
MSnB

Figure B-1. TPM Block Diagram

The central component of the TPM is the 16-bit counter that can operate as a free-running counter, a
modulo counter, or an up-/down-counter when the TPM is configured for center-aligned PWM. The TPM
counter (when operating in normal up-counting mode) provides the timing reference for the input capture,
output compare, and edge-aligned PWM functions. The timer counter modulo registers,
TPM1MODH:TPM1MODL, control the modulo value of the counter. (The values 0x0000 or 0xFFFF
effectively make the counter free running.) Software can read the counter value at any time without
affecting the counting sequence. Any write to either byte of the TPM1CNT counter resets the counter
regardless of the data value written.

MC9S08EN32 Series Data Sheet, Rev. 2

304 Freescale Semiconductor
 Appendix B Timer Pulse-Width Modulator (TPMV2)

All TPM channels are programmable independently as input capture, output compare, or buffered
edge-aligned PWM channels.

B.4 External Signal Description

When any pin associated with the timer is configured as a timer input, a passive pullup can be enabled.
After reset, the TPM modules are disabled and all pins default to general-purpose inputs with the passive
pullups disabled.

B.4.1 External TPM Clock Sources

When control bits CLKSB:CLKSA in the timer status and control register are set to 1:1, the prescaler and
consequently the 16-bit counter for TPM1 are driven by an external clock source, TPMxCLK, connected
to an I/O pin. A synchronizer is needed between the external clock and the rest of the TPM. This
synchronizer is clocked by the bus clock so the frequency of the external source must be less than one-half
the frequency of the bus rate clock. The upper frequency limit for this external clock source is specified to
be one-fourth the bus frequency to conservatively accommodate duty cycle and phase-locked loop (PLL)
or frequency-locked loop (FLL) frequency jitter effects.
On some devices the external clock input is shared with one of the TPM channels. When a TPM channel
is shared as the external clock input, the associated TPM channel cannot use the pin. (The channel can still
be used in output compare mode as a software timer.) Also, if one of the TPM channels is used as the
external clock input, the corresponding ELSnB:ELSnA control bits must be set to 0:0 so the channel is not
trying to use the same pin.

B.4.2 TPM1CHn — TPM1 Channel n I/O Pins

Each TPM channel is associated with an I/O pin on the MCU. The function of this pin depends on the
configuration of the channel. In some cases, no pin function is needed so the pin reverts to being controlled
by general-purpose I/O controls. When a timer has control of a port pin, the port data and data direction
registers do not affect the related pin(s). See the Pins and Connections chapter for additional information
about shared pin functions.

B.5 Register Definition

The TPM includes:
• An 8-bit status and control register (TPM1SC)
• A 16-bit counter (TPM1CNTH:TPM1CNTL)
• A 16-bit modulo register (TPM1MODH:TPM1MODL)
Each timer channel has:
• An 8-bit status and control register (TPM1CnSC)
• A 16-bit channel value register (TPM1CnVH:TPM1CnVL)
Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address
assignments for all TPM registers. This section refers to registers and control bits only by their names. A

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 305
Appendix B Timer Pulse-Width Modulator (TPMV2)

Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.

B.5.1 Timer Status and Control Register (TPM1SC)

TPM1SC contains the overflow status flag and control bits that are used to configure the interrupt enable,
TPM configuration, clock source, and prescale divisor. These controls relate to all channels within this
timer module.
7 6 5 4 3 2 1 0

R TOF
TOIE CPWMS CLKSB CLKSA PS2 PS1 PS0
W

Reset 0 0 0 0 0 0 0 0

= Unimplemented or Reserved

Figure B-2. Timer Status and Control Register (TPM1SC)

Table B-1. TPM1SC Register Field Descriptions

Field Description

7 Timer Overflow Flag — This flag is set when the TPM counter changes to 0x0000 after reaching the modulo
TOF value programmed in the TPM counter modulo registers. When the TPM is configured for CPWM, TOF is set
after the counter has reached the value in the modulo register, at the transition to the next lower count value.
Clear TOF by reading the TPM status and control register when TOF is set and then writing a 0 to TOF. If another
TPM overflow occurs before the clearing sequence is complete, the sequence is reset so TOF would remain set
after the clear sequence was completed for the earlier TOF. Reset clears TOF. Writing a 1 to TOF has no effect.
0 TPM counter has not reached modulo value or overflow
1 TPM counter has overflowed

6 Timer Overflow Interrupt Enable — This read/write bit enables TPM overflow interrupts. If TOIE is set, an
TOIE interrupt is generated when TOF equals 1. Reset clears TOIE.
0 TOF interrupts inhibited (use software polling)
1 TOF interrupts enabled

5 Center-Aligned PWM Select — This read/write bit selects CPWM operating mode. Reset clears this bit so the
CPWMS TPM operates in up-counting mode for input capture, output compare, and edge-aligned PWM functions. Setting
CPWMS reconfigures the TPM to operate in up-/down-counting mode for CPWM functions. Reset clears
CPWMS.
0 All TPM1 channels operate as input capture, output compare, or edge-aligned PWM mode as selected by the
MSnB:MSnA control bits in each channel’s status and control register
1 All TPM1 channels operate in center-aligned PWM mode

4:3 Clock Source Select — As shown in Table B-2, this 2-bit field is used to disable the TPM system or select one
CLKS[B:A] of three clock sources to drive the counter prescaler. The external source and the XCLK are synchronized to the
bus clock by an on-chip synchronization circuit.

2:0 Prescale Divisor Select — This 3-bit field selects one of eight divisors for the TPM clock input as shown in
PS[2:0] Table B-3. This prescaler is located after any clock source synchronization or clock source selection, so it affects
whatever clock source is selected to drive the TPM system.

MC9S08EN32 Series Data Sheet, Rev. 2

306 Freescale Semiconductor
 Appendix B Timer Pulse-Width Modulator (TPMV2)

Table B-2. TPM Clock Source Selection

CLKSB:CLKSA TPM Clock Source to Prescaler Input

0:0 No clock selected (TPM1 disabled)

0:1 Bus rate clock (BUSCLK)

1:0 Fixed system clock (XCLK)

1:1 External source (TPM1CLK)1,2

1
The maximum frequency that is allowed as an external clock is one-fourth of the bus
frequency.
2
If the external clock input is shared with channel n and is selected as the TPM clock source,
the corresponding ELSnB:ELSnA control bits should be set to 0:0 so channel n does not try
to use the same pin for a conflicting function.

Table B-3. Prescale Divisor Selection

PS2:PS1:PS0 TPM Clock Source Divided-By

0:0:0 1

0:0:1 2

0:1:0 4

0:1:1 8

1:0:0 16

1:0:1 32

1:1:0 64

1:1:1 128

B.5.2 Timer Counter Registers (TPM1CNTH:TPM1CNTL)

The two read-only TPM counter registers contain the high and low bytes of the value in the TPM counter.
Reading either byte (TPM1CNTH or TPM1CNTL) latches the contents of both bytes into a buffer where
they remain latched until the other byte is read. This allows coherent 16-bit reads in either order. The
coherency mechanism is automatically restarted by an MCU reset, a write of any value to TPM1CNTH or
TPM1CNTL, or any write to the timer status/control register (TPM1SC).
Reset clears the TPM counter registers.
7 6 5 4 3 2 1 0

R Bit 15 14 13 12 11 10 9 Bit 8

W Any write to TPM1CNTH clears the 16-bit counter.

Reset 0 0 0 0 0 0 0 0

Figure B-3. Timer Counter Register High (TPM1CNTH)

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 307
Appendix B Timer Pulse-Width Modulator (TPMV2)

7 6 5 4 3 2 1 0

R Bit 7 6 5 4 3 2 1 Bit 0

W Any write to TPM1CNTL clears the 16-bit counter.

Reset 0 0 0 0 0 0 0 0

Figure B-4. Timer Counter Register Low (TPM1CNTL)

When background mode is active, the timer counter and the coherency mechanism are frozen such that the
buffer latches remain in the state they were in when the background mode became active even if one or
both bytes of the counter are read while background mode is active.

B.5.3 Timer Counter Modulo Registers (TPM1MODH:TPM1MODL)

The read/write TPM modulo registers contain the modulo value for the TPM counter. After the TPM
counter reaches the modulo value, the TPM counter resumes counting from 0x0000 at the next clock
(CPWMS = 0) or starts counting down (CPWMS = 1), and the overflow flag (TOF) becomes set. Writing
to TPM1MODH or TPM1MODL inhibits TOF and overflow interrupts until the other byte is written. Reset
sets the TPM counter modulo registers to 0x0000, which results in a free-running timer counter (modulo
disabled).
7 6 5 4 3 2 1 0

R
Bit 15 14 13 12 11 10 9 Bit 8
W

Reset 0 0 0 0 0 0 0 0

Figure B-5. Timer Counter Modulo Register High (TPM1MODH)

7 6 5 4 3 2 1 0

R
Bit 7 6 5 4 3 2 1 Bit 0
W

Reset 0 0 0 0 0 0 0 0

Figure B-6. Timer Counter Modulo Register Low (TPM1MODL)

It is good practice to wait for an overflow interrupt so both bytes of the modulo register can be written well
before a new overflow. An alternative approach is to reset the TPM counter before writing to the TPM
modulo registers to avoid confusion about when the first counter overflow will occur.

MC9S08EN32 Series Data Sheet, Rev. 2

308 Freescale Semiconductor
 Appendix B Timer Pulse-Width Modulator (TPMV2)

B.5.4 Timer Channel n Status and Control Register (TPM1CnSC)

TPM1CnSC contains the channel interrupt status flag and control bits that are used to configure the
interrupt enable, channel configuration, and pin function.
7 6 5 4 3 2 1 0

R 0 0
CHnF CHnIE MSnB MSnA ELSnB ELSnA
W

Reset 0 0 0 0 0 0 0 0

= Unimplemented or Reserved

Figure B-7. Timer Channel n Status and Control Register (TPM1CnSC)

Table B-4. TPM1CnSC Register Field Descriptions

Field Description

7 Channel n Flag — When channel n is configured for input capture, this flag bit is set when an active edge occurs
CHnF on the channel n pin. When channel n is an output compare or edge-aligned PWM channel, CHnF is set when
the value in the TPM counter registers matches the value in the TPM channel n value registers. This flag is
seldom used with center-aligned PWMs because it is set every time the counter matches the channel value
register, which correspond to both edges of the active duty cycle period.
A corresponding interrupt is requested when CHnF is set and interrupts are enabled (CHnIE = 1). Clear CHnF
by reading TPM1CnSC while CHnF is set and then writing a 0 to CHnF. If another interrupt request occurs before
the clearing sequence is complete, the sequence is reset so CHnF would remain set after the clear sequence
was completed for the earlier CHnF. This is done so a CHnF interrupt request cannot be lost by clearing a
previous CHnF. Reset clears CHnF. Writing a 1 to CHnF has no effect.
0 No input capture or output compare event occurred on channel n
1 Input capture or output compare event occurred on channel n
6 Channel n Interrupt Enable — This read/write bit enables interrupts from channel n. Reset clears CHnIE.
CHnIE 0 Channel n interrupt requests disabled (use software polling)
1 Channel n interrupt requests enabled

5 Mode Select B for TPM Channel n — When CPWMS = 0, MSnB = 1 configures TPM channel n for
MSnB edge-aligned PWM mode. For a summary of channel mode and setup controls, refer to Table B-5.

4 Mode Select A for TPM Channel n — When CPWMS = 0 and MSnB = 0, MSnA configures TPM channel n for
MSnA input capture mode or output compare mode. Refer to Table B-5 for a summary of channel mode and setup
controls.

3:2 Edge/Level Select Bits — Depending on the operating mode for the timer channel as set by
ELSn[B:A] CPWMS:MSnB:MSnA and shown in Table B-5, these bits select the polarity of the input edge that triggers an
input capture event, select the level that will be driven in response to an output compare match, or select the
polarity of the PWM output.
Setting ELSnB:ELSnA to 0:0 configures the related timer pin as a general-purpose I/O pin unrelated to any timer
channel functions. This function is typically used to temporarily disable an input capture channel or to make the
timer pin available as a general-purpose I/O pin when the associated timer channel is set up as a software timer
that does not require the use of a pin.

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 309
Appendix B Timer Pulse-Width Modulator (TPMV2)

Table B-5. Mode, Edge, and Level Selection

CPWMS MSnB:MSnA ELSnB:ELSnA Mode Configuration

X XX 00 Pin not used for TPM channel; use as an external clock for the TPM or
revert to general-purpose I/O

0 00 01 Input capture Capture on rising edge only

10 Capture on falling edge only

11 Capture on rising or falling edge

01 00 Output Software compare only

compare
01 Toggle output on compare

10 Clear output on compare

11 Set output on compare

1X 10 Edge-aligned High-true pulses (clear output on compare)

PWM
X1 Low-true pulses (set output on compare)

1 XX 10 Center-aligned High-true pulses (clear output on compare-up)

PWM
X1 Low-true pulses (set output on compare-up)

If the associated port pin is not stable for at least two bus clock cycles before changing to input capture
mode, it is possible to get an unexpected indication of an edge trigger. Typically, a program would clear
status flags after changing channel configuration bits and before enabling channel interrupts or using the
status flags to avoid any unexpected behavior.
B.5.5 Timer Channel Value Registers (TPM1CnVH:TPM1CnVL)
These read/write registers contain the captured TPM counter value of the input capture function or the
output compare value for the output compare or PWM functions. The channel value registers are cleared
by reset.
7 6 5 4 3 2 1 0

R
Bit 15 14 13 12 11 10 9 Bit 8
W

Reset 0 0 0 0 0 0 0 0

Figure B-8. Timer Channel Value Register High (TPM1CnVH)

7 6 5 4 3 2 1 0

R
Bit 7 6 5 4 3 2 1 Bit 0
W

Reset 0 0 0 0 0 0 0 0

Figure B-9. Timer Channel Value Register Low (TPM1CnVL)

MC9S08EN32 Series Data Sheet, Rev. 2

310 Freescale Semiconductor
 Appendix B Timer Pulse-Width Modulator (TPMV2)

In input capture mode, reading either byte (TPM1CnVH or TPM1CnVL) latches the contents of both bytes
into a buffer where they remain latched until the other byte is read. This latching mechanism also resets
(becomes unlatched) when the TPM1CnSC register is written.
In output compare or PWM modes, writing to either byte (TPM1CnVH or TPM1CnVL) latches the value
into a buffer. When both bytes have been written, they are transferred as a coherent 16-bit value into the
timer channel value registers. This latching mechanism may be manually reset by writing to the
TPM1CnSC register.
This latching mechanism allows coherent 16-bit writes in either order, which is friendly to various
compiler implementations.

B.6 Functional Description

All TPM functions are associated with a main 16-bit counter that allows flexible selection of the clock
source and prescale divisor. A 16-bit modulo register also is associated with the main 16-bit counter in the
TPM. Each TPM channel is optionally associated with an MCU pin and a maskable interrupt function.
The TPM has center-aligned PWM capabilities controlled by the CPWMS control bit in TPM1SC. When
CPWMS is set to 1, timer counter TPM1CNT changes to an up-/down-counter and all channels in the
associated TPM act as center-aligned PWM channels. When CPWMS = 0, each channel can
independently be configured to operate in input capture, output compare, or buffered edge-aligned PWM
mode.
The following sections describe the main 16-bit counter and each of the timer operating modes (input
capture, output compare, edge-aligned PWM, and center-aligned PWM). Because details of pin operation
and interrupt activity depend on the operating mode, these topics are covered in the associated mode
sections.

B.6.1 Counter
All timer functions are based on the main 16-bit counter (TPM1CNTH:TPM1CNTL). This section
discusses selection of the clock source, up-counting vs. up-/down-counting, end-of-count overflow, and
manual counter reset.
After any MCU reset, CLKSB:CLKSA = 0:0 so no clock source is selected and the TPM is inactive.
Normally, CLKSB:CLKSA would be set to 0:1 so the bus clock drives the timer counter. The clock source
for the TPM can be selected to be off, the bus clock (BUSCLK), the fixed system clock (XCLK), or an
external input. The maximum frequency allowed for the external clock option is one-fourth the bus rate.
Refer to Section B.5.1, “Timer Status and Control Register (TPM1SC)” and Table B-2 for more
information about clock source selection.
When the microcontroller is in active background mode, the TPM temporarily suspends all counting until
the microcontroller returns to normal user operating mode. During stop mode, all TPM clocks are stopped;
therefore, the TPM is effectively disabled until clocks resume. During wait mode, the TPM continues to
operate normally.
The main 16-bit counter has two counting modes. When center-aligned PWM is selected (CPWMS = 1),
the counter operates in up-/down-counting mode. Otherwise, the counter operates as a simple up-counter.

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 311
Appendix B Timer Pulse-Width Modulator (TPMV2)

As an up-counter, the main 16-bit counter counts from 0x0000 through its terminal count and then
continues with 0x0000. The terminal count is 0xFFFF or a modulus value in TPM1MODH:TPM1MODL.
When center-aligned PWM operation is specified, the counter counts upward from 0x0000 through its
terminal count and then counts downward to 0x0000 where it returns to up-counting. Both 0x0000 and the
terminal count value (value in TPM1MODH:TPM1MODL) are normal length counts (one timer clock
period long).
An interrupt flag and enable are associated with the main 16-bit counter. The timer overflow flag (TOF) is
a software-accessible indication that the timer counter has overflowed. The enable signal selects between
software polling (TOIE = 0) where no hardware interrupt is generated, or interrupt-driven operation
(TOIE = 1) where a static hardware interrupt is automatically generated whenever the TOF flag is 1.
The conditions that cause TOF to become set depend on the counting mode (up or up/down). In
up-counting mode, the main 16-bit counter counts from 0x0000 through 0xFFFF and overflows to 0x0000
on the next counting clock. TOF becomes set at the transition from 0xFFFF to 0x0000. When a modulus
limit is set, TOF becomes set at the transition from the value set in the modulus register to 0x0000. When
the main 16-bit counter is operating in up-/down-counting mode, the TOF flag gets set as the counter
changes direction at the transition from the value set in the modulus register and the next lower count value.
This corresponds to the end of a PWM period. (The 0x0000 count value corresponds to the center of a
period.)
Because the HCS08 MCU is an 8-bit architecture, a coherency mechanism is built into the timer counter
for read operations. Whenever either byte of the counter is read (TPM1CNTH or TPM1CNTL), both bytes
are captured into a buffer so when the other byte is read, the value will represent the other byte of the count
at the time the first byte was read. The counter continues to count normally, but no new value can be read
from either byte until both bytes of the old count have been read.
The main timer counter can be reset manually at any time by writing any value to either byte of the timer
count TPM1CNTH or TPM1CNTL. Resetting the counter in this manner also resets the coherency
mechanism in case only one byte of the counter was read before resetting the count.

B.6.2 Channel Mode Selection

Provided CPWMS = 0 (center-aligned PWM operation is not specified), the MSnB and MSnA control bits
in the channel n status and control registers determine the basic mode of operation for the corresponding
channel. Choices include input capture, output compare, and buffered edge-aligned PWM.

B.6.2.1 Input Capture Mode

With the input capture function, the TPM can capture the time at which an external event occurs. When an
active edge occurs on the pin of an input capture channel, the TPM latches the contents of the TPM counter
into the channel value registers (TPM1CnVH:TPM1CnVL). Rising edges, falling edges, or any edge may
be chosen as the active edge that triggers an input capture.
When either byte of the 16-bit capture register is read, both bytes are latched into a buffer to support
coherent 16-bit accesses regardless of order. The coherency sequence can be manually reset by writing to
the channel status/control register (TPM1CnSC).

MC9S08EN32 Series Data Sheet, Rev. 2

312 Freescale Semiconductor
 Appendix B Timer Pulse-Width Modulator (TPMV2)

An input capture event sets a flag bit (CHnF) that can optionally generate a CPU interrupt request.

B.6.2.2 Output Compare Mode

With the output compare function, the TPM can generate timed pulses with programmable position,
polarity, duration, and frequency. When the counter reaches the value in the channel value registers of an
output compare channel, the TPM can set, clear, or toggle the channel pin.
In output compare mode, values are transferred to the corresponding timer channel value registers only
after both 8-bit bytes of a 16-bit register have been written. This coherency sequence can be manually reset
by writing to the channel status/control register (TPM1CnSC).
An output compare event sets a flag bit (CHnF) that can optionally generate a CPU interrupt request.

B.6.2.3 Edge-Aligned PWM Mode

This type of PWM output uses the normal up-counting mode of the timer counter (CPWMS = 0) and can
be used when other channels in the same TPM are configured for input capture or output compare
functions. The period of this PWM signal is determined by the setting in the modulus register
(TPM1MODH:TPM1MODL). The duty cycle is determined by the setting in the timer channel value
register (TPM1CnVH:TPM1CnVL). The polarity of this PWM signal is determined by the setting in the
ELSnA control bit. Duty cycle cases of 0 percent and 100 percent are possible.
As Figure B-10 shows, the output compare value in the TPM channel registers determines the pulse width
(duty cycle) of the PWM signal. The time between the modulus overflow and the output compare is the
pulse width. If ELSnA = 0, the counter overflow forces the PWM signal high and the output compare
forces the PWM signal low. If ELSnA = 1, the counter overflow forces the PWM signal low and the output
compare forces the PWM signal high.

OVERFLOW OVERFLOW OVERFLOW

PERIOD
PULSE
WIDTH

TPM1C

OUTPUT OUTPUT OUTPUT

COMPARE COMPARE COMPARE

Figure B-10. PWM Period and Pulse Width (ELSnA = 0)

When the channel value register is set to 0x0000, the duty cycle is 0 percent. By setting the timer channel
value register (TPM1CnVH:TPM1CnVL) to a value greater than the modulus setting, 100% duty cycle
can be achieved. This implies that the modulus setting must be less than 0xFFFF to get 100% duty cycle.
Because the HCS08 is a family of 8-bit MCUs, the settings in the timer channel registers are buffered to
ensure coherent 16-bit updates and to avoid unexpected PWM pulse widths. Writes to either register,
TPM1CnVH or TPM1CnVL, write to buffer registers. In edge-PWM mode, values are transferred to the
corresponding timer channel registers only after both 8-bit bytes of a 16-bit register have been written and

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 313
Appendix B Timer Pulse-Width Modulator (TPMV2)

the value in the TPM1CNTH:TPM1CNTL counter is 0x0000. (The new duty cycle does not take effect
until the next full period.)

B.6.3 Center-Aligned PWM Mode

This type of PWM output uses the up-/down-counting mode of the timer counter (CPWMS = 1). The
output compare value in TPM1CnVH:TPM1CnVL determines the pulse width (duty cycle) of the PWM
signal and the period is determined by the value in TPM1MODH:TPM1MODL.
TPM1MODH:TPM1MODL should be kept in the range of 0x0001 to 0x7FFF because values outside this
range can produce ambiguous results. ELSnA will determine the polarity of the CPWM output.

pulse width = 2 x (TPM1CnVH:TPM1CnVL) Eqn. 15-1

period = 2 x (TPM1MODH:TPM1MODL);
for TPM1MODH:TPM1MODL = 0x0001–0x7FFF Eqn. 15-2

If the channel value register TPM1CnVH:TPM1CnVL is zero or negative (bit 15 set), the duty cycle will
be 0%. If TPM1CnVH:TPM1CnVL is a positive value (bit 15 clear) and is greater than the (nonzero)
modulus setting, the duty cycle will be 100% because the duty cycle compare will never occur. This
implies the usable range of periods set by the modulus register is 0x0001 through 0x7FFE (0x7FFF if
generation of 100% duty cycle is not necessary). This is not a significant limitation because the resulting
period is much longer than required for normal applications.
TPM1MODH:TPM1MODL = 0x0000 is a special case that should not be used with center-aligned PWM
mode. When CPWMS = 0, this case corresponds to the counter running free from 0x0000 through
0xFFFF, but when CPWMS = 1 the counter needs a valid match to the modulus register somewhere other
than at 0x0000 in order to change directions from up-counting to down-counting.
Figure B-11 shows the output compare value in the TPM channel registers (multiplied by 2), which
determines the pulse width (duty cycle) of the CPWM signal. If ELSnA = 0, the compare match while
counting up forces the CPWM output signal low and a compare match while counting down forces the
output high. The counter counts up until it reaches the modulo setting in TPM1MODH:TPM1MODL, then
counts down until it reaches zero. This sets the period equal to two times TPM1MODH:TPM1MODL.
COUNT = 0
OUTPUT OUTPUT
COUNT = COMPARE COMPARE COUNT =
TPM1MODH:TPM (COUNT DOWN) (COUNT UP) TPM1MODH:TPM

TPM1C
PULSE WIDTH
2x
PERIOD
2x
Figure B-11. CPWM Period and Pulse Width (ELSnA = 0)

Center-aligned PWM outputs typically produce less noise than edge-aligned PWMs because fewer I/O pin
transitions are lined up at the same system clock edge. This type of PWM is also required for some types
of motor drives.

MC9S08EN32 Series Data Sheet, Rev. 2

314 Freescale Semiconductor
 Appendix B Timer Pulse-Width Modulator (TPMV2)

Because the HCS08 is a family of 8-bit MCUs, the settings in the timer channel registers are buffered to
ensure coherent 16-bit updates and to avoid unexpected PWM pulse widths. Writes to any of the registers,
TPM1MODH, TPM1MODL, TPM1CnVH, and TPM1CnVL, actually write to buffer registers. Values are
transferred to the corresponding timer channel registers only after both 8-bit bytes of a 16-bit register have
been written and the timer counter overflows (reverses direction from up-counting to down-counting at the
end of the terminal count in the modulus register). This TPM1CNT overflow requirement only applies to
PWM channels, not output compares.
Optionally, when TPM1CNTH:TPM1CNTL = TPM1MODH:TPM1MODL, the TPM can generate a TOF
interrupt at the end of this count. The user can choose to reload any number of the PWM buffers, and they
will all update simultaneously at the start of a new period.
Writing to TPM1SC cancels any values written to TPM1MODH and/or TPM1MODL and resets the
coherency mechanism for the modulo registers. Writing to TPM1CnSC cancels any values written to the
channel value registers and resets the coherency mechanism for TPM1CnVH:TPM1CnVL.

B.7 TPM Interrupts

The TPM generates an optional interrupt for the main counter overflow and an interrupt for each channel.
The meaning of channel interrupts depends on the mode of operation for each channel. If the channel is
configured for input capture, the interrupt flag is set each time the selected input capture edge is
recognized. If the channel is configured for output compare or PWM modes, the interrupt flag is set each
time the main timer counter matches the value in the 16-bit channel value register. See the Resets,
Interrupts, and System Configuration chapter for absolute interrupt vector addresses, priority, and local
interrupt mask control bits.
For each interrupt source in the TPM, a flag bit is set on recognition of the interrupt condition such as timer
overflow, channel input capture, or output compare events. This flag may be read (polled) by software to
verify that the action has occurred, or an associated enable bit (TOIE or CHnIE) can be set to enable
hardware interrupt generation. While the interrupt enable bit is set, a static interrupt will be generated
whenever the associated interrupt flag equals 1. It is the responsibility of user software to perform a
sequence of steps to clear the interrupt flag before returning from the interrupt service routine.

B.7.1 Clearing Timer Interrupt Flags

TPM interrupt flags are cleared by a 2-step process that includes a read of the flag bit while it is set (1)
followed by a write of 0 to the bit. If a new event is detected between these two steps, the sequence is reset
and the interrupt flag remains set after the second step to avoid the possibility of missing the new event.

B.7.2 Timer Overflow Interrupt Description

The conditions that cause TOF to become set depend on the counting mode (up or up/down). In
up-counting mode, the 16-bit timer counter counts from 0x0000 through 0xFFFF and overflows to 0x0000
on the next counting clock. TOF becomes set at the transition from 0xFFFF to 0x0000. When a modulus
limit is set, TOF becomes set at the transition from the value set in the modulus register to 0x0000. When
the counter is operating in up-/down-counting mode, the TOF flag gets set as the counter changes direction

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 315
Appendix B Timer Pulse-Width Modulator (TPMV2)

at the transition from the value set in the modulus register and the next lower count value. This corresponds
to the end of a PWM period. (The 0x0000 count value corresponds to the center of a period.)

B.7.3 Channel Event Interrupt Description

The meaning of channel interrupts depends on the current mode of the channel (input capture, output
compare, edge-aligned PWM, or center-aligned PWM).
When a channel is configured as an input capture channel, the ELSnB:ELSnA control bits select rising
edges, falling edges, any edge, or no edge (off) as the edge that triggers an input capture event. When the
selected edge is detected, the interrupt flag is set. The flag is cleared by the 2-step sequence described in
Section B.7.1, “Clearing Timer Interrupt Flags.”
When a channel is configured as an output compare channel, the interrupt flag is set each time the main
timer counter matches the 16-bit value in the channel value register. The flag is cleared by the 2-step
sequence described in Section B.7.1, “Clearing Timer Interrupt Flags.”

B.7.4 PWM End-of-Duty-Cycle Events

For channels that are configured for PWM operation, there are two possibilities:
• When the channel is configured for edge-aligned PWM, the channel flag is set when the timer
counter matches the channel value register that marks the end of the active duty cycle period.
• When the channel is configured for center-aligned PWM, the timer count matches the channel
value register twice during each PWM cycle. In this CPWM case, the channel flag is set at the start
and at the end of the active duty cycle, which are the times when the timer counter matches the
channel value register.
The flag is cleared by the 2-step sequence described in Section B.7.1, “Clearing Timer Interrupt Flags.”

MC9S08EN32 Series Data Sheet, Rev. 2

316 Freescale Semiconductor
Appendix C
Ordering Information and Mechanical Drawings
C.1 Ordering Information
This section contains ordering information for MC9S08EN32 Series devices.
Example of the device numbering system:

MC 9 S08 EN 32 M XX

Status
(MC = Fully Qualified) Package designator (see Table C-2)
(S = Auto Qualified)
Memory Temperature range
(9 = Flash-based) (C = –40°C to 85°C)
(V = –40°C to 105°C)
Core
(M = –40°C to 125°C)
Family Approximate Flash size in KB

C.1.1 MC9S08EN32 Series Devices

Table C-1. Devices in the MC9S08EN32 Series

Memory
Device Number Available Packages1
Flash RAM
MC9S08EN32 33,792 1024 48-LQFP, 32-LQFP
MC9S08EN16 16,896 512 48-LQFP, 32-LQFP
1
See Table C-2 for package information.

C.2 Mechanical Drawings

The following pages are mechanical drawings for the packages described in the following table:

Table C-2. Package Descriptions

Pin Count Type Abbreviation Designator Document No.

48 Low Quad Flat Package LQFP LF 98ASH00962A
32 Low Quad Flat Package LQFP LC 98ASH70029A

MC9S08EN32 Series Data Sheet, Rev. 2

Freescale Semiconductor 317
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