MICRO AND NANO ELECTRONIC DESIGN

MIDTERM EXAM
DEPARTAMENT D'ENGINYERIA ELECTRÒNICA FALL 2019-20, November 13, 2019
FACULTY: Jordi Cosp, Jordi Madrenas, Francesc Moll

Time: 1 hour 15 min. SOLVED VERSION

No mobile phones, calculator or any other electronic device are allowed.

Question 1 (10%). The table shows four technology nodes of a cutting-edge CMOS process.
a) Briefly comment whether the prediction follows Moore’s Law.
b) Calculate approximately the cost for each technology as C = Area-Power-Delay product. Notice that the
delay is the performance inverse.
c) Compare these values and discuss whether it is worth continuing transistor size scaling or not.

a) It follows quite well Moore’s Law, reducing the 0.7 linear scale factor every 2 years, for all cases,
except for the transition from 5 nm to 3 nm, when it is even faster (0.6x factor), as the 2022 node should
be 3.5 nm.

b) Assuming Delay ≈ 1 for all nodes, and area = A7, power = P7 for 7 nm,
2018: C7 = A·D·P = A7·1·P7 = A7P7
2020: C5 = 0.72·0.8·C7 ≈ 0.4 C7
2022: C3 = 0.62·0.85·C5 = 0.1224A7P7 ≈ 0.12C7
2024: C2.1 = 0.72·0.85· C3 ≈ 0.05C7

c) The cost values are progressively reduced mainly due to the area reduction, because performance is
constant while power dissipation slightly decreases, but not remarkably. Thus, provided the fab set up
costs can be recovered, it is worth to continue scaling because of chip cost reduction, despite performance
is not improved.

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Question 2 (15%).
a) Design a XNOR logic function with LEAP (LEAn integration with Pass transistors) logic. How many
transistors are needed?
b) Comment the role of the PMOS feedback transistor and a drawback of this logic.
c) Is this a ratioed logic? Explain why.

a) Truth table: Since the LEAP scheme contains an inverter, the XOR operation is computed by the pass
transistors to obtain the pursued XNOR function.

A B XOR XNOR
0 0 0 1
0 1 1 0
1 0 1 0
1 1 0 1

b)The keeper transistor (PMOS) restores the high voltage at the intermediate node. This produces extra
current consumption at the transitions.
c) Yes, because the keeper has to be sized weak in order to allow transition of the internal node from high
to low.
d) 9 transistors (5 plus A and B inverters).

Question 3 (10%). In some CMOS technologies, for the same channel size, the PMOS conductivity is 3
times smaller than NMOS. Taking into account the conductivity factor:
a) Design the compound gate with Y = not(A·(B+C)) logic function and size it.
b) Calculate the logical effort for all inputs.

a) Circuit diagram. In this case, the PMOS/NMOS conduction ratio is 3.

5 8
b) gA= gB =gC = =2
4 4

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Question 4 (20%).
a) Design a dynamic falling-edge D Flip-flop using tristate inverters.
b) Design a static multiplexer based on compound gate plus inverters.
c) Combine the multiplexer and the D-flip-flop to create a T flip-flop.
d) Calculate the number of transistors needed.

a) Falling-edge dynamic D flip-flop:

b) Two-input MUX (inverting)

c) Dynamic T flip-flop

d) #transistors = 8 (DFF) + 10 (MUX) + 2 (INV) = 20

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Question 5 (20%). Design the logic function Y = not(A·(B + C)·D) using a static CMOS compound gate.
a) Draw the transistor-level schematic trying to minimize the number of parasitic capacitances.
b) Search an Euler path and draw the stick diagram.
c) Size the transistors for equal rising and falling edges. Obtain all the parasitic capacitances, assuming
shared diffusion capacitances for serially-connected devices. Assume the output Y is connected to 3 unit
inverters.
d) Calculate the propagation and contamination delays.

a) Schematic b) Euler path: ADBC Stick diagram

c) Sizing and parasitic capacitances

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d) Propagation and contamination times

tpdr: A = D = 1; B = C = 0 tpdf: A = B = D = 1; C = 0

R R 2R
t pdr = 4 C + R·32 C=34 RC t pdf = 9 C+ 3 C+ R (20+4 )C=29 RC
2 3 3

tcdr: A = B = C = D = 0 tcdf: A = B = C = D = 1

R 20 2R R 5 50
t cdr= 20 C= RC t cdf =( + )20 C= 20 RC = RC
3 3 3 6 6 3

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Question 6 (10%). DVS (Dynamic Voltage Scaling) is a power-saving technique that dynamically adjusts
the clock frequency and power supply voltage to the computing requirement of a given moment.
a) Assuming that the dynamic power dissipation is 10 W when operating at fCKmax and VDDmax, what will be
the power dissipation in low-computation requirement periods when f CK is reduced to fCKmax/10 and VDD =
VDDmax/2?
b) What will be the average power dissipation assuming that only 10% of the time the circuit operates at
full computing power?

a) PMAX = αCLfCKmaxVDDmax2 = 10 W
PLOW = αCL(fCKmax/10)(VDDmax/2)2 = αCLfCKmaxVDDmax2/40 = 10/40 W = 250 mW

b) PAV = 0.1·10 + 0.9·0.25 W = 1.225 W

Question 7 (15%)
a) Find the set of test vectors {[A, B, C, D]} that detect the S-a-1 (Stuck-at-one) fault of node X.
b) What will be the value of Y in the correct circuit and in the faulty circuit?

a) We need to generate 0 at node X to detect the difference with stuck-at-1 fault. Thus, A = B = 1.
It is also necessary to propagate X to the output, so the output of the lower NOR has to be 0. Thus,
either C = 1 or D = 1.

The set of vectors is: {[1, 1, X, 1], [1, 1, 1, X]} ≡ {[1, 1, 0, 1], [1, 1, 1, 1], [1, 1, 1, 0]}

b) Applying one of the previous vectors, in the faulty circuit Y = 0 and in the correct circuit, Y = 1, so
the fault can be detected.

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