8086 Instruction Set and Assembly Language Programming 3.1 Introduction The 8086 instruction set includes equivalents of the 8085 instructions plus many new ones. The new instructions contain operations such as signed /unsigned multiplication and division, bit manipulation instructions, string instructions, and interrupt instructions. ‘The 8086 has approximately 117 different instructions with about 300 opcodes. The 8086 instruction set contains no operand, single operand, and two operand instructions. Except for string instructions which involve array operations, the 8086 instructions do not permit memory to memory operations. In this chapter we study the addressing modes, instruction set of 8086 and assembler directives. 3.2 Addressing Modes We have seen how the 8086 fetches code bytes from memory by generating 20-bit physical address with the help of IP and CS. We have also seen how the 8086 accesses the stack using SS and SP. In this section we will see the different ways that an 8086 can ‘access the data. The different ways that a processor can access data are referred to as addressing modes. ‘The addressing modes of any processor can be broadly classified as : © Data addressing modes. © Program memory addressing modes. © Stack memory addressing modes. 3.2.1 Data Addressing Modes The data addressing modes can be further classified as 1. Addressing modes for accessing immediate and register data (register and immediate modes) 2. Addressing modes for accessing data in memory (memory modes). 3. Addressing mades for accessing [/O ports (I/O modes). @-1)Microprocessors and Interfacing 3-2 8086 Instruction Set and ALP Addressing Modes for Accessing Immediate and Register Data 1. Register Addressing Made This mode specifies the source operand, destination operand, or both to be contained in an 8086 register. Direcion of deta ow wv ace [x | Destin egbtir Source pater Note : Both source and destination operands are in 8086 register Examples : MOV BX, CX ‘Copies the 16-bit contents of CX into BX MOV CL, BL ; Copies &-bit contents of BL into CL. 2. Immediate Addressing Mode In an immediate mode, 8 or 16-bit data can be specified as a part of instruction 7 ° MOW AL. 20H aL |-————20H Destination operand Immediate data 5 2 8086 register asa source operand 15 ° MOV AX, 1234H aK Jie 4 Destination operand Immediate data is 2 8086 register asa source operand Note : Arrow indicates direction of data flow Examples MOV BL, 26H ; Copies the 8-bit data 26H into BL MOV CX, 4567H ; Copies the 16-bit data 4567H into CX.Microprocessors and Interfacing 3-3 8086 Instruction Set and ALP Addressing Modes for Accessing Data in Memory As mentioned before, the Execution Unit (EU) has direct access to all registers and data for register and immediate operands. However, the EU cannot directly access the memory operands. It must use the BIU segment registers to access memory operands. For example, when the EU needs to access a memory location, it sends an offset value to the BIU. This offset is also called the Effective Address (EA). Note that EA is displacement of the desired location from the segment base. As mentioned before, the BIU generates a 20-bit physical address after shifting the contents of the desired segment register four bits to the left and then adding the 16-bit EA to it. There are six ways to specify effective address (EA) in the instruction. a, Direct addressing mode b. Register indirect addressing mode c. Based addressing mode d. Indexed addressing mode ¢. Based indexed addressing mode £. String addressing mode. 1. Direct Addressing Mode : In this mode, the 16-bit effective address (EA) is taken directly from the displacement field of the instruction. The displacement (unsigned 16-bit or sign-extended 8-bit number) is stored in the location following the instruction opcode. Memory AL SOW | s3001H MOV AL, [30004] 6oH GOH | 13000 =— +10000++3000H os[ 10 “Toston (MOV (3000H), CX Note ; 1, Assume DS = 1000 Physical address. = DS «(10H}+ 3000H = 1000(0)+ 3000H = 13000H (2. Arrow indicates direction of data flow.Microprocessors and Interfacing Example : MOV CL, [9823H] _; This instruction will copy the contents of the ; memory location, at a displacement af 9823H from the ; data segment base, into the CL register. Here, 9823H is } the effective address (EA) which is written ; directly in the instruction. 8086 Instruction Set and ALP 2. Register Indirect Addressing Mode In this mode, the EA is specified in either a pointer register or an index register. The pointer register can be either base register BX or base pointer register BP and index register can be either Source Index (SI) register or Destination Index (DI) register. The 20-bit physical address is computed using DS and EA. Memory a 20__|120001H wovexcx [20 | 90 | {_2_| #20001 oH BL tFFFH Bx —— Example : 1, MOV [DI], BX _; The instruction copies the 16-bit contents of BX into a ; memory location offset by the value of EA specified in DI 3 from the current contents in DS. Now, if [DS] = 7205H, ; [D1] = 0030H, and [BX] = 8765H, then after MOV [Di], BX, : content of BX (8765H) is copied to memory locations 3 P2080H and 72081H.Microprocessors and Interfacing 3-5 8086 Instruction Set and ALP 2.MOV DL, [BP] _; This instruction copies the &-bit j contents in DL from the memory location offset by the ; value of EA specified in BP from the contents of $5. ; Because data addressed by BP are by default located in ; stack segment (88). 3. Base-Plus-Index-Addressing,: Base-plus-index addressing is similar to indirect addressing because it indirectly addresses memory data. This addressing uses one base register (BP or BX), and one index register (DI or SI) to indirectly address memory. The base register often holds the beginning location of a memory array, while the index register holds the relative position of an element in the array. Remember that whenever BP addresses the memory data, the contents of stack segment, BP and index register are used to generate physical address. Locating Data with Base-Pulse-Index Addressing : MOV CX, (BX*D1) : 1000) S| 1000H Tos « (10) 20004 or | 20004 Locating Array Data Using Base-Plus-index Addre: A main use of the base-plus-index addressing mode is to address elements in a memory array. Suppose that the array is located in the data segment beginning from memory location ARRAY. To access a particular element within the array we have to load the BX register (base) with the beginning address of the array, and the DI register (index) with the element number to be accessed. This is illustrated in Fig. 3.1Microprocessors and Interfacing 3-6 8086 Instruction Set and ALP rn Bxebi ARRAY +6—=——— ARRAYS ARRAYS ARRAY + DI JARRAY*3 Di Element Jindex ARRAY ARRAY x [ ARRAY base | Fig. 3.4 4, Register Relative Addressing Register relative addressing is similar to base-plus-index addressing. Here, the data in a segment of memory are addressed by adding the displacement to the contents of a base or an index register (BP, BX, DI or SI). Remember that displacement should be added to the register within the [ ]. This is illustrated in the Fig. 3.2. Displacement can be any 8-bit or 16-bit number. MOW CX, [BX + 0003H] or MOV CX, [BX +3] j61004H 610034 61002H DS (107)Microprocessors and interfacing 3-7 8086 Instruction Set and ALP # Displacement can be subtracted from the register : MOV AL, [DI-2}. © Displacement can be an offset address appended to the front of the [ | = MOV AL, OFF_ADD [DI + 4]. Example :MOV AL, LAST [SI + 2] ; This instruction copies the contents of the 20-bit address computed from the displacement LAST, SI + 2 and DS into: AL Addressing Array Data with Register Relativ The Fig. addressing. shows how to address data element within the array with register relative: MOV CX, ARRAY (D1) ARRAY +6 |ARRAY+5 = ARRAYS JARRAY+3 DI [ Element ]index ARRAY#2 ARRAY ARRAY ps [Segment base ARRAY | Displacement in the ‘segment register Fig. 3.3 5, Base Relative Plus Index Addressing : The base relative plus index addressing mode is similar to. the base plus index addressing mode, but it adds a displacement, besides using a base register and an index register to generate a physical address of the memory. This addressing mode is suitable to address data within the two dimensional array.Microprocessors and Interfacing 3-8 8086 Instruction Set and ALP Addressing Data with Base Relative Plus index : The Fig. 3.4 shows how data can be accessed with bs mode. relative plus index addressing MOV ALJBX + $1 + 10H] DS = (108) Fig. 3.4 Addressing Arrays with Base Relative-Plus-index : ‘As mentioned earlier this addressing mode is useful in addressing two dimensional array. Two dimensional array usually stores records, For example, student record such as its name, roll no etc. Therefore, each record contains number of data elements. To access data element from a particular record we use base register to hold the beginning address of the array of records, index register ta point a particular record in the array of records and displacement to point a particular element in the record. This is illustrated in Fig. 3.5. es = os, — 8 Fig. 35Microprocessors and Interfacing 3-9 8086 Instruction Set and ALP 6. String Addressing. Mode : This mode uses index registers. The string instructions automatically assume SI to point to the first byte or word of the source operand and DI to point to the first byte or word of the destination operand. The contents of SI and DI are automatically incremented (by clearing DF to 0 by CLD instruction) or decremented (by setting DF to 1 by STD instruction ) to point to the next byte or word. The segment register for the source is DS. ‘The segment register for the destination must be ES. Example : MOVS BYTE If {DF] = 0, [DS] = 3000H, [SI] = 0600H, [ES] =50008, ; [DI] = 0400H, [30600H] = 38H, and [504001] = 45H, then ; after execution of the MOVS BYTE, [50400H] = 38H, ; ISH] = 0601H, and [DI] = O401H, Addressing Modes for Accessing /O Ports (0 Modes) Standard 1/O devices uses port addressing modes. For memory-mapped I/O, nhemory addressing modes are used. There are two types of port addressing modes : direct and indirect. In direct port mode, the port number is an S-bit immediate operand. This allows fixed access to ports numbered 0 to 255. Example : OUT 05H, AL 3 Sends the contents of AL to 8-bit port OSH. IN AX, 80H ; Copies 16-bit contents of port 80H In indirect port mode, the port number is taken from DX allowing 64K -bit ports or 3K 16-bit ports, Example : IN AL, DX ; If [DX] = 7890H, then it copies S-bit content of port 7890H ; into AL. IN AX, DX ; Copies the 8-bit contents of ports 7890H and 7891H into AL and AH, respectively. Note : The 3-bit and [6-bit [/O transfers must take place via AL and AX, respectively. 3.2.2 Program Memory Addressing Modes JMP (Jump) and CALL instructions use program memory addressing modes. These instruction have three distinet forms : direct, relative and indirect. Let us see these forms and corresponding addressing modes.Microprocessors and Interfacing 3-10 8086 Instruction Set and ALP Direct program memory addressing : In this addressing mode address where to transfer program control is specified within the instruction alongwith the opcode. The Fig, 36 shows the direct intersegment JMP instruction and the four bytes required to store the address 20000H. This JMP instruction loads C$ with 2000H and IP with 0000H to jump to memory location 20000H for the next instruction. An intersegment jump is a jump where destination location is from a different segment; it can be any memory location within the entire memory locations. Therefore, intersection jump is also known as far jump. Opcode Offset (low) Offset (high) Segment (low) Segment (high) seom[ a Too [= [Te | @ | Fig. 3.6 Like JMP instruction, CALL instruction also uses direct program addressing with Intersegment or far CALL instruction, Usually, in both instructions (MP or CALL) the name of a memory address, called a label is specified in the instruction instead of address. Relative program memory addressing : In this addressing mode, the term relative is restricted to instruction pointer (IP). For example, if a JMP instruction skips the next 5 bytes of memory, the address in relation to the instruction pointer is a 5 that adds to the instruction pointer. This generates the address of the next program instruction, This is illustrated in Fig. 3.7. 20000 20001 20002 4 20003 4 20004 4 20005 H 20008 H 20007 20008 Fig. 3.7 It is important to note that in JMP instruction, opcode takes one byte and displacement may take one or two byte. When displacement is one byte (S-bit), it is called short jump. When displacement is two byte (16-bit), it is called near jump. In both (short and near} cases only contents of IP register are modified; contents of CS register are not modified. Such jumps are called intrasegment jumps because jumps are within the current code segment. The relative JMP and CALL instructions can have either an 8-bit or a 16-bit signed. lacement that allows a forward memory reference or a reverse memory reference.Microprocessors and Interfacing 3-11 8086 Instruction Set and ALP Indirect program memory addressing : The 8086 allows several forms of program indirect memory addressing for the JMP and CALL instructions. In this addressing mode, it is possible to use any I6-bit register (AX, BX, CX, DX, SP, BP, DI or SI); any relative register ({BP], [BX], [DI], or [SI}); and any relative register with displacement to specify the jump address. This is illustrated Table 3.1. Jumps to: memory location addressed by BX within current code ‘segment IP BX IMP NEAR PTR (BX) stumps lo memory location addressed by the contents of the data ‘Segment memory location addressed by BX within the current code ‘segment. IP + ({Bx+ 1, (8x) High byte_Low byte. UMP NEAR PTR [D1 + 2] Jumps to memory location addressed by the contents of the data ‘Segment memory location addressed by DI plus 2 within the current ‘code segment P< ((DE+ 3}, [OF* 2) High byte Low byte IMP ARRAY [BX] Jumps to memory location addressed by the contents of the data ‘segment memory location addressed by ARRAY plus BX with the ‘aurrent code segment IP — (ARRAY + BX + 1], [ARRAY + BX)) High byte Low byte Table 3.4 3.2.3 Stack Memory Addressing Modes The stack is a portion of read/write memory set aside by the user for the purpose of storing information temporarily. When the information is written on the stack, the operation is called PUSH. When the information is read from stack, the operation is called a POP. The microprocessor stores the information, much like stacking plates. Using. this analogy of stacking plates it is easy to illustrate the stack operation, 3 Fig, 3.8 shows the stacked plates. Here, we realize that if it is desired to take out the first stacked plate we 2 have to remove all plates above the first plate in the 1 reverse order. This means that to remove first plate we will have to remove the third plate, then the second Fig. 3.8 Stacked plates Pilate and finally the first plate. This means that, the first information pushed on to the stack is the last information popped off from the stack. This type of operation is known as a first in, last out (FILO). This stack is implemented with the help of special memory pointer registerMicroprocessors and Interfacing 3-12 8086 Instruction Set and ALP The special pointer register is called the stack pointer. During PUSH and POP operation, stack pointer register gives the address of memory where the information is to be stored or to be read, The stack pointer’s contents are automatically manipulated to point to stack top. The memory location currently pointed by stack pointer is called top of stack. ‘Stack Structure of 8086/88 The 8086/88 has a special 16-bit register, SP to work as a stack pointer. The stack pointer (SP) register contains the 16-bit offset from the start of the segment to the top of stack, For stack operation, physical address is produced by adding the contents of stack Pointer register to the segment base address in $5. To do this the contents of the stack segment register are shifted four bits left and the contents of SP are added to the shifted result. If the contents of SP are 9F20H and SS are 4000H then the physical address is calculated as follows. (Refer Fig. 3:9) SS = 4000H after shifting four bits left SS = 40000H Now ss 40000H + SP 9F20H_ Physical address 49F20H — End of stack segment 4FFFFH = =— Top of stack 49F20H SP = 9F20H SS = 4000H — Start of stack segment 40600H Fig. 3.9 Stack and stack pointer PUSH and POP Operations Temporarily stores the contents of 16-bit register or memory location or program status word, and retrieves when required, When programmer realizes the shortage of the registers, he stores the present contents of tite registers in the stack with the help of PUSH instruction and then uses the registers for other function, After completion of other function programmer loads the previous contents of the register from the stack with the help of POP instruction. PUSH Operation = ‘The PUSH instruction decrements stack pointer by two and copies a word from some source to the location in the stack where the stack pointer points. Here the source must be a word (I6bit). The source of the word can be a general purpose register, a segment register or memory. The Fig. 3.10 shows the map of the stack before and after execution of PUSH AX and PUSH CX instructions.Microprocessors and Interfacing 3-13 8086 Instruction Set and ALP Ef wa pent __ End fsck sagt arerEH a —fereren sFrFDH S| 4FFFOH arrrcH tan Jarrrcr AFFFoH sp| |—— [Tar aH — Top of stack area arFrAH 00 00034 90024 soot ‘0001H ‘oon = suatotsinceregren 89a] =| Sta of ck segment sono ‘oon tr (0) Before execxtion (9) After execution of PUSH AX ond PUSH CX Fig. 3.10 POP Operation : nstruction copies a word from the stack location pointed by the stack pointer n. The destination can be a general purpose register, a segment register, or a memory location. After the word is copied to the specified destination, the stack pointer is automatically incremented by 2. The Fig. 3.11 shows the map of the stack before and after execution of POP DX and POP BX instructions, End of stack segment 4FFFFH Tap of stack AFeFEH ssi MFFFOH Tam |4FFFCH Mn Jareron LFFFAK 00034 ‘00024 so00% 88 [e600] =|] siartcr stack nagmert 88 [20008] = Start of stack sogment 00004 au (b) After execution of PUSH AX and PUSH CX Fig. 3.14 CALL Operation ‘The CALL instruction is used to transfer execution to a subprogram or procedure. There are two basic types of CALLs, near and far. A near CALL is a call to a procedure which is in the same code segment as the CALL instruction. When the 8086 executes aMicroprocessors and Interfacing 3-14 8086 Instruction Set and ALP near CALL instruction it decrements the stack pointer by two and copies the offset of the next instruction after the CALL on the stack, It loads IP with the affset of the first instruction of the procedure in sime segment A far CALL is a call to a procedure which is in a different segment from that which contains the CALL instruction. When the 8086 executes a far CALL it decrements the stack pointer by two and copies the contents of the CS register to the stack. It then decrements the stack pointer by two again and copies the offset of the instruction after the CALL to the stack, “inally, it loads CS with the segment base of the segment which contains the procedure and IP with the offset of the first instruction of the procedure in that segment, RET Operation ‘The RET instruction will return execution from a procedure to the next instruction after the CALL instruction in the calling program. If the procedure is a near procedure: (in the same code segment as the CALL instruction), then the return will be done by replacing the instruction pointer with a word from the top of the stack. If the procedure is a far procedure (in a different code segment from the CALL truction which calls it), then the instruction pointer will be replaced by the word at the top of the stack. The stack pointer will then be incremented by two. The code segment register is then replaced with a word from the new top of the stack. After the code segment word is popped off the stack, the stack pointer is again incremented by two. ‘These words/‘word are the offset of the next instruction after the CALL. So 8086 will fetch the next instruction after the CAI Overflow and Underflow of Stack We have seen the PUSH operation. During this operation stack pointer is decremented by two. We know that maximum length of stack segment is 64K. IF we go on performing PUSH operations successively, at one time the contents of SP will be 000H. Any further attempt to PUSH data on the stack will result in stack overflow. On the other hand, if we go on performing POP operations successively, at one time the contents of SP will be FFFFE. Any further attempt to POP data from the stack will result in stack underflow. 3.3 Instruction Set of 8086/8088 The instruction set of the 8086 is divided into Eight major groups as follows : * Data Movement Instructions + Arithmetic and Logie Instruetions * String Instructions and * Program Control Transfer Instructions Iteration Control Instructions + Processor Control InstructionsMicroprocessors and Interfacing 3-15 8086 Instruction Set and ALP © External Hardware Synchronization Instructions © Interrupt Instructions 3.4 Data Movement Instructions The data movement instructions can be classified as * MOV instructions to transfer byte or word. © PUSH/POP instructions. © Load effective address instructions. © String data transfer instructions. © Miscellaneous data transfer instructions, 3.4.1. MOV Instruction It is a general purpose instruction to transfer byte or word from register to register, register to memory or from memory to register. MOV destination, source The MOV instruction copies a word of a byte of data from some source to a destination. The destination can be a register or a memory location. The source can be a register, a memory location, or an immediate number, The source and destination in an instruction can’t both be memory locations, The source and destination in a MOV instruction must be of same type ie. either both must be byte or word, MOV instruction does not affect any flags. Examples : MOV BX, 592FH ; Load the immediate number 592FH in BX ‘MOV CL, [357AH] ; Copy the contents of memory location, at a displacement of 357AH from data segment base, into the CL register, MOV [7#4AH], BX ; Copy the contents of BX register to two memory ; locations in the data segment. Copy the contents } of BL register to memory location at a j displacement of 734AH and BH register } ta memory location at a displacement of ; 734BH. MOV DS, CX ; Copy word from CX register to data ; Segment register. MOV TOTAL [BP], AX; Copy AX to two memory locations. AL to ; first location, AH to second. Effective j address, FA, is the sum of displacementMicroprocessors and Interfacing 3-16 8086 Instruction Set and ALP ; represented by TOTAL and contents of BP. ; Physical address = EA + SS. MOV CS: TOTAL [BP], AX; Same as above instruction, but physical ; address = EA¥CS. Because the segment ; overide prefix is CS. 3.4.2 PUSHIPOP Instructions ‘These instruct?1ns are used to load or receive data from the stack memory. PUSH source ‘The PUSH instruction decrements stack pointer by two and copies a word from some source to the location in the stack where the stack pointer points. Here the source must be a word (16 bit). The source of the word can be a general purpose register, a segment register or memory. It is important to note that whenever data is pushed onto the stack, the first (most significant) data byte moves into the stack segment memory location addressed by SP-1. The second (least significant) data byte moves into the stack segment memory location addressed by SP-2. Examph 1. PUSH CX ; Decrements SP by 2, copy CX to stack ‘The Fig, 3.12 shows the execution of PUSH CX instruction. ‘SSx 10H Fig. 3.12Microprocessors and Interfacing 3-417 ‘8086 Instruction Set and ALP Note : After execution of installation SP = 0082 H and it is indicated by dotiad arrow. 2 PUSH DS ; Decrement $P by 2, copy DS to stack 3. PUSH NEXT [BX]; Decrement SP by 2, copy a word from memory in 7 DS (ie. PA = EA + DS) to stack with 3 EA = NEXT + [BX] PUSHF Puts the flag register contents on the stack. Whenever this instruction is executed, the most significant byte of flag register moves into the stack segment memory location addressed by SP-1. The least significant byte of flag register moves into the stack segment memory location addressed by SP-2. POP destination ‘The POP instruction copies a word. from the stack location pointed by the stack pointer to the destination, The destination can be a general purpose register, a segment register, or a memory location. After the word is copied to the specified destination, the stack pointer is automatically incremented by 2. Whenever data is remaved from the stack, the byte from the stack segment memory location addressed by SP moves into the most significant byte of the destination register and the byte from the siack segment memory location addressed by SP + 1 moves into the least significant byte of the destination register. Examples : 1. POP CX ; Copy a word from top of stack ; to CX and increment SP by 2. The Fig. 3.13 shows the execution of POP CX instruction. Fig. 3.13,Microprocessors and Interfacing 3-18 8086 instruction Set and ALP Note : After execution of instruction SP = OO44H and it is indicated by dotted arrow. 2. POP DS ; Copy a word from top of stack : to DS and increment SP by 2 3. POP NEXT [BX] Copy a word from top of stack to memory in DS . PA = EA + DS) with EA = NEXT + [BX], and ; increment SP by 2. ‘Note : POP CS is illegal. POPF Removes the word from top of stack to the flag register. Whenever this instruction is executed, the byte from the stack segment memory location addressed by SP moves into the most significant byte of the flag register and the byte from the stack segment memory location addressed by SP+1 moves into the least significant byte of the flag register. Initializing the stack Before going to use any instruction which uses stack for its operation we have initialize stack segment, and we have reverse the memory area required for the stack. The stack can be initialized by including following sequence of instructions in the program. METHOD 1: ASSUME CS: CODE, DS : DATA, SS : STACK STACK SEGMENT S_DATA DB 100 DUP (7) STACK ENDS Note : Matter typed in Bold letters is included to initialize stack. This program sequence reserves 100 bytes for the stack operation. METHOD 2 : Syntax : - Stack [size] Example : - Stack 100 ‘The - stack is a directive, which provides shortcut in definition of the stack segment. ‘The default size is 1024 bytes. The instruction - stack 100 reserves 100 bytes for the stack ‘operation. 3.4.3 Load Effective Address The load effective address group includes following instructions. ° LEAMicroprocessors and Interfacing 3-19 8086 Instruction Set and ALP * Ups + LES LEA Instruction: Load Effective Address : LEA register, source This instruction determines the offset of the variable or memory location named as the source and loads this address in the specified 16-bit register. Flags are not affected by LEA instruction. Examples : LEA CX, TOTAL j Load CX with offset of TOTAL in DS. LEA BP, SS : STACK_TOP _; Load BP with offset of STACK_TOP in SS. LEA AX, [BX] [DI] ; Load AX with BA = [BX] + [DI] LDS Instruction : Load register and DS with words from memory. LDS. register, memory address of first word, This instruction copies a word from two memory locations into the register specified in the instruction. It then copies a word from the next two memory locations into the DS register. Examples : LDS CX, [391AH] j Copy contents of memory at displacement of 391AH and 391BH to CX. Then copy contents at 3 displacement of 391CH and 391DH in Ds. LES Instruction : Load register and ES with words from memory. LES register, memory address of first word. ‘This instruction loads new values into the specified register and into the ES register from four successive memory locations. The word from the first two memory location is copied into the specified register and the word from the next two memory locations is copied into the ES register. Example : LES CX, [34834] ; Copy contents of memory at displacement of 3483HO ; in DS to CL, contents of 3484H in DS to CH and ; copy the contents of memory at displacement of 7 3485H and 3486H in DS to ES register. 3.4.4 String Data Transfer Instructions MOVS/MOVSB/MOVSW These instructions copy a byte or word from a location in the data segment to a location in the extra segment. The offset of the source byte or word in the data segment must be in the SI register. The offset of the destination in the extra segment must be contained in the DI register. For multiple byte or multiple word moves the number of elements to be moved is put in the CX register so that it can function as a counter. After the byte or word is moved SI and DI are automatically adjusted to point to the next sourceMicroprocessors and Interfacing 3-20 8086 Instruction Set and ALP and the next destination. If the direction flag is 0, then SI and DI will be incremented by 1 after a byte move and they will incremented by 2 after a word move. If the DF is a 1, then SI_and DI will be decremented by 1 after a byte move and they will be decremented by 2 alter a word move. MOVS affects ne flags. The way to tell the assembler whether to code the instruction for a byte or word move is to add a “B’ or a “W" to the MOVS mnemonic. MOVSB, for example, says move a string as bytes. MOVSW says move a string as words. Examples : cLD } Clear Direction Flag to autoinerement SI and DI MOV AX, 0000H MOV DS, AX : Initialize data segment register to 0 MOV ES, AX ; Initialize extra segment register to 0 MOV SI, 2000H ; Load offset of start of source string into SI MOV DI, 2400H 3 Load offset of start of destination into Dl MOV CX, 04H ; Load length of string in CX as counter REP MOVSB 3 Decrement CX and MOVSB until CX will be 0. After move SI will be one greater than offset of last byte in source string. DI will be one greater than offset of last byte of destination string. CX will be 0. REP is a prefix which is written before MOVSB to repeat execution of it until CX=0. REP/REPE/REP2/IREPNE/REPNZ Prefix REP is a prefix which is written before one of the string instructions. These instructions repeat until specified co is REP REPEREPZ REPNE/REPNZ Examph REPZ CMP SB ; Compare string bytes until CX = 0 ; oF until string bytes not equal. LODS/LODSB/LODSW This instruction copies a byle from a string location pointed to by SI to AL, or a word from a string location pointed to by SI to AX. LODS does not affect any flags. LODSB copies byte and LODSW copies a word.Microprocessors and Interfacing 2 8086 Instruction Set and ALP Examples cLD ; Clear direction flag so SI is autoincremented MOV SI, OFFSET S_STRING _; Point SI at string LODS $ STRING. STOS/STOSBISTOSW ‘The STOS instruction copies a byte from AL or a word from AX to a memory location in the extra segment. DI is used to hold the offset of the memory location in the extra segment. After the copy, DI is automatically incremented or decremented to point to the next string clement in memory. If the direction flag, DF, is cleared, then DI will automatically be incremented by one for a byte string or incremented by two for a word string. If the direction flag is set, DI will be automatically decremented by one for a byte string or decremented by two for a word string. STOS does not affect any flags. STOSB copies byte and STOSW copies a word. Examples : MOV DI, OFFSET D_STRING ; Point DI at destination string STOS D_STRING ; Assembler uses string name to determine > whether string is of type byte or type word If byte string, then string byte replaced ; with contents of AL. If word string, then ; string word replaced with contents of AX. MOV DI, OFFSET D_STRING __; Point DI at destination string STOSB ; “B" added to STOS mnemonic directly } tells assembler to replace byte in string with byte from ; AL. STOSW would tell assembler directly to replace a 3 word in the string with a word from AX. 3.4.5 Miscellaneous Data Transfer Instructions This group consists of following instructions. © XCHG * LAHF * SAHF © XLAT * INand OUTMicroprocessors and Interfacing 3-22 8086 Instruction Set and ALP XCHG Instruction: XCHG destination, source. ‘The XCHG instfuction exchanges the contents of a register with the contents of another register or the contents of a register with the contents of a memory location(s). The instruction cannot exchange the contents of two memory locations. The source and destination both must be words or bytes. The segment registers can’t be used in these instructions. Examples : XCHG BX, CX + Exchange word in BX with word in CX. XCHG AL, CL ; Exchange byte in AL with byte in CL. XCHG AL, SUM [BX] ; Exchange byte in AL with byte in memory at ; EA = SUM + [BX]. PA = EA + DS. LAHF Instruction : Load lower byte of flag register in AH. This instruction copies the contents of lower byte of 8086 flag register to AH register. SAHF Instruction: Copy AH register to low byte of flag register. The contents of the AH register are copied into the lower byte of the 8086 flag register. XLAT Instruction : Translate byte in AL. The XLAT instruction replaces a byte in the AL register with a byte from a lookup table in memory. BX register stores the offset of the starting address of the lookup table and AL register stores the byte number from the lookup table. This instruction copies byte from address pointed by [BX + AL] back into AL. IN and OUT Instructions IN Instruction ; Input a byte or word from port. The IN instruction will copy data from a port to the accumulator, If an 8-bit port is read, the data will go to AL and if an 16-bit port is read the data will goto AX. The IN instruction can be executed in two different addressing modes, 1, Direct : In direct addressing mode 8-bit address of the port is a part of the instruction. Examples : IN AL, OF8H_ ; Copy a byte from port OF8H to AL. IN AX, 95H, ; Copy a word from port 95H to AX, 2. Indirect : In indirect addressing, the address of the port is referred from DX register. Since DX is a 16-bit register, the port address can be any number between 0000H to FFEFH. Therefore it is possible address to upto 65,536 ports in this mode,Microprocessors and Interfacing 3 23 8086 Instruction Set and ALP Examples : MOV DX, 30F8H ; Load 16-bit address of the port in DX. IN AL, DX 3 Copy a byte from 8-bit port 30FBH to AL. IN AX, DX 3 Copy a word from 16-bit port 30F8H to AX, OUT Instruction : Send a byte or word to a port, ‘The OUT instruction copies a byte from AL or a word from AX to the specified port. ‘The OUT instruction can be executed in two different addressing modes. 1. Direct : In direct addressing mode 8-bit address of the port is a part of the instruction. Examples : QUT OF8H, AL ; Copy contents of AL to 8 bit port OF8H. QUT OFBH, AX ; Copy contents of AX to 16-bit port OFBH. 2. Indirect : In indirect addressing, the address of the port is referred from DX register. It has advantage of accessing, 2! i.e. 65536 ports as mentioned earlier. Examples : MOV DX, 30F8H ; Load 16-bit address of the port in DX OUT DX, AL ; Copy the contents of AL to port 30F8H. OUT DX, AX 3 Copy the contents of AX to port 30F8H. 3.5 Arithmetic and Logic Instructions ‘The arithmetic and logic group of instructions include * Addition instructions Subtraction instructions Multiplication instructions © Division * BCD and. ASCII arithmetic instructions © Comparison © Basic logic instructions - AND, OR NOT, XOR * Shift and rotate instructions 3.5.1 Addition This group of instructions consist of following instructions * ADD : Addition * ADC: Addition with carry * INC: Increment (Add 1)Microprocessors and Interfacing 3-24 ‘8086 Instruction Set and ALP ADDIADC I struction : ADD destination, source / ADC destination, source. These instructions add a number from source to a number from destination and put the result in the destination. The ADC, instruction also adds the status of carry flag into the result. The source may be an immediate number, a register, or a memory location. The souree and the destination in an instruction cannot both be memory locations. The source and destination both must be a word or byte. If you want to add a byte to a word, you must copy the byte to a word location and fill the upper byte of the word with zeroes before adding. Flags affected : AF, CF, OF, PF, SF, ZF. Examples = ADD AL, OFOH ; Add immediate number OFOH to contents of AL. ADC DL, CL ; Add contents of CL to contents of DL with carry j and store result in DL ie. DL DL +CL+CY ADC DX, BX ; Add contents of BX to contents of DX with carry ; and store result in DX ie, DX + DX + BX + CY ADD CL, TOTAL [BX] ; Add byte from effective address 3 TOTAL [BX] to contents of CL ADD CX, TOTAL [BX] ; Add word from effective address TOTAL [BX] to contents of CX. ING Instruction : Increment destination. The INC instruction adds 1 to the specified destination. The destination may be a register or memory location. The AF, OF, PF, SF and ZF flags are affected. Examples : INC AL 5 Add 1 to contents of AL. INC BX 3 Add 1 to contents of BX. NOTE : The carry flag CF is not affected If contents of 8-bit register are FFH and 16-bit register are FFFFH, after INC instruction contents of registers will be zero without affecting carry flag. INC BYTE PTR [BX] ; Increment byte at offset of BX in DS. ; BYTE PTR directive indicates to the assembler ; that the byte from memory is to be incremented INC WORD PTR [BX] ; Increment word at offset of BX in DS. ; WORD PTR directive indicates to the assembler ; that the word from memory is to be incremented.Microprocessors and Interfacing 3-25 8086 Instruction Set and ALP 3.5.2 Subtraction This group of instructions consist of following group of instructions. ‘+ SUB ; Subtraction © SBB : Subtraction with borrow © DEC : Decrement (subtract 1) + NEG : 2's complement of a number SUB/SBE Instruction : SUB destination, Source. SBB destination, Source, ‘These instructions subtract the number in the source from the number in the destination and put result in the destination. The SBB, instruction also subtracts the status of carry flag from the result. The source may be an immediate number, a register, or a memory location. The destination may be a register or a memory location. The source and the destination both cannot be memory locations, The source and destination both must be word or byte. If you want to subtract a byte from a word, you must copy the byte to a word location and fill the upper byte of the word with zeroes before subtracting Flags affected - AF, CF, OF, PF, SF, and ZF. Examples : SUB AL, OFOH j Subtract immediate number OFOH 5} fram contents of AL store result in AL. $BB DL, CL j Subtract contents of CL and status of carry flag 3 from the contents of DL and store result in DL. jie. DL + DL-CL-CyY SBB DX, BX Subtract contents of BX and status of carry 5 flag from the DX and store result in DX. jie. DX — DX - BX - CY SUB CL, TOTAL [BX] ; Subiract byte from effective address TOTAL [BX] 3 from the contents of CL and store result in CL SUB CX, TOTAL [BX] ; Subtract word from effective address TOTAL [BX] ; from the contents of CX and store result in CX. DEC Instruction : Decrement destination. The DEC instruction subtract 1 from the specified destination. The destination may be a register or a memory location. The AF, OF, PF, SF and ZF flags are affected.Microprocessors and Interfacing 3-26 8086 Instruction Set and ALP Examples : DEC AL ; Subtracts 1 from the contents of AL. DEC BX 3 Subtracts 1 from the contents of BX. Note : The carry flag CF is not affected, If the contents of S-bit register are OOH and 16-bit register are O000H, after DEC instruction contents of registers will be FFH and FFFFH respectively without affecting carry flag. DEC BYTE PTR [BX] ; Decrement byte at offset of BX in DS. ; BYTE PTR directive indicates to the assembler ; that the byte from memory is to be decremented. DEC WORD PTR [BX] ; Decrement word at offset of BX in DS. ; WORD PTR directive indicates to the assembler ; that the word from memory is to be decremented. NEG Instruction : Form 2's complement. This instruction replaces the number in a destination with the 2’s complement of that number, The destination can be a register or a memory location. This instruction can be implemented by inverting each bit and adding 1 to it. ‘The negate instruction updates the AF, CF, SF, PF, ZF and OF flags. Examples : 7 AL = 011 0101 35H NEG AL ; Replace number in AL with its 2's complement 3 AL = 1100 1011 = CBH 3.5.3. Comparison The comparison instruction (CMP) compares a byte/word from the specified source with a byte/word from the specified destination. The source and destination both must be byte or word. The source may be an immediate number, a register, or a memory location. The destination may be a register or a memory location. However the source and destination both can’t be memory locations. The comparison is done by subtracting the source byte or word from the destination byte or word. But the result is not stored in the destination. Source and destination remain unchanged, only flags are updated. Flags : The AF, OF, SF, 2F, PF and CF are updated by the CMP instruction. Examples : (CMP BL, 01H ; Compare immediate number 01H with byte in BL. ‘CMP CX, BX + Compare word in BX with word in CX. CMP CX, TOTAL + Compare word at displacement ; TOTAL in DS with word in CX. Note : It is not possible to compare segment registers.Microprocessors and Interfacing 3-27 8086 Instruction Set and ALP The result of comparison is checked by conditional jump, conditional call and conditional return instructions. We discuss these instructions later in this chapter. 3.5.4 Multiplication ‘This group of instructions consist of following group of instructions, MUL: Unsigned multiplication « IMUL: Signed multiplication MUL Instruction ; | MUL source. ‘This instruction multiplies an unsigned byte from source and unsigned byte in AL register or unsigned word from source and unsigned word in AX register. The source can be a register or a memory location. When the byte is multiplied by the contents of AL, the result is stored in AX. The most significant byte is stored in AH and least significant byte is stored in AL. When a word is multiplied by the contents of AX, the most significant word of result is stored in DX and least significant word of result is stored in AX. Flags : MUL instruction affect AF, PF, SF, and ZF flags. Examples : MUL BL } ALx BL, result in AX MUL BX ; AX x BX, result high word in DX low word in AX. MUL WORD PTR [BX] ; AX times word in DS pointed by [BX] j result high word in DX low word in AX. IMUL Instruction : ‘This instruction multiplies a signed byte from some source and a signed byte in AL, or a signed word from some source and a signed word in AX. The source can be register or memory location. When a signed byte is multiplied by AL a signed result will be put in AX. When a signed word is multiplied by AX, the high-order word of the signed result is put in DX and the low-order word of the signed result is put in AX. If the upper byte of a 16-bit result or the upper word of 32-bit result contains only copies of the sign bit (all 0's or all 1's), then the CF and the OF flags will both be 0's, The AF, PE, SF, and ZF flags are undefined after IMUL. To multiply a signed byte by a signed word it is necessary to move the byte into a word location and fill the upper byte of the word with copies of the sign bit. This can be done using CBW instruction. ‘Examples : IMUL BL i AL ® BL, result in AX IMUL CX AX « CX, high-order word of result in DX and j low-order word of result in AX.Microprocessors and Interfacing 3-28 8086 Instruction Set and ALP 3.5.5 Division This group of instructions consists of following group of instructions * DIV * IDIV DIV Instruction : DIV source This instruction is used to divide an unsigned word by a byte or to divide an unsigned double word by a word, When dividing a word by a byte, the word must be in AX register. After the division AL will contain an 8-bit quotient and AH will contain an 8-bit remainder. If an attempt is made to divide by 0 or the quotient is too large to fit in AL (greater than FFH), the 8086 will automatically execute a type 0 interrupt. When a double word is divided by a word, the most significant word of the double word must be in DX and the least-significant word must be in AX. After the division AX will contain a 16-bit quotient and DX will contain a 16-bit remainder. Again, if an attempt is made to divide by 0 or the quotient is too large to fit in AX register (greater than FFFFH), the 8086 will do a type 0 interrupt. For DIV instruction source may be a register or memory location. To divide a byte by a byte, it is necessary to put the dividend byte in AL and fill AH with all 0's. Similarly, to divide a word by a word, it is necessary to put the dividend word in AX and fill DX with all 0's, Flags : All flags are undefined after a DIV instruction. Examples : DIV CL ; Word in AX/byte in CL, ; Quotient in AL, remainder in AH. DIV CX ; Double word in DX and AX/word in CX, ; Quotient in AX, remainder in DX. IDIV Instruction : IDIV source This instruction is used to divide a signed word by a signed byte, or to divide a signed double word (32-bits) by a signed word. Rest all is similar to DIV instruction. 3.5.6 BCD and ASCII Arithmetic The 8086 allows arithmetic manipulation of both BCD (Binary coded decimal) and ASCII (American Standard Code for Information Interchange) data. This is accomplished by instructions that adjust the numbers for BCD and ASCII arithmetic, Let us see instructions used for BCD and ASCII arithmetic.Microprocessors and Interfacing ‘8086 Instruction Set and ALP 3.5.6.1 BCD Arithmetic The 8086 provides two instructions to support BCD arithmetic. They correct result of a BCD addition and a BCD subtraction. The DAA (decimal adjust after addition) instruction follows BCD addition, and the DAS (decimal adjust after subtraction) follows BCD subtraction. Both instructions correct the result of the addition or subtraction so that it is a BCD number. DAA Instruction : Decimal Adjust Accumulator. This instruction is used to make sure the result of adding two packed BCD numbers is adjusted to be a legal BCD number. Instruction works as follows : 1. If the value of the low-order four bits (D,-D,) in the AL is greater than 9 or if AF is set, the instruction adds 6 (06) to the low-order four bits. 2. If the value of the high-order four bits (D,-D,) in the AL is greater than 9 or if carry flag, is set, the instruction adds 6 (60) to the high-order four bits. Examples : 1 ; AL = 0011 1001 = 39 BCD 2 CL = 0001 0010 = 12 BCD Add AL, CL i Al 0100 101: 4BH DAA j Add 0110 Because 1011 > 9 } AL = 0101 0001 = 51 BCD 2 j Al 1001 0110 = 96 BCD 3 BL. = 0000 0111 = 07 BCD ADD AL, BL 3 AL = 100] 1101 = 9DH DAA 3 Add 0110 Because 1101 > 9 2 AL = 1010 0011 = ASH 5 1010 > 9 so add 0110 0000 3 AL = 0000 0011 = 03 BCD, CF = 1. The result is 103. The instruction updates the AF, CF, PF, and ZF. The OF is undefined after DAA instruction. Note : only works for AL. DAS Instruction : Decimal Adjust After Subtraction. This instruction is used after subtracting two packed BCD numbers to make sure the result is correct packed BCD. Instruction works as follows = 1. If the value of the low-order four bits (D,-D,) in the AL is greater than 9 or if AF is set; the instruction subtracts 6 (06) from the low-order four bits. 2. If the value of the high-order four bits (D,-D,) in the AL is greater than 9 or if, carry flag is set, the instruction subtracts 6 (60) from the high-order four bits.Microprocessors 30 8086 Instruction Set and ALP Examples : 1 ; AL = 0011 0010 = 32 BCD 3 CL = 0001 0111 = 17 BCD SUB AL, CL 3 AL = 0001 1011 = 1BH 3 Subtract 0110 Because 1011 > 9 3 AL = 0001 0101 = 15 BCD 2 } AL = 0010 0011 = 23 BCD: ~ CL = 0101 1000 = 58 BCD SUB AL, CL ; AL = 1100 1011 = CBH CF = 1 ; Subtract 0110 (6) Because 1011 > 9 ; AL = 1100 0101 = CSH ; Subtract 0110 0000 Because 1100 > 9 AL = 0110 0101 = 65 BCD CF =1, 7 CF =1 means borrow ; is needed means number is negative ( 65). The DAS instruction updates the AF, CF, PF, and ZF. The OF flag is undefined after DAS instruction. Note : DAS only works for AL 3.5.6.2 ASCII Arithmetic: ASCH numbers range in value from 30H to 39H for the numbers 0-9. The 8086 provides four instructions for ASCII arithmetic, * AAAVASCII adjust after addition © AAS :ASCTI adjust after subtraction * AAM:ASCII adjust after multiplication * AAD.-ASCII adjust before division AAA Instruction : ASCII Adjust for Addition. ‘The numbers from 0-9 are represented as 30H-39H in ASCII code. When you want to add two decimal digits which are represented in ASCII code, it is necessary to mask upper nibble (3) from the code before addition. The 8086 allows you to add the ASCII codes for two decimal digits without masking off the “3" in the upper nibble of each digit. The AAA instruction can be used after addition to get the current result in unpacked BCD form. AL 0011 0100 ASCII 4 0011 1000 ASCII 8 AL = 0110 1100 6CH = Incorrect temporary result Al = 0000 0010 Unpacked BCD for 2. ADD AL, CL é AAA 3Microprocessors and Interfacing 3-34 8086 Instruction Set and ALP ; Carry = 1 to indicate correct answer is 12 decimal. The AAA instruction updates the AF and the CF, but the OF, PF, SF, and ZF are left undefined, Note : The AAA instruction only works on the AL register. AAS Instruction : ASCII Adjust After Subtraction, The numbers from 0-9 are represented as 30-39 in ASCII code. When you want to subtract two decimal digits which are represented in ASCIE code, it is necessary to mask upper nibble (3) from the code before subtraction. The 8086 allows you to subtract the ASCII codes for two decimal digits without masking off the “3" in the upper nibble of each digit, The AAS instruction can be used after subtraction to get the current result in unpacked BCD form. Examples : 1 3 AL = 0011 1000 ASCH 8 CL = 0011 0010 ASCH 2 SUB AL, CL 0000 0110 BCD 06 cF=0 AAS : 0000 0010 = BCD 06 ; CF = 0 no borrow required 2 O11 0010 ASCH 2 7 CL = 0011 1000 ASCH 8 SUB AL, CL 3 111 1010 = FAH AAS 0000 110 = BCD 6 borrow needed means (— 6) AAM Instruction: ASCII Adjust After Multiplication. After the two unpacked BCD digits are multiplied, the AAM instruction is used to adjust the product to two unpacked BCD digits in AX. Examples 7 AL = 0000 0100 = Unpacked BCD 4 3 CL = 0000 0110 = Unpacked BCD 6 MUL CL 3 ALx CL Result in AX. 3, AX = 0000 0000 0001 1000 = 0018H AAM ; AX = 0000 0010 0000 0100 = 020411 ; Which is unpacked BCD for 24. Now by adding 3030H in AX register we get the result in ASCII form.Microprocessors and:interfacing 3-32 8086 Instruction Set and ALP AAD Instruction : ASCII Adjust Before Division. AAD converts two unpacked BCD digits in AH and AL to the equivalent binary number in AL. This adjustment must be made before dividing the two unpacked BCD digits in AX by an unpacked BCD byte. After the division AL will contain the unpacked BCD quotient and AH will contain the unpacked BCD remainder, The PF, SF and ZF are updated. The AF, CF and OF are undefined after AAD. Example: ; AX = 0403 unpacked BCD for 43 decimal, CL = 07H AAD 3 Adjust to binary before division, ; AX = 002BH = 2BH = 43 decimal. Div CL ; Divide AX by unpacked BCD in CL. : AL = quotient = 06 unpacked BCD ; AH = remainder = 01 unpacked BCD Now by adding 9080H in AX register we get the quotient and remainder in ASCIL form. 3.5.7 Basic Logic Instructions. The basic logic instructions include AND, OR, Exclusive-OR, and NOT. This group also includes TEST instruction which is a special form of the AND instruction. AND Instruction : AND destination, source. We know that, AND operation with two inputs produces result logic 1 only when both the inputs are logic 1. ie. Y= A-B A B Y 0 0 o o 1 o 1 0 o 1 1 1 Table 3.2 : Truth table for AND gate This instruction logically ANDs each bit of the source byte or word with the corresponding bit in the destination and stores result in the destination. The source may be an immediate number, a register or a memory location. The destination may be a registerMicroprocessors and Interfacing 3-33 8086 Instruction Set and ALP ‘or a memory location. The source and destination both cannot be memory locations in the same instruction. The CF and OF are both 0 after AND. The PF, SF and ZP are affected AF is undefined. Examples. : L ; AL = 1001 0011 = 93H ; BL = 0111 0101 = 75H AND BL, AL ; AND byte in AL with byte in BL ; BL = 0001 0001 = 11H 2 3 CX = 0110 1011 1001 1110 AND CX, OOFOH + CX = 0000 0000 1001 0000 ‘The AND operation clears bits of a binary number. The task of clearing a bit in a binary number is called masking. The Fig. 3.14 shows the process of masking. “Chl XXKK XXKK Unknown 8-bit binary number eartitd ooo ‘Masking patiern XXXX OOOD Result \— estas Fig. 3.14 Masking using AND operation OR Instruction : OR destination, source. We know that, OR operation with twe inputs produces result logic 1 when any one or both inputs are logic 1 ie, Y= A+B. Table 3.3 Truth table for OR gate This instruction logically ORs each bit of the source byte or word with the corresponding bit in the destination and stores result in the destination. The source may be an immediate number, a register or a memory location. The destination may be a registerMicroprocessors and Interfacing 3-6 8086 Instruction Set and ALP ‘or a memory location. The source and destination both can not be memory locations in the same instruction. The CF and OF are both 0 after OR. The PE, SF and ZF are affected. AF undefined. Examples : 1 ; AL = 1001 0011 = 93H ; BL = 0111 O101 = 75H OR BL, AL ; OR byte in AL with byte in BL. iL = 1111 O111 = F7H 2 ; CX = 0110 1011 1001 1110 OR CX, 0OFOH ; CX = O10 1011 1111 110. ‘The OR instruction is used to set (make one) any bit in the binary number, This is illustrated in Fig. 3.15. RoE XXXX XXX Unknown &-bit binary number +1441 9000 ‘Setting pattern XX KX Result sat ita Fig. 3.15 Setting bit/s using OR operation XOR Instruction : XOR destination, source. We know that, XOR operation produces result logic 1 when odd number of inputs are logic 1 ie, Y=AB+AB A B Y o 0 0 1 1 0 1 1 0 Table 3.4 : Truth table for XOR gate This instruction logically XORs each bit of the source byte or word with the corresponding bit in the destination and stores result in the destination. The source may beMicroprocessors 35 8086 Instruction Set \d Interfacing id ALP. an immediate number, » register or a memory location. The destination may be a register or a memory location. “she source and destination both cannot be memory locations in the same instruction. The CF and OF are both 0 after XOR, The PF, SF and 7F are affected. AF is undefined. Examples : 1 ;AL= 1010 HI = AFH = iit 0000 = FOH XOR BL, AL; XOR byte in AL with byte in BL ;BL= O01 1111 = SFH The XOR instruction is used if some bits of a register or memory location must be inverted. This instruction allows part of 2 number to be inverted of coinplemenied. This is illustrated in Fig. 3.16. KXXK XXX Unknown B-bit binary number @ 0000 4498 Pattern for inverting lower 4-bits XXXX KERR Result \—— verted its Fig. 3.16 Inversion of part of a number using XOR operation NOT Instruction ; NOT destination. The NOT instruction i register or a memory location. Flags : NOT instruction affects no flag, verts h bit of a byte or a word. The destination can be Examples : 7 AL = 0110 1100 NOT AL. 7 AL = 1001 0011 7 CX = 1010 1111 0010 0110 NOT CX 7 CX = 0101 0000 1101 1601 Test and bit test instructions : The TEST instruction performs the AND operation. The difference is that the AND instruction changes the destination operand, while the TEST instruction does not. A TEST only affects the condition of the flag register, which indicates the result of the test PE, SF and ZF will be updated to show the results of the ANDing. PF has meaning only for the lower 8 bits of the destination. AF will be undefined,Microprocessors and Interfacing 3-36 8086 Instruction Set and ALP Examples : TEST AL, CL ; AND CL with AL. ; Update flags, result is not stored. ‘TEST BX, CX ; AND CX with BX. ; Update flags, result is not stored. ‘The TEST instruction functions in the similar manner as a CMP instruction. The difference is that the TEST instruction normally tests a single bit (or occasionally multiple bits), while the CMP instruction tests the entire byte or word. The Fig. 3.17 shows the bit pattern and test operation for testing of bit 0. If zero flag is set (Z = 1) after this operation, the bit under test bit-0 is zero ; otherwise bit-0 is 1. ‘The zero flag is usually tested by JZ or JNZ instructions. Therefore, the TEST instruction is usually followed by either the JZ ar JNZ instruction, XXXX XK KX Unknown &bit binary number e000 0001 Bit pattem to test bit 0 oo000 00 Ok Result Tested bit Fig. 3.17 TEST operation 3.5.8 Shift and Rotate 3.5.8.1 Shift Shift instructions position or move binary data to the left ot right by shifting them within the register or memory location. They also perform multiplication by powers of 2°" (left shift) and division by powers of 2-* (right shift). The shift operations can be classified as logical shifts and arithmetic shifts. The logical shifts move a 0 into the rightmost bit position for a logical left shift (SHL) and a 0 into the leftmost bit position for a logical right shift (SHR). The arithmetic left shift (SAL) and logical left shift operations are identical. However, arithmetic and logical right shifts are different because the arithmetic right shift (SAR) copies the sign bit through the number, while the logical right shift copies a0 through the number. This is illustrated in Fig. 3.18. Logical shift operations are used with unsigned numbers; they perform multiplication or division of unsigned numbers, On the otherhand, arithmetic shift operations are used with signed numbers; they perform multiplications or division of signed numbers.Microprocessors and Interfacing 3-37 8086 Instruction Set and ALP Target register or memory cy cy Oo Sign bit (MSB) Fig. 3.18 Shift operations SAL/SHL Instruction : SAL/SHL destination, count. SAL and SHL are two mnemonics for the same instruction. This instruction shifts each bit in the specified destination to the left and 0 is stored at LSB position. The MSB is shifted into the carry flag. The destination can be a byte or a word, It can be in a register or in a memory location. The number of shifts are indicated by count, But if the number of shifts required is one, you can place 1 in the count position. If number of shifts are greater than 1 then shift count must be loaded in CL register and CL must be placed in the count position of the instruction. Diagram shows SAL instruction for byte operation. x ® smereecston FT] EET TTT Te] Flags : All flags are affected.Microprocessars and.Interfacing 3638 ‘6086 Instruction Set and ALP. Examples : SAL CX, 1 3 Shift word in CX 1 bit position left, 0 in LSB MOV CL, 05H Load desired number of shifts in CL SAL AX, CL ; Shift word in AX left § times 7 Os in 5 least-significant bits, SHR Instruction : | SHR destination, count This instruction shifts each bit in the specified destination to the right and 0 is stored at MSB position. The LSB is shifted into the carry flag. The destination can be a byte or a word. It can be in a register of in a memory location. The number of shifts are indicated by count. If number of shifts required is one, you can place 1 in the count position. But if the number of shifts are greater than 1 then shift count must be loaded in CL register and CL must be placed in the count position of the instruction. Di. am shows SHR instruction for byte operation. 8 B&B et —LELCEEEEEI—E] FFI Flags : All flags are affected. Examples : SHR CX, 1 7 Shift word in CX 1 bit position right, 0 in MSB. MOV CL, 05H ; Load desired number of shifts in CL. SHR AX, CL ; Shift word in AX right 5 times 3 0's in 5 most significant bits, SAR Instruction : SAR destination, count. ‘This instruction shifts each bit in the specified destination some number of bit positions to the right. As a bil is shifted oul of the MSB position, a copy of the old MSB is put in the MSB position. The LSB will be shifted into CF, In the case of multiple shifts, CF will contain the bit most recently shifted in from the LSB, Bits shifted into CF previously will be lost, The destination can be a byte or a word, It can be in a register or in a memory location, The number of shifts are indicated by count, If number of shifts required is one, you can place 1 in the count position. If number of shifts are greater than 1 then shift count must be loaded in CL register and CL must be placed in the count position of the instruction,Microprocessors and Interfacing 3-39 8086 Instruction Set and ALP Diagram shows SAR instruction for byte operation Flags : All flags are affected. Examples : SAR BL, 1 } Shift byte in BL one bit position right MOV CL, 04H : Load desired number of shifts in CL. SAR DX, CL Shift word stored in DX 4 bit positions right. 3.5.8.2 Rotate Rolate instructions position or move binary data by rotating the information in a register or memory location, either from one end to another or through the carry flag. This is illustrated in Fig. 3.19. cy Target register or memary, RCL (ran wa a) cy ROL (Rotate left ) cy cr CT —- (aera CL ——— cr ron _———F7 { Rotate right } LI Fig. 3.19 Rotate operationsMicroprocessors and Interfacing 3-40 8086 Instruction Set and ALP ROL Instruction : ROL destination, count. This instruction rotates all bits in a specified byte or word to the left some number of bit positions. MSB is placed as a new LSB and a new CF. Diagram shows ROL instruction for byte rotation. E The destination can be a byte or a word. It can be in a register or in a memory location. The number of shifts are indicated by count. If number of shifts required is one you can place 1 in the count position. If number of shifts are greater than 1 then shift count must be loaded in CL register and CL must be placed in the count position of the instruction. Examples : ROL CX, 1 ; Word in CX one bit position leit, MSB to LSB and CF MOV CL, 03H ; Load desired number of bits to rotate in CL. ROL BL, CL ; Rotate BL three positions. ROR Instruction ; ROR destination, count, This instruction rotates all bits in a specified byte or word to the right some number of bit positions. LSB is placed as a new MSB and a new CP. The destination can be a byte or a word. It can be in a register or in a memory location. The number of shifts are indicated by count. If number of shifts required is one, you can place 1 in the count position. If number of shifts are greater than 1 then shift count must be loaded in CL register and CL must be placed in the count position of the instruction. Diagram shows ROR instruction for byte rotation. & Bs By a COLETTE)Microprocessors and Interfacing 3-41 8086 Instruction Set and ALP Examples : ROR CX, 1 ; Rotated word in CX one bit position right, 7 LSB to MSB and CF. MOV CL, 03H ; Load number of bits to rotate in CL. ROR BL, CL ; Rolate BL three positions. RCL Instruction : RCL destination, count. ‘This instruction rotates all of the bits in a specified word or byte some number of bit positions to the left along: with the carry flag. MSB is placed as a new carry and previous carry is placed as a new LSB. The destination can be a byte or a word. It can be in a register or in a memory location. The number of shifts are indicated by count. If number of shifts required is one, you can place 1 in the count position. If number of shifts are greater than 1 then shift count must be loaded in CL register and CL must be placed in the count position of the instruction. Diagram shows RCL instruction for byte rotation. BB 8 8, 8) B; Bb Examples : RCL CX, 1 ; Rotated word in CX 1 bit left, MSB to CF, CF to LSB. MOV CL, O44 ; Load number of bit positions to rotate in CL. RCL AL, CL ; Rotate AL 4 bits left. RCR Instruction : RCR destination, cou: This instruction rotates all of the bits in a specified word or byte some number of bit positions to the right along with the carry flag. LSB is placed as a new carry and previous carry is placed as a new MSB, ‘The destination can be a byte or a word. It can be in a register or in a memory location. The number of shifts are indicated by count. If number of shifts required is one you can place 1 in the count position. If number of shifts are greater than 1 then shift count must be loaded in CL register and CL must be placed in the count position in the instruction.Microprocessors and Interfacing 3-42 8086 Instruction Set and ALP Diagram shows RCR instruction for byte rotation. CEEETEET 2] ples = RCR CX, 1 3 Word in CX 1 bit right, LSB to CF, CF to MSB. MOV CL, 4H 3 Load number of bit positions to rotate in CL. RCR AL, CL 2 Rotate AL 4 bits right. 3.6 String Instructions ‘The 8086 instruction set provides following string instructions. REP/REPE/REPZ /REPNE/REPNZ MOVS/MOVSB/MOVSW LODS/LODSB/LODSW STOS/STOSB/STOSW (CMPS/CMPSB/CMPSW SCAS/SCASB/SCASW From the above six thucuctions we have already studied first four instructions in section 3.4. the remaining two instructions are string compare instructions. The string comparison instructions allow the programmer to test a section of memory against a constant or against another section of memory. ‘CMPS/CMPSB/CMPSW Instruction A string is a series of the same type of data items in sequential memory locations, The ‘CMPS instruction can be used to compare a byte in one string with a byte in another string the off oF to compare a word in one string with a word in another string: SI is used to hold fset of a byte or word in the source string and DI is used to hold the offset of a byte ‘or a word in the other string. The comparison is done by subtracting the byte or word pointed to by DI from the byte or word pointed to by Sl. The AF, CF, OF, PF, SF, and ZF flags are affected by the comparison, but neither operand is affected.Microprocessors and Interfacing 3-43 8086 Instruction Set and ALP Examples : ; Point SI at source string, Point DI at ; destination string MOV SI, OFFSET F_STRING MOV DI, OFFSET S_STRING CLD ; DF cleared so St and DI will ; autoincrement after compare CMPS F_STRING, S_STRING —_—_; The assembler uses names to determine whether ; strings were declared as type byte or as type | word. MOV CX, 100 ; Put number of string elements in CX, Point SI at ; source of string and DI at destination of string MOV SI, OFFSET F_STRING MOV DI, OFFSET $_STRING sTD ; DF set 50 SI and DI will autodecrement after ; compare REPE CMPSB ; Repeat the comparison of string bytes until end of string or until compared bytes are not equal. After the comparison SI and DI will be automatically incremented or decremented according to direction flag to point to the next element in the two strings (if DF = 0, SI and DI f otherwise | ) CX functions as a counter which is decremented after each comparison. This will go on until CX SCAS/SCASB/SCASW Instruction : SCAS compares a string byte with a byte in AL or a string word with word in AX. ‘The instruction affects the flags, but it does not change either the operand in AL (AX) or the operand in the string, The string to be scanned must be in the extra segment and DI must contain the offset of the byte or the word to be compared. After the comparison DI will be automatically incremented or decremented according, to direction flag to point to the next element in the two strings (if DF =0, Sl and DIT otherwise 4 ) CX functions as a counter which is decremented after each comparison. This will go on until CX = 0. SCAS affects the AF, CF, OF, PF, SF and 2F flags. Examples : ; Scan a text string of 80 characters ; for a carriage return MOV AL, ODH Wyte to be scanned for into AL MOV DI, OFFSET TEXT_STRING set of string to DI MOV CX, 80 ; CX used as element counter cLD ; Clear DF, so Di autoincrementsMicroprocessors and Interfacing 3-44 8086 Instruction Set and ALP REPNE SCAS TEXT_STRING 3 Compare byte in string with byte in : AL SCASB says compare strings as bytes and SCASW says compare strings as words, 3.7 Program Control Transfer Instructions ‘These instructions ane classified as * Unconditional transfer instructions - CALL, RET, JMP © Condit onal transfer instructions = J cond 3.7.1 CALL and RET Instructions Whenever we need to use a group of instructions several times throughout a program there are two ways we can avoid having to write the group of instructions each time we want to use them, One way is to write the group of instructions as a separate procedure. We can then just CALL the procedure whenever we need to execute that group of instructions. For calling the procedure we have to store the return address onto the stack. This process takes some time. If the group of instructions is big enough then this overhead time is negligible with respect to execution time. But if the group of instructions is too short, the overhead time and execution time are comparable. In such cases, it is not desirable to write procedures, For these cases, we can use macros. Macro is alsa a group of instructions. Each time we “CALL” a macro in our program, the assembler will insert the defined group of instructions in place of the “CALL”. An important point here is that the assembler generates machine codes for the group of instructions each time macro is called. So there is not overhead time involved in calling and returning from a procedure. The disadvantage of macro is that it generates inline code each tite when the macro is called which takes more memory. In this section we discuss the procedures From the above discussions, we know that the procedure is a group of instructions stored as a separate program in the memory and it is called from the main program whenever required. The type of procedure depends on where the procedure is stored in the memory. If it is in the same code segment where the main program is stored then it is called near procedure otherwise it is referred to as far procedure, For near procedure CALL instruction pushes only the IP register contents on the stack, since CS register contents remains unchanged for main program and procedure. But for far procedures CALL instruction pushes both IP and CS on the stack. Let us see the detail description and. examples of CALL instruction to enter the procedure and RET instruction to return from the procedure.Microprocessors and Interfacing 3-45 8086 Instruction Set and ALP CALL Instruction : The CALL instruction is used to transfer execution to a subprogram or procedure. ‘There are two basic types of CALLs, near and far. A near CALL is a call to a procedure which is in the same code segment as the CALL instruction. When the 8086 executes a near CALL instruction it decrements the stack pointer by two and copies the offset of the next instruction after the CALL on the stack. It loads IP with the offset of the first instruction of the procedure in same segment. A far CALL is a call to a procedure which is in a different segment from that which contains the CALL instruction, When the 8086 executes a far CALL it decrements the stack pointer by two and copies the contents of the CS register to the stack. It then decrements the stack pointer by two again and copies the offset of the instruction after the CALL to the stack. Finally, it loads CS with the segment base of the segment which contains the Procedure and IP with the offset of the first instruction of the procedure in that segment. Examples : Direct within segment (near) CALL PRO ; PRO is the name of the procedure. ; The assembler determines displacement of pro ; from the instruction after the CALL and codes ; this displacement in as part of the instruction. Indirect within-segment (near) CALL CX ; CX contains, the offset of the first instruction ; of the procedure. Replaces contents of IP with ; contents of register CX. Indirect to another segment (far) CALL DWORD PTR [BX] ; New values for CS and IP are fetched from four } memory locations in DS. The new value for CS ; is fetched from [BX] and [BX + 1], the new IP ; is fetched from [BX + 2] and [BX + 3]. RET Instruction : The RET instruction will return execution from a procedure to the next instruction after the CALL instruction in. the ealling program. If the procedure is a near procedure (in the same code segment as the CALL instruction), then the return will be done by replacing: the instruction pointer with a word from the top of the stack. If the procedure is a far procedure (in a different code segment from the CALL instruction which calls it), then the instruction pointer will be replaced by the word at the top of the stack, The stack pointer will then be incremented by two. The code segment register is then replaced with a word from the new top of the stack. After the code segment word is popped off the stack, the stack pointer is again incremented by two. These words/word are the offset of the next instruction after the CALL. So 8086 will fetch, the next instruction after the CALL.Microprocessors and Interfacing 3-46 8086 Instruction Set and ALP A RET instruction can be followed by a number, for example, RET 4. In this case the stack pointer will be incremented by an additional four addresses after the [P or the [P and CS are popped off the stack. This form is used to increment the stack pointer up over parameters passed to the procedure on the stack. Flags : The RET instruction affects no flags. 3.7.2 JMP Instruction This group of instructions will always cause the 8086 to fetch its next instruction from the location specified or indicated by instruction rather than from the next location after the JMP instruction. The JMP instructions are basically classified as unconditional jump UMP) and conditional jump instructions. A conditional jump instruction allows the programmer to make decisions based upon numerical tests. The results of numerical tests are held in the flag bits, which are then tested by conditional jumy The jump instructions are further classified as short, near and far jump instructions. A short jump is a two-byte instruction that allows jumps or branches to memory locations within +127 and -128 bytes fram the address following the jump. A three byte near jump allows a branch or jump within + 32 Kbytes (or anywhere in the current code segment) from the instruction in the current code segment, The segments are cyclic in nature, This means that, one location above off address FFFFH is offset address 0000H, two locations above offset address FFFFH is offset address O001H and so on. Thus, a displacement of + 32 kbytes allow a jump to any location within the current code segment. In near jump only LP is changed, the contents of CS remains same. A five byte far jump allows a jump to any memory location within the real memory system. A far jump is a jump where destination location is from a different segment. In this case both IP and CS are changed as specified in the destination. The short and near jump are often called intrasegment jumps, and the far jumps are often called intersegment jumps. The short jumps are also called relative jumps because in such instructions the destination location is specified relative to the current location, The Fig. 3.20 shows instruction formats for short, near and far jump instructions. Near and far jumps are further described as either direct or indirect. If the destination address for the jump is specified directly within the instruction, then the jump is described as direct. If the destination address for the jump is contained in a register or memory location, the jump is referred as indirect, because the 8086 has to access the specified register or memory location to get the required destination address.Microprocessors and Interfacing 3-47 ‘8086 Instruction Set and ALP Fig. 3.20 Instruction formats for short, near and far jumps Examples. : (Unconditional jump) JMP NEXT ; Fetch next instruction from address at label NEXT. ; If label is in same segment, an offset coded as part of ; the instruction will be added to the instruction pointer ; to produce the new fetch address. If the label is in ; another segment then IP and CS will be replaced with ; values coded in as part of the instruction, ; This type of jump is referred to as direct ; because the displacement of the destination or the } destination itself is specified directly in the instruction. JMP BX ; Replace the contents of IP with the contents of BX. + BX must first be loaded with the offset of the j destination instruction in CS. This is a near jump. It is j referred to as an indirect jump because the new value j for IP comes from a register rather than from the instruction itself as in a direct-type jump. JMP WORD PTR [BX] } Replace IP with a word from a memory location ; pointed to by BX in DS. This is an indirect near jump. JMP DWORD PTR [SI] ; Replace IP with word pointed to by SI in DS. ; Replace CS with word pointed to by SI + 2 in DS. ) This is an indirect far jump.Microprocessors and Interfacing 3-48 8086 Instruction Set and ALP As explained earlier, a near type jump instruction can cause the next instruction to be fetched from anywhere in the current code segment, To produce the new instruction fetch address, this instruction adds a 16-bit signed displacement contained in the instruction to the contents of the instruction pointer register. A 16 bit signed displacement means that the jump can be to a location anywhere from +32,767 to ~32,768 bytes from the current instruction pointer location. A positive displacement usually means jump is “ahead” in the program, and a negative displacement usually means jump is “backward” in the program. A special cay of the direct near jump instruction is direct short jump. If the destination for the jump is within a displacement range of +127 to -128 bytes from the current instruction pointer location, the destination can be reached with just an 8 bit displacement. 3.7.3 Cond - Conditional Jump Conditional jumps are always short jumps in. the 8086. These instructions will cause a jump to a label given in the instruction if the desired condition(s) occurs in the program before the execution of the instruction. The destination must be in the range of -128 bytes to +127 bytes from the address of the instruction after the conditional transfer instruction. If the jump is not taken, execution simply goes on to the next instruction. Instruction Code Description Condition for jump JANE Jump if aboveljump if not below or equal CF = 0 and ZF =0 JAEHINE Jump if above or equaliJump if not below. CF = 0 and ZF = 1 ABIINAENIC Jump if below/Jump if not above or equal CF = 1 and ZF =0 JBENINA Jump if below or equaliump if not above. CF = 1 and ZF = 1 JEAZ Jump if equalJump if zero flag a JGUINLE ump if greateriJump if not less than nor equal GENUINE Jump if greater than ar equallJump if not tess than. SF SUINGE Jump if ess than/Jump if not greater than or equal. Jump if less than or equai/Jump if not greater Aurrip if no cary Jump if not equaliiump if not zero Jump if no. overtioer Jump if not parityidump if parity odd Jump if not sign oF jump if positive dum@ if overtiow flag = 1. Jump if party/lump if parity even dump if sign flag = 1 oF jump if negative Jump if CX is zero Note : The terms greater and less are used to refer to the relationship of two signedMicroprocessors and Interfacing 3 3.8 Iteration Control Instructions These instructions are used to execute a series of instructions some number of times. The number is specified in the CX register. The CX register is automatically decremented by one, each time after execution of LOOP instruction. Until CX = 0, execution will jump to a destination specified by a label in the instruction. 49 ‘8086 Instruction Set and ALP The destination address for the jump must be in the range of - 128 bytes to + 127 bytes from the address of the instruction after the iteration control instruction. For LOOPE/LOOPZ and LOOPNE/LOOPNZ instructions there is one more condition for exit from loop, which is given below. If the loop is not taken, execution simply goes on to the next instruction after the iteration control instruction. Instruction Code Description Condition for Exit 4. LOOP Loop through a sequence of instructions cx =0 2. LOOPENLOOPZ, Loop through @ sequence of instructions CX= 00 ZF=0 3. LOOPNEMLOOPNZ | Loop through a sequence of instructions CX = 00 2F = 1 3.9 Processor Control Instructions * sic + cic * CMC * sID * cLD * st cu STC Instruction : ‘This instruction sets the carry flag, STC does not affect any other flag, CLC Instruction = ‘This instruction resets the carry flag to zero. CLC does not affect any other flag. CMC Instruction = ‘This instruction complements the carry flag. CMC does not affect any other flag, STD Instruction : This instruction is used to set the direction flag to one so that SI and/or DI can be decremented automatically after execution of string. instructions. STD does not affect any other flag.icroprocessors and Interfacing 3-50 8086 CLD Instruction This instruction is used to reset the direction flag to zero, so that SI and/or D1 can be incremented automatically after execution of string instructions. CLD does not affect any other flag, STI Instruction : This instruction sets the interrupt flag to one. This enables INTR interrupt of the 8086. STI does not affect any other flag. CLI Instruction : This instruction resets the interrupt flag to zero. Due to this 8086 will not respond to an interrupt signal on its INTR input. CLI does not affect any other flag, 3.10 External Hardware Synchronization Instructions * HLT * WAIT * ESC * LOCK * NOP HLT Instruction : The HLT instruction will cause the 8086 to stop fetching and executing instructions, ‘The 8086 will enter a halt state. The only ways to get the processor out of the halt state are with an interrupt signal on the INTR pin, an interrupt signal on the NMI pin, or a reset signal on the RESET input. WAIT Instruction = When this instruction executes, the 8086 enters an idle condition where it is doing no processing. The 8086 will stay in this idle state until a signal is asserted on the 8086 TEST input pin, or until a val terrupt signal is received on the INTR or the NMI interrupt input pins. If a valid interrupt occurs while the 8086 is in this idle state, the 8086 will return to the idle state after the execution of interrupt service procedure. WAIT affects no flags. The WAIT instruction is used to synchronize the 8086 with extemal hardware such as the 8087 math coprocessor, ESC Instruction : This instruction is used to pass instructions to a coprocessor such as the 8087 math coprocessor which shares the address and data bus with an 8086. Instructions for the coprocessor are represented by a &bit code embedded in the escape instruction. When the ‘8086 feiches an ESC instruction, the coprocessor decodes the instruction and carries out theMicroprocessors and Interfacing 3-51 8086 Instruction Set and ALP action specified by the 6-bit code specified in the instruction. In most cases the 8086 treats the ESC instruction as a NOP. In some cases the 8086 will access a data item in memory for the coprocessor. LOCK Instruction : In a multiprocessor system each microprocessor has its own local buses and memory. The individual microprocessors are connected together by a system bus so that each can access system resources such as disk drives or memory. Each microprocessor only takes control of the: system bus when it needs to access some system resources. The LOCK prefix allows a microprocessor to make sure that another processor does not take control of the system bus while it is in the middle of a critical instruction which uses the system bus. ‘The LOCK prefix is put in front of the critical instruction. When an instruction with a LOCK prefix executes, the 8086 will assert its bus lock signal output. This signal is connected to an external bus controller device which then prevents any other processor from taking over the system bus. LOCK affects no flags. Examples : LOCK XCHG SEMAPHORE, AL ; The XCHG instruction requires two bus accesses. ; The LOCK prefix prevents another processor ; from taking control of the system bus between j the two accesses. NOP Instruction : [At the time of execution of NOP instruction, no operation is performed except fetch and decode. It lakes three clock cycles to execute the instruction. NOP instruction does not affect any flag. This instruction is used to fill in time delays or to delete and insert instructions in the program while trouble shooting 3.11 Interrupt Instructions INT Instruction : INT Type This instruction causes the 8086 to call a far procedure. The term type in the instruction refers to a number between 0-255 which identifies the interrupt. The address of the procedure is taken from the memory whose address is four times the type number. INTO Instruction : If the overflow flag is set, this instruction will cause the 8086 to do an indirect far call to a procedure you write to handle overflow condition. To do call the 8086 will read a new value for IP from address 00010H and a new value of CS from address 00012H.Microprocessors and Interfacing 3-52 8086 Instruction Set and ALP IRET Instruction : The IRET instruction is used at the end of the interrupt service routine to return execution to the interrupted program. The 8086 copies return address from stack into IP and CS registers and the stored value of flags back to the flag register. Note : The RET instruction does not copy the flags from the stack back to the flag register. 3.12 Assembler Directives ‘There are some instructions in the assembly language program which are not a part of procéssor instruction set. These instructions are instructions to the assembler, linker, and loader. These are referred to as pseudo-operations or as assembler directives. The assembler directives enable us to control the way in which a program assembles and lists. They act during the assembly of a program and do not generate any executable machine code. ‘There are many specialized assembler directives. Let us see the commonly used assembler directive in 8086 assembly language programming. ALIGN : The align directive forces the assembler to align the next segment at an address divisible by specified divisor. The general format for this directive is as shown. below, ALIGN number where number can be 2, 4, $ or 16. Example : ALIGN 8; This forces the assembler to align the next segment } at an address that is divisible by 8 The assembler fills ; the unused bytes with 0 for data and NOP instructions ; for code. Usually ALIGN 2 directive is used to start the data segment on a word boundary and ALIGN 4 directive is used to start the data segment on a double word boundary, ASSUME : The 8086, at any time, can directly address four physical segments which include a code segment, a data segment, a stack segment and an extra segment. The 8086 may contain a number of logical segments. The ASSUME directive assigns a logical segment to a physical segment at any given time. That is, the ASSUME directive tells the assembler what addresses will be in the segment registers at execution time. Example : ASSUME CS : code, DS : Data, $S : stack. -CODE : This directive provides shortcut in definition of the code segment. General format for this directive is as shown below. code [name] The name is optional. It is basically specified to distinguish different code segments when there are multiple code segments in the program.