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CMOS Devices Book

The document provides an overview of CMOS devices and fabrication. It discusses the MOSFET transistor model, wire resistance and capacitance models, delay modeling, and CMOS fabrication process including diffusion, metallization, lithography and more advanced techniques like FinFETs. Key topics covered include the metal-oxide-semiconductor structure, threshold voltage, I-V characteristics, parasitic capacitance, Elmore delay model, mask sets, design rules, bulk vs SOI processing, and lithography enhancements.

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teddy lee
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77 views

CMOS Devices Book

The document provides an overview of CMOS devices and fabrication. It discusses the MOSFET transistor model, wire resistance and capacitance models, delay modeling, and CMOS fabrication process including diffusion, metallization, lithography and more advanced techniques like FinFETs. Key topics covered include the metal-oxide-semiconductor structure, threshold voltage, I-V characteristics, parasitic capacitance, Elmore delay model, mask sets, design rules, bulk vs SOI processing, and lithography enhancements.

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teddy lee
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© © All Rights Reserved
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Lecture 2

CMOS Devices

Xuan ‘Silvia’ Zhang


Washington University in St. Louis

http://classes.engineering.wustl.edu/ese566/
Outline

Transistor Model

Wire Model

Delay Model

CMOS Fabrication

2
Fundamental Building Block: MOSFET

3
Metal-Oxide-Semiconductor Structure

Accumulation:
Voltage source puts negative charge on gate, attracts
positively-charged majority carriers in p-type silicon body

4
Metal-Oxide-Semiconductor Structure

Depletion:
Voltage source puts positive charge on gate, pushes
positively-charged carriers away from surface, uncovers
some negatively-charged dopant atoms in substrate

5
Metal-Oxide-Semiconductor Structure

Inversion:
Voltage source puts more positive charge on gate,
instead of pushing holes even further away, draws free
electrons to surface.

6
NMOS Transistor

7
Simple NMOS Circuit

8
Key Qualitative Characteristics of MOSFET

9
Quantitative CMOS Model

• Threshold Voltage

VT = VT 0 + γ ( | −2φ F | +VSB − | −2φF | )


kT N A N D
φ0 = ln
q ni2

• I-V Curve
µnCox W Vds2
– linear/triode ID = (Vgs − Vth )Vds −
2 L 2
µC W
I D = n ox (Vgs − Vth ) (1 + λVds )
2
– saturation
2 L

• Parasitic Capacitance
– gate cap
ε si q ⎛ N A N D ⎞ 1
– junction cap C j0 = ⎜⎜ ⎟⎟
2 ⎝ N A + N D ⎠ φ0
10
Outline

Transistor Model

Wire Model

Delay Model

CMOS Fabrication

11
Wire Resistance

• Thickness fixed in given manufacturing process


• Resistance quoted as ohm/square
• TSMC 180nm 6 Aluminum metal layers
– M1-M5: 0.08 ohm/square (0.5um x 1mm wire = 160 ohm)
– M6: 0.03 ohm/square (0.5um x 1mm wire = 60 ohm)

12
Wire Capacitance

• Capacitance depends on geometry of surrounding


wires and relative permittivity, εr, of dielectric
– Silicon dioxide, SiO2, εr = 3.9
– Silicon flouride, SiOF, εr = 3.1
– SiLK polymer, εr = 2.6

13
Outline

Transistor Model

Wire Model

Delay Model

CMOS Fabrication

14
Qualitative Characteristics of Wire Delay

Wire resistance ∝ length


Wire capacitance ∝ length
è
Wire delay ∝ length2

15
Quantitative Delay Model

• RC Ladder
– Elmore delay model

t pd = ∑R C
i −to− source i
nodes i

= R1C1 + ( R1 + R2 )C2 + ! + ( R1 + R2 + ! + RN )C N

16
Outline

Transistor Model

Wire Model

Delay Model

CMOS Fabrication

17
Mask Set for NMOS (circa 1986)

18
Design Rules for Masks (circa 1986)

19
Start with an Un-Doped Wafer

20
Wet Etch to Remove Unmasked Regions

21
Use Diffusion Mask to Implant N-Type

22
Metallization Completes Device

23
Final NMOS Transistor

24
PMOS—Dual of NMOS

25
Single- and Triple-Well Process

26
Local Interconnect

27
Intel Metal Stacks: 90nm and 45nm

28
Intel Metal Stacks: 45nm with M9 and I/O Bump

29
Intel Metal Layer Dimensions in 45nm

30
IBM Metal Stack

31
Bulk vs Silicon-on-Insulator (SOI) Processing

• Eliminate parasitic cap between S/D and body


– lower energy, higher performance
• Lower sub-Vth leakage, but Vth varies over time
• 10-15% increase in total manufacturing cost
– due to substrate cost

32
Lithography

• Pattern resolution exceeds wavelength of light


– 193nm from argon fluoride laser
• Sophisticated patterning tricks
– immersion lithography
– optical proximity correction (OPC)
– double patterning

33
Processing Enhancements

34
FinFET Transistors

• Small footprint, good gate control


– use the vertical dimension
– Intel starts using FinFET in 20nm

35
Questions?

Comments?

Discussion?

36
Acknowledgement

N. Weste and D. Harris, “CMOS VLSI Design”, 2011


Cornell University, ECE 5745
UC Berkeley, CS 230
MIT, 6.371

37

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