Cuapter 2 INTRODUCTION TO VHDL As integrated circuit technology has improved to allow more and more components on a chip, digital systems have continued to grow in complexity. As digital systems have become more complex, detailed design of the systems at the gate and flip-flop level has become very tedious and time consuming. For this reason, use of hardware description languages in the digital design process continues to grow in importance. A hardware description language allows a digital system to be designed and debugged at a higher level before conversion to the gate and flip-flop level. Use of synthesis computer-aided design tools to do this conversion is becoming more widespread. This is analogous to writing software programs in a high-level language such as C and then using a compiler to convert the programs to machine langage. The two most popular hardware description languages are ‘VHDL and Veritog. VDL is a hardware description language used to describe the behavior and structure of digital systems, The acronym VHDL stands for VHSIC Hardware Description Language, and VHSIC in tum stands for Very High Speed Integrated Circuit. However, VHDL is a general-purpose hardware description language that can be used to describe and simulate the operation of a wide variety of digital systems, ranging in complexity from a few gates to an interconnection of many complex integrated circuits. VHDL was originally developed for the military to allow a uniform method for specifying digital systems. The VHDL. language has since become an IEEE standard, and it is widely used in industry. VHDL can describe a digital system at several different levels—behavioral, data flow, and structural. For example, a binary adder could be described at the behavioral level in terms of its function of adding two binary numbers, without giving any implementation details. The same adder could be described at the data flow level by giving the logic equations for the adder. Finally, the adder could be described at the structural level by specifying the interconnections of the gates that comprise the adder. VHDL leads naturally to a top-down design methodology, in which the system is first specified at a high level and tested using a simulator. After the system is debugged at this level, the design can gradually be refined, eventually leading to a structural description closely related to the actual hardware implementation. VHDL was designed to be technology independent. If a design is described in VHDL and implemented in today’s technology, the same VHDL description could be used as a starting point for a design in some future technology.Chaetér 2 © Introoucrion 10 VHDL In this chapter, we describe the basic features of VHDL and illustrate how we can describe simple combinational and sequential networks using VHDL. We will use VHDL in later chapters to design more complex digital systems. In Chapter 8, we introduce some of the more advanced features of VHDL, and we discuss the use of CAD software tools for automatic synthesis from VHDL descriptions 2.4 VHDL DESCRIPTION OF COMBINATIONAL NETWORKS We start by describing a simple gate network in VHDL. If each gate in the network of Figure 2-1 has a 5-ns propagation delay, the network can be described as follows: c A and B after 5 ns; CorD after 5 ns; where A, B,C, D, and E are signals. A signal in VADL usually corresponds to a signal in a physical system. The symbol "<=" is the signal assignment operator, which indicates the value computed on the right side is assigned to the signal on the left side. When these Satements are simulated, the first statement will be evaluated any time A or B changes, and the second statement will be evaluated any time C or D changes. Suppose that initially A= 1,and B=C=D=E=0. If B changes to | at time 0, C will change to | attime=5 ns. ‘Then E will change to | at time = 10 ns. As c een D VHDL signal assignment statements, like the ones in the preceding example, are called concurrent statements when they are not contained in a VHDL process or block. ‘The VHDL simulator monitors the right-hand side of each concurrent statement, and any time a signal changes, the expression on the right-hand side is immediately re-evaluated. ‘The new value is assigned to the signal on the left-hand side after an appropriate delay. When we initially describe a network, we may not be concerned about propagation delays. If we write Figure 2-1. Gate Network c A and B this implies that the propagation delays are O ns. In this case, the simulator will assume an infinitesimal delay referred to as A (delta). For this example, if B is changed to 1 attime = 0, then C will change at time 0 + A and E will change at time 0 + 2A. Unlike a sequential program, the order of the preceding statement we write is unimportant. If2.1 ® VHDL Description of Combinational Networks 45{ © or D; A and the simulation results would be exactly the same as before. Even if a VHDL program has no explicit loops, concurrent statements may execute repeatedly as if they were in a loop. ‘The VHDL statement CLK <= mot CLK after 10 ns; will generate a clock waveform with a half-period of 10 ns. If CLK is initially '0', it will change to'l’ after 10 ns. When CLK changes to'l’, the statement will be executed again, and CLK will change back to '0 after another 10 ns. This process will continue indefinitely. On the other hand, the concurrent statement <= not CLK; will cause a run-time error during simulation. Since there is 0 delay, the value of CLK will change at times 0 + A, 0 + 2A, 0 +34, etc., and real time will never advance. In general, VHDL is not case sensitive; that is, capital and lowercase letters are treated the same by the compiler and simulator. Thus the statements Clk <= NOT clk After 10 and cnx <= not CLK after 10 are treated exactly the same. Signal names and other VHDL identifiers may contain letters, numbers, and the underscore character (_). An identifier must start with a letter, and it cannot end with an underscore. Thus C123, and ab_23 are legal identifiers, but !ABC and ABC_are not. Every VADL statement must be terminated with a semicolon. Entity-Architecture Pairs To write a complete VHDL program, we must declare all the input and output signals and specify the type of each signal. As an example, we will describe the full adder of Figure 1-2(a). A complete description must include an entity declaration and an architecture declaration. The entity declaration specifies the inputs and outputs of the adder module: entity Fulladder is port (%, Y, Cin end Fulladder -> Inputs == Outputs ‘The words entity, is, port, in, out, and end are reserved words (or keywords), which have a special meaning to the VHDL compiler. In this text, we will put all reserved words in boldface type. Aaything that follows a double dash (--) is a VHDL comment. The port declaration specifies that X, ¥, and Cin are input signals of type bit and that Cour and Sum are output signals of type bit. Each signal in this example is of type bit, which means it can assume only values of '0' or I’46 (Chaprer 2 * Iurrooucnion To VHDL. ‘The operation of the full adder is specified by an architecture declaration: architecture Equations of FullAdder is begin -- Concurrent Assignments Sum <= X xor ¥ xor Cin after 10 ns; Cout <= (x and ¥) or (X and Cin) or (¥ and Cin) after 10 ns; end Equations; In this example, the architecture name (Equations) is arbitrary, but the entity name (FullAdder) must match the name used in the associated entity declaration. The VHDL. assignment statements for Sum and Cout represent the logic equations for the full adder ‘(Equations 1-31 and 1-22). Several other architectural descriptions, such as a truth table or an interconnection of gates, could have been used instead. In the Cour equation, parentheses are required around (X and Y), since VHDL does not specify an order of precedence for the logic operators. ‘When we describe a system in VHDL, we must specify an entity and an architecture at the top level, and also specify an entity and architecture for each of the component modules that are part of the system (see Figure 2-2). Each entity declaration includes a list of interface signals that can be used to connect to other modules or to the outside world. ‘We will use entity declarations of the form entity entity-name is [port (interface-signa’ end [entity] [entity-name]; declaration) ;] The items enclosed in brackets are optional. The interface-signal-declaration normally has the following form: list-of-interface-signals: mode type [:= initial-value {; list-of-interface-signals: mode type [:= initial-valuel] ‘The curly brackets indicate zero or more repetitions of the enclosed clause. Input signals are of mode in, output signals are of mode out, and bidirectional signals are of mode inout. So far, we have used only type bit; other types are described in Sections 2.6 and 2.7. ‘The optional initial value is used to initialize the signals on the associated list; otherwise, the default initial value is used for the specified type. For example, the port declaration port(A, B: in integer := 2; C, D: out bit); indicates that A and B are input signals of type integer, which are initially set to 2, and C and D are output signals of type bit, which are initialized by default to ‘0.2.1 © VHDL Description of Combinational Networks 47} Figure 2-2. VHDL Program Structure Entity Architecture Entity Entity Entity Architecture| | Architecture! Architecture ee Module 1 | | Module 2 Module N Associated with each entity is one or more architecture declarations of the form architecture architecture-name of entity-nane ie [declarations] begin architecture body end [architecture] Four-bit Full Adder Next we will show how to use the Full Adder module defined earlier as a component in a system that consists of four full adders connected to form a 4-bit binary adder (see Figure 2-3). We first declare the 4-bit adder as an entity (see Figure 2-4). Since the inputs and the: sum output are 4 bits wide, we declare them as bit_vectors, which are dimensioned 3 downto 0. (We could have used the range 1 to 4 instead). Figure 2-3. Four-bit Binary Adder architecture-name) : S@) SQ) sq) S@) t t + 4 ] Coe] Full CG) | Full C@) | Fun Cd) | Fut Ci 7) Adder ~~~] Adder [7] Adder }* Adder tf Tf tf ft AG) BG) AQ) BQ) A(1) BC) A) BO)Cuneren 2 # IntRooucTION TO VHDL Next we specify the FullAdder as a component within the architecture of Adder4 (Figure 2-4). The component specification is very similar to the entity declaration for the full adder, and the input and output port signals correspond to those declared for the full adder. Following the component statement, we declare a 3-bit internal carry signal C. In the body of the architecture, we create several instances of the FullAdder component. (in CAD jargon, we “instantiate” four copies of the Full Adder.) Each copy of FullAdder has a name (such as FAO) and a port map. The signal names following the port ‘map correspond one-to-one with the signals in the component port. Thus, A(0), B(0), and Ci correspond to the inputs X, ¥, and Cin, respectively, C(1) and S(0) correspond to the Cout and Sum outputs. Figure 2-4 Structural Description of 4-bit Adder port (A, B: in bit_vector(3 downto 0}; Ci: in bit; -- Inputs S: owt bit_vector(3 downto 0); Co: out bit); -- Outputs end Adder larchitecture Structure of Adder4 is component Fulladder port (X, ¥, Cin: in bit; => Inputs Cout, Sum: out bit); -- Outputs end component; signal C: bit_vector(3 downto 1); begin FAO: FAI --instantiate four copies of the Fulladder Fulladder port map (A(0), B(O), Ci, C(1}, $(0)); ladder port map (A(1}, B(1), C(1), C(2), S(1)): FullAdder port map (A(2), B(2), C(2), C(3), $(2)); ladder port map (A(3), B(3), C(3), Co, $(3)); end Structure; In preparation for simulation, we can place the entity and architecture for the FulAdder and for Adder4 together in one file and compile. Alternatively, we could compile the FullAdder separately and place the resulting code in a library that is linked in when we ‘compile Adder. lll the simulation examples in this text use the V-System/Windows simulator from Model Tech. Most other VHDL simulators use similar command files and can produce output in a similar format. We use the following simulator commands to test Adder4: list ABCoC CIS put these signals on the output list force A 1111 -- set the A inputs to 1111 force 5 0001 -+ set the B inputs to 0001 force Ci 1 -- set Ci tol run 50 -- run the simulation for 50 ns / force Ci 0 force A 0101 force B 1110 run 502.1 ¢ VHDL Description of Combinational Networks 49| ‘We have chosen to run the simulation for 50 ns, since this is long enough for the carry to propagate through all the full adders. The simulation resulis for the above command list are ns delta ° +0 ° 41 10 +0 20 +9 30 +0. 40 +0 50 +0 60 +0 70 +0 80 +0 0 ‘The listing shows how the carry propagates one position every 10 ns. The full adder inputs change at time = 9 9 time =A. t t 0 0-4 FA3 —) FAO f—1 Tr FP PT TT 10 10 10 141 The sum and carry are computed by each FA and appear at the FA oatputs 10 ns later: 1 1 1 I time = 10 t t t t a 0 ras AY rar ROY ear FY Fao bi tr TT tT 10 10 10 141 Since the inputs to FAI have changed, the outputs change 10 ns later: 1 0 1 time = 20 t t t o | ras fe? FAL FAO fey gees |u| Io 10 to 11 The final simulation results are 1111 +0001 + 1 = 0001 with a carry of 1 (at time = ms) and 0101 + 1110 +0 =0011 with a carry of | (at time = 80 ns) The simulation stops at 80 ns, since no further changes occur after that time.[50 Cuaerer 2 # Inrrooucrion 10 VHDL 2.2 MODELING FLIP-FLOPS USING VHDL PROCESSES common way of modeling sequential logic in VHDL uses a process. A process may have the form proceas(sensitivity-list) begin sequent ial-statements end procs Whenever one of the signals in the sensitivity list changes, the sequential statements in the process body are executed in sequence one time. The following example illustrates the difference in the ay sequential and concurrent statements are executed. A VHDL program has signals A, B, C, and D of type integer. The signals are initialized to A= 1, B= and D = 0. The program contains the following concurrent statements: Ace Br -- statement 1 Bes Cj; ~~ statement 2 c <= D; statenent 3 Assume that D changes to 4 at time = 10. The following sequence of events then occurs: Since D has changed, statement 3 executes, and C is changed to 4 at time 10 + A. Next, since C has changed, statement 2 executes, and B is updated a time 10 + 2A. Then the change in B triggers execution of statement 1, and A is updated at time 10 + 3. Since A does not appear on the right-hand side of any statement, no further execution is triggered, me delta A B Cc D Ora A a0 10 +0 1 2 3 4 (statement 3 executes first) 10 +1 1 2 4 4 (then statement 2 executes) 10 42 1 4 4 4 ithen statement 1 executes) 10 43 4 4 4 4 (no further execution occurs) Now consider a program with the same statements placed in a process: process (B, C, D) begin Aco By -~ statement 1 B<=C; -- statement 2 C <=D; +> statement 3 end process; Assume that A, B, C, and D are initialized as before and D changes to 4 at time = 10. Since Dias changed, and D is on the sensitivity list, the process begins execution. Stateents 1, 2, and 3 are executed in sequence; then the process goes back to the top and waits until a signal on the sensitivity list changes. Execution of the three statements takes place2.2 * Modeling Flip-flops Using VHDL Processes 51 instantaneously at time = 10; not even delta time is required to execute the statements. However, since A, B, and C are signals, their values are not updated until time 10 + A. ‘Therefore, the old values of B, C, and D are used when the statements are executed. Signals A,B, and C will change value at time 10 + A, so the process will execute again. As a result, A and B will change at time 10 + 2A, and the process will execute a third time. The sequence of events is summarized as follows: time delta A BoC OD o 40 1230 0 40 1 2 3 4 (statement 1,2,3 execute; then update A,B,C) +1 2 3 4 4 (statements 1.2,3 execute; then update A,B,C) 10 42 3 4 4 4 (statements update A,B,C 044 4 4 (no her execution occurs) 2,3 execute; then This example shows how signal assignment statements can be used as sequential statements in a process. Another commonly used sequential statement is the if statement The basic if statement has the form Af condition then sequential statenentst else sequential statements? end if; The condition is a Boolean expression, which evaluates to TRUE or FALSE. If itis TRUE, sequential statements] are executed; otherwise, sequential statements2 are executed. Next we use a VHDL process to model a simple D flip-flop (Figure 1-10), which changes state on the rising edge of the clock input. The signal QN represents the Q" output of the flip-flop. In the entity declaration (see Figure 2-5), QN is explicitly initialized to'l', since it must be the complement of Q, and bit signals are initialized to '0' by default. VHDL requires that bit values such as ("znd '’ be enclosed in single quotes. The architecture name, SIMPLE, is an arbitrary choice. Since the flip-flop can change state only when the clock changes, we define a process that is executed only when CLK changes. Thus CLK is the only signal in the sensitivity list. The clock signal is also tested within the process, and if CLK ='1', this means that a rising edge has just occurred on CLK. In this case, Q is set equal to D, and QNis set to the complement of D. The 10-ns delay represents the propagation delay between the time the clock changes and the flip-flop outputs change.52 Cheree 2 # Inrrooucnon ro VHDL, Figure 2-5 D Flip-flop Mode! entity DFF is port (D, CLK: in bits | Q: out bit; ON: out bit " |-- initialize oN to ‘1' since bit signals are initialized end DEF; "0" by default [architecture SIMPLE of DFF is | begin | process (CLK) process is executed when CLK changes | begin ie CLK - '1" then -- rising eage of clock D after 10 ns; not D after 10 ns; Next, we model a J-K flip-flop (Figure 2-6) that has active-low direct set (SN) and reset (RN) inputs and changes state on the falling edge of the clock. In this chapter, we have used a suffix N to indicate an active-low (negative-logic) signal. For simplicity, we assume that the condition SW = RN = 0 does not occur. Later, we discuss a more complete ‘model that takes this case into account. The VHDL code for the J-K flip-flop is given in Figure 2-7. The next state of the flip-flop is determined by its characteristic equation: O=J+K'O Figure 2-6 J-K Fli QN i RN—d JKFF p—~SN kde] Since the process is executed whenever SN, RN, or CLK changes, we must determine when the falling edge of CLK has occurred. Simply checking for CLK ='0' would not work if the process were activated by achange in SN or RN. Instead, we have used (elsif CLK = '0' and CLK'event). CLK‘event (read as CLK tick event) evaluates to ‘TRUE if CLK has just changed value. Thus, (CLK = '0' and CLK'event) is TRUE only if a falling edge of CLK has just occurred, CLK’event is an example of a signal attribute, and attributes are discussed in detail in Section 8.1.2.2 « Modeling Flip-flops Using VHDL Processes 53 Figure 2-7 J-K Flip-flop Model entity JKeF is | port (SN, RN, J, K, CLK: im bit; -- inputs Q: dmout bit; QN: out bit := '1'); see Note 1 Fy end Ix) architecture JKFF1 of JKFF is begin process (SN, RN, CLK) -- see Note 2 begin df RN = '0' then Qc= '0' after 10 ns; > RN=0 will clear the Fl | elsig sw = 10" then ges '1' after 10 ns; -- sN=0 will | set the FF elsif chk = '0' and cLX'event then -- sce Note 3 (g and not Q) or (not X and 0) after 10 n see Note 4 end process; ON <= not Q -- see Note 5 end JKFF1; Note 1: Q is declared as Inout (rather than out) because it appears on both the left and right sides of an assignment within the architecture Note 2: The flip-flop can change state in response to changes in SN, RN, and CLK, so these 3 signals ere in the sensitivity list. Note 3: The condition (CLK = ‘0' and CLX'event) is TRUE only if CLK hes ust changed from '1' to '0". Note 4: Characteristic equation chat describes behavior of J-K flip flop. Note 5: Every time Q changes. QN will be updated. If this statemen! placed within the process, the old value of Q would be used instead of the new value. The preceding example introduces the use of elsif, which is an alternative way of writing nested if statements. The most general form of the if statement is, if condition then sequential statements {elsif condition then sequential statements } 0 or more elsif clauses may be included sequential statements. The curly brackets indicate that any number of elsif clauses may be included, and the square brackets indicate that the else clause is optional. The example of Figure 2-8 shows how a flowchart can be represented using nested ifs or the equivalent using elsifs. In this54 Chwerer 2 # InrRopucTion To VHDL. example, Cl, C2, and C3 represent conditions that can be true or false, and $1, $2,..., $8 represent sequential statements. Each if requires a corresponding end if, but elsif does not. Figure 2-8 Equivalent Representations of a Flowchart Using Nested Ifs and Elsifs if (Cl) then si; $2; if (Cl) then si; $2; else if (C2) then 83; 34; elsif (C2) then 53; 54; else if (C3) then $5; 86; elsif (C3) then $5; 86; else S7; s8; else S7; S8; end if; end if; end if; end if; 2.3 VHDL MODELS FOR A MULTIPLEXER Figure 2-9 shows a4-to-1 multiplexer (MUX) with four data inputs and two control inputs, Aand B. The control inputs select which one of the data inputs is transmitted to the output. The logic equation for the 4-to-1 MUX is A'B'1, + A'BI, + AB'L, + ABI, Thus, one way to model the MUX is with the VHDL statement F <= (mot A and not 8 and 10) or (not A and 8 and 11) or (A and not 5 and [2) or (A and 5 and 13);2.3 ¢ VHDL Models for a Multiplexer 55 Figure 2-9 4-to-1 Multiplexer ip— — MUX F bh— — AB ‘To model the MUX at the behavioral level, we can use a conditional assignment statement. This statement has the form signal_name <- expression! when condition: else expression? when condition? lelae expressionN]; ‘This concurrent statement is executed whenever an event occurs ona signal used in one of the expressions or conditions. If condition! is true, signal_name is set equal o the value of expression else if condition? is true, signal_name is set equal to the value of expression2, ete. ‘We can also model the 4-t0-1 MUX of Figure 2-9 using a selected signal assignment statement: F <= 10 when sel = 0 else [1 when Sel <1 else 12 when Sel = 2 else I In the above concurrent statement, Sel represents the integer equivalent of a 2-bit binary number with bits A and B. If a MUX model is used inside a process, a concurrent statement cannot be used. As an alternative, the MUX can be modeled using a ease statement: case sel is when 0 => F <= 10; when 1 => F <= Il; when 2 => F <= 12; when 3 => F <= 13; end case;{56 Chapres 2 » Inrropuction to VHDL. ‘The ease statement has the general form expression ia when choicel => sequential statements1 when choice? => sequential statements? [when others -> sequential statements! end case; ‘The “expression” is evaluated first. itis equal te “choice1”, then “sequential statements!” are executed; if it is equal to “choice2”, then “sequential statements2” are executed; etc. All possible values of the expression must be included in the choices. If all values are not explicitly given, a “when others” clause is required in the case statement. 2.4 COMPILATION AND SIMULATION OF VHDL CODE Figure 2-10 After describing a digital system in VHDL, simulation of the VHDL code is important for two reasons. First, we need to verify the VHDL code correetly implements the intended design; second, we need to verify that the design meets its specifications. Before the VHDL model of a digital system can be simulated, the VHDL code must first be compiled (see Figure 2-10). The VHDL compiler, also called an analyzer, first checks the VHDL source code to see that it conforms to the syntax and semantic rules of VHDL. If there is a syntax error such as a missing semicolon, or if there is a semantic error such as trying to add two signals of incompatible types, the compiler will output an appropriate error message. The compiler also checks to see that references to libraries ate correct. If the VHDL code conforms to all the rules, the compiler generates intermediate code, which can be used by a simulator or by a synthesizer. (Synthesis of digital logic from VHDL code is discussed in Chapter 8.) Compilation, Elaboration, and Simulation of VHDL Code Resource ‘Simulator " Libraries \ ~ Inver Compiler [ mediate. | working roel ee corre Elaborator Simulator J ‘Simulator Output In preparation for simulation, the VHDL intermediate code must be converted to a form that can be used by the simulator. This step is referred to as elaboration. During elaboration, ports are created for each instance of a component, memory storage is allocated58 Chsorer 2 ¢ Inrropucnon To VHDL. VHDL simulators use event-driven simulation, as illustrated in the preceding example. A change in a signal is referred to as an event, Each time an event occurs, any processes that have been waiting on the event are executed in zero time, and any resulting signal changes are queued up to occur at some future time. When all the active processes are finished executing, simulation time is advanced to the time for which the next event is scheduled, and the simulator processes that event. This continues until either no more events have been scheduled or the simulation time limit is reached, Figure 2-12 Signal Drivers for Simulation Example Queved Curent values value After elaboration: “7 time = 0 vee After initialization: [jy @ 5 ota time = 0 ‘a Simulation step: 0@5 t/a time = A Tei |o bes Te [ops 0 @15 [1 @ 1044] 0 A o@is [thea time = 10+ we oomal ii B 15 a en [rs 2.5 MODELING A SEQUENTIAL MACHINE In this section we discuss several ways of writing VHDL descriptions for sequential ‘machines, First, we write a behavioral model for a Mealy sequential network based on the state table of Figure 1-17. As shown in Figure 1-16, the Mealy machine consists of a combinational network and a state register. The VHDL model of Figure 2-13 uses two processes to represent these two parts of the network. At the behavioral level, we will represent the state and next state of the network by integer signals initialized to 0. The first2.5 # Modeling a Sequential Machine 59 process represents the combinational network, Since the network outputs, Zand Nextstate, can change when either the State or X changes, the sensitivity list includes both State and X. The case statement tests the value of State, and depending on the value of X, Z and. Nextstate are assigned new values. The second process represents the state register. Whenever the rising edge of the clock occurs, State is updated to the value of Nextstate, so CLK appears in the sensitivity list. In Figure 2-13, State is an integer. Since only seven integer values of State are explicit choices, the statement when others => null is included. The null implies no action, which is appropriate, since the other values of State should never occur. Figure 2-13 Behavioral Model for Figure 1-17 -- This is a behavioral model of a Mealy state machine (Figure 1-17) - based on its state table. The output (Z) and next state are - computed before the active edge of the clock. The state change occurs on the rising edge of the cl entity SMi_2 is port (X, CLK: in bi Zs out bit); end sM1_2; architecture Table of swi_2 is signal State, Nextstate: intege: begin process (State, X) --Combinational Network begin case State de when 0 => if x=0" Nextstatec-1; end if; if x11 Nextstatec=2; end if; when 1 => af x=" Nextstatec=3; end if if x=1' Nextstatec=4; end if; when 2 => if x='0" Nextstatec=4; end if; if X=11" Nextstate<=4; end if; Nextstatec Nextstatec=5 } end if; end if; Nextstate<=5; end if; Nextstatec-6; end if; when 5 => if x='0" Nextetate<=0; end if; if x=" Nextstatec=0; end if; Nextetatec-0; end if; -- should not occur when others end case end process;60 Cuaerer 2 # INroouction 10 VHDL process (CLK) State Register begin Af CLK='1' then -- rising edge of clock State <= Nextstate; end if; end proce: end vabie; A simulator command file that can be used to test Figure 2-13 is as follows: wave CLK X State Nextstate Z force CLK 0 0, 1 100 -repeat 200 force X 0 0, 1 350, 0 £59, 1 750, 0 950, 1 1350 run 1600 The first command specifies the signals that are to be included in the waveform output. ‘The next command defines a clock with period of 200 ns. CLK is'0' at time 0 ns, is ‘I’ at time 100 ns, and repeats every 200 ns. In a command of the form force signal_name vi tl, v2 t2, ... signal_name gets the value v1 at time t1, the value v2 at time (2, etc. X is 0’ at time O-ns, changes tol’ at time 350 ns, changes to’ at time 550 ns, etc. The X input corresponds to the sequence 0010 1001, and only the times at which X changes are specified. These changes occur at the same times relative to the clock, as shown in Figure 1-27. Execution of the preceding command file produces the waveforms shown in Figure 2-14, which ate similar to those in Figure 1-27. Figure 2-14 Waveforms for Figure 2-13 mS LS LP LS LS -_riy Li aT yr UE ssate8XL a > —) sexstateL XE g © Tee 1 Lu [eee eee ls eee ed2.5 * Modeling a Sequential Machine 61] The data-flow VHDL model of Figure 2-15 is based on the next-state and output equations, which are derived in Figure 1-19. The flip-flops are updated in a process that is sensitive to CLK, When the rising edge of the clock occurs, Q/, 2, and Q3 are all assigned new values. A {0-ns delay is included to represent the propagation delay between the active edge of the clock and the change of the flip-flop outputs. Even though the assignment statements in the process are executed sequentially, 07, 02, and Q3 are all scheduled to be updated at the same time, T + A, where T is the time at which the rising edge of the clock occurred. Thus, the old value of Q1 is used to compute Q2*, and the old values of Q7, 02, and Q3 are used to compute Q3*. The concurrent assignment statement for Z causes Z to tbe updated whenever a change in X or Q3 occurs. The 20-ns delay represents two gate delays. Figure 2-15 Sequential Machine Model Using Equations == The following is @ description of the sequential machine of -- Figure 1-17 in terms of its next state equations - The following state assignment was used: == 80-30; >4; S2-->8; S3-->7; S4-->6; S5--a3; S6-->2 entity SMI_? is port (X,CEK: in bit; out bit); architecture Equationsi_! of sMi_2 is | signal 01,02,Q3: bit; | begin process (CLK) begin | Af CLK="1) then -- rising edge of clock Ql<-not Q2 after 10 ns; Q2<=91 after 10 ns; Q3<=(Q1 and 02 and Q3) or ((not xX) and Ql and (not 03)) oF (% and (not Ql) and (not Q2)) after 10 ns; end if; end process; 2<=((not X) and (not Q3)) or (x and Q3) after 29 as; end Equationsl_4; Figure 2-16 shows a structural VHDL representation of the network of Figure 1-20. Seven NAND gates, three D flip-flops, and one inverter are used. All these elenients are defined in a library named BITLIB. The element definitions are contained in a package called bit_pack. (See Appendix B fora listing of bit_pack.) The library and use statements are explained in Section 2.11. Since Q1, 02, and Q3 are initialized to 0, the complementary flip-flop outputs (Q/N, Q2N, and Q3N) are initialized to''. G1 is a 3-input NAND gate with inputs Q/, Q2, Q3, and output AJ. FP] is a D flip-flop (see Figure 2-5) with the D input connected to Q2N. All the gates and flip-flops in bit_pack have a default delay of62 (Cuserer 2 # INTRODUCTION To VHDL, 10 ns. Executing the simulator command file given below produces the waveforms of Figure 2-17, which are very similar to Figure 1-28, wave CLK X Ql Q2 Q3 2 force CLK € 0, 1 100 -repeat 200 force K 0 C, 1 350, 0 $50, 1 750, 0 950, 1 1350 pin 1600 Figure 2-16 Structural Model of Sequential Machine The following ie a STRUCTURAL VHDL descriptil |aapeary errcre; use BITLIB.bit_pack.all: entity sui? de [nore ix, cEx: tm bic; | event} | ena smi_2; [architecture structure of sii_2 de signal A1,A2.A3,85, 86°03" bies="0"; tignal 01,02,03" bie pignel O21, 02", 038, | begin pet Inverter port map (X, 18) ; | Git Nenas pore map 0102,03,A1) G2: Nand} port map (01,03H, 21,92); G3: Nand} port map [X,0:N,O2N, a3); lcci vara eoctmaed aaah bsih FPL: DEP port nap (02H, CLR Qi 018) Pr2: DEP port nap (9:,CLx, 02,0230 1 | PR3: DEF port map (D3,CLK,Q3,03N) + | GS: Nand2 port map /X,Q3, Z | G6: Nand2 port map |XN,Q3N,A6); G7: Nand? port map (A5,86.2) 7 . end Structure; Figure 2-17 Waveforms for Figure 2-16 folk iB walt wrt a3} he 0 500 1000 15002.5 * Modeling a Sequential Machine ‘An alternative form for a process uses wait statements instead of a sensitivity list. A process cannot have both wait statement(s) and a sensitivity list. A process with wait ‘statements may have the form process begin sequent jal-statements wait-statement sequent ial-statements wait-statement end process; This process will execute the sequential-statements until a wait statement is encountered. ‘Then it will wait until the specified wait condition is satisfied, It will then execute the next set of sequential-statements until another wait is encountered. It will continue in this manner until the end of the process is reached. Then it will start over again at the beginning of the process. ‘Wait statements can be of three different forms: wait on sensitivity-list; wait for time-expression; ‘wait until boolean-expression; The first form waits until one of the signals on the sensitivity list changes. The second form waits until the time specified by time expression has lapsed. If wait for 5 ns is used, the process waits for 5 ns before continuing, If wait for 0 ns is used, the wait is for one delta time. For the third form, the boolean-expression is evaluated whenever one of the signals in the expression changes, and the process continues execution When the expression evaluates to TRUE. For example, wait until A = B; will wait until either 4 or B changes. Then A = Bis evaluated, and if the result is TRUE, the process wiif continue; else the process will continue to wait until A or B changes again and A= Bis TRUE. ‘The following example (Figure 2-18) uses a single process with wait statements to ‘model the behavior of a Mealy sequential network. The case statement in this process is the same as in Figure 2-13. After exiting the case statement, the process waits for either the clock or X to change. If the rising edge of the clock has occurred, the state is updated. Since updating the state requires a delta time, wait for 0 ns ensures that the state is updated before the case statement is executed again. For Figure 2-18, if X changes at the same time as the rising edge of the clock, the new value of X will be used to compute the values of Mextstate and Z, and the timing waveforms will be correct. If X changes after the rising edge of the clock, Nextstate and Z will have already been computed using the old value of X. The change in X will cause Nextstate and Z to be updated again, and the timing waveforms will also be correct. In general, the two-64 Cuarrer 2 # IntroDuCTION To VHDL process model fora state machine is preferable to the one-process model, since the former ‘more accurately models the actual hardware. When we use CAD tools for automatic synthesis, constructs like wait for O ns are not allowed, In order to modify the code in Figure 2-18 to account for propagation delay in updating the state register, we could replace the if statement with if rising_edge(CLx) then state <= Nextstate after delay1; wait for de end if; However, the process then would not tespond to any change in X that occurred while waiting for delay. The state machine would still function correctly, but we might miss some glitches that occur in the output waveform. This may not be important ifthe behavioral ‘model ofthe sequential machine is used by itself just to check the output sequence; however, iff the model is used as part of a larger system, correct timing may become very important. Figure 2-18 Behavioral Model for Figure 1-17 Using a Single Process is is a behavioral model of a Mealy state machine based on puted, 7 -- its state table. The output (z) and next state are -- on the rising edge of the clock OR when the input (X) - Whe state change occurs on the rising edge of the clock. library B1TLIB use BITLTB.Bit_pack.all; entity sMi_2 is port (x, CLK: in bit 2: out pit); end sul_2; architecture Table of Sii_2 is signal State, Nextstate: integer begin proces! begin | case Stace ie when 0 i if then Nextstatec=1; end if; if then Nextstatec if; when 1 if then 3; end if; if then end if; when 2 Nextstateca4; end if; Nextstatec=4; end if; 4f X="0" then if X="1' then2.6 + Variables, Signals, and Constants 65 when 3 | ie then end if; | if then Z end i | when 4 | if then Z<= end if; | ae then 7, end if; | when 5 | if then Z<= ext ite<-0; end if; | it then Z<-'1'; Nextstatec=0; end if; | when 6 | if X-'0' then when othere -> null; end case; +) Nextstate<=0; end if; - should not occur wait on CLE, X; 4£ (rising_edge(CLx)) then - rising_edge function is in BITLIB State <= Nextstate; wait for 0 ns; -- wait for state to be updated end if; end process lend table; 2.6 VARIABLES, SIGNALS, AND CONSTANTS Up to this point, we have used only signals in processes and have not used variables Variables may be used for local storage in processes, procedures, and functions. A variable declaration has the form variable 1ist_of_va: ble_nanes : type_name [ tial_valuel; Variables must be declared within the process in which they are used and are local to that process. (An exception to this rule is shared variables, which are not discussed in this, text.) Signals, on the other hand, must be declared outside of a process. Signals declared at the start of an architecture can be used anywhere within that architecture. A signal declaration has the form signal list_of_signal_names : typename initial_ve te ‘A common form of constant declaration is constant constant_name : type_name := constant_value; A constant delay! of type time having the value of 5 ns can be defined as constant delayl time := 5 ns; Constants declared at the start of an architecture can be used anywhere within that architecture, but constants declared within a process are local to that process.Cuaerer 2 # InrRooucTION To VHDL, ‘Variables are updated using a variable assignment statement of the form variable_name := expression: ‘When this statement is executed, the variable is instantaneously updated with no delay, not even a delta delay. In contrast, consider a signal assignment of the form signal_name <= expression [after delay]; ‘The expression is evaluated when this statement is executed, and the signal is scheduled to change after delay. If no delay is specified, then the signal is scheduled to be updated after adelta delay. ‘The examples in Figures 2-19 and 2-20 illustrate the difference between using variables, and signals in a process. The variables must be declared and initialized inside the process, whereas the signals must be declared and initialized outside the process. in Figure 2-19, if trigger changes at time = 10, Var1, Var2, and Var3 are computed sequentially and updated instantly, and then Sum is computed using the new variable values. The sequence is Varl =2+3=5, Var2 = 5, Var3 = 5. Then Sum =5 +5 +5 is computed. Since Sum is a signal, it is updated A time later, so Sum = 15 at time = 10 + A. In Figure 2-20, if trigger changes at time = 10, signals Sig/, Sig2, Sig3, and Sum are all computed at time 10, but the signals are not updated until time 10 + A. The old values of Sig/ and Sig2 are used to compute Sig2 and Sig3. Therefore, at time = 10 + A, Sigi = 5, Sig2 = 1, Sig3 = 2, and Sum =6. Figure 2-19 Process Using Variables entity dummy is end dunmy: architecture var of dummy is signal tricyer, sum: integer begin process | variable varl: integer: | variable va nteger: variable var}: integer:= begin wait on trigger; varl := var2 + var3; | var? := vari; var3 r= var2; sun <= varl + var2 + var3; end proce: end var;2.6 « Variables, Signals, and Constants 67 Figure 2-20 Process Using Signals entity dummy ie end dunn architecture sig of dummy is signal trigger, sum: integer:-0; signal sigi: integer signal sig2: integer signal sig3: integer: begin wait on trigger; sigl <= sig2 + sig3; sig2 <= sigl; sig3 <= sig? sum <= sig] + sig2 + sig3; end process; lend sig: Variables, signals, and constants can have any one of the predefied VHDL types or they can have a user-defined type. Some of the predefined types are bit ‘O'or'l’ boolean FALSE or TRUE integer an integer in the range ~(2"!~ 1) to +(2!— 1) (some implementations support a wider range) real floating-point number in the range ~1.0E38 to +1.0E38 character any legal VHDL character including upper- and lowercase letters, digits, and special characters (each printable character ‘must be enclosed in single quotes; e.g.,","7,'+") time an integer with units fs, ps, ns, us, mts, sec, min, or hr Note that the integer range for VHDL is symmetrical, even though the range for a 32-bit 2's complement integer is -2*! to 4(25"— 1), ‘A.common user-defined type is the enumeration type in which all of the values are enumerated. For example, the declarations type state_type is (s0, Sl, 82, $3, Sd, signal state : state_type := 81; define a signal called state that can have any one of the viaues $0, S1, $2, $3, $4, or $5, and that is initialized to S1. If no initialization is given, the default initialization is the leftmost element in the enumeration list, SO in this example. VHDL is a strongly typed language, so signals and variables of different types generally cannot be mixed in the same assignment statement, and no automatic type conversion is performed. Thus the statement A<=B or C is valid only if A, B, and C all have the same type or closely related types.‘Cuaprer 2 Inrropuction To VHDL 2.7 ARRAYS In order to use an array in VHDL, we must first declare an array type and then declare an array object. For example, the following declaration defines a one-dimensional array type named SHORT_WORD: type SHORT_WORD is array (15 downto 0) of bit; An array of this type has an integer index with a range from 15 downto 0, and each element of the array is of type bi Next, we declare array objects of type SHORT_WORD: signal DATA_WOR SHORT_WORD; variable ALT_WORI SHORT_WORD *0101010101010101"; constant ONE_WORD: — SHORT_WORD (others => '1'}; DATA_WORD is a signal array of 16 bits, indexed 15 downto 0, which is initialized (by default) to all '0' bits. ALT_WORD is a variable array of 16 bits, which is initialized to altemating 0s and Is. ONE_WORD is a constant array of 16 bits; all bits are set to 1 by (others => '1'), Wecan reference individual elements of the array by specifying an index value, For example, ALT_WORD(0) accesses the rightmost bit of ALT_WORD. We can also specify a portion of the array by specifying an index range: ALT_WORD(5 downto 0) accesses the low-order 6 bits of ALT_WORD, which have an initial value of 010101 ‘The array type and array object declarations illustrated here have the general forms type array_type_name is array index_range of element_type; signal array_name: array_type_name [ i= initial_values ]; In the preceding declaration, signal may be replaced with variable or constant. Multidimensional array types may also be defined with two or more dimensions. ‘The following example defines a two-dimensional array variable, which is a matrix of integers with four rows and three colurnns: type matrix4x3 4s array (1 to 4, 1 to 3) of integer; variable matrixA: matrix4x3 := ((1, 2, 3), (4, 5, 6), (7, 8, 9), (49, 12, Lay); The variable matrixA, will be initialized to 1 4 7 3 6 9 01 2 ‘The array element matrixA(3, 2) references the element in the third row and second column, which has a value of 8. When an array type is declared, the dimensions of the array may be lefi undefined.2.7» Arrays 69 This is referred to as an unconstrained array type. For example, type intvec ds array (natural range <>) of integer; declares intvec as an array type that defines a one-dimensional array of integers with an unconstrained index range of natural numbers. The default type for array indices is integer, but another type may be specified. Since the index range is not specified in the unconstrained array type, the range must be specified when the array object is declared. For example, signal intvecS: intvec(1 to 5) := (3,2,6,8,1); defines a signal array named intvec5 with an index range of 1 to 5 that is initialized to 3, 2, 6, 8, 1. The following declaration defines matrix as a two-dimensional array type with unconstrained row and column index ranges: type matrix is array (natural range <>, wal range <>) of integer; ‘The VHDL code in Figure 2-21 is a behavioral model for the sequential machine of Figure 1-17(a) using arrays to represent the state and output tables. Two two-dimensional array types are defined—an integer array for the state table and a bit array for the output table. In both cases, the first index is an integer of unconstrained range, and the second index is a bit of unconstrained range. When the actual state and output tables are declared as constants, the actual index ranges are specified as 0 to 6 for the rows and ‘0’ to 't' for the two columns. Every time X or Stare changes, the state and output tables are read by the concurrent statements to determine the NextState and Z values. The State is updated on the rising edge of the clock by the process. Figure 2-21 Sequential Machine Model Using State Table entity Mi2ie port (x, CLK: dm bit; Z: out bit); end SM1_2; architecture Table of SMi_2 is type SteteTable is array (integer range <>, bit range <>) of integer; type OutTable is array (integer range <>, bit range <>) of signal State, NextState: integer | constant st: stateTable (0 to 6, '0' to ‘1") : (1,2), (3,4), (44d, (5,5b, (5¢6), (0,0), COLON: constant OT: OutTable (0 to 6, '0' to '1") := COLO, C110, COT, COLIN, CL 0D, COLD, C10); begin concurrent statements NextState <= sT(state,X); read next state from state table 2B <= OT(State,X); read output from output tableCuapren 2 # Inneoouction To VHDL | process (CLK) begin if CLE = then -- rising edge of CLK State <= NextState; end if; end proces: ‘able: Predefined unconstrained array types in VHDL include bit_vector and string, which are defined as follows: type bit_vector is array (natural range <>) of bit; type string is array (positive range <>) of character; The characters in a string literal must be enclosed in double quotes. For example, “This is a string.” is a string literal. The following example declares a constant string! of type string: constant stringl: string(1 te 29) “This string is 29 characters.” A bit_vector literal may be written either as a list of bits separated by commas or a string. For example, (1'/0''1'/1',0) and "10110" are equivalent forms. ‘The following declares a constant A that is a bit_vector with a range 0 to 5, constant A; bit_vector(0 to 5) := "iO101i"; After a type has been declared, a related subtype can be declared to inchude a subset of the values specified by the type. For example, the type SHORT_WORD, which was defined at the start of this section, could have been defined as a subtype of bit_vector: 10RD is bit_vector (15 downto 0); subtype SHORT. ‘Two predefined subtypes of type integer are POSITIVE, which includes all positive integers, and NATURAL, which includes all positive integers and 0. VHDL OPERATORS Predefined VHDL operators can be grouped into seven classes: 1. Binary logical operators: and or nand nor xor xnor 2. Relational operators: <<>> 3. Shift operators: sll srl sla sra rol ror 4. Adding operators: + — & (concatenation) 5. Unary sign operators: + — 6. Multiplying operators: * / mod rem 7. Miscellaneous operators: not abs **2.8 * VHDL Operators m1 When parentheses are not used, operators in class 7 have highest precedence and are applied first, followed by class 6, then class 5, etc. Class 1 operators have lowest precedence and are applied last. Operators in the same class have the same precedence and are applied from left to right in an expression, The precedence order can be changed by using parentheses. In the following expression, A, B, C, and D are bit_vectors: (A & not B or C ror 2 and dD) = "110010" ‘The operators are applied in the order: not, &, ror, or, and, If A="I10", B= "111", C= "011000", and D = "111011", the computation proceeds as follows: not B = "000" (bit-by-bit complement) A & not B = "110000" (concatenation) C ror 2= "000110" (rotate right 2 places) (A & not B) or (C ror 2)="110110. (bit-by-bit or) (A & not B or C ror 2) and D= "110010" (bit-by-bit and) [(A & not B or C ror 2 and D) ="110010"] = TRUE (the parentheses force the equality test to be done last and the result is TRUE) The binary logical operators (class 1) as well as not can be applied to bits, booleans, bit_vectors, and boolean_vectors. The class 1 operators require two operands of the same type, and the result is of that type. The result of applying a relational operator (class 2) is always a boolean (FALSE or ‘TRUE). Equals (=) and not equals (/=) can be applied to almost any type. The other relational ‘operators can be applied to any numeric or enumerated type as well as to some array types. For example, if A = 5, B=4, and C=3, the expression (A >= B) and (B <= C) evaluates to FALSE. ‘The shift operators can be applied to any bit_vector or boolean_vector. Inthe following, examples, A is a bit_vector equal to "10010101 Asil2_ is "01010100" (shift left logical, filled with '0') Asrl3_ is "00010010" (shift right jogical, filled with 0) Asla3 is "JO101I11" (shift left arithmetic, filled with right bit) Asra2 is "11100101" (shift right arithmetic, filled with left bit) Arol3 is "10101100" (rotate left) Aror5 is "10101100" (rotate right) The + and — operators can be applied to integer or real numeric operands. The & ‘operator can be used to concatenate two vectors (or an clement and a vector, or two elements) to form a longer vector. For example, "010" & 'I' is “O101" and "ABC" & "DEF" is "ABCDEP". The * and / operators perform multiplication and division on integer or floating- point operands. The rem and mod operators calculate the remainder and modulus for integer operands. The ** operator raises an integer or floating-point number to an integer power, and abs finds the absolute value of a numeric operand,|zz Chaprer 2 # InrRopucTiON To VHDL. 9 VHDL FUNCTIONS A function executes a sequential algorithm andreturns a single value to the calling program. ‘When the following function is called, it returns a bit vector equal to the input bit vector (reg) rotated one position to the right: function rotate_right (reg: bit_vector) return bit_vector is begin return reg ror 1; end rotate right; A function call can be used anywhere that an expression can be used, For example, if A= "10010101", the statement B <= rotate_right (A): would set B equal to "11001010", and leave A unchanged. ‘The general form of a function declaration is function function-name (formal-paraneter-1ist) return return-type 4e [declarations] begin sequential statements -- must include return return-value; end function-name; ‘The general form of a function call is function_name (actual-parameter-list} ‘The number and type of parameters on the actual-parameter-list must match the formal- parameter-list in the function declaration. The parameters are treated as input values and cannot be changed during execution of the function. ‘The function defined in Figure 2-22 uses a for loop. The general form of a for loop is lnesp-label:] for ioop-index in range loop sequential statements end loop (loop-lebel] ; The loop-index is automatically defined when the loop is entered, and it should notexplicitly be declared. Itis initialized to the first value in the range and then the sequential statements are executed. The loop-index can be used within the sequential statements, but it cannot be changed within the loop. When the end of the loop is reached, the loop-index is set to the next Value in the range and the sequential statements are executed again, This process continues until the loop has been executed for every value in the range, and then the loop2.9 * VHDL Functions 7a} terminates, After the loop terminates, the loop-index is no longer available. In Figure 2- 22, the loop index (i) will be initialized to 0 when the for loop is entered, and the sequential statements will be executed. Execution will be repeated for i = 1, i= 2, and i= 3; then the loop will terminate. ‘An exit statement of the form exit; or exit when condition: may be included in the loop. The loop will terminate when the exit statement is executed, provided that in the second case, the condition is TRUE. Figure 2-22 Add Function 8 and a carry ion adds 2 4-bit vect: This func -- It rng a S-bit sum function add4 (A,8: bit_vector(3 downto 0); carry: bit) return bit_vector ie variable cout: bit; variable cin: bit := carry: variable sum: bit_vector (4 downte 6) :="00000"; pl: for i in 0 to 3 loop cout t= (A(i) and Bi)) or (Ali) and cin) or (B(i) and cin); sum(i) := A(i) xor B(i) xor cin; cin := cout; end loop loop1; sum(4):= cout; return sum; . end add IfA, B, and C are integers, the statement C<=A +B will set C equal to the sum of A and B. However, if A, B, and C are bit_vectors, this statement will not work, since the “4” operation is not defined for bit_vectors. However, we can write a function to perform bit_vector addition. The function given in Figure 2-22 adds two 4-bit vectors plus a carry and returns a 5-bit vector as the sum. The function name is add4, the formal parameters are A, B, and carry, and the return-type is bit_vector. Variables cout and cin are defined to hold intermediate values during the calculation. The variabie sum is used to store the value to be returned. When the function is called, cin will be initialized to the value of the carry. ‘The for loop adds the bits of A and B serially in the same manner as a serial adder. The first time through the loop, cout and swm(0) are computed using A(0), B(Q), and cin. Then the Cin value is updated to the new cout value, and execution of the loop is repeated. The second time through the loop, cout and sum(1) are computed using A(1), B(1), and the new: cin. After four times through the loop, all values of swm(i) have been computed and sum is returned. The total simulation time required to execute the add4 function is zero. Not even74 Cupra 2 © Inrrooucion 10 VHDL delta time is required, since all the computations are done using variables, and variables are updated instantaneously. The function call is of the form add4( A, B, carry } A and B may be replaced with any expressions that evaluate to bit_vectors with dimensions 3 downto 0, and carry may be replaced with any expression that evaluates to a bit, For example, the statement Z <= add4(x, not ¥, '1'); calls the function add4. Parameters A, B, and carry are set equal to the values of X, not ¥, and"1’, respectively. X and ¥ must be bit_vectors dimensioned 3 downto 0, The function computes Sum=A4 B+ carry =X-+ not ¥+'l! and returns this value. Since Sum is a variable, computation of Sum requires zero time. Afier delta time, Zis set equal 10 the retumed value of Sum. Since not ¥+'l' equals the 2's complement of ¥, the computation is equivalent to subtracting by adding the 2’s complement. i we ignore the carry stored in Z(4), the result is 23 downto 0) = X ~ ¥. Functions are frequently used to do type conversions. The function vec2ini(birvec) accepts a bit_vector as input and returns the corresponding integer value. The function int2vec(int,N) accepts two positive integers as inputs and converts int to a bit_vector of length N. We have written these functions in a general manner so that the bit_vector can be of any length (see Chapter 8) and placed them in the bit_pack package in the BITLIB library. 2.40 VHDL PROCEDURES Procedures facilitate decomposition of VHDL code into modules. Unlike functions, which return only a single value through « return statement, procedures can return any number of values using output parameters. The form of « procedure declaration is procedure procedure_name (formal-parameter-list) 18 [declarations] begin sequential statenents end procedure-name; ‘The formal-parameter-list specifies the inputs and ourputs tothe procedure and their types. A procedure call is a sequential or concurrent statement of the form procedure_name (actual-parameter-list) ;2.10 © VHDL Procedures 75 As an example we will write a procedure Addvec,which will add two N-bit vectors and a carry, and return an N-bit sum and a carry, We will use a procedure call of the form Addvec ( A, B, Cin, Sum, Cout, N); where A, B, and Sum are N-bit vectors, Cin and Cour are bits, and N is an integer. Figure 2-23 gives the procedure definition, Addi, Add2, and Cin are input parameters, and Swm and Cout are output parameters, N is a positive integer that specifies the number of bits in the bit_vectors. The addition aigorithm is essentially the same as the one used in the addé function. C must be a variable, since the new value of C is needed each time through the loop; however, Sum can be a signal since Sum is not used within the loop. ‘After N times through the loop, all the values of the signal Sum have been computed, but ‘Sum is not updated until delta time after exiting from the loop. Figure 2-23 Procedure for Adding Bit_vectors ‘This procedure adds two n-bit bit_vectors and a carry and returns an n-bit sum and a carry. Addl and Add? are assumed to be of the same length and dimensioned n-1 downto 0. procedure Addvec (Add1,add2: dm bit_vect! cin: im bit; signal Sum: out bit_vector; signal Cout: out bit; nid positive) is variable C: b: begin C := Cin; for i in 0 to n-1 loop Sum(i) <= Addi (i) xor Adé2(i) xox C; C t= (Addi (i) and Add2(i)) or (Add1(i) and c) or (Add2/i) and cy; ‘end loop. Cout <= end Addvec; Within the procedure declaration, the class, mode, and type of each parameter must be specified in the formal-parameter-list. The class of each parameter can be signal, variable, or constant. If the class is omitted, constant is used as the default. Ifthe class is a signal, then the actual parameter in the procedure call must be a signal of the same type. Similarly, for a formal parameter of class variable, the actual parameter must be a variable of the same type. However, for a constant formal parameter, the actual parameter can be any expression that evaluates to a constant of the proper type. This constant value is used inside the procedure and cannot be changed; thus a constant formal parameter is always of mode in. Signals and variables can be of mode in, out, or inout. Parameters of mode ‘out and inout can be changed in the procedure, so they are used to return values to the caller.76 ‘Cyapter 2 InrkopucTion ro VHDL Inprocedure Addvec, parameters Add] , Add2, and Cin are, by default, of class constant. ‘Therefore, in the procedure call, Add/, Add2, and Cin can be replaced with any expressions that evaluate to constants of the proper type and dimension, Since Sum and Cout change within the procedure and are used to return values, they have been declared as class signal, Thus, in the procew.re call, Sum and Cout can be replaced only with signals of the proper type and dimension. ‘The formal-parameter-list in a function declaration is similar to that of a procedure, except parameters of class variable are not allowed, Furthermore, all parameters must be of mode in, which is the default mode. Parameters of mode out or inout are not allowed, since a function returns only a single value, and this value cannot be returned through parameter. Table 2-1 summarizes the modes and classes that may be used for procedure and function parameters. Table 2-1. Parameters for Subprogram Calls, ‘Actual Parameter Procedure Call [Function ‘constant expression ‘expression signal signal signal variable variable wa ouvinout } — signat signal nla variable? variable wa + default mode for functions ? default for in mode 3 default for out/inout mode 2.414 PACKAGES AND LIBRARIES Packages and libraries provide a convenient way of referencing frequently used functions and components. A package consists of a package declaration and an optional package body. The package declaration contains a set of declarations, which may be shared by several design units. For example, it may contain type, signal, component, function, and procedure declarations. The package body usually contains the function and procedure bodies. The package and its associated compiled VHDL models may be placed in a library so they can be accessed as required by different VHDL designs. A package declaration has the form package package-name is package declaration end [package] [package-name) ; A package body has the form Package body package-name is package body declarations end [package body} [package name] ;2.11 # Packages and Libraries 7| We have developed a package called bit_pack that is used in a number of examples in this book. This package contains commonly used components and functions that use signals of type bit and bit_vector. Appendix B contains a complete listing of this package and associated component models. Most of the components in this package have a default delay of 10 ns, but this delay can be changed by use of generics, as explained in Section 8.6. We have compiled this package and the component models and placed the result in a library called BITLIB. (One of the components in the library is a two-input NAND gate named Nand2, which has default delay of 10 ns. The package declaration for bit_pack includes the component declaration component Nand2 generic (DELAY : time := 10 ns) port (Al, A2 : in bit; % : out bit); end component ; ‘The NAND gate is modeled using a concurrent statement. The entity-architecture pair for this component is, -- 2-input NAND gate entity Nand? is generic (DELAY : time) port (Al, A2 : in bi Z + out bit); end Nand2; architecture concur of Nand2 is begin 2 <= not (Al and A2) after DELAY; end; To access components and functions within a package requires a library statement and a use statement. The statement library BITLIB; allows your design to access the BITLIB. The statement UIB-bit_pack.a ick package, A statement of the form allows your design to use the entire bit_ use BITLIB.bit_pack.Nand2; ‘may be used if you want to use a specific component or function in the package.