ELEC 2441 - Computer

Organization and Microprocessors

(Lecture Note #3: Instructions of the ARM

Assembly)

by Dr. Vincent TAM

* Ref: Chapter 2 of “Computer Organization & Design : The

Hardware/Software Interface – ARM Edition”, David A.
Patterson & John L. Hennessy, Morgan Kaufmann
Publishers, 2018.

Today’s Quote

The most beautiful thing we can experience is the mysterious.

It is the source of all true art and science.

- Albert Einstein, What I Believe, 1930.

Chapter 3 1
3. Instructions of the ARM Assembly

Learning Outcomes:

¨ Introduction of An Instruction Set;

¨ Basic Operations of the ARM Assembly
Language;
¨ Operands of the ARM Assembly Language;
¨ Signed and Unsigned Numbers;
¨ Logical Operations of the ARM Assembly.

** Remark : all the subsequent sample programs are

based on the latest VisUAL2 ARM simulator (URL :
https://tomcl.github.io/visual2.github.io/) in which
semi-colon (;) is used to start a comment line.

Chapter 3 2
 • The VisUAL2 ARM simulator is a cross-platform
and user-friendly educational tool that make it
very easy for beginners to write small and
medium-sized ARM assembler programs;

• The VisUAL2 simulator will run on Microsoft

Windows, Mac OS-X and Linux, and is
distributed as binaries;

• To install the VisUAL2 (v1.06.9), simply

download the latest binary release from:

https://github.com/tomcl/V2releases

and then follow the detailed instructions of the

above website to complete the installation
procedure;

• Besides, the following website may contain

other latest information/doc together with
various binary releases:

https://scc416.github.io/Visual2-doc/download

Chapter 3 3
3.1 Introduction of An Instruction Set

“It is easy to see by formal-logical methods that

there exists certain [instruction set] that are in
abstract adequate to control and cause the execution
of any sequence of operations…The really decisive
considerations from the present point of views, in
selecting an [instruction set], are more of a
practical nature: simplicity of the equipment
demanded by the [instruction set], and the clarity of
its application to the actually important problems
together with the speed of its handling of these
problems.”
Burks, Goldstine, and von Neumann, 1947

o Words of a computer language are “instructions”

and its vocabulary is called “an instruction set”;
o The goal of any “instruction set” is to demonstrate
the simplicity of the equipment;
o By learning an “instruction set” and its
underlying H/W, one may discover the “stored-
program concept” (as invented by von Neumann).
The idea is that instructions and data of many

Chapter 3 4
 types can be stored in memory as numbers,
leading to the stored-program computers;
o The ARM Assembly Language (or Instruction
Set) : the most popular 32-bit instruction set in the
world with 4 billion ARM processors shipped in
2008, 15 billion shipped in 2015, and upto 21.3
billion in 2017.

Chapter 3 5
3.2 Basic Operations of the ARM Assembly
Language
“There must certainly be instructions for performing the
fundamental arithmetic operations.”

Burks, Goldstine, and von Neumann, 1947

o Basically, each ARM arithmetic instruction

performs only one operation (such as addition or
subtraction) and must always have exactly 3
variables (i.e. 3-operand instructions):

ADD a, b, c

§ The natural number of operands for any binary

arithmetic operation like addition is 3: adding
the 2nd and 3rd operands to put their sum (s =
b+c) to the 1st (destination) operand (a).
§ Requiring each arithmetic instruction to have
exactly 3 operands, no more and no less,
conforms to the first H/W design principle of
“simplicity favors regularity” to keep the H/W
simple: in general, H/W for a variable no. of
operands is always more complicated than H/W
for a fixed no. of operands.

Chapter 3 6
 o A high-level C, C++ or Java statement will always
be compiled into several ARM instructions.

Consider the following C or Java statement:

a = b + c + d + e;

that will be compiled / translated into the following

3 ARM instructions:
ADD a, b, c; The sum of b and c is placed in a
ADD a, a, d; The sum of b, c & d is now in a
ADD a, a, e; The sum of b, c, d & e is now in a

Note : the word to the right of the semi-colon (;)

until the end of each line are comments for human
readers to understand, the computer simply ignore
such comments.

Ø Other than arithmetic and (binary) logical

operations [AND/OR], the ARM assembly
language also has other instructions requiring
2 or 1 operand only. Examples include the
MOV instruction for data transfer and the
unconditional (always) branch instruction as
below:
MOV r1, r2; Copying the value of r2 to r1 (r1 =
r2)

Chapter 3 7
 B 2500; unconditional branch to [PC] + 8 +
(2500 words*4)

Below is an example of a complete and very simple

ARM assembly program named “simple.s” to load
two integers (of 100 & 200 in decimal) into register
r1 & r2 and then use to compute r3 & r4
respectively:
Num1 DCD 100

Num2 DCD 200

LDR r0,=Num1 ; load addr of Num1 into r0

LDR r1, [r0,#0] ; load the value of Num1 into r1

LDR r2, [r0,#4] ; load the value of Num2 into r2

ADD r3, r1, r2 ; r3 = r1 + r2

SUB r4, r3, r1 ; r4 = r3 - r1

END

After invoking the VisUAL2 ARM simulator

(installable on MS Windows/MacOS/Linux),
loading the “simple.s” program, and clicking on
the “run” button, the following output window will
be generated on the MacOS:

Chapter 3 8
After this simple assembly program is executed,
r0 = $200 (i.e. address of the Num1 integer);
r3 = Num1 + Num2 = $64 (= 100 in decimal) + $c8 = $12c
r4 = r3 – r1 = $12c - $64 = $c8

The instruction END will stop the program execution and

then return the control back to the underlying O.S.

Chapter 3 9
3.3 Operands of the ARM Assembly Language
1) Registers
o Registers are the most primitive and frequently used
operands in any assembly program;
o The size of a register in the ARM architecture is 32
bits, with groups of 32 bits (i.e. 4 bytes) forming a
computer word for an ARM processor;
o The various versions / generations of ARM
processors have different number of registers
(typically 16 to 32 registers on current computers).
For consistency and backward compatibility with
most ARM processors, we simply assume the limit of
16 registers in all the following discussion.
o Effective uses of all these 16 registers (named as r0,
r1,…, r15 ) is very critical to the overall program
performance !
§ An example of compiling a C assignment
statement to a ARM program using registers:

For the following C assignment statement,

f = (g + h) – (i + j);
assuming that the values of g, h, i, j and f are
already loaded into the registers r0, r1, r2, r3 and
r4.

Chapter 3 10
 The following ARM instructions would achieve the
same assignment task:
ADD r5, r0, r1; register r5 contains g+h
ADD r6, r2, r3; register r6 contains i+j
SUB r4, r5, r6; register r4=r5-r6 = (g+h) – (i+j)

2) Memory Operands
o Simple variables may contain single data elements (as
the Num1 in the above “simple.s” in Sec. 3.2) or more
complex data structures like arrays and structures;
o In either case, values are preloaded into specific
memory addresses that will be used as “memory
operands” in the relevant assembly language;
o ARM must include instructions to transfer data
between the memory and registers. Such instructions
are called data transfer instructions that will include
the memory addresses of any single data / array
element as its “memory operand”;
o The data transfer instructions in ARM to transfer a
data from the main memory to a register is called
“load” (LDR – load word into register) whereas the
instruction to transfer from a register to memory
address is called “store”) (STR – store word from a
register);
o As each computer word is 32-bit (i.e. 4 bytes), the
ARM processors address each sequentially stored

Chapter 3 11
 computer word with a difference of 4 bytes in the
main memory as shown in the following diagram.
… …
12 100
8 10
4 100
0 1
Byte Content
Address (Data)
ARM Processor
Memory

üConsidering the example program “simple.s” in

which the memory address ($1018) of Num1 (an
integer) is “loaded” as the base address thru the
instruction LDR into r0 (as the base register), its
value is loaded into r1 with the operand address
specified as [base register, offset] = [r0, #0]
meaning an offset (or distance) of 0 byte from the
base address held by r0 as below.
LDR r0, =Num1 ; load addr of Num1 into r0
LDR r1, [r0,#0] ; load the value of Num1 into r1
LDR r2, [r0,#4] ; load the value of Num2 into r2

Similarly, the operand address of Num2 is

specified as [r0, #4] meaning an offset (or
distance) of 4 byte (as the next computer word)
from the base address held by R0 in the above.

Chapter 3 12
 üLet’s consider another example with an array
named A with its base address already loaded into
r3, to load the value of A[8] from the main
memory into the register r5 of an ARM processor,
one may specify the following ARM instruction:
LDR r5, [r3,#32] ; Temp. reg. r5 gets A[8]

üIn ARM, words must start at addresses that are

multiples of 4. This requirement is called an
alignment restriction;
üIn general, computers are divided into 2
categories according to their byte
addressing/ordering:
1) big-endian machines using the address of
the leftmost or “big-end” byte as the word
address. Most mainframes like the IBM
z/Architecture or mini-computers are big-
endian;
2) little-endian machines using the address of
the rightmost or “little-end” byte as the word
address. The ARM and Intel x86 computers
are little-endian.
üAs mentioned before, the ARM instruction STR is
to “store word from a register”. The format of
STR is similar to that of LDR, i.e. the instruction
followed by the register to be stored and then the

Chapter 3 13
 operand address specified as [base register, offset].
For the following C assignment statement
A[12] = h + A[8];
assume r2 stores the value of h, and the base
register r3 holds the base address of A[0], the
above C statement can be compiled into the
following 3 ARM instructions
LDR r5, [r3,#32] ; temp. reg. r5 gets A[8]
ADD r5, r2, r5 ; r5 gets h+A[8]
STR r5, [r3,#48] ; store the result from r5
to A[12]

üLoad word and store word are the instructions to

copy words between memory and registers in the
ARM architecture;
üRegisters take less time to access and have higher
throughput than memory, making data in
registers both faster to access and simpler to use;
üTo achieve the highest overall performance and
conserve energy, compilers must use registers
efficiently.

Chapter 3 14
3) Constant (or Immediate) Operands
o An ARM assembly program may use a constant in
various operations, e.g. to specify the offset part of a
targeted address as below.
LDR r5, [r1,#8] ; r1+8 is the address of a constant
4 to load into r5
ADD r3, r3, r5 ; r3 = r3 + 4
o To avoid using the LDR instruction in the above
example, an alternative way is to have one operand
of the arithmetic instruction (like ADD) be a
constant, called an immediate operand as below.

ADD r3, r3, #4 ; r3 = r3 + 4

üNOTE: the sharp or hash symbol (#) indicates

the following number is a constant in the above
operation.

Chapter 3 15
Below are useful summaries of ARM operands
and instructions
a) ARM operands
Name Example Comments
16 registers r0,r1,r2,….,r11,r12, sp, lr, Fast storage
pc for data. In
ARM, data
must be in
registers to
perform
arithmetic.
232 (~ 4G) Memory[0],Memory[4],…, Accessed only by
memory Memory[4294967292] data transfer
instructions. ARM
addresses
uses byte addresses
(i.e. each address
holds 1 byte), so
sequential word
addresses differ by
4. Memory holds
data structures,
arrays, and spilled
registers.

Chapter 3 16
 b) ARM instructions
Category Instruction Example Meaning Comments
add ADD r1, r2, r3 r1 = r2 + r3 3 register
Arithmetic operands

subtract SUB r1, r2, r3 r1 = r2 - r3 3 register

operands

load register LDR r1, [r2, #20] r1 = Memory[r2+20] Word from

memory to
register
Data Transfer store register STR r1, [r2, #20] Memory[r2+20]=r1 Word from
register to
memory

load register halfword LDRH r1, [r2, #20] r1 = Memory[r2+20] Halfword (2

bytes) from
memory to

register

load register halfword LDRHS r1, [r2, r1 = Memory[r2+20] Halfword

signed #20] from

memory to
register

store register halfword STRH r1, [r2, #20] Memory[r2+20]=r1 Halfword

from register
to memory

load register byte LDRB r1, [r2, #20] r1 = Memory[r2+20] Byte from
memory to
register

Chapter 3 17
 load register byte LDRBS r1, [r2, r1 = Memory[r2+20] Byte from

signed #20] memory to

register

store register byte STRB r1, [r2, #20] Memory[r2+20]=r1 Byte from
register to
memory

swap SWP r1, r2, [r0] r1 = Memory[r0], Atomic swap

Memory[r0] = r2 register &

memory

move MOV r1, r2 r1 = r2 Copy value

into register

Logical and AND r1, r2, r3 r1 = r2 & r3 3 reg.

operands;
bit-by-bit
AND

or ORR r1, r2, r3 r1 = r2 | r3 3 reg.

operands;
bit-by-bit OR

not MVN r1, r2 r1 = ~ r2 2 reg.

operands;
bit-by-bit
NOT

logical shift left LSL r1, r2, #10 r1 = r2 << 10 Shift left by
(optional operation) constant

logical shift right LSR r1, r2, #10 r1 = r2 >> 10 Shift right by
(optional operation) constant

Chapter 3 18
 Conditional compare CMP r1, r2 cond. flag = r1 – r2 Compare for

Branch conditional
branch

branch on EQ, NE, BEQ 25 if (r1 == r2) go to PC Conditional

LT, LE, GT, GE, LO, + 8 + 100 test; PC-
LS, HI, HS, VS, VC, relative

MI, PL

Unconditional branch (always) B 250 go to PC + 8 + 250*4 Branch

Branch branch and link BL 250 r14 = PC+4 (return For
address); go to PC + procedure
8 + 250*4 call

Chapter 3 19
3.4 Signed and Unsigned Numbers

ü In general, for any number base (B), the value of

i-th digit d is : d × B i
where i starts from 0 and increases from right to
left;
ü Therefore, the following binary number
10112 = (1 × 2 3) + (0 × 2 2) + (1 × 2 1) + (1 × 2 0)
= 1110
ü The following diagram shows the labeling of 32
bits within an ARM word
31…28 27…24 … … … … 7654 3210
0000 0000 … … … … 0000 0000
MSB LSB
The least significant bit (LSB = bit 0) refers to the
rightmost bit whereas the most significant (MSB
= bit 31) is the leftmost bit.
ü When an ARM word (of 32 bits) is used to
represent an unsigned integer, the range of values
is from 0 to 232-1 (i.e. 0 ….4,294,967,295 ~ 4.3G) as
below.
0000 0000 0000 0000 0000 0000 0000 0000 = 010
0000 0000 0000 0000 0000 0000 0000 0001 = 110
…
1111 1111 1111 1111 1111 1111 1111 1110 =
4,294,967,29410

Chapter 3 20
 1111 1111 1111 1111 1111 1111 1111 1111 =
4,294,967,29510

ü Computers handle both +ve and –ve integers (i.e.

signed integers). When the MSB (bit 31) is used to
represent the sign (i.e. 0 = +ve or 1 = –ve) with the
remaining 31 bits (bit 0 – 30) denoting the
magnitude, the representation scheme is called
sign-and-magnitude. Clearly, the size of the range
of the +ve OR –ve integers is half (4,294,967,296 /
2 = 2,147,483,648 = 231) of that of the original range
for unsigned integers. Thus, its range of
-ve and +ve integers is :
-(231- 1)….-0,+0,…., +(231- 1)
ü To avoid the shortcoming of both -0 and +0 in sign-
and-magnitude scheme, the ARM computers adopt
the 2’s complement scheme to denote the signed
integers as in most modern computers;
ü Under the 2’s complement scheme, when the sign
bit (bit 31) = 0 denoting a +ve integer, its value is
simply the magnitude (i.e. summing up all the
values of bit 0 – 30 = ∑"# !
!$# 𝑏! × 2 ). Yet when the
sign bit = 1 denoting a –ve integer, its actual value
is obtained by flipping the bit pattern of bit 0 – 30
to its opposite (= 1’s complement ) and then adding
1 to it, e.g. 1000 0000 … 0000 0000 =
-(01111 1111 … 1111 1111 + 1) = - 231
Chapter 3 21
 = -2,147,483,64810

Thus, the range of a 32-bit signed integer in any

ARM architecture is: -(231)….-1,0,…., +(231- 1)
that can be represented as follows.
0000 0000 0000 0000 0000 0000 0000 0000 = 010
0000 0000 0000 0000 0000 0000 0000 0001 = 110
…
0111 1111 1111 1111 1111 1111 1111 1111 = 2,147,483,64710
1000 0000 0000 0000 0000 0000 0000 0000 = -2,147,483,64810
1000 0000 0000 0000 0000 0000 0000 0001 = -2,147,483,64710
….
1111 1111 1111 1111 1111 1111 1111 1110 = -210
1111 1111 1111 1111 1111 1111 1111 1111 = -110

ü Since the sign bit (bit 31) is the determining bit to

represent a +ve or –ve integer, we may actually
calculate the value of any +ve or –ve integer
under the 2’s complement scheme using the
following expression.

(b31 × -2 31) + (b30 × 2 30) +….+ (b1 × 2 1) + (b0 × 2 0)

Essentially the sign is multiplied by -2 31, and then

the rest of the bits are then multiplied by positive
versions of their respective base values.

Chapter 3 22
 § An example: The following 32-bit signed integer
(represented in the 2’s complement format) was
loaded from a specific memory location to the
register r2 of an ARM processor. What’s the
decimal value of this 32-bit signed integer?

1111 1111 1111 1111 1111 1111 1111 11002

Answer: substituting the signed integer’s bit

values into the above expression:

(b31 × -2 31) + (b30 × 2 30) +….+ (b1 × 2 1) + (b0 × 2 0)

= (1 × -2 31) + (1 × 2 30) +….+ (1 × 2 2)+ (0 × 2 1) +
(0 × 2 0)
= -2 31 + 2 30 +….+ 2 2 + 0 + 0
= -2,147,483,648 + 2,147,483,644
= -4

ü Sign extension technique: to convert a signed

integer of n bits (under the 1’s or 2’s complement
scheme) to a number with more than n bits – without
changing its magnitude, the shortcut technique is to
take the MSB (sign bit) from the smaller quantity
and “extend” it to fill the new bits of the larger
quantity, thus the name “sign extension”! For
example, the immediate field in the load, store,

Chapter 3 23
 branch, ADD instructions contain a 2’s
complement 16-bit value, ranging from
-32,768 (-2 15) to 32,767 (+2 15-1). To add this
immediate value to a 32-bit register, the ARM
processor must convert this 16-bit 2’s complement
integer into its 32-bit equivalent as follows.
§ An example: Assume the 16-bit signed integer is
0000 0000 0000 11002 = 1210

To convert the 16-bit signed integer to a 32-bit

register, the sign bit (0) is extended/repeated to fill
up all extra 16 bits (i.e. bit 16 – 31) of the register
value to keep its value unchanged:

0000 0000 0000 0000 0000 0000 0000 11002 = 1210

§ Yet another example: Assume the 16-bit signed

integer is: 1111 1111 1111 01002 = -1210

To convert the 16-bit signed integer to a 32-bit

register, the sign bit (1) is extended/repeated to fill
up all extra 16 bits (i.e. bit 16 – 31) of the register
value to keep its value unchanged:

1111 1111 1111 1111 1111 1111 1111 01002 = -1210

Chapter 3 24
 ü Overflow : the ALU of any computer, including the
ARM architecture, is designed to perform binary
arithmetic like add, subtract, multiply, and divide
on signed/unsigned integers. When the result of
such operation cannot be represented by all the
H/W bits (say the 32 bits of an ARM register),
overflow occurs. In general, it’s up to the
programming language, the O.S., and the program
to decide what to do if overflow occurs;
ü Specifically for the 2’s complement scheme, when
overflow occurs, the sign bit is incorrect. That is :
sign bit = 0 when the signed integer is actually –ve
or sign bit = 1 when the signed integer is +ve.

3.5 Logical Operations of the ARM Assembly

ü These group of ARM instructions (like
AND/ORR/MVN) operate on fields of bits within a
word or even on individual bits are called logical
operations;

Chapter 3 25
 ü The following table shows the C and Python
logical operators with their corresponding ARM
instructions:
Logical C Python ARM
operations operators operators instructions
Bit-by-bit & & AND
AND
Bit-by-bit | | ORR
OR
Bit-by-bit ~ ~ MVN
NOT
Shift left << << LSL
Shift right >> >> LSR
§ For example, if r1 contains
1111 0000 1111 0000 1111 0000 1111 01102
and r2 contains
0000 1111 0000 1111 0000 1111 0000 11102

After executing the ARM instruction

AND r5, r1, r2 ; reg. r5 = r1 & r2

The value of r5 would be:

0000 0000 0000 0000 0000 0000 0000 01102

Chapter 3 26
 Yet for the following ARM instruction
ORR r5, r1, r2 ; reg. r5 = r1 | r2

The value of r5 would be:

1111 1111 1111 1111 1111 1111 1111 11102

ü Another class of the logical operations is the logical

/ arithmetic shifts: LSL – logical shift left or LSR –
logical shift right, that is moving the bits in a word
to the left or right, and filling the emptied bits with
0’s. Shifting left / right by n bits is equivalent to
multiplying / dividing it by 2n.

§ For example, if r0 contains

0000 0000 0000 0000 0000 0000 0000 01102
=610

After executing an LSL instruction to shift it

left by 4 bits

The value of r0 should be:

0000 0000 0000 0000 0000 0000 0110 00002
=9610 = 6 × 24

Chapter 3 27
 ü In ARM, shift operations are NOT separate
instructions. Typically, they are bundled with
other microprocessor instruction set. That is ARM
offers the ability to shift the 2nd operand as part of
any data processing (DP) instruction!

§ For instance, the following variant of the

ADD instruction will firstly shift the 2nd
register operand r2 to left by 2 bits before
adding with r1 and storing the result to r5

ADD r5, r1, r2, LSL #2; r5 = r1 + (r2 << 2)

Similarly, these 2 variants of the MOV

instruction will shift register r5 right by 4
bits or the number of bits as stored in r3
before placing the result to r6 as the
destination.

MOV r6, r5, LSR #4; r6 = (r5 >> 4)

MOV r6, r5, LSR r3; r6 = (r5 >> r3)

Chapter 3 28
Summary:
¨ The ARM Assembly Language (or Instruction Set) is the most
popular 32-bit instruction set with its simplicity & efficiency as
based on the stored-program concept.

¨ Basic ARM instructions include the fundamental operations for

arithmetic (ADD/SUB) and (binary) logical operations [AND/OR]
typically requiring 3 operands. Besides, the ARM assembly
language also has other instructions requiring 2 or 1 operand only.
Examples include the MOV instruction for data transfer and the
conditional / unconditional branch instructions to control the
program flow.

¨ ARM allows 3 major operand types including: register operands,

memory operands & constant operands to be used in various
instructions.
o Registers (including 16 registers as r0….r12, sp, lr, pc) are the
most common and frequently used operands in many ARM
instructions;
o Memory operands can be used to hold simple variable values
or data structures such as arrays (base address + offset) or
linked lists. They are often used in many data transfer
instructions (like LDR – load word into register or STR – store
word from a register) to transfer data between the memory
and registers. Each computer word (as integers, instructions
or other data values) in ARM is 32 bits (i.e. 4 bytes)
sequentially stored as 4 consecutive bytes in the main
memory. Thus, it is important to notice that with the base
address of an array as v, to access v[i] as the i-th integer/word,
the address of v[i] = v + i * 4 (i.e. in multiples of 4 bytes);
o Constant operands: a constant (to be specified as #c) can be
used in various ARM instructions. An example is to specify

Chapter 3 29
 the “constant” offset as in “LDR r0, [r1, #8]” for a fixed offset
of 8 bytes from the base address stored in r1.

¨ When an ARM word (of 32 bits) is used to represent an unsigned integer,

the range of values is from 0 to 232-1 (i.e. 0 ….4,294,967,295 ~ 4.3G).
With the leading sign for sign and the remaining 31 bits for
magnitude/value, the sign-and-magnitude has its range of -ve and +ve
integers as : -(231- 1)….-0,+0,…., +(231- 1). To avoid the shortcoming of
both -0 and +0 in sign-and-magnitude scheme, the ARM computers
adopt the 2’s complement scheme with the range of:
-(231)….-1,0,…., +(231- 1) to denote any signed integer as
(b31 × -2 31) + (b30 × 2 30) +….+ (b1 × 2 1) + (b0 × 2 0).
Basically, for any signed integers,
o Sign extension concerns about extending a signed integer of n
bits (under the 1’s or 2’s complement scheme) to a number with
more than n bits – without changing its magnitude. The shortcut
technique is to take the MSB (sign bit) from the smaller quantity
and “extend” it to fill the new bits of the larger quantity, thus
the name “sign extension”!
o When the result of such operation cannot be represented by
all the H/W bits (say the 32 bits of an ARM register), overflow
occurs.

¨ ARM instructions (like AND/ORR/MVN) operate on fields of bits

within a word or even on individual bits are called logical
operations. In ARM, shift operations are NOT separate instructions.
Typically, they are bundled with other microprocessor instruction
set. That is ARM offers the ability to shift the 2nd operand as part of
any data processing (DP) instruction. For example, shifting the 2nd
register operand r2 to left by 2 bits (i.e. = r2 × 4) before adding with
r1 and storing the result to r5 as in the following ADD instruction:
ADD r5, r1, r2, LSL #2; r5 = r1 + (r2 << 2)
~~~~~~End of Lecture Note #3 ~~~~~~~~

Chapter 3 30