International Journal of Advanced Research in

ISSN : 2347 - 8446 (Online) International Journal of Advanced Research

ISSN : 2347 in
- 8446 (Online)
Computer Science
ISSN : 2347 - 9817 Vol. 2, Issue
(Print) & Technology 2, Ver.2014)
(IJARCST Vol.
2 (April - June 2, Issue 2, Ver.Computer
2014) 3 (April Science
- June 2014)
& Technology (IJARCST
ISSN : 2347 - 98172014)
(Print)

FPGA Design of a Reduced Complexity Sphere Decoder for

Wireless Applications
I
M.Sheeba, IIK.Monisha
I
Final Year, M.E. – VLSI DESIGN, Sethu Institute of Technology, Kariapatti, India
II
Asst. Professor, ECE Dept., Sethu Institute of Technology, Kariapatti, India

Abstract
0XOWLSOHLQSXWDQGPXOWLSOHRXWSXW 0,02 WHFKQRORJ\KDVEHHQZLGHO\DSSOLHGLQZLUHOHVVFRPPXQLFDWLRQVVLQFHLWRIIHUVVLJQL¿FDQW
increases in data throughput a link range without additional bandwidth or increased transmit power. In this project, a MAP Algorithm
for Multi input Multi Output (MIMO) Sphere Decoder for wireless applications is proposed. FEC (Forward Error Correction)
Algorithm for sphere decoder to reduce its error rate and its VLSI architecture is also proposed for the iterative MIMO receiver.
7KHGHHSO\SLSHOLQHGDUFKLWHFWXUHHPSOR\VWKHRSWLPL]HGK\EULGHQXPHUDWLRQVHDUFKIRUWKHEHVWFKLOGQRGHWRHVWLPDWHHI¿FLHQWO\
By adding the counterhypotheses in parallel with other candidates, the proposed iterative MIMO detector improves the detection
SHUIRUPDQFHVLJQL¿FDQWO\ZLWKORZGHWHFWLRQODWHQF\&RPSDUHGZLWKSUHYLRXVORZFRPSOH[LW\WHFKQLTXHVWKLVZRUNUHGXFHVJDWH
FRXQWVZKHQFRPSDUHGZLWKH[LVWLQJPHWKRGDQGUHTXLUHVRQO\DRQHOLQHEXIIHUPHPRU\7KLVSURSRVHGELRUWKRJRQDOEDVHGVSKHUH
GHFRGHUV\VWHPLVGHVLJQHGXVLQJ9HULORJ+'/VLPXODWHGXVLQJ0RGHOVLP6RIWZDUHDQGV\QWKHVL]HGXVLQJ;LOLQ[3URMHFW1DYLJDWRU

Keywords
FEC, MIMO, Power, Sphere, Latency and Hybrid.

I. Introduction II. Proposed Maethod

Multiple-input and multiple-output (MIMO) technology has 7KH SURSRVHG 9/6, DUFKLWHFWXUH RI 6,62 )6' LV VKRZQ LQ
been widely applied in wireless communications since it offers )LJ7KLVDUFKLWHFWXUHFRQVLVWRISURFHVVLQJHOHPHQWV&DQGLGDWH
VLJQL¿FDQWLQFUHDVHVLQGDWDWKURXJKSXWDQGOLQNUDQJHZLWKRXW JHQHUDWLRQXQLW &*8 DQG /&8 ORJOLNHOLKRRGUDWLRFDOFXODWLRQ
additional bandwidth or increased transmit power. By incorporating unit modules.
MIMO with bit-interleaved coded modulation with iterative
detection and decoding (BICM-IDD), the channel capacity can
be approached [1] at the cost of much higher complexity and lower
throughput compared with non-iterative schemes. Thus, it is very
important to develop a high-speed iterative detector to meet the
increasing demand for gigabit-per-second wireless systems such
DVWKH,(((DFZLUHOHVVORFDODUHDQHWZRUN :/$1 DQG
*33/7($GYDQFHG'XHWRLWVSUDFWLFDOLPSRUWDQFHWKHYHU\
ODUJHVFDOHLQWHJUDWLRQ 9/6, GHVLJQRIVRIWLQSXWVRIWRXWSXW
6,62 GHWHFWRUVKDVUHFHQWO\UHFHLYHGDORWRIDWWHQWLRQ7KH¿UVW
UHSRUWHGLPSOHPHQWDWLRQRID6,620,02GHWHFWRULVEDVHGRQ
the minimum mean square error parallel interference cancellation
006(3,& DOJRULWKP>@EXWLWFDQQRWIXOO\H[SORLWWKHVSDWLDO
diversity provided by MIMO. To overcome this limitation,
LPSOHPHQWDWLRQVRI6,62VLQJOHWUHHVHDUFK 676 VSKHUHGHFRGLQJ
6' >@>@DUHSUHVHQWHGZKLFKKDYHPD[ORJPD[LPXPD )LJ3URSRVHG9/6,$UFKLWHFWXUHRI6,62)6'
posteriori 0$3 SHUIRUPDQFH+RZHYHUOLNHRWKHUGHSWK¿UVW
tree-search algorithms, it suffers from variable throughput and A. Processing element (PE-A) Architecture:
FRPSOH[LW\GHSHQGLQJRQWKHVLJQDOWRQRLVHUDWLR 615  %\HPSOR\LQJWKH259'WKHMPcomputation (i.e.,MP(si),MP(si+1))
0RUHUHFHQWO\DQRYHO6,62GHWHFWLRQDOJRULWKPEDVHGRQWUHOOLV in two adjacent levels can be conducted in parallel with Ri,i+1 being
VHDUFKDQGLWV9/6,DUFKLWHFWXUHKDVEHHQSURSRVHGLQ>@ZKLFK zero for i = 1, 3, . . . , 2Nt ->@
SURYLGHVDSHDNWKURXJKSXWRI*ELWVEXWLWFRQVXPHVODUJH $VDFRQVHTXHQFHWKHQXPEHURISURFHVVLQJHOHPHQW 3( VWDJHV
VLOLFRQDUHDDQGLVKDUGWRVXSSRUWKLJKRUGHUPRGXODWLRQ>HJ is reduced by half compared to those pipelined detectors using
TXDGUDWXUHDPSOLWXGHPRGXODWLRQ 4$0 @)L[HGFRPSOH[LW\6' traditional real-value decomposition [10]. The architecture
)6' LVDEUHDWK¿UVWWUHHVHDUFKDOJRULWKPSUHYLRXVO\SURSRVHG supports both hard outputs and soft outputs. The hard-output
for hard-output MIMO detection. It is capable of providing near PRGXOHJHQHUDWHVWKHRULJLQDOKDUGRXWSXW)6'FDQGLGDWHOLVW
PD[LPXPOLNHOLKRRG 0/ GHWHFWLRQSHUIRUPDQFHZLWK¿[HGDQG /LQZKLFKWKHEHVWSDWKZLWKWKHPLQLPXPMP is found. The
ORZFRPSOH[LW\>@$KLJKO\HI¿FLHQWVLOLFRQLPSOHPHQWDWLRQRI soft-output module generates an expanded list L+ by employing
)6'LVUHSRUWHGLQ>@ZKLFKFDQDFKLHYHD*ELWVGHWHFWLQJ WKH3&$VFKHPHDQGFDOFXODWHVWKH//5VEDVHGRQWKHXQLRQ
WKURXJKSXWZLWKWKHSDUDOOHOPXOWLVWDJH9/6,DUFKLWHFWXUH,WLV of the two lists L‰L+. The PEs in our design is divided into
very attractive to extend the hard-output base architecture to WKUHHW\SHV3($3(%DQG3(&3($LVORFDWHGLQWKH¿UVW
support iterative MIMO detection. stage where multiple child nodes are expanded. PE-B performs
the single expansion in their remaining three stages. PE-C in
WKHVRIWRXWSXWPRGXOHDGRSWVWKHELWÀLSSLQJVWUDWHJ\WRDGG

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International Journal of Advanced Research in
ISSN : 2347 - 8446 (Online) International Journal of Advanced Research
ISSN : 2347 in
- 8446 (Online)
Computer Science
ISSN : 2347 - 9817 Vol. 2, Issue
(Print) & Technology 2, Ver.2014)
(IJARCST 3 (April - June 2014)
Vol. 2, Issue 2, Ver.Computer
2 (April Science
- June 2014)
& Technology (IJARCST
ISSN : 2347 - 98172014)
(Print)

the counterhypotheses to the expanded list L+. To identify the

SDUWLDO0$3QRGHDPRQJWKHLWKHPLQLPXP 0,1 VHDUFKEORFN 7KH0,1EORFNFRPSDUHVWKHMP of and sCA,i, and then
at the soft-output module is needed to select the node with the selects the node with smaller MP.
smallest LP:LWK Lm2Nt-1 >, , , , 3, 3, 1, 1], the number
of candidates in L is NLcand= 32. In the hard-output module, we C. Processing element (PE-C) Architecture:
instantiate eight PE-Bs at each stage where eight nodes can be In PE-C architecture, Best Child node selection unit is employed.
processed simultaneously, and thus, four cycles are needed to This unit is used to select the best child nodes among the set of
complete the processing of all the candidates in L. The candidate DYDLODEOHFKLOGQRGHVZLWKUHVSHFWWRSDUHQWRUURRWQRGH)LJ
generation unit (CGU) is adopted to generate all possible values VKRZVWKHDUFKLWHFWXUHRI3(&ZKLFKLPSOHPHQWVWKH3&$
of |5i,jsj| which are shared by the MP(si) calculations at the same scheme.
OHYHO$GGLWLRQDOO\WKHMA(si) and Msi(si) of all possible symbols
are also precomputed to further enhance the hardware sharing.

)LJ$UFKLWHFWXUHRI3($ )LJ$UFKLWHFWXUHRI3(&

Moreover, the best node ZLWKWKHPLQLPXP0$DWHDFKOHYHOLV 7KH EHVW FKLOG HVWLPDWH VHOHFWLRQ XQLW %&68  UHFHLYHV WKH
DOVRLGHQWL¿HGDQGEXIIHUHGLQ&*8DFFRUGLQJWRWKHVLJQRI/$i,b
ZKLFKDYRLGVIXOOVRUWLQJRIWKHVHW^0$ Vi `7KH//5FDOFXODWLRQ SDUWLDO0$3QRGH DQG¿QGVLWVEHVWFKLOGHVWLPDWH by
XQLW /&8 LQWKHODVWVWDJHFDOFXODWHVWKH//5VRIHDFKWUDQVPLWWHG
HPSOR\LQJWKH2+(MXVWWKHVDPHDVLWLVLQ3(%7KHFDQGLGDWH
ELWDFFRUGLQJWR  EDVHGRQWKHFDQGLGDWHOLVWVL and L+. DGGLQJXQLW &$8 XVHVELWÀLSSLQJVWUDWHJ\WRDGGWKUHHVLEOLQJ
nodes of , which feed forward to a multiplexer, and only one
B. Processing element (PE-B) Architecture: of them is selected per cycle for MP computation. The serial
PE-B is used to implement the single expansion where only the best computation method saves the number of MP FRPSXWDWLRQEORFNV
QRGHHVWLPDWHLVVHOHFWHGDQGSUHVHUYHGXVLQJWKHSURSRVHG2+( LQ&$8E\DQGUHGXFHVWKHQXPEHURI3(%VIROORZLQJLQ
the subsequent stages compared to the parallel method, without
impacting the throughput of the whole architecture.

D. Candidate Generation Unit (CGU):

$VRIWRXWSXWVSKHUHGHFRGHUW\SLFDOO\FRQVLVWVRIDOLVWJHQHUDWRU
WKDW¿QGVDVHWRIFDQGLGDWHV\PEROYHFWRUDQGDORJOLNHOLKRRG
//5 JHQHUDWRUWKDWFDOFXODWHVWKHVRIWRXWSXWELWYDOXHIRUWKH
MIMO channel decoder

(1)

where and is the regularization parameter.

(2)

)LJ$UFKLWHFWXUHRI3(%
(3)
$VVKRZQLQ)LJWKHLQWHUIHUHQFHFDQFHOODWLRQXQLW ,&8 LQ
PE-B computes in (1) to eliminate the inter antenna interference :KHUH denotes the bth bit.
introduced by previously detected symbols. To enumerate the best
child node with the minimum MC, a quantization step Q is E. LLR Calculation Unit (LCU)
UHTXLUHGWR¿QGWKHV\PEROZKLFKLVQH[WWR /Ri,i7KH+(XQLW 7KH//5 ORJOLNHOLKRRGUDWLR &DOFXODWLRQ8QLWLVXVHGWRFDOFXODWH
+(8 FKRRVHVsCA,i DFFRUGLQJWRVWHS RIWKH2+(PHWKRG WKHOLNHOLKRRG¶VEHWZHHQWKHWZRRUPRUHGDWDPRGHOV,Q/&8
XQLW0$3 PD[LPXPa posteriori) algorithm is proposed to reduce

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International Journal of Advanced Research in
ISSN : 2347 - 8446 (Online) International Journal of Advanced Research
ISSN : 2347 in
- 8446 (Online)
Computer
ISSN : 2347 - 9817Science Vol. 2, Issue
(Print) & Technology 2, Ver.2014)
(IJARCST Vol.
2 (April - June 2, Issue 2, Ver.Computer
2014) 3 (April Science
- June 2014)
& TechnologyISSN
(IJARCST
: 2347 - 98172014)
(Print)

WKHKDUGZDUHFRPSOH[LW\DQG)(& )RUZDUG(UURU&RUUHFWLRQ 
is also proposed to reduce its bit error rate during transmission.
7KHSURSRVHG/&8DUFKLWHFWXUHFRQVLVWVRIF\FOLFVKLIWUHJLVWHU
;25 PDWUL[ PDMRULW\ JDWH DQG FRQWURO XQLW7KH F\FOLF VKLIW
UHJLVWHUZLOOVHQGWKHLQSXWVWRHDFKÀLSÀRSVDQGWKHRXWSXWVDUH
IHGEDFNLQDF\FOLFPDQQHU,Q;250DWUL[WKHYDOXHVDUHWDNHQ
IURPWKHVKLIWUHJLVWHU$QGWKHVHYDOXHVDUH;25RQHE\RQH
$QG3DULW\FKHFNVXPLVSHUIRUPHG7KDWLVFRXQWLQJWKHQXPEHU
of zeros and ones. If number of ones is greater than zeros error
correction is performed. Otherwise the bits are under gone cyclic
VKLIW7KHVH3URFHVVHVDUHGRQHLQ0DMRULW\*DWH$QGLWFDQEH
done until all the bits are evaluated.

)LJ)(&7UDQVPLWWHU

7KHIRUZDUGHUURUFRUUHFWLRQFRGHLVJLYHQEHORZ
‡ r0=a2+a1+a0 modulo-2
‡ r1=a3+a2+a1 modulo-2
‡ r2=a1+a0+a3 modulo-2
7KH)(&UHFHLYHULVVKRZQLQ¿JWKDWFRQVLVWVRIELWVIURPWKH
WUDQVPLWWHUDQGWKHELWVDUHJLYHQWRWKHFKHFNHUDQGIRUHDFKELW
the syndrome value will be estimated using the code given below.
7KHFRUUHFWLRQORJLFDQDO\]HUZLOOFKHFNIRUHUURUDFFRUGLQJWR
the calculated syndrome values using the Table I shown below.
)LJ3URSRVHG'HFRGHU$UFKLWHFWXUH

The control unit manages the detection process. It uses a counter

WKDWFRXQWVXSWRWKUHHZKLFKGLVWLQJXLVKHVWKH¿UVWWKUHHLWHUDWLRQV
RIWKH0/GHFRGLQJ,QWKHVH¿UVWWKUHHLWHUDWLRQVWKHFRQWUROXQLW
HYDOXDWHVWKH^%M`E\FRPELQLQJWKHPZLWKWKH25IXQFWLRQ
This value is fed into a three-stage shift register, which holds the
UHVXOWVRIWKHODVWWKUHHF\FOHV,QWKHWKLUGF\FOHWKH25JDWH
HYDOXDWHVWKHFRQWHQWRIWKHGHWHFWLRQUHJLVWHU:KHQWKHUHVXOW
LV³´WKH)60VHQGVRXWWKH¿QLVKVLJQDOLQGLFDWLQJWKDWWKH
processed word is error-free. In the other case, if the result is “1,”
WKH0/GHFRGLQJSURFHVVUXQVXQWLOWKHHQG

)LJ)(&5HFHLYHU

6\QGURPHHVWLPDWLRQ
‡ 60=b2+b1+b0+q0 modulo-2
‡ 61=b3+b2+b1+q1 modulo-2
‡ 62=b2+b1+b0+q2 modulo-2

7DEOH/RJLFDOGHVLJQPDGHE\FRUUHFWLRQORJLFDQDO\]HULQ
)(&UHFHLYHU
Syndrome 000 001 010 011 100 101 110 111
)LJ$UFKLWHFWXUHRI&RQWURO8QLW
Error 1RQH q0 q1 b2 q2 b0 b3 b1
7KH)(&WUDQVPLWWHULVVKRZQLQ¿J7KHJHQHUDWRUUHFHLYHV
DGDWDZRUGDQGJHQHUDWHVSDULW\FKHFNELWVDORQJZLWKWKHGDWD
ZRUG(DFKRIWKHSDULW\FKHFNELWVKDQGOHVRXWRIELWVRIWKH MAP Algorithm:
data word using forward error correction code. The forward error 0$3DOJRULWKPLVXVHGWR¿QGWKHHUURULQPXOWLELWVDQGLWDOVR
correction code for transmitter is given below. reduces the hardware complexity.

III. Simulation Results

The proposed sphere decoder architecture is designed using verilog
+'/VLPXODWHGXVLQJPRGHOVLPVRIWZDUHDQGV\QWKHVL]HGXVLQJ

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International Journal of Advanced Research in
ISSN : 2347 - 8446 (Online) International Journal of Advanced Research
ISSN : 2347 in
- 8446 (Online)
Computer Science
ISSN : 2347 - 9817 Vol. 2, Issue
(Print) & Technology 2, Ver.2014)
(IJARCST 3 (April - June 2014)
Vol. 2, Issue 2, Ver.Computer
2 (April Science
- June 2014)
& Technology (IJARCST
ISSN : 2347 - 98172014)
(Print)

Xilinx project navigator. The simulated waveform is illustrated in V. Acknowledgement

¿JDQGLWV57/VFKHPDWLFYLHZLVGLVSOD\HGLQ¿J
References
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a multiple antenna channel,” IEEE Trans. Commun., vol.
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of soft input soft-output MIMO detection using MMSE
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Circuits, vol. 46, no. 7, pp. 1754–1765, Jul. 2011.
[3] E. M. Witte, F. Borlenghi, G. Ascheid, R. Leupers, and H.
Meyr, “A scalable VLSI architecture for soft-input soft-output
single tree-searchsphere decoding,” IEEE Trans. Circuits
6\VW,,([S%ULHIVYROQRSS±6HS
[4] F. Borlenghi, E. M. Witte, G. Ascheid, H. Meyr, and A. Burg,
“A 772 Mbit/s 8.81 bit/nJ 90 nm CMOS soft-input soft-output
)LJ:DYHIRUP6LPXODWLRQ sphere decoder,”in Proc. ASSCC, Jeju, Korea, 2011, pp.
297–300.
[5] Y. Sun and J. R. Cavallaro, “Trellis-search based soft-
input soft-output MIMO detector: Algorithm and VLSI
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>@ /*%DUEHURDQG-67KRPSVRQ³)L[LQJWKHFRPSOH[LW\
of the sphere decoder for MIMO detection,” IEEE Trans.
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>@ //LX-/RIJUHQDQG31LOVVRQ³$UHDHI¿FLHQWFRQ¿JXUDEOH
highthroughput signal detector supporting multiple MIMO
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>@ / * %DUEHUR DQG - 6 7KRPSVRQ ³([WHQGLQJ D ¿[HG
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56, no. 10, pp. 4827–4842, Oct. 2010.
7DEOH3HUIRUPDQFH$QDO\VLV
Parameter Previous Proposed Author’s Profile

Power 203mw PZ M.SHEEBA received her B.E., degree in Electronics

Consumption and Communication Engineering from the K.L.N
College of Engineering, Sivagangai, India, in
2012. Currently doing M.E - VLSI Design in Sethu
IV. Conclusions Institute of Technology, Virudhunagar, India. Her
This brief presents the algorithm optimization and VLSI research interest includes: low Power VLSI and
implementation of a SISO FSD. Based on the hard-output Wireless network.
imbalanced FSD, the proposed SISO FSD algorithm employs the
GHſEKGPV1*'VQCXQKFVJGGZJCWUVKXGUGCTEJQHVJGDGUVEJKNFHQTVJG
UQHVKPRWVUEGPCTKQCPFCFQRVUVJGUKORNG2%#UEJGOGVQKORTQXG Ms.K.MONISHA received her B.E., from K.L.N
the quality of the output LLRs. In addition, the compensation of College of Engineering in 2010 and completed
VJGUGNHKPVGTHGTGPEGECWUGFD[EJCPPGNOCVTKZTGIWNCTK\CVKQPKU her M.E from Sethu Institute of Technology in
incorporated in the tree search, leading to further performance 2012. Presently working as an Assistant Professor
ICKP 6JGUG RTQRQUGF VGEJPKSWGU ECP TGFWEG VJG EQORNGZKV[ in the Department of ECE at Sethu Institute
UKIPKſECPVN[CPFRTQXKFGPGCTOCZŌNQIŌ/#2RGTHQTOCPEG#V of Technology, Tamilnadu, India. Her current
VJGCTEJKVGEVWTGNGXGNVJGRTQRQUGFOWNVKUVCIGCTEJKVGEVWTGWUKPI research areas includes: Image Processing and
VJGVKOGOWNVKRNGZKPIJCTFYCTGUJCTKPIHCUJKQPHWTVJGTTGFWEGU Signal Processing.
VJGCTGCEQUV+ORNGOGPVCVKQPTGUWNVUUJQYVJCVQWT5+51(5&
QWVRGTHQTOUQVJGTTGRQTVGFKVGTCVKXG/+/1FGVGEVQTUKPVGTOUQH
VJTQWIJRWVCPFCTGCGHſEKGPE[

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