1.

Introduction
If the automobile had followed the same
development cycle as the computer, a Rolls-
Royce would today cost $100, get one million
miles to the gallon and explode once a year

Most of slides come from Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

Digital IC
Introduction
 outline
• Course Introduction
• a brief history
• Design Metrics
• DIC characteristics
• Design partitioning/CMOS logic
• Semiconductor processing

Digital IC
 Semiconductor processing
• Semiconductor fabrication
• Layout fundamental
• Semiconductor testing
• Semiconductor assembling

Digital IC
 Different Electrical Tests for IC Production
(From Design Stage to Packaged IC)

Stage of IC Wafer- or
Test Test Description
Manufacture Chip-Level
Characterize, debug and verify new chip
IC Design Verification Pre-Production Wafer level
design to insure it meets specifications.
Production process verification test
In-Line Parametric
Wafer fabrication Wafer level performed early in the fabrication cycle
Test
(near front-end of line) to monitor process.
Product functional test to verify each die
Wafer Sort (Probe) Wafer fabrication Wafer level
meets product specifications.
ICs powered up and tested at elevated
temperature to stress product to detect
Packaged
Burn-In Reliability Packaged IC early failures (in some cases, reliability
chip level
testing is also done at the wafer level
during in-line parametric testing).
Packaged Product functionality test using product
Final Test Packaged IC
chip level specifications.

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Automated Electrical Tester

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 Wafer Fab Process Flow with Test

Wafer Fabrication (front-end)

Wafer start
Thin Films Polish

Unpatterned
wafer

Completed wafer Diffusion Photo Etch

Test/Sort
Implant

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 Wafer Test
• In-line Parametric Test (a.k.a. wafer electrical
test, WET)
• In-line test structure
• In-line test type
Scribe line with
• In-line test data explain monitor test
structures
• In-line test equipment

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 In-line Parametric Test
Systems
• Probe card interface
• Wafer positioning Instrumentation
• Tester instrumentation
• Computer as host or Electronic
interface Computer
server/network

Probe card

Wafer positioning
(X, Y, Z, q)
q-Z stage X-Y stage

8
Digital IC
Probe Card for Automatic Tester

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 Examples of Test Structure

Test Structure Fault Measurement

Leakage current, breakdown voltage, threshold
Discrete transistors
voltage and effective channel length
Various line widths Critical dimensions
Box in a box Critical dimensions and overlay registration
Serpentine structure over
Continuity and bridging
oxide steps
Resistivity structure Film thickness
Capacitor array structure Insulator materials and oxide integrity
Contact or via string Contact resistance and connections

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 Data Trends
• The same die location keeps failing a parameter
on a wafer.
• The same parameter is consistently failing on
different wafers.
• There is excessive variation (e.g., > 10%) in
measurement data from wafer to wafer.
• Lot-to-lot failure for the same parameter,
indicating a major process problem.

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 Wafer Sort
• Wafer Sort (a.k.a. wafer probe)
• DC testing
• Output checking
• Function testing
• The Objectives of Wafer Sort
• Chip functionality: verify the operation of all chip functions to insure only
good chips are sent to the next IC manufacturing stage of assembly
and packaging.
• Chip sorting: sort good chips based on their operating speed
performance (this is done by testing at several voltages and varying
timing conditions).
• Fab yield response: Provide important fab yield information to assess
and improve the performance of the overall fabrication process.
• Test coverage: Achieve high test coverage of the internal device nodes
at the lowest cost.

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 Wafer Bin Map with Bin Failures

1 1 1 1 10 10
Device: Example 10 2 1 1 1 3 7 7
Lot: Example
Wafer: 200 mm 1 12 12 1 1 1 1 1 1 1
Layer: Hardware Bins 1 1 6 6 1 1 1 1 1 1
Yield: 79.54%
3 7 1 1 1 1 1 1 1 1
Good: 70
Total: 88 10 1 1 5 1 1 1 1 1 1
1 1 1 4 1 1 4 1 1 1

Good 1 1 2 1 12 10 1 1 1 7
1 1 1 1 1 1 10 2
Bad
1 1 1 1 1 1

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Reduced Partial Die on Large Wafer

10.8% partial die

14.5% partial die

200 mm 300 mm

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Reduced Time to Product Maturity for
DRAM Production
Pilot
R&D Line Full Production
100
256 Mb
1 Mb 256 Kb
80
DRAM Probe Yield, After Repair

64 Kb
60 4 Mb

40

20
64 Mb

0
16 Mb

-1 0 1 2 3 4 5 6 7
Year

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 Semiconductor processing
• Semiconductor fabrication
• Layout fundamental
• Semiconductor testing
• Semiconductor assembling

Digital IC
 Packaging Requirements
• Electrical: Low parasitics
• Mechanical: Reliable and robust
• Thermal: Efficient heat removal
• Economical: Cheap

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 Important Functions of IC
Packaging
• Protection from the environment and
handling damage.
• Interconnections for signals into and out of
the chip.
• Physical support of the chip.
• Heat dissipation.

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Traditional Assembly and Packaging

Wafer Test and Sort Die Separation Die Attach

Wire Bond Plastic Package Final Package and Test

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 Typical IC Packages

Dual in-line package Single in-line package Thin small outline package
(DIP) (SIP) (TSOP)

Quad flat pack Plastic leaded chip carrier Leadless chip carrier
(QFP) (PLCC) (LCC)

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 Levels of IC Packaging

First level packaging: Metal leads for mounting

IC packaging onto printed circuit board
Leads Pins

Surface- Pins are

mount chips inserted
are soldered into holes
on top of then
2nd level packaging: tinned pads soldered on
on the PCB. rear of
Printed circuit board PCB.
assembly
Edge connector plugs into main system.

PCB subassembly
Final product assembly:
Final assembly of circuit
boards into system
Main electronics
assembly board

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 Traditional Assembly
• Wafer preparation (backgrind)
• Die separation
• Die attach
• Wire bonding

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Schematic of the Backgrind Process

Downforce

Rotating and
oscillating spindle

Wafer on
rotating chuck

Table rotates only during

indexing of wafers

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Wafer Saw and Sliced Wafer

Wafer

Stage

Blade

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Typical Leadframe for Die Attach

Leadframe Lead Die

Plastic DIP

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 Epoxy Die Attach

Die

Epoxy

Leadframe

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Wires Bonded from Chip Bonding Pads
to Leadframe

Die
Moulding compound
Bond wire

Bonding pad Leadframe

Pin tip

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Wirebonding Chip to Leadframe

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 Traditional Packaging
• Plastic Packaging
• Ceramic Packaging
• TO-Style Metal Package(old)

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 General package mode
Plastic Dual In-Line Package (DIP) Single In-Line Package (SIP),
for Pin-In-Hole (PIH)1970s-1980s decreasing capacity and cost
Memory application

Thin Small Outline Package (TSOP)

Memory and smartcard Single In-
Line Memory Module (SIMM)

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 General package mode
Quad Flatpack (QFP) with Gull Plastic Leaded Chip Carrier (PLCC)
Wing Surface Mount Leads with J-Leads for Surface Mount

Laminated Refractory Ceramic

Leadless Chip Carrier (LCC)
Process Sequence
Ceramic interconnect layers

4-layer laminate

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 Advanced Packaging
• Flip chip
• Ball grid array (BGA)
• Chip on board (COB)
• Tape automated bonding (TAB)
• Multichip modules (MCM)
• Chip scale packaging (CSP)
• Wafer-level packaging

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 Advanced Packaging
Flip Chip Package

Connecting pin

Substrate
Via
Metal interconnection Solder bump
Silicon chip on bonding pad Flip Chip Area Array Solder
Bumps Versus Wirebond
Bonding pad
perimeter array
Flip chip bump
area array
Solder bump

Chip

Epoxy

Substrate Digital IC 33/57

 Ball Grid Array

Bonding pad
Molded cover Chip
Wire Epoxy

Substrate

Metal via
Solder ball Thermal via

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Multichip Module (MCM)

Individual die MCM substrate

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 Summary
• MOS Transistors are stack of gate, oxide, silicon
Can be viewed as electrically controlled switches
• Build logic gates out of switches
• Draw masks to specify layout of transistors
• Using different packaging&assembing tech.
• to start designing schematics and layout for a
simple chip!

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