Chip ScalePackage Joint Integrity Under Isothermal Aging

bY
Rem Ghaffarian, Ph.11.
Jet Propulsion Laboratory
California Instituteof Technology

ABSTRACT

The popularity of emerging miniaturized Chip Scale Packages (CSPs) is rapidly growing because of their benefits and
smaller size, though they may be considered to be an interim solution. There are more than forty CSPs availablefrom
different sources with only a few applications. Implementation will be facilitated as the necessary infrastructure is
developed. Many aspects of this technology, with focus on assembly reliability characteristics, are being investigated by
the JPL-led MicrotypeBGA consortium. Three types of test vehicles were considered for evaluation and currently two
configurations have been builtto optimize attachment processes. These test vehiclesuse numerous package types. To
understand potential failure mechanisms of the packages, particularly solder ball attachment, the grid type packages
weresubjectedtoenvironmentalexposure.Package I/Os rangedfrom 40 to nearly 300. The CSPpackageswere
subjected to visual inspection and scanning electron microscopy (SEM) to characterize their joint quality, solder ball
metallurgy, and elemental compositions. They were then subjected to ball shear testing, with results compared to the 4

plastic ball grid arrays. After initial testing, these CSPs along with BGAs were subjected to isothermal aging at two
different temperatures for two intervals. The exposed packages were then subjected to inspection, SEM, and shear
testing, and thelevels of damages documented. This paper presents the CSP test results.

frrst five years and will almost plateau withan increase

MINIATURIZATION TRENDS of only two billion for another five years. Within ten
Projectionregardingtheuse of throughhole anq years, the COB (Chip On Board), not shownin&gure,
surface mount IC packages are significantly differad i expected to increase from5 billion to 13 billion.
thenumbersdependonthemarketingsource.One
The increase in the use of CSP and flip chip packages
projectionfromtheBPA, UK, isshown in Figure 1.
are the same, projected to reach 6 billion by 2006. In
Several trends areapparent.
contrast, the increase in BGAs for the same ten years is
expected to be minimal, reaching to total use of only
1.5 billion.Theprojectionfor BGAs indicatesthat
perhaps these packages were only an interim solution
- 1
...."...,..............i;... .......... i.l.2001 and werethe stepping stone for theindustry'swider
acceptance of flip chip and chip scale packages. CSPs
............. .............. .......... ............. meet better the demands for denser and lighter towards
miniaturized applications.
BGA i
.........................................................
Why Chip Scale Packages
EmergingCSPs are competing with bare
die
Dl P, assemblies. "any ,mnnufacturers now refer to CSP as
thepackagethatis a miniaturizedversion of the
0 5 2010 15 previous generation. Two conceptsof CSPs are shown
Total Packages (Billion) in Figure 2. Theconceptsinclude: (1) packages with
flex or rigid interposer and(2) wafer level molding and
Figure 1 Projection for Package Use (1996-2006) assembly redistribution.
TheDual I n Line
Package (DIP) had the
most Packaging accomplishes many purposes, including the
reduction i n use, decreasing from 16 billion in 1996 to following:
about 5 billion in tenyears,Le.,about a onebillion
reductionperyear. In contrast, theuse of surface 0 Rovidcs solder balls andleadsthat;uecompatible
mountablepackagesincluding PQWs (Plastic Quad wid1 the PWB pad metollurgy for retlow assembly
FlatPacks)projected to increase in thenextdecade. proccsses.
'L'he increase fOreciLStcd from 7 to 18 billion within the
0 Redistributes the tight pitch ofthe die to thepitch' attribute ha.. permittedreduction in thenumber of
level that is within the norm ofPWB fabrication. solder joint defects to lowerlevels Lhan conventional
The small sizes of CSPs do not permit significant SM packages.
redistributionand current costeffective PWB
fabrication limits full adgption of the technology, Many factors affect self alignment characteristics, but
especially for highI/O counts. themainfactoristhemoltensoldersurfacetension
that provides the pull force on the package toward the
0 Protectsthediefromphysicalandalpharadiation padcenters.Thecounterforceistheweight ofthe
damages,andprovides a vehicle
for
thermal package.ForPlastic BGAs (PBGAs),thepullforces
dissipation. induced from the melt of eutectic balls are larger than
0 Easesdiefunctionalitytesting. the forces from the partial molten joints in the ceramic
BGAs (CBGAs) or solder paste melts in conventional
CSPs Concepts packages.Hence,better self alignment forPBGAs.
The symmetry ofBGAball patterns helps further in
Die Tight Pitch permitting both X and Y as well as rotational
80)1-Wlrebond,WOpFlipchlp placement offsets for BGAs.
A1 Pad- Non Reflow .................................. ......
:::;:.. :.:.:.;....
............
..... ................................................. '>..
.:.; ............
:.:.:.:.>::
,x::
,:.:.: ................
......... . , . . . . ................
. . . . ,,.,.,, ,,...,,...
,...,.l..
. . . , , . . , . . . I....... ....
:.:. ..... -.
:<.:.:
For grid CSPs, the molten surface tensions are much
1::3>2,
......
...... $:<.
.:+: .c ., ........
......
...... ....
:x,
......
.x.:
:.:.:. Interposer Wafer w;smaller than BGAs since they have lower solder ball
:3z
...
...
...
.... volumes. This, coupled with the CSPs finer pitch, can
.......
.:.:.:.. Polymer, Ccramlc, Fks ,:;% Pitch ltrnlllltbn
..,.
....
....
.........
....
.....
.....
....
Cu:NiAu Pad ,;:>;s
.:+:.:.:. deratetheirselfalignmentperformance,especially
.:.:.:.:.:
......
....... ,23>y
....
......
..... .:.:.:.:.:..
......
........
..........
............
.............
.:.:.:.:.:..
.....
......
............
.... ..:.:.:.>:..
withheavypackages.Therefore,theCSPsmight
.......
....... :.:.::::
............
....
..........
....................
..............
......
.....
3:::::::::::.
...................
:::A:::::::::.:'
............
require much tighter placement accuracy than the 50
..:,>: .....
,
'L:: ~~ . ~ ~ : ~ . ~ ~ ~ . ~ ~ ~ ~ +." mil
~ ~8.' ~ ~ . - . ; . ~ = . : . : . : . ~ ~ . : ~
'~'""' ~ ~pitch
-~;~ BGAs.
~-~

Norm Pitch for PWB

0.5137 mm Grid CSPsshow
self alignment, but
there
is
________~ ~~

Figure 2: Two Chip Scale Package Concepts disagreement on best offset limits.
An offset of only 25% for a grid CSP with 46 UOs
was found to be acceptable. The acceptable offsets
Self Alignment of Grid BGAs were 62% for PBGAs and 50% for CBGAs
CSPs can be categorized into grid arrays and leads or (Noreika,
SurfaceMountInternational
(SMI),
noleadsusingI/Oexpandabilityandmanufacturing 1997).
robustness as Figure
shown
in 3. Key An offset of 80% reported by another investigator
advantageddisadvantages of eachcategoryarealso (Pauidge, SMI '97).
listed.
Only two bridges out of 16,100 solder joints were
reported. Thesewere due to foreign materials with
/ CSPSL nodefectsfounddue to placementinaccuracy.
Grid Arravs Leads The test was a qualitative determination in which
threehundredCSPswith 46 I/Os werehand
placed,reflowed,and joint defectswerethen
characterized (Bauer, etal, SMI '97).

High 110s
e Low IlOS
Only two solder joint shorts were detected out of
200 hundredassembledCSPpackageswith 44
W i E bond I/O Limitation No Leads,
Reliability? I/Os (Hunter, et al, CHIPCON '98).
CJ ceramic,Wafer, Reli'ability? Assembly Robustness?
Assembly Robustness
Self Alignment Thermo-mechanicalFailures
Figure 3: Two Chip Scale Package Categories The thermo-mechanical wear (creep) of solder joints is
thecauseoffailureformostCSPboardassemblies.
The mini (fine pitch)gridarrays canaccommodate Failure a t theboardlevelcan also be duetopackage
higherpincounts,andsimilarly toBGAs,theyhave intenlnl
failure or fromthe
solder
bnlls/package
selfnlignmcnt (centering) characteristics. For BGAs, interface in grid CSl's.
the ease of package placement requirements has k e n
widelypublished ;is one of their advantqes. This A non-uniformthermalexpansionand/orcontraction
of different
matcrials in the
assembly
induces
 3 mechanical stresson solder joints. To achieve the least failure mechanisms under differcnt environments were
damage to solder joints, thermal mismatch between the investigation
under
another
progr'm.
Figure 5,
die and board should be minimized either by package adaptedfromReference 3, showscumulativefailure
optimization or use of board materialsthatclosely percentages versus increasing cyclcs for several plastic
match coefficient of thermal expansion (CTE) ofthe BGA assemblies. Wider distribution for two peripheral
package. BGA packages are evidenced from this figure.

Only a few CSPpackageshave been designed to The exact causes ofwider distributions are yet to be
alleviatedamagedue to thethermalexpansion of identified.Possiblecausesinclude: PWB materials
packagehoard mismatches. floating
Thepad (FR-4, polyimide),soldervolume,andball/package
technology (FPT) is another technique that was integrity. Packagehall integrityplays a rolesince
recentlyconceived withtheaim of absorbingCTE failureanalyses of cycled BGA assembliesindicated
mismatches at the pad level (Wojnarowski, ITAP '98). thatfailuresoccurredeither at package or board
The literature data on assembly reliability of a CTE interfaces.Thismeansthatsolder joint cyclingtest
absorbed package along with numerous other packages results for packages from prototypeor early production
were presented previously''*2'. might not be representatives of full production results.
Wider distributions are also expected if processes are
Failure Shift not optimized.
Assembly failure canbe misinterpreted when there is a
shiftinfailuremechanisms. For example,package This investigation included BGAs as well as grid CSPs
internal TAB lead failures at heels were reported for to determine if there were differences in packagehall
the CTE absorbed CSP- a fatigue failure mechanism interface integrity before and after isothermal exposure
shift from the solderjoint to the internal package. An and if this correlated with cycles to failure test results.
example of cycles to failure theoretical projection with The isothermal temperatureswere
the
maximum
no consideration on failure shift is shown in Figure 4. thermalcyclingtemperatures.ThegridCSPswere
A life of more than 7,000 cycles for a thermal cycle fromthelist of leaded,leadless,andCSPs.Their
profile of -55°Cto125°Cwasprojected. This is an boardassembliesarebeingevaluated by theJPL-led
order of magnitude larger than experimental cycles to MicrotypeBGA consortium.
failure of 1,000 to 1,500 cycles. The TAB failure just
beforeassemblyfailurewasdetected at 1,000cycles CYCLES TO FAILURE DATA FOR PLASTIC PACKAGES
(Greathouse, CHIPCON'96)

CSP Reliabilitv Prediction J

W/O Consideration for Failure Mechanisms

Pre
Test Results
7,130 13,14
(-55"C1125"C) -
1,500 Shinko
I

15,190 27,820 (-55"C/85"C) -

1,000 Intel
Increw in M b e r olThcrnul Cycler

Figure 5 Wide Distribution for

Source: R. Larmouth, SMI '97 Two BGA Package Types
FCOB/F
FR-4flex
77 178 (-5SoC/l 25°C) SEM Characterization
Figure 4 Fatigue Failure Projection based on the Representative SEM photomicrographs of CSPball
Wrong Failure Mechanism Assumption for shapesandtheirinterfacesareshown in Figure 6.
a CTE Absorbed CSP Photos fora TAR CSP from two suppliers are shownin
a and b, and for a wafer version in c. Note differences
in interfaces for the s,me package,butfrom two
IhIV1'ackage Interface Failure suppliers as well as different package categories. The
For grid CSPs, theinterfacebetweenpackageand 'TAB CSP-I had a non solder mask defined
solderballsisanotherpotentialfailure site. This contigurationwhereas the CSP-2 had a solder mask
detined iIppe;UXtlce. Thesedifferencesmight not be
failure
type was observed for
plastic
BGAs after
significant for this specitic package since this CSP is
thermalcycling. For RGAs, cyclestofailureand

a
 Shear Iiorcesafter Isothermal I:4 x posu re
Kcsults for those exposed to 100 hours at 100°C are
nlso shown i n 1:igurc 7. ‘l’hcwaferlevelpackage
showed
improvement after
exposure. ‘The most
probable cause of this improvcmcnt is microstructural
changeswhich could hnvereducedtheprocessing
residual stresses. ‘This was not verified.

SEM of Shear Failures

SEM photomicrographsforthree CSPs areshownin

(a) Wafer Level CSP

(b) TABCSP-1
 I00 150 200 250 300 350 400 4x
JP L/N ASA (Grams)
Shear Force Rera Ghaflanan

Figure 7 Shear Force Distribution for Various CSPs

Table 1 Shear force and stress for various CSPs

Shear Shear Stress
Shear Shear Force
Package YO Diameter (grm) at Stress 100 Hours
Type (mm) 50 % (grm/mm’) at 100°C
TABCSP- 1 46 0.320 376 4,676 4,663
TABCSP-2 40 0.30 397 5,616 NIA
Wafer CSP 275 0.250 185 3,768 4,094
GridCSP 172 0.170 7,576
176 NIA

5
 ACKNOWLEDGMENTS
Theresearchdescribed in this publicationisbeing
CONCIAUSIONS carried outby the Jet Propulsion Laboratory, California
The allowable offset placement levels which result Institute of Technology,under n contractwiththe
in gridCSPacceptablenssembly are notwell National Aeronautics and Space Administration.
established. It was postulated that
tighter
a
placementcontrolmight be requiredforCSPs, I would like to acknowledge in-kind contribution and
than BGAs. cooperative. efforts of the MicrotypeBGA consortium
team members and those who have been contributing
Failureshiftfromsolder joint to package may to the progress of the program. Especial thanks to J.
occur more often for miniaturized CSP packages. Okunoand K. Evansforperformingsheartestsand
Projection based on the wrong failure mode results SEM characterizations.
in wrong forecast cycles for failure.
TheMicrotypeBGAconsortiumwasformedto
systematically address many of the CSP assembly
ball/package
Theissues.
reliability
characterization
performed was aimed at
understanding of other-than-boardsolder joint
sources of assembly failures.
Ballshearforces wm’differ for different CSPs.
Shear force distributions for the same package
type
differ for two suppliers.
Difference in shearforcesdepended on many
variables
including
interface
area,
metallurgy,
soldermaskdefined or non defined,andfailure
mechanisms.
Slight improvementin shear force or narrower
distribution was observed after packages exposure
at 100°C for 100 hr. Improvement may be due to
stress relaxation by annealing.
Assemblyhandlingcould be anissueforthose
CSP packages with low resistance to shear force.
Lowervalueinforce did nottranslate to lower
shear strengths (forcelarea).

REFERENCES

Ghaffari‘an,
“Update
R. CSP
on
Assembly
ReliabilityandJPL-ledMicrotypeBGAConsortium”,
The Third InternationalConference on Chio-scale
Packaging (CHIPCON’98), Feb. 12-13, 1998
2.Ghaffruian,R. “A Reviewof ChipScalePackage
Assembly
Reliability,” The Second
International
Conference on Chio-scale Packaging (CHIPCON ‘97A
Feb. 20-21, 1997

3. Ghaffarim, R., Kim, N.,“ReliabilityandFailure

Analysis o f Thermally
Cycled
Ball
Grid
Array
Assemblies,”
48th
Electronic
ComDoncnts
and
Technology Conference (EC‘I‘C), May 25-28, 1098