Scribd
Upload
18 views

Notes DEE604 Unit1

Here are the key steps to map a 2KB memory with a starting address of C000H: 1) 2KB memory = 2048 bytes 2) Each memory address is 16 bits (2 bytes) 3) To map 2048 bytes we will need 2048/2 = 1024 addresses 4) Starting address is given as C000H 5) Last address = Starting address + Number of addresses - 1 = C000H + 1024 - 1 = C3FFH Therefore, the 2KB memory will be mapped from address C000H to C3FFH.

Uploaded by

arselankhan9415
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
18 views

Notes DEE604 Unit1

Here are the key steps to map a 2KB memory with a starting address of C000H: 1) 2KB memory = 2048 bytes 2) Each memory address is 16 bits (2 bytes) 3) To map 2048 bytes we will need 2048/2 = 1024 addresses 4) Starting address is given as C000H 5) Last address = Starting address + Number of addresses - 1 = C000H + 1024 - 1 = C3FFH Therefore, the 2KB memory will be mapped from address C000H to C3FFH.

Uploaded by

arselankhan9415
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 16

Scanned by CamScanner

Scanned by CamScanner
Scanned by CamScanner
Scanned by CamScanner
Scanned by CamScanner
Scanned by CamScanner
214=24x210byte=24KB=16KB=16K
8085=3MHz
8085A=5MHz
216=210x210byte=1MB
ALU size=8 bitMicroprocessor is 8 bit
8BIT DATA BUS
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0 0 00H
1 1 1 1 1 1 1 1FFH
RANGE OF DATA 00H-FFH

MEMORY WORD SIZE (1,4,8)THE SIZE OF EACH


CELL.
MEMORY SIZE= TOTAL NO. OF BITS IT CAN
STORE
4X1 (SIZE=4BIT)
0
1
0
1

4X4(SIZE=16BIT)
4BIT= 1 NIBBLE
1011
1100
1101
0010

4X8 (SIZE=32BIT)
8 BIT=1 BYTE
10101111

16 BIT= 1 WORD
DESIGN THIS1024X8=1KBYTE
AVAILABLE -1024X4, 1024X4=1024X8
WE NEED 2 CHIPS OF 1024X4
NO. OF CHIPS=DESIGN MEMORY/AVAILABLE MEMORY
8X1024X8/1024X1=64

Available memory= 256x4


Design =2k
Total no. chips=2x1024x8/256x4=16
A15-A0=lower 8 bit (A7-A0 ) & higher 8 bit (A15-A8)
Data bus (D7-D0)
lower 8 bit (A7 -A0 ) multiplex with Data bus (D7-D0)AD7 -AD0
Register Classification of 8085
1. 6 general purpose registers (B, C, D, E, H, L) ALL ARE 8 BITS
2. 3 SPECIAL REGISTERS0 Reg A (Accumulator),
INSTURCTION REG (IR), FLAG REG (PSW) 8 bit wide
3. Temperaroy RegW & Z, Temporary data reg 8 bit wide
4. 16 bit Registers PC (Program Counter), SP (Stack Pointer)

ProgramAssembly Languagestore in memory Microprocessor


fetch instructions from memory
SODserial out data
SIDserial in data

Architecture of 8085
8085 Architecture Divided in various functional blocks
1. Registers
2. ALU
3. Instruction decoder
4. Increment/decrement address latch
5. Interrupt control unit
6. Serial i/o control
7. Address buffer
8. Address / data buffer
9. Timing & control unit

Register Classification of 8085

1. 6 general purpose registers  r (B, C, D, E, H, L) ALL ARE 8


BITS
Ex data48H (1 hex bit= 4 binary bit)=01001000
B=48H
They can also use as a register pair of 16 bit (rp)
Ex data485BH0100 1000 0101 1011
1st pair BCB
2nd pair DED
3rd pair HLH
r pB485BH (B=48H , C= 5BH )
2. 3 SPECIAL REGISTERS0 Reg A (Accumulator),
INSTURCTION REG (IR), FLAG REG (PSW) 8 bit wide
D7 D6 D5 D4 D3 D2 D1 D0
S Z -- AC -- P -- CY
0
Bit pattern of flag register
Ssign flag after the arithmetic or logical operation if result comes –
ve(this will check the D7 th bit of result, if D7=1, means no. is
negative)sign flag will be set
if result comes +ve (this will check the D7 th bit of result, if D7=0,
means no. is positive)sign flag will be reset
Zzero flag after the arithmetic or logical operation if result is zero
then flag set otherwise reset
ACduring the arithmetic operation when any carry generated from
lower nibble to higher nibble or from bit D3 to D4 then AC will be set
otherwise reset.

Pparity flag- after the arithmetic or logical operation in the result if


no. 1’s is even then flag set if no .of 1’s odd then reset.

P=0
CYcarry flag during the arithmetic operation any carry generated
from bit D7, then CY will be set otherwise reset.
3. Temperaroy RegW & Z, Temporary data reg 8 bit wide
We can not access these temp reg. microprocessor can access
these reg for internal work.
XCHG- data of HL pair swaped from data of DE pair.

4. 16 bit Registers PC (Program Counter), SP (Stack Pointer)


PC (Program Counter):it is a 16 bit reg, it holds the 16 bit address of
the instruction that is going to be executed next.
User task: Assemblyhex codememory store
Microprocessor task: memory fetchdecodeexcecute (run)
0000H 1st instruc
0001H 2nd instruct
.0010 3rd
.0011 4th
.0100 5th
.
.
.
.
.
FFFFH

SP (Stack Pointer):
LIFO-last in first out

Signed number representation


+45=8 bit form01000101 (MSB bit will be used as a sign bit)
+ve0
-ve1
-4511000101
+2000100000
00000000
00001000

0001 1st instruction


0002 2nd instruction
0003 2nd instruction
0004
0005
Memory Mapping:

Address range:
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

EXAMPLE- INTERFACE 256BYTE MEMORY IN SUCH AS


WAY THAT FIRST ADDRESS SHOULD BE A900H, ALSO FIND
THE LAST ADDRESS.
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0
1 0 1 0 1 0 0 1 1 1 1 1 1 1 1 1

FA=A900H
LA=A9FFH

ASSIGNMENT:
Map a memory of 2KB so that first address will be C000H. Also find
the last address.

You might also like