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MIPS Reference Data

This document contains a summary of the MIPS instruction set architecture including core instructions, floating point instructions, and pseudo-instructions. It lists the instruction name, mnemonic, operation format, and operation code for arithmetic, logical, branch, jump, data transfer, and floating point instructions. Floating point instructions are shown to have an FR format with fields for opcode, format, source registers, destination register, and immediate value.

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0% found this document useful (0 votes)
266 views

MIPS Reference Data

This document contains a summary of the MIPS instruction set architecture including core instructions, floating point instructions, and pseudo-instructions. It lists the instruction name, mnemonic, operation format, and operation code for arithmetic, logical, branch, jump, data transfer, and floating point instructions. Floating point instructions are shown to have an FR format with fields for opcode, format, source registers, destination register, and immediate value.

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Việt Hoàng
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© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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M I P S Reference Data 0 0

A RITHMETIC CORE INSTRUCTION SET OPCODE


/FMT /FT
FOR- /FUNCT
NAME, MNEMONIC MAT OPERATION (Hex)
CORE INSTRUCTION SET OPCODE Branch OnFP True belt FI if(FPcond)PC=PC+4+BranchAddr (4) 11/8/1/--
FOR- /FUNCT Branch OnFPFalse bclf FI if(!FPcond)PC=PC+4+BranchAddr(4) 11/8/0/--
NAME, MNEMONIC MAT OPERATION (in Verilog) (Hex) Divide div R Lo=R[rs]/R[rt]; Hi=R[rs]%R[rt] 0/--/--/l a
Add actct R R[rd] = R[rs] + R[rt] (I) 0 I 20hex Divide Unsigned divu R Lo=R[rs]/R[rt]; Hi=R[rs]%R[rt] (6) 0/--/--/l b
F P Add Single add.s FR F[fd ]=F[fs] +F[ft] 11/10/--/0
Add Immediate addi I R[rt] = R[rs] + SignExtlmm (1, 2) 8hex FP Add {F[fd],F[fd+l]} = {F[fs],F[fs+l]} +
add.ct FR 11/11/--/0
Add Imm. Unsigned addiu R[rt] = R[rs] + SignExtlmm (2) 9hex Double {F[ft],F[ft+l ]}
Add Unsigned addu R R[rd] = R[rs] + R[rt] O I 2 l hex FP Compare Single c.x.s* FR FPcond = (F[fs] op F[ft])? I : 0 11/10/--/y
FP Compare FPcond = ( {F[fs],F[fs+l]} op
And and R R[rd] = R[rs] & R[rt] O I 24hex c.x.d* FR 11/11/--/y
Double {F[ft],F[ft+l]})? I: 0
And Immediate andi R[rt] = R[rs] & ZeroExtlmm (3) *(xis eq, 1 t, or le) (op is ==, <, or <=) ( y is 32, 3c, or 3e)
if(R[rs]==R[rt]) FP Divide Single div.s FR F[fd] =F[fs] IF[ft] 11/10/--/3
Branch On Equal beq FP Divide
PC=PC+4+BranchAddr (4) div.ct FR {F[fd],F[fd+l]} {F[fs],F[fs+l]} I
=
11/11/--/3
if(R[rs]! =R[rt]) Double {F[ft],F[ft+l]}
Branch On Not Equaibne FP Multiply Single mul.s FR F[fd] =F[fs] * F[ft] 11/10/--/2
PC=PC +4+BranchAddr (4)
FP Multiply F[fd+l ]} = {F[fs],F[fs+l ]} *
Jump PC=JumpAddr (5) mul.d FR {F[fd], 11/11/--/2
Double {F[ft],F[ft+I]}
Jump And Link j al R[31]=PC+8;PC=JumpAddr (5) FP Subtract Single sub.s FR F[fd]=F[fs] -F[ft] 11/10/--/1
Jump Register jr FP Subtract
R PC=R[rs] PC + 4 sub.ct FR {F[fd],F[fd+l]) {F[fs],F[fs+l]}
=
11/l l /--/l
R[rt]={ 24'b0,M[R[rs] Double {F[ft],F[ft+l]}
Load Byte Unsigned lbu LoadFP Single lwcl F[rt]=M[R[rs]+SignExtlmm] (2) 311--/--1--
+SignExtlmm ](7:0)} (2)
Load Halfword R[rt]= { 16'b0, M[R[rs] LoadFP F[rt]=M[R[rs]+SignExtlmm]; (2)
lhu 25hex ldcl 35/--/--/--
Unsigned +SignExtlmm](15:0)} (2) Double F[rt+1]=M[R[rs ]+SignExtimm+4]
MoveFrom Hi mfhi R R[rd] = Hi 0 /--1--110
Load Linked 11 R[rt] = M[R[rs]+SignExtlmm] (2,7) 30hex
MoveFrom Lo mflo R R[rd] = Lo 0 /--/--/12
Load Upper Imm. lui R[rt] = { imm, 16'b0} fhex MoveFrom Control mfcO R R[rd] = CR[rs] 10 /0/--/0
Load Word lw R[rt] = M[R[rs]+SignExtlmm] (2) 23hex Multiply mult R { Hi, Lo} = R[rs] * R[rt] 0/--/--/18
Nor R R[rd] = - (R[rs] I R[rt]) O I 27hex Multiply Unsigned multu R { Hi;Lo} = R[rs] * R[rt] (6) 0/--/--119
Shift Right Arith. R R[rd] = R[rt] »> shamt 0/--/--/3
Or R R[rd] = R[rs] I R[rt] O I 25hex swcl
StoreFP Single M[R[rs]+SignExtlmm] =F[rt] (2) 39/--/--/--
Or Immediate ori R[rt] = R[rs] I ZeroExtlmm (3) dhex StoreFP M[R[rs]+SignExtlmm] =F[rt]; (2)
sdcl 3d/--/--/--
Set Less Than sl t R R[rd] = (R[rs] < R[rt])? I : 0 O I 2ahex Double M[R[rs]+SignExtlmm+4] =F[rt+l]
Set Less Than Imm. slti R[rt] = (R[rs] < SignExtlmm)? I : 0 (2) ahex FLOATING-POINT INSTRUCTION FORMATS
Set Less Than Imm. R[rt] = (R[rs] < SignExtimm) bhex FR I opcode I fmt I ft I fs fd f�
sl tiu
Unsigned ?I:0 (2,6) 31 26 25 21 20 16 15 II IO 65 0
Set Less Than Unsig. slt u R R[rd] = (R[rs] < R[rt])? I : 0 (6) 0 I 2bhex FI I opcode I fmt ft immediate
Shift Left Logical s11 R R[rd] = R[rt] « shamt O I OOhex 31 26 25 21 20 16 15
Shift Right Logical sr 1 R R[rd] = R[rt] » shamt O I 02hex PSEUDOINSTRUCTION SET
M[R[rs]+SignExtlmm](7:0) = NAME MNEMONIC OPERATION
Store Byte sb
R[rt](7:0) (2) Branch Less Than blt if(R[rs]<R[rt]) PC = Label
M[R[rs]+SignExtlmm] = R[rt]; Branch Greater Than bgt if(R[rs]>R[rt]) PC = Label
Store Conditional Branch Less Than or Equal ble if(R[rs]<=R[rt]) PC = Label
R[rt] =(atomic)? I : 0 (2,7)
M[R[rs]+SignExtlmm](l5:0) = Branch Greater Than or Equal bge if(R[rs]>=R[rt]) PC = Label
Store Halfword sh 29hex Load Immediate li R[rd] = immediate
R[rt](15:0) (2)
Move move R[rd] = R[rs]
Store Word M[R[rs]+SignExtlmm] = R[rt] (2) 2b hex
REGISTER NAME, NUMBER, USE, CALL CONVENTION
Subtract sub R R[rd] = R[rs] - R[rt] {!) 0 I 22hex
PRESERVED ACROS S
Subtract Unsigned subu R R[rd] = R[rs] - R[rt] O I 23hex NAME NUMBER USE
A CALL?
(I) May cause overflow exception $zero 0 The Constant Value O N.A.
(2) SignExtlmm { 16{ immediate[15]}, immediate }
=
$at I Assembler Temporary No
(3) ZeroExtlmm = { 16{ lb'O}, immediate }
Values forFunction Results
(4) BranchAddr = { 14{ immediate[15]}, immediate, 2'b0 } $v0-$vl 2-3 No
and Expression Evaluation
(5) JumpAddr = { PC+4[31:28], address, 2'b0 }
(6) Operands considered unsigned numbers (vs. 2's comp.) $a0-$a3 4-7 Arguments No
(7) Atomic test&set pair; R[rt] = I if pair atomic, 0 if not atomic $t0-$t7 8-15 Temporaries No
$s0-$s7 16-23 Saved Temporaries Yes
BASIC INSTRUCTION FORMATS
R I 3I
opcode I rs I rt I rd I shamt I funct
$t8-$t9
$k0-$ki
24-25 Temporaries
26-27 Reserved for OS Kernel
No
No
26 25 21 20 16 15 11 10 65
$gp 28 Global Pointer Yes
[ opcode I rs I rt immediate $sp 29 Stack Pointer Yes

I
31 26 25 21 20 16 15
$fp Frame Pointer Yes
I
30
J �code address $ra 31 Return Address Yes
31 26 25 0
Copyright 2009 by Elsevier, Inc., All rights reserved.From Patterson and Hennessy, Computer Organization and Design, 4th ed.

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