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Digital Circuits & Microprocessors

(Practice Questions)

06. Consider the equation (123)5 = (x8)y with x

Number System
and y as unknown. The number of possible
solutions is _______.
01. Given (135)x + (144)x = (323)x What is the
value of base x?
07. Let X be the number of distinct 16-bit integers
(a) 5 (b) 3
in 2’s complement representation. Let Y be
(c) 12 (d) 6
the number of distinct 16-bit integers in sign
02. The number of 1’s in 8-bits representation of magnitude representation.
–127 in 2’s complement form is m and that in Then X − Y is ________.
1’s complement form is n. What is the value of
m : n? 08. Match List- I with List- II and select the correct
(a) 2:1 (b) 1:2 answer by using the Codes given below the
(c) 3:1 (d) 1:3 lists:
03. A number in 4- bit two’s complement List – I List – II
representation is X3 X2 X1 X0. This number when (Hexadecimal) (Octal)
stored using 8 - bits will be A. 68 1. 150
(a) 0000 X3 X2 X1 X0. B. 8C 2. 214
(b) 1111 X3 X2 X1 X0. C. 4F 3. 117
(c) X3 X3 X3 X3 X3 X2 X1 X0 D. 5D 4. 135
(d) x3 x3 x3 x3 x3 x2 x1 x 0
Codes:
A B C D
04. The 2’s complement representation of
(a) 3 2 4 1
(-539)10 in hexadecimal is
(b) 2 3 1 4
(a) ABE (b) DBC
(c) 1 2 3 4
(c) DE5 (d) 9E7
(d) 3 1 2 4

05. The base (or radix) of the number system such

that the following equation holds is _________
312
20 = 13.1

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 2 Digital Circuits & MP

09. Match List – I with List – II and select the cor- The value of the bit pattern in 2’s comple-
rect answer by using the codes given below
ment representation is given in terms of the
the lists:
original number N is as
List – I List - II
(Octal) (Binary) (a) 32 a3+2N+1 (b) 32a3– 2N–1
A. 75 1. 010110 (c) 2N–1 (d) 2N+1
B. 65 2. 110101
C. 37 3. 111101
KEY
D. 26 4. 011111
01. (d) 02. (a) 03. (c) 04. (c)
Codes:
A B C D 05. 5 06. 3 07. 1 08. (c)
(a) 3 1 4 2
09. (b) 10. (a) 11. (a) 12. (d)
(b) 3 2 4 1
(c) 1 2 3 4
(d) 4 1 2 3 Logic Gates & Boolean Algebra
10. Statement (I): 2’s complement arithmetic is
preferred in digital computers. 01. Two 2’s complement numbers having sign
Statement (II): The hardware required to ob- bits x and y are added and the sign bit of the
tain the 2’s complement of a number, is sim- result is z. Then, the occurrence of overflow is
ple. indicated by the Boolean function.
(a) xyz (b) x y z
11. If (11X1Y)8 = (12C9)16 then the values of X and (c) x yz + xyz (d) xy + yz + zx
Y are
(a) 3 and 1 (b) 5 and 7 02. If the input to the digital circuit (in the figure)
(c) 7 and 5 (d) 1 and 5 consisting of a cascade of 20 XOR- gates is X,
then the output Y is equal to
12. A number N is stored in a 4-bit 2’s comple-
ment representation as 1
Y
a3 a2 a1 a0
X

It is copied into a 6-bit register and after a (a) 0 (b) 1 (c) X (d) X

few operations the final bit pattern is

03. How many min terms (excluding redundant
terms) does the minimal switching function
f ^v, w, x, y, zh = x + yz originally have?
a3 a3 a2 a1 a0 1
(a) 16 (b) 20
(c) 24 (d) 32

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 3 Objective Practice Questions

04. Given f1, f3, and f in canonical sum of products 06. Let, x1⊕x2⊕x3⊕x4 = 0 where x1,x2,x3,x4 are
form (in decimal) for the circuit. Boolean variables, and ⊕ is the XOR operator.
f1 = ∑ m (4, 5, 6, 7, 8) Which one of the following must always be
f3 = ∑ m (1, 15) TRUE?
f = ∑ m (1, 6, 8, 15) Then f2 is
(a) x1x2x3x4 = 0

f1 (b) x1x3 + x2 = 0
f
f2=? (c) x1 5 x3 = x2 5 x 4

f3 (d) x1+x2+x3+x4 = 0

(a) ∑ m (4, 6) 07. A 3 input majority gate is defined by the logic

(b) ∑ m (4, 8) function M(a,b,c) = ab + bc + ca. Which one
(c) ∑ m (6, 8) of the following gates is represented by the
function M ^M (a, b, c), M ]a, b, c g, c h ?
(d) ∑ m (4, 6, 8)

(a) 3-Input NAND gate

05. Consider the following circuit composed of
XOR gates and non-inverting buffers. (b) 3-Input XOR gate
(c) 3-Input NOR gate
B
A (d) 3-Input XNOR gate

δ1=2 δ2=4
08. All the logic gates shown in the figure have a
The non-inverting buffers have delays δ1= 2
propagation delay of 20 ns. Let A = C = 0 and
ns and δ2 = 4 ns as shown in the figure. Both
B =1 until time t = 0. At t = 0, all the inputs flip
XOR gates and all wires have zero delay.
Assume that all gate inputs, outputs and (i.e, A = C = 1 and B = 0) and remain in that
wires are stable at logic level 0 at time = 0. state. For t > 0, output Z =1 for a duration (in
If the following waveform is applied at input ns) of ___________
A, how many transition(s) (change of logic
levels) occur(s) at B during the interval from 0
A
to 10 ns? Z
B
Logic 1
C
A
Logic 0

1 2 3 4 5 6 7 8 9 10 11ns 09. A universal logic gate can implement any

Boolean function by connecting sufficient
(a) 1 (b) 2 number of them appropriately. Three gates
(c) 3 (d) 4
are shown.

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 4 Digital Circuits & MP

X F1=X+Y Codes:
Y A B C D
(a) 3 1 4 2
Gate 1
(b) 2 1 4 3
(c) 3 4 1 3
X F2=X.Y (d) 2 4 1 3
Y
Gate 2 11. Statement (I): XOR gate is not a universal
gate
Statement (II): It is not possible to realize
X F3=X+Y
any Boolean function using XOR gates only
Y
Gate 3 12. Match List-I with List-I and select the correct
answer using the codes given below the lists:
Which one of the following statements is
TRUE?
List-I List-II
(a) Gate 1 is a universal gate. A. A⊕B = 0 1. A≠B
(b) Gate 2 is a universal gate. B. A  B  0 2. A=B
(c) Gate 3 is a universal gate. C. A.B = 0 3. A = 1 OR B =1
D. A⊕B = 1 4. A = 1OR B =0
(d) None of the gates shown is a universal
gate. Codes:
A B C D
(a) 3 2 1 4
10. Match List-I with List-II and select the correct (b) 2 3 4 1
answer using the codes given below the (c) 3 2 4 1
lists: (d) 2 3 1 4

List - I List -II 13. Match List-I (Boolean Logic Function) with
A. A 1. AB List-II(Inverse of Function) and select the
x
B correct answer using the code given below
the lists:
B. A
x
2. AB
B
List-I
C. A x 3. A+B
B
A. ab+bc+ca+abc
B. ab + a b + c
D. A 4. C. a + bc
x
A+B
D. ^a + b + c h^a + b + c h^a + b + ch
B

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 5 Objective Practice Questions

List-II 16. Statement (I): A NAND gate represents a

1. a ( b + c) universal logic family.
2. a b+b c+c a Statement (II): Only two NAND gates are
3. (a 5 b) c sufficient to accomplish any of the basic
4. abc + abc + abc gates.
(a) Both I and II are true and II is the correct
Codes:
explanation of I
A B C D
(b) Both I and II are true but II is NOT the
(a) 3 2 1 4
(b) 2 3 1 4 correct explanation of I
(c) 3 2 4 1 (c) I is true but II is false
(d) 2 3 4 1 (d) I is false but II is true

14. Match List – I with List – II and select the

correct answer using the code given below
KEY
the lists : 01. (c) 02. (b) 03. (b) 04. (c) 05. (d)
List – I
A. AND gate 06. (c) 07. (b) 08. 40 09. (c) 10. (d)
B. OR gate 11. (a) 12. (b) 13. (b) 14. (c) 15. (a)
C. NOT gate
16. (c)
List – II
1. Boolean complementation
2. Boolean addition
K - Mpas
3. Boolean multiplication

Codes: 01. Minimum SOP for f(w, x, y, z) shown in

A B C Karnaugh -map below is
(a) 3 1 2
(b) 1 2 3 wx
yz 00 01 11 10
(c) 3 2 1
(d) 1 3 2 00 0 1 1 0

01 x 0 0 1
15. Statement (I): When all inputs of a NAND-
gate are shorted to get a one input, one x 0 0
11 1
output gate, it becomes an inverter.
Statement (II): When all inputs of a NAND – 10 0 1 1 x

gate are at logic ‘0’ level, the output is at

(a) xz + y′z (b) x z′ + z x′
logic ‘1’ level
(c) x′ y + z x′ (d) None

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 6 Digital Circuits & MP

02. What is the minimal form of the Karnaugh 05. Which of the following logic circuits is a
map shown below? Assume that X denotes a realization of the function F, whose Karnaugh
don’t care term. map is shown in figure.

ab
00 01 11 10 AB
cd 00 01 11 10
C
00 1 X X 1
0 1 1
01 X 1
1 1 1
11

10 1 X (a)
A

(a) b d (b) b d + b c
(c) b d + ab cd (d) b d + b c + c d
B
C
03. Find the SOP and POS expressions for the
K- MAP shown below.
(b) A
wz→ 00 01 11 10
xy↓
00 0 X 0 0
01 0 X 1 1 B
11 1 1 1 1 C
10 0 X 0 0

04. For an n-variable Boolean function, the (c) A

maximum number of prime implicants is
(a) 2(n – 1) (b) n/2
(c) 2n (d) 2(n+1)
C

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 7 Objective Practice Questions

(d) 09.
For the Karnaugh map shown in the given
A
figure, the minimum Boolean function is
C x yz 0 1
00 1 1
01 1
B
11 1 1
10 1 1
06. The number of min-terms after minimizing the
following Boolean expression is ___________.
(a) x1 y1 + z1 + yz (b) xz1 + z + zy1
6D + AB + AC + ACD + A CD@ (c) xy + z + y1z (d) x1z1 + yz

07. The total number of prime implicants of the 10. The K-map for a Boolean function is shown
function f(w, x, y, z) = ∑(0, 2, 4,5, 6, 10) is in figure. The number of essential prime
_______________. implicants for this function is

08. Consider the Karnaugh map given below: AB

CD 00 01 11 10
The function represented by this map can be
00 1 1 0 1
simplified to the minimal form as
01 0 0 0 1
X1X2
X3X4 00 01 11 10 11 1 0 0 0
00 1 d d
10 1 0 0 1
01 1 d 1
11 d 1
10 1 d d
(a) 4 (b) 5
(c) 6 (d) 8
(a) X1 X 2 X 4 + X 2 X 4 + X1 X 3
(b) X1 X 2 X 4 + X 2 X 4 + X1 X 2 X 3 X 4
(c) X 2 X 4 + X 2 X 4 + X1 X 3 KEY
(d) X1 X 2 X 4 + X1 X 2 X 3 X 4 + X1 X 2 01. (b) 02. (b) 03. SOP: xy + yw,

POS : (y) (x+w)

04. (a) 05. (c) 06. 1 07. 3 08. (c)

09. (a) 10. (a)

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 8 Digital Circuits & MP

03. Consider the ALU shown below

Combinational Circuits
K B0
B1 A0
A1
01. Consider the multiplexer based logic circuit
shown in the figure.

C1 C0
W 0 C2 Full Adder Full Adder
MUX 0
F
1 MUX S1 S0
1 If the operands are in 2’s complement

S1
representation, which of the following

S2 operations can be performed by suitably

setting the control lines K and C0 only (+

Which one of the following Boolean functions and – denote addition and subtraction
is realized by the circuit? respectively)?

(a) A+B, and A–B, but not A+1

(a) F = WS1 S2
(b) A+B, and A+1, but not A–B
(b) F = WS1 + WS2 + S1 S2
(c) A+B, but not A–B, or A+1
(c) F = W + S1 + S2
(d) A+B, and A–B, and A+1
(d) F = W 5 S1 5 S2

02. A half adder is implemented with XOR and 04. A 1-to-8 demultiplexer with data input Din,
AND gates. A full adder is implemented address inputs S0, S1, S2 (with S0 as the LSB) and
with two half adders and one OR gate. The Y0 to Y7 as the eight demultiplexed outputs,
propagation delay of an XOR gate is twice is to be designed using two 2-to-4 decoders
that of and AND/OR gate. The propagation (with enable input and address inputs A0 and
delay of an AND/OR gate is 1.2 microseconds.
A1) as shown in the figure. Din, S0, S1 and S2
A 4-bit ripple-carry binary adder is
are to be connected to P,Q,R and S , but not
implemented by using four full adders. The
necessarily in this order. The respective input
total propagation time of this 4-bit binary
adder in microseconds is _______________. connections to P, Q, R and S terminals should
be

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 9 Objective Practice Questions

07. Statement (I): The race hazard problem does

1Y0 Y0
P not occur in combinational circuits.
1E 2-to-4 1Y Y1
Q 1 Statement (II): The output of a combinational
decoder
R 1A0 1Y2 Y2 circuit depends upon present inputs only.
S 1A1 1Y3 Y3
08. Statement (I): A de-multiplexer can be used
as a decoder.
Statement (II): A de-multiplexer is built by
2Y0 Y4
using AND gates.
2E 2-to-4 2Y1 Y5
decoder
2A0 2Y2 Y6 09. Match List – I (function/circuit) with List – II
2Y3 Y7 (circuit realization) and select the correct
2A1
answer using the codes given below the
(a) S2, Din, S0, S1 (b) S1, Din, S0, S2 Lists:
List – I
(c) Din, S0, S1, S2 (d) Din, S2, S0, S1
A. D – flip flop
B. T – flip flop
05. For the circuit shown in figure, the delays of
C. Exclusive OR
NOR gates, multiplexer and inverters are 2ns,
D. Half adder
1.5ns and 1ns, respectively. If all the inputs
List – II
P,Q,R,S and T are applied at the same time
instant, the maximum propagation delay (in 1.
ns) of the circuit is _______
Input Output
P
0
Q
0 Y
R 2. Input J Q
MUX
MUX
Output
S 1 1 S K
0 Q
S0

T
3. Input J Q
Output
06. Consider an eight-bit ripple-carry adder for
K Q
computing the sum of A and B, where A and
B are integers represented in 2’s complement
form. If the decimal value of A is one, the
4.
Output
decimal value of B that leads to the longest Input
latency for the sum to stabilize is _________.

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 10 Digital Circuits & MP

Codes:
Sequential Circuits
A B C D
(a) 2 3 1 4
(b) 2 3 4 1 01. In the circuit shown, choose timing the
(c) 3 2 4 1 correct timing diagram of the output (y) from
(d) 3 2 1 4
the given waveforms W1, W2, W3 and W4.

10. Statement (I): A 64 input MUX can be

X1 D Q
constructed using eight 8-input multiplexers.
FF1
Statement (II): Any six variable functions can Clk Q Output (y)
always be implemented by a multiplexer with
six selection lines.
X2 D Q
FF2
11. A 16-bit ripple carry adder is realized using Q
16 identical full adders (FA) as shown in the
figure. The carry-propagation of each FA is 12
ns and the sum-propagation delay of each
clk
FA is 15 ns. The worst case delay (in ns) of this
16-bit adder will be ______. x1
A0 B0 A1 B1 A14 B14 A15 B15
x2
C0 C1 C14 C15
FA0 FA1 FA14 FA15 w1

S0 S1 S14 S15 w2

12. Statement (I): Any Boolean function can be w3

realized by using a suitable multiplexer.
Statement (II): A multiplexer can be realized w4
using NAND and NOR gates, which are
universal gates. (a) W1 (b) W2
(c) W3 (d) W4
KEY

01. (d) 02. 19.2 03. (a) 04. (d) 05. 6

06. –1 07. (d) 08. (b) 09. (b) 10. (b)

11. 195 12. (b)

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 11 Objective Practice Questions

02. We want to design a synchronous counter (a)

that counts the sequence 0-1-0-2-0-3 and 1

then repeats. The minimum number of J-K

0
flip-flops required to implement this counter is t1+ΔT
2T
________.
03. A mod-n counter using a synchronous binary
up-counter with synchronous clear input is (b)
shown in the figure. The value of n is ______ 1

0
4-Bit Binary QA QA
Counter QB QB t1+2ΔT
4T
Set
CLK QC QC
CLEAR QD QD
(c)
1

0
t1+2ΔT
04. For each of the positive edge-triggered 2T

J-K flip flop used in the following figure, the

propagation delay is ∆ T
(d)
1
1 J0 1 J1 Q1
Q0
0
CLK t1+ΔT
Q0 Q1 4T
1 K0 1 K1

05. Let k = 2n. A circuit is built by giving the output

CLK
of an n-bit binary counter as input to an n-to-
1
2n bit decoder. This circuit is equivalent to a

0 (a) k-bit binary up counter.

(b) k-bit binary down counter.
t1 T t
(c) k-bit ring counter.
(d) k-bit Johnson counter.
Which of the following waveforms correctly
represents the output at Q1?

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 12 Digital Circuits & MP

06. The shift register shown in fig. is initially loaded

(c)
with the bit pattern 1010. Subsequently the
shift register is clocked, and with each clock J
T Qn
pulse, the pattern gets shifted by one bit
K T-FF
position to the right. With each shift, the bit
Clk Qn
at the serial input is pushed to the left most
position (MSB). After how may clock pulses
will the content of the shift register become (d)
1010 again?
J Qn
Clk T

1 0 1 0 K T-FF
Serial
input Clk
Qn

08. Assume that all the digital gates in the circuit

(a) 3 (b) 7 (c) 11 ( d ) shown in the figure are ideal, the resistor
15 R = 10 kΩ and the supply voltage is 5V. The
D flip-flops D1, D2 D3, D4 and D5 are initialized
07. A JK flip flop can be implemented by T flip- with logic values, 0, 1, 0, 1 and 0, respectively.
flops. Identify the correct implementation. The clock has a 30% duty cycle.

(a)

J Qn D Q D Q D Q D Q D Q R=
T 10kΩ
D1 D2 D3 D4 D5
K T-FF

Clk Clk
Qn

The average power dissipated (in mW) in the

(b)
resistor R is ___________

J
T Qn

K T - FF

Clk
Qn

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 13 Objective Practice Questions

09. Find the number of states after reducing the Which one of the following statements is
following state table correct?
(a) T r a n s i t i o n s f r o m S t a t e A a r e
Present Next State Output (Y) ambiguously defined
State X=0 X=1 X=0 X=1 (b) Transition from State B are ambiguously
A A E 0 0 defined
B C A 1 0
(c) Transitions from State C are
C B A 1 0
ambiguously defined
D A B 0 1
(d) All of the state transitions are defined
E A C 0 1
unambiguously.
(a) 4 (b) 3 (c) 2 (d) 5

12. Statement (I): Asynchronous sequential

10. Determine the function of the following FSM,
circuits are difficult to design.
1/0 Statement (II): External clock is used for
synchronization of asynchronous sequential
0/1 S0 S1 1/0 circuits.

0/1 13. Statement (I): Master-slave JK flip-flop is

preferred to an edge-triggered JK flip-flop in
* given ‘s0’ is the initial state
high speed circuits.
(a) 2’s complement of a binary input Statement (II): Master-slave JK flip-flop is free
(b) sequence detector of sequence 110 from race-around problem.
(c) 1’s complement of a binary input
(d) none of the above 14. Match List I with List II and select the correct
answer using the codes given below the Lists:
11. The state transition diagram for a finite state
machine with states A, B and C, and binary List I (Application of circuit)
input X, Y and Z, is shown in the figure. A. Divider
Y=1 B. Clips input voltage at Two predetermined
X=0, Y=0, Z=0 levels
A B C. Square wave generator
Y=0, Z=0 Y=1
D. Narrow current pulse generator
X=0, Z=1
1
X=

, Z=
1,

1
X=

List II (Circuit Name)

X=
Y=

Z=
1,

0,

1. Astable multivibrator
Y=

Y=
0

C 2. Schmitt trigger
3. Bi stable multivibrator

Z=0 4. Blocking oscillator

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 14 Digital Circuits & MP

Codes:
Logic Gate Families
A B C D
(a) 4 2 1 3
(b) 3 2 1 4 01. Given that for a logic family, VOH is the minimum

(c) 4 1 2 3 output high-level voltage VOL is the maximum

(d) 3 1 2 4 output low-level voltage VIH is the minimum

acceptable input high- level voltage and VIL
15. Statement (I): A flip-flop is a bistable is the maximum acceptable input low-level
multivibrator. voltage. (GATE - 87)
Statement (II): A flip-flop remains in one The correct relationship is:
stable state indefinitely until it is directed by (a) VIH > VOH > VIL > VOL
an input signal to switch over to the other (b) VOH > VIH > VIL > VOL
stable state.
(c) VIH > VOH > VOL > VIL
(d) VOH > VIH > VOL > VIL
16. Statement (I): The collection of all state
variables (memory element stored values) 02. The DTL, TTL, ECL and CMOS family GATE of
at any time, contain all the information digital ICS are compared in the following 4
about the past, necessary to account for the columns
circuit’s future behaviour. (GATE - 03)

Statement (II): A change in the stored values

(P) (Q) (R) (S)
in memory elements changes the sequential
Fan out is
circuit from one state to another DTL DTL TTL CMOS
minimum
Power
KEY consumption TTL CMOS ECL DTL
is minimum
01. (c) 02. 4 03. 7 04. (b) 05. (c) Propagation
06. (b) 07. (b) 08. 1.5 09. (b) 10. (c) delay is CMOS ECL TTL TTL
minimum
11. (c) 12. (c) 13. (d) 14. (b) 15. (a)
The correct column is
16. (a)
(a) P (b) Q
(c) R (d) S

03. The circuit diagram of a standard TTL NOT

gate is shown in the figure.
When Vi = 2.5V, the modes of operation of
the transistors will be

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 15 Objective Practice Questions

digital signals with 0 V as logic 0 and Vcc as

VCC=5V
logic 1, then the Boolean expression for Z is

4k 1.4k 100Ω
+VCC
+ Q4
Q1
Vi
Q2 R1
D

+ Z
Q3
V0 R2
1k
–
X Q1
Diode

(a) Q1: reverse active (b) Q1: reverse

active Q2: normal active Y
Q2: saturation
(a) XY (b) XY
Q3: saturation Q3: saturation (c) XY (d) XY
Q4: cut-off Q4: cut-off
06. Statement (I): Schottky transistors are
(c) Q1: normal active (d) Q1: saturation
preferred over normal transistors in digital
Q2: cut-off Q2: saturation
circuits.
Q3: cut-off Q3: saturation
Statement (II): Schottky transistors operate in
Q4: saturation Q4: normal active active and saturation region.

04. The logic function implemented by the 07. Statement (I): To obtain high switching speed
following circuit at the terminal out is in BJT based logic circuits, transistors are
vdd operated in active region.
Statement (II): In active region, a transistor
works as a linear element.
out
P Q
08. Statement (I): When transistor switches are
to be used in an application where speed is
a premium, it is better to reduce the storage
(a) P NOR Q (b) P NAND Q time.
(c) P OR Q (d) P AND Q Statement (II): It is comparatively easy to
reduce storage time rather than the rise time
05. In the circuit shown below, Q1 has negligible and fall time of a transistor switch.
collector-to-emitter saturation voltage and
the diode drops negligible voltage across it
under forward bias. If Vcc is +5V, X and Y are

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 16 Digital Circuits & MP

09. Statement (I): The TTL NAND gate in tri-state 03. If the input X3, X2, X1, X0 to the ROM in the figure
output configuration can be used for a are 8421 BCD numbers, then the outputs Y3,
bus arrangement with more than one gate Y2, Y1, Y0 are
output connected to a common line.
Statement (II): The tri-state configuration has
X3 X2 X1 X0
a control input, which control the bus line.

KEY ROM
BCD-to-Decimal Decoder
01. (b) 02. (b) 03. (b) 04. (d) 05. (b)

D0 D1 ................. D8 D9
06. (c) 07. (b) 08. (a) 09. (a)

Y3
Y2
Semiconductor Memories Y1
Y0
01. A ROM is to be used to implement a “squarer”,
which outputs the square of a 4-bit number.
(a) Gray code numbers
What must be the size of the ROM?
(b) 2421 BCD numbers
(a) 16 address lines and 16 data lines.
(c) excess-3 code numbers
(b) 4 address lines and 8 data lines.
(d) none of the above.
(c) 8 address lines and 8 data lines
(d) 4 address lines and 16 data lines 04. In the circuit shown in the figure. A is parallel-
in, parallel out 4 bit register, which loads at
02. A single ROM is used to design a combinational the rising edge of the clock ‘C’. The input lines
circuit described by a truth table. What is the are connected to a 4 bit bus, W. Its output
number of address lines in the ROM? acts as the input to a 16 x 4 ROM whose
(a) Number of input variables in the truth output is floating when the enable input E is
table. 0. A partial table of the contents of the ROM
(b) Number of output variables in the truth is as follows.
table. Address Data
(c) Number of input plus output variables in 0 0011

the truth-table. 2 1111

4 0100
(d) Number of lines in the truth-table.
6 1010
8 1011
10 1000
11 0010
14 1000

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 17 Objective Practice Questions

(b)
The clock to the register is shown, and the WL
VDD
data on the W bus at time t1 is 0110. The data
BL BL
on the bus at time t2 is

C A
(c) WL
VDD

BL BL

1 ROM
E

C
(d) WL
VDD
time BL BL
t1 t2

(a) 1111 (b) 1011

(c) 1000 (d) 0010

05. If WL is the Word Line and BL the Bit Line, as

SRAM cell is shown in
06. Static RAM is preferred over dynamic RAM
(a)
when the requirement is of
WL
VDD (a) Slow speed of operation
BL BL (b) larger storage capacity
(c) Lower access time
(d) lower power consumption

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 18 Digital Circuits & MP

07. Match List I (Name of Memory) with List II 09. Consider the following statements for a
(Features/Characteristics) and select the DRAM:
correct answer using the codes given below 1. Bit is stored as a charge.
the List: 2. It is made of MOS transistors.
3. Speed of DRAM is faster than processors
List I (Name of Memory)
4. Each memory cell requires six transistors
A. SRAM
B. ROM
Which of these statements are correct.
C. PLA
(a) 1 and 2 only (b) 2 and 3 only
D. DRAM
(c) 3 and 4 only (d) 1, 2, 3 and 4

List II (Features/Characteristics)
KEY
1. This contains conventional storage like
latches (BJT or MOSFET) and it is non
01. (b) 02. (a) 03. (b)
volatile.
04. (c) 05. (b) 06. (c)
2. This contains conventional storage like
latches (BJT or MOSFET) and has both 07. (b) 08. (d) 09. (a)
Read and Write operation.

3. This contains a set of AND, OR and INVERT

AD & DA Converters
logic gates and can be programmed.

4. This contains only MOSFET’s and needs

01. A 4-bit D/A converter is connected to a
periodic refreshing.
free-running 3-bit up counter, as shown
in the following figure which of the
Codes:
following waveforms will be observed at
A B C D V0= ?
(a) 3 4 2 1
(b) 2 1 3 4 1K
(c) 3 1 2 4 Q2 D3
(d) 2 4 3 1 D2 –
+ V0
Q1 D1
08. Consider the following statements: Q0 D0
1. SRAM is made up of flip flops 3 bit 4 bit
Clock up counter
DAC
2. SRAM stores bit as voltage
3. DRAM has high speed and low density
In the figure shown above, the ground has
4. DRAM is cheaper than SRAM.
been shown by the symbol
Which of the above statements are correct?
(a) 1, 2, and 3 (b) 1, 3 and 4
(c) 2, 3 and 4 (d) 1, 2 and 4

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 19 Objective Practice Questions

(b) The counter starts from the clear state.

(a)

VDAC 4 Bit
D/A
Converter
(d)
(c)
Binary 2 Digit
to LED
+5V BCD Display
Clk
– 4 Bit
Statement for Linked Answer Qs. 02 & 03: + Up
In the Digital-to-Analog converter circuit shown in Vin=6.2V Counter
the figure below, VR= 10 V and R = 10 Clock Clock

R R R i 2R
VR 04. The stable reading of the LED display is
(a) 06 (b) 07
2R 2R 2R 2R R
(c) 12 (d) 13
–
V0
+ 05. The magnitude of the error between VDAC
and Vin at steady state in volts is
(a) 0.2 (b) 0.3
02. The current i is
(c) 0.5 (d) 1.0
(a) 31.25μA (b) 62.5 μA
(c) 125 μA (d) 250 μA
06. For a dual ADC type 3 ½ digit DVM, the
reference voltage is 100 mV and the first
03. The voltage V0 is
integration time is set to 300 ms. For some
(a) -0.781V (b) -1.562V
input voltage, the “de integration” period is
(c) -3.125V (d) -6.250V
370.2ms. The DVM will indicate.
(a) 123.4 (b) 199.9
Statement for Linked Answer Qs. 04 & 05:
(c) 100.0 (d) 1.414
In the following circuit, the comparator output is
logic “1” if Vin > VDAC and is logic “0” otherwise. 07. For an 8-bit digital-to-analog converter having
The D/A conversion is done as per the relation reference voltage of 8 V, the least significant
3
VDAC = / 2n - 1 bn Volts, where b3(MSB), b2, b1and b0 4 bits of the input are grounded and the most
n=0
significant 4 bits are driven by 4 bit data from
(LSB) are the counter outputs. a binary counter. The maximum obtainable
peak-to-peak amplitude of a waveform at

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 20 Digital Circuits & MP

the output of the digital-to-analog converter for proper conversion. Assume that the time
is taken by the thermometer to binary encoder
(a) 4 V (b) 6 V is negligible.
(c) 7.2 V (d) 7.5 V

–
08. The simplified block diagram of a 10-bit A/D Vref255
+
converter of dual slope integrator type is
shown in the Fig. The 10-bit counter at the
output is clocked by a 1 MHz clock. Assuming
negligible timing overhead for the control – Thermometer Digital
Vref2 code Output
logic, the maximum frequency of the analog +
to binary
signal that can be converted using this A/D conversion
converter is approximately. Vin –
+ +
– Vref1
Integrator,
Va 10-bit
comparator Digital
counter
and control output
Vr Logic
If the flash ADC has 8 bit resolution, which
one of the following alternatives is closest to
Clock Frequency the maximum sampling rate?
1MHz
(a) 1 megasamples per second
(a) 2 kHz (b) 1 kHz (b) 6 megasamples per second
(c) 500 Hz (d) 250 Hz (c) 64 megasamples per second
(d) 256 megasamples per second
09. In an N bit flash ADC, the analog voltage is
fed simultaneously to 2N – 1 comparators. The
10. Statement (I): Dual-slope A/D converter is the
output of the comparators is then encoded
most preferred A/D conversion approach in
to a binary format using digital circuit.
digital multimeters.
Assume that the analog voltage source Vin
(whose output is being converted to digital Statement (II): Dual-slope A/D converter
provides high accuracy in A/D conversion,
format) has a source resistance of 75Ω as
while at the same time suppressing the hum
shown in the circuit diagram below and the
effect on the input signal.
input capacitance of each comparator is 8
pF. The input must settle to an accuracy of (a) Both I and II are true and II is the correct
explanation of I.
1/2 LSB even for a full scale input change

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 21 Objective Practice Questions

(b) Both I and II are true but II is not the List – II (Properties of A/D converters)
correct explanation of I. 1. Fixed conversion time, depends on the
(c) I is true but II is false. no of bits
(d) I is false but II is true. 2. High speed operation
3. Hum rejection Approximation
11. Match List I with List II and select the correct 4. Conversion time dependent on single
answer using the codes given below the lists amplitude
5. Large conversion time
List - I
A. SAR type ADC Codes:
A B C D
B. Flash ADC
(a) 3 2 5 4
C. Dual slope ADC
(b) 2 3 4 1
D. Counter-DAC (c) 3 4 1 2
(d) 4 1 2 5
List – II
1. Settling time dependent on the input 13. Statement (I): The output of an 8-bit A to D
2. Works well even in noisy environment converter is 40H for an input of 2.5V.
3. (2 – 1) comparators required for n-bit
n
Statement (II): ADC has an output range of
4. Settling time for n-bits type ADC 00 to FFH for an input range of –5V to +5V.
(single RAMP) is (n + 2).T clock pulses.
14. Statement (I): Digital ramp converter is the
Codes: slowest ADC.
A B C D
Statement (II): It requires N2 clock pulses for
(a) 3 4 1 2 conversion.
(b) 4 3 1 2
(c) 3 4 2 1 15. The resolution of a 12 bit Analog to Digital
(d) 4 3 2 1 converter in percent is
(a) 0.01220 (b) 0.02441
12. Match List I with List II and select the correct (c) 0.04882 (d) 0.09760
answer using the codes given below the lists

KEY
List – I (Types of A/D converter)
A. Dual Slope 01. (b) 02. (b) 03. (c) 04. (d)
B. Counter-Ramp 05. (b) 06. (a) 07. (d) 08. (d)
C. Successive
09. (a) 10. (a) 11. (d) 12. (c)
D. Simultaneous
13. (a) 14. (c) 15. (b)

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 22 Digital Circuits & MP

(a) 0100H-02FFH (b) 1500H-16FFH

Architecture, Pinout of 8085 &
8KB RAM. (c) F900H-FAFFH (d) F800H-F9FFH
Interfacing with 8085

03. For the 8085 microprocessor, the interfacing

01. The decoding circuit shown below has been circuit to input 8-bit digital data (DI0 - DI7)
used to generate the active low chip select from an external device is shown in the figure.
signal for a microprocessor peripheral. (The The instruction for correct data transfer is
address lines are designated as A0 to A7 for
7
I/O addresses) 6 I/O Device
A2 C 5
3-to-8 Digital
A2 A1 B Decoder 43 DI0-DI7
inputs DO0-DO7 Digital Bus
A3 A0 A 2
(D0-D7)
1
0
G2A G2B G1 DS1 DS2
A4
IO/M
A5 RD A8
CHIP A
A3 A9
SELECT A54
A6 A10
A6 A7 A11
A12
A7 A13
A14
A15
The peripheral will correspond to IO addresses
in the range
(a) MVI A, F8H (b) IN F8H
(a) 60 H to 63 H (b) A4 H to A7 H
(c) OUT F8H (d) LDA F8F8H
(c) 50 H to AF H (d) 70 H to 73 H
04. An output device is interfaced with 8 bit
02. What memory address range is NOT microprocessor 8085A. The interfacing circuit
represented by chip 1 and chip 2 in the figure. is shown in figure
A0 to A15 in this figure are address lines and CS
means chip select. AB
8
BDB
256B 3L×8L Decoder
A7-A0 Chip1 A15
8
I 0
A14 2
CS A13 I1 1 output port
2
A8 A12 I0 8
3
A9 A11 E1 4
5 output Device
A8 E2
6
A9 E3 7
A7-A0 CS IO/M WR
256B BCB
Chip2

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 23 Objective Practice Questions

The interfacing circuit makes use of 3 line to 8 06. An 8 Kbyte ROM with an active low Chip Select
line decoder having 3 enable lines E1, E2 , E3 input is to be used in an 8085 microprocessor
The address of the device is based system. The ROM should occupy the
(a) 50H (b) 5000 H
address range 1000H to 2FFFH. The address
(c) A0H (d) A000H
lines are designated as A15 to A0, where A15
is the most significant address bit. Which one
05. There are four chips each of 1024 bytes
connected to a 16 bit address bus as shown of the following logic expression will generate

in the figure below. RAMs 1, 2, 3 and 4 the correct signal for this ROM?
respectively are mapped to addresses. (a) A15 + A14 + ^A13 .A12 + A13 . A12 h
(b) A15 .A14 .(A13 + A12)
(c) A15 . A14 . ^A13 . A12 + A13 .A12h
RAM#4
1024B (d) A15 + A14 + A13 .A12
E

07. 3 × 8 decoder with two enable inputs is to be

RAM#3
8 - bit data bus

1024B used to address 8 blocks of memory. What

E
will be the size of each memory block when
addressed from a sixteen bit bus with two
RAM#2
A0- A9 1024B MSB’s used to enable the decoder?
E (a) 2K (b) 4K

A10
(c) 16K (d) 64K
RAM#1
A11 1024B
A12 11
08. Statement (I): The data path contains all the
Input

A13 10 E
A14 01
S1 S0 00
circuits to process data within the CPU with
A15 the help of which data is suitably transformed.
Statement (II): It is the responsibility of the
control path to generate control and timing
a) 0C00H-0FFFH, 1C00H-1FFFH, 2 C 0 0 H - signals as required by the opcode.
2FFFH,3C00H-3FFFH
(a) Both I and II are true and II is the correct
(b) 1800H-1FFFH, 2 8 0 0 H - 2 F F F H ,
explanation of I.
3800H-3FFFH, 4800H-4FFFH
(c) 0500H-08FFH, 1 5 0 0 H - 1 8 F F H , (b) Both I and II are true but II is not the
3500H-38FFH, 5500H-58FFH correct explanation of I.
(d) 0 8 0 0 H - 0 B F F H , 1 8 0 0 H - 1 B F F H , (c) I is true but II is false.
2800H-2BFFH, 3800H-3BFFH (d) I is false but II is true.

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 24 Digital Circuits & MP

09. Statement (I): Program counter is a register 14. Statement (I): Instruction SIM is necessary to
that contains the address of the next implement the interrupts INTR.
instruction to be executed Statement (II): INTR requires external
Statement (II): IR (Instruction Register) is not
hardware for implementation.
accessible to programmer.

10. Statement (I): A processor can reference a

KEY
memory stack without specifying an address. 01. (a) 02. (d) 03. (d) 04. (b) 05. (d)
Statement (II): The address is always available
06. (a) 07. (a) 08. (a) 09. (b) 10. (a)
and automatically updated in the stack
11. (c) 12. (b) 13. (c) 14. (d)
pointer.

11. Which one of the following statements does Instruction set of 8085 &
not describe property/characteristic of a Programming with 8085
stack pointer register in 8085 microprocessor?
(a) It points to top of the stack
01. The following instructions have been executed
(b) It is UP/DOWN counter
by an 8085 µP
(c) It is automatically initialized to 0000H on
ADDRESS INSTRUCTION
power-on
(HEX)
(d) It is a 16-bit register
6010: LXI H, 8A79H
6013: MOV A, L
12. Statement (I): The DMA technique is more
6014: ADD H
efficient than the Interrupt-driven technique
6015: DAA
for high volume I/O data transfer. 6016: MOV H, A
Statement (II): The DMA technique does not 6017: PCHL
make use of the Interrupt mechanism. From which address will the next instruction
be fetched?
13. Statement (I): The main difference between (a) 6018
a microprocessor and a microcontroller is (b) 0379
that the former does not have any on-chip (c) 6979
memory. (d) None of the above
Statement (II): A microprocessor does not
need memory to run programs.

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 25 Objective Practice Questions

Common Data for Questions 02 & 03 Instruction T-state

Consider an 8085 microprocessor system
MVI B,0AH 7T
02. The following program starts at location LOOP:MVI C,05H 7T
0100H. DCR C 4T
LXI SP, 00FF DCR B 4T
LXI H, 0107 JNZ LOOP 10T/7T
MVI A, 20H
The execution time of the program in terms of
SUB M
T-states is
The contents of accumulator when the
(a) 247T (b) 250T
program counter reaches 0109H is
(c) 254T (d)257T
(a) 20H (b) 02H
(c) 00H (d) FFH.
06. A software delay subroutine is written as given
below:
03. If in addition following code exists from
DELAY: MVI H, 255D
0109H onwards ORI 40H,ADD M What will be
MVI L, 255D
the result in the accumulator after the last
LOOP: DCR L
instruction is executed
JNZ LOOP
(a) 40H (b) 20H
DCR H
(c) 60H (d) 42H
JNZ LOOP
How many times DCR L instruction will be
04. In an 8085 processor, the main program calls
executed?
the subroutine SUB1 given below. When the
program returns to the main program after (a) 255 (b) 510 (c) 65025 (d) 65279
executing SUB1, the value in the accumulator
is 07. An 8085 microprocessor executes “STA
Address Opcode Mnemonics 1234H” with starting address location1FFEH
2000 3E,00 SUB1: (STA copies the contents of the Accumulator
MVI A,00H to the 16–bit address location). While the
2002: CD,05,20 CALL SUB2 instruction is fetched and executed, the
2005: 3C SUB2: INR A sequence of values written at the address
2006: C9 RET pins A15 – A8 is
(a) 1FH, 1FH, 20H, 12H
(a) 00H (b) 01H (c) 02H (d) 03H
(b) 1FH, FEH, 1FH, FFH, 12H
05. An 8085 assembly language program is (c) 1FH, 1FH, 12H, 12H
given as follows. The execution time of each (d) 1FH, 1FH, 12H, 20H, 12H
instruction is given against the instruction in
terms of T-state.

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 26 Digital Circuits & MP

08. In an 8085 microprocessor, which one of the (b) Memory write operations are slower
following instructions changes the content of than memory read operations in an 8085
the accumulator? bases system.
(a) MOV B, M (b) PCHL (c) The stack pointer needs to be pre-
(c) RNZ (d) SBI BEH determined before writing registers in a
PUSH, whereas a POP operation uses the
09. Which one of the following 8085 microprocessor address already in the stack pointer.
programs correctly calculates the product of (d) Order of register has to be interchanged
two 8-bit numbers stored in registers B and C? for a PUSH operation, whereas POP uses
(a) MVI A, 00H their natural order.
JNZ LOOP
CMP C 11. In an 8085 microprocessor, the contents of
LOOP: DCR B the accumulator and the carry flag are A7
HLT
(in hex) and 0, respectively. If the instruction
(b) MVI A, 00H
RLC is executed then the contents of the
CMP C
accumulator (in hex) and the carry flag,
LOOP: DCR B
JNZ LOOP respectively, will be

HLT (a) 4E and 0 (b) 4E and 1

(c) MVI A, 00H (c) 4F and 0 (d) 4F and 1
LOOP: ADD C
DCR B 12. Statement (I): The port address in IN/OUT
JNZ LOOP instruction is 8 bit.
HLT
Statement (II): The address byte is duplicated
(d) MVI A, 00H
in machine cycle for IN/OUT instruction.
ADD C
(a) Both I and II are true and II is the correct
JNZ LOOP
LOOP: INR B explanation of I.

HLT (b) Both I and II are true but II is not the

correct explanation of I.
10. In a 8085 system, a PUSH operation requires (c) I is true but II is false.
more clock cycles than a POP operation, (d) I is false but II is true
which one of the following options is the
correct reason for this?
13. When RET instruction is executed by any
(a) For POP, the data transceivers remain in
subroutine then
the same direction as for instruction fetch
(memory to processor), whereas for PUSH (a) The top of the stack will be popped out
their direction has to be reversed and assigned to the PC

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 27 Objective Practice Questions

(b) Without any operation, the calling 16. Match List – I with List – II and select the

program would resume from instruction correct answer using the codes given below

immediately following the call the lists:

List – I List - II
instruction
A. Immediate addressing 1. LDA 30FF
(c) The PC will be incremented after the
B. Implied addressing 2. MOV A, B
execution of the instruction
C. Register addressing 3. LXIH, 2050
(d) Without any operation, the calling
D. Direct addressing 4. RRC
program would resume from instruction

immediately following the call instruction, Codes:

and also the PC will be incremented A B C D
(a) 3 4 2 1
After the execution of the instruction
(b) 2 1 3 4
(c) 3 1 2 4
14. How many and which types of machine (d) 2 4 3 1
cycles are needed to execute PUSH PSW by

an Intel 8085 A microprocessor? 17. With reference to 8085 microprocessor, which

of the following statements are correct?
(a) 2, Fetch and Memory write
1. The DAD instruction adds the contents of
(b) 3, Fetch and 2 Memory write
the specified register pair to the contents
(c) 3, Fetch and 2 Memory read
of the DE register pair.
(d) 3, Fetch, Memory read and Memory 2. The program counter is an instruction
write pointer
3. Whenever an instruction uses the HL

15. Statement (I): The zero-flag of a 8085 pointer, the addressing is called indirect
addressing.
microprocessor is not affected after the
4. HL register pair is also called data
execution of the following couple of pointer.
instructions:
(a) 1 and 2 only (b) 1,2 and 3
MVI B,03H
(c) 2, 3 and 4 (d) 2 and 4 only
MOV A, B

Statement (II): After the execution of a 18. Each instruction in an assembly program has
data transfer instruction, zero-flag is set if the following fields:
1. Label field. 2. Mnemonic field.
accumulator content is zero
3. Operand field. 4. Comment field.

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 28 Digital Circuits & MP

The correct sequence / order of these fields is: 21. Match List- I (Instruction) with List- II
(Operation) for Intel 8085 and select the
(a) 1, 2, 3, 4 (b) 1, 2, 4, 3
correct answer using the codes given below
(c) 2, 1, 3, 4 (d) 2, 1, 4, 3
the lists :
List- I (Instruction)
19. For Intel 8085, match List I (Addressing Mode)
A. PCHL
with List II (Instruction) and select the correct
B. SPHL
answer using the codes given below the lists :
C. XTHL
List-I (Addressing Mode)
D. XCHG
A. Implicit addressing
List- II (Operation)
B. Register-indirect
1. Exchange the top of the stack with the
C. Immediate
contents of HL pair
D. Direct addressing
2. Exchange the contains of HL with those
List-II (Instruction)
of DE pair
1. JMP 3FA0H
3. Transfer the contents of HL to the stack
2. MOV A, M
pointer
3. LDA 03FCH
4. Transfer the contents of HL to the program
4. RAL
counter
Codes:
Codes:
A B C D
A B C D
(a) 4 1 2 3
(a) 3 4 1 2
(b) 4 2 1 3
(b) 3 4 2 1
(c) 3 2 1 4
(c) 4 3 2 1
(d) 3 1 2 4
(d) 4 3 1 2

20. On the 8085, which of the following

machine cycle are not used in the call
instruction? KEY
1. Instruction fetch 01. (c) 02. (c) 03. (c) 04. (c) 05. (c)
2. I/O. 06. (d) 07. (a) 08. (d) 09. (c) 10. (c)
3. Memory read 11. (d) 12. (b) 13. (a) 14. (b) 15. (c)
4. Memory write. 16. (a) 17. (c) 18. (a) 19. (b) 20. (a)
Select the correct answer using the code 21. (d)
given below?

(a) 2 only (b) 1 and 4

(c) 2, 3 and 4 (d) none of these

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 29 Objective Practice Questions

05. For 8086 microprocessor, the jump distance in

8086 Microprocessors
bytes for short jump range is
01. As compared to 16 bit microprocessor, 8 bit (a) Forward 255 and Backward 256
microprocessors are limited in:
(b) Forward 127 and Backward 128
1. Speed
(c) Forward 31 and Backward 32
2. Directly addressable memory
(d) Forward 15 and Backward 16
3. Data handling capability
(a) 1 and 2 only (b) 2 and 3 only
(c) 1 and 3 only (d) 1, 2 and 3 06. What is the address space of 8086
CPU?
02. In the case of a 16-bit processor, a single (a) 1MB (b) 256 KB
instruction is enough to process a function. (c) 1 MB (d) 64 KB
For processing the same function
(a) more than one 8-bit processors will be
07. The instruction queue length in INTEL 8086 and
required to work in sequence
8088 are
(b) more than one 8-bit processors will be
required to work in parallel (a) 6 bytes in both processors
(c) a long sequence of instructions will be (b) 4 bytes in both processors
required for a 8-bit processor (c) 4 bytes in 8086 and 6 bytes in 8088
(d) the same instruction will do for a 8- bit (d) 6 bytes in 8086 and 4 bytes in 8088
processor also

08. To have the multiprocessing capabilities of

03. Consider the following statements
the 8086 microprocessor, the pin connected
1. A total of about one million bytes can
be directly addressed by the 8086 to the ground is
microprocessor (a) DEN (b) ALE
2. 8086 has thirteen 16-bit registers (c) INTR (d) MN/ MX
3. 8086 has eight flags
4. Compared to 8086, the 80286 provides a 09. In a 16-bit microprocessor, words are stored
higher degree of memory protection
in two consecutive memory locations. The
Which of the statements given above are
entire word can be read in one operation
correct?
provided the first
(a) 2, 3 and 4 (b) 1, 3 and 4
(c) 1, 2 and 4 (d) 1, 2 and 3 (a) Word is even
(b) Word is odd
04. Which one of the following control bits of 8086 (c) Memory location is odd
flag register is used to put the 8086 in single (d) Memory address is even
step mode?
(a) DF (b) IF (c) TF (d) ZF

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 30 Digital Circuits & MP

10. If (BX) = 0158 (a) T1 and T2 (b) T2 and T3

(DI) = 1045 (c) T3 and T4 (d) T4 and T1
Displacement = 1B57
(DS) = 2100 14. When an 8086 executes an INT type
instruction, it
(where DS is used as a segment register)
(a) Resets both IF an TF flags
then the effective and physical addresses
(b) Resets all flags
produced using “RELATIVE BASE
(c) Sets both IF and TF
INDEXED INDIRECT ADDRESSING” will be (d) Resets the CF and TF
respectively
(a) 2D54 and 23D54 15. The interrupt vector table IVT of 8086 contains
(b) 23CF4 and 2CF4 (a) The contents of CS and IP of the main

(c) 1B57 and 1CAF program address at which the interrupt

has occurred
(d) 1CAF and 1B57
(b) The contents of CS and IP of the main
program address to which the control
11. In 8086 microprocessor, if the code segment
has to come back after the service
register contains IFAB and IP register contains
routine
10A1, the effective memory address is
(c) The starting CS and IP values of the
(a) 20B51 (b) 304C
interrupt service routine
(c) FBC0 (d) FDB5
(d) The starting address of the IVT

12. Consider the following functions of an 8086

microprocessor: 16. The 8086 arithmetic instructions work on

1. Temporary storage of data 1. Signed and unsigned numbers.

2. Storing offset of a memory address in DS 2. ASCII data
3. String instructions 3. Unpacked BCD data
4. JCXZ instructions Select the correct answer using the codes
Which of these functions require the use of
given below:
the SI and DI registers?
(a) 1 and 2 (b) 2 and 3
(a) 1, 2 and 3 (b) 1, 2 and 4
(c) 1 and 3 (d) 1, 2 and 3
(c) 2, 3 (d) 3, 4 and 5

17. Which of the following instructions of an 8086

13. The length of a bus cycle in 8086/8088 is four microprocessor uses the contents of a CX
clock cycles, T1, T2, T3, T4 and an indeterminate register as a counter.
number of wait state clock cycles denoted 1. LOCK
by Tn. The wait states are always inserted 2. LOOP
between 3. ROTATE

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 31 Objective Practice Questions

Select the correct answer using the code

8051 Microcontroller
given below:
(a) only 1 and 2 (b) only 1 and 3
01. How many bytes of bit addressable memory
(c) only 2 and 3 (d) 1, 2 and 3 is present in 8051 microcontroller
(a) 8 (b) 32
18. In a multi-processor configuration, two (c) 16 (d) 128 Bytes
coprocessors are connected to the host 8086
processor. The two co-processor instruction 02. In 8051 microcontroller, the size of RAM, ROM
sets available respectively are
(a) Must be the same (a) 128Bytes, 4KB (b) 256Bytes, 4KB
(b) May overlap (c) 256Bytes, 2KB (d) 128Bytes, 2KB
(c) Must be disjoint
03. In 8051 microcontroller, if we push the data
(d) Must be the same as that of the host
on to the stack, then the stack pointer
(a) increases with every push
19. The action performed by the following
(b) decreases with every push
instruction of 8086: mov [1234h], AX
(c) both (a) and (b)
(a) Move contents of memory location
(d) none of the above
1234h to register AX
(b) Move the contents of register AX to 04. Find the status of carry, Auxiliary carry and
memory offset 1234h parity flags after executing the following
(c) Add contents at 1234h and AX instructions
(d) Add contents of 1234h and AX and store MOV A, #9CH
the result in 1234h ADD A, #64H
(a) CY = AC = P = 0
(b) CY = 1, AC = 1, P = 1
KEY
(c) CY = 1, AC = 1, P = 0
01. (c) 02. (c) 03. (c) 04. (c) 05. (b) (d) AC = 0, CY = 1, P = 1

06. (a) 07. (d) 08. (d) 09. (d) 10. (b)
05. In the following instructions which one doesn’t
11. (a) 12. (c) 13. (b) 14. (a) 15. (c) produce op-code
16. (d) 17. (c) 18. (c) 19. (b) (a) ADD A, R2 (b) MOV A, #12
(c) ORG 2000H (d) SJMP Here

06. The memory assigned for 4 register banks in

8051 microcontroller is
(a) 00H – 0FH (b) 00H – 20H
(c) 00H – 1FH (d) 00H – 31H

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 32 Digital Circuits & MP

07. On power UP, the 8051 uses RAM location 04. ‘I2C’ is
_____ for register R0 (a) it is a serial bus for inter connecting IC’s
(a) 00H (b) FFH (c) 1FH (d) 08H (b) it is a bus for inter connecting a central
control network
KEY (c) it is a serial bus for interconnecting a
system
01. (c) 02. (a) 03. (a) 04. (c) (d) it is a high level data link control

05. (c) 06. (c) 07. (d)

KEY

Embeded Systems 01. (b) 02. (b) 03. (d) 04. (a)

01. Which of the following is a real time

embedded systems
(a) Ceiling fan
(b) Microwave oven
(c) TV
(d) Desktop key board

02. SOC is
(a) Application specific integrated circuit
(b) Embedded system design on a single
chip
(c) Embedded system with ASIC
(d) None

03. Which of the following are the considerations

when selecting a processor in an embedded
system?
(a) Instruction set
(b) Processor ability
(c) Max bits in the operand
(d) All of the above

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