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CISC Vs RISC

RISC vs CISC architectures are compared. CISC CPUs were originally simple but gained complexity over time through additional instructions. This led to issues like reduced performance and higher complexity. RISC architectures returned to simpler designs with fewer general purpose instructions that execute in single cycles. This improved performance while reducing complexity. Neither RISC nor CISC is clearly superior, and hybrid approaches combining aspects of both may be optimal. The debate involves hardware/software tradeoffs and factors beyond just instruction set design.

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36 views

CISC Vs RISC

RISC vs CISC architectures are compared. CISC CPUs were originally simple but gained complexity over time through additional instructions. This led to issues like reduced performance and higher complexity. RISC architectures returned to simpler designs with fewer general purpose instructions that execute in single cycles. This improved performance while reducing complexity. Neither RISC nor CISC is clearly superior, and hybrid approaches combining aspects of both may be optimal. The debate involves hardware/software tradeoffs and factors beyond just instruction set design.

Uploaded by

Shopon Pal
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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RISC vs.

CISC
with guidance from Rui Wang
& Tibor Horvath’s presentation
CISC
• CISC: complex instruction set computer
• But original CPUs very simple
• Poorly suited to evolving high level languages
• Extended with new instructions
– e.g. function calls, non-linear data structures, array bound
checking, string manipulation
• Implemented in microcode (which are RISC like)
– sub-machine code for configuring CPU sub-components
– 1 machine code == > 1 microcode
• e.g. Intel X86 architecture
CISC continued
• CISC introduced integrated combinations of
features
– e.g. multiple address modes, conditional execution
– required additional circuitry/power
– multiple memory cycles per instruction
– over elaborate/engineered
• many feature combinations not often used in practise
• Could lead to loss of performance
• Better to use combinations of simple instructions
CISC Problems
• Performance tuning unsuccessful
• Rarely used high-level instructions
• Sometimes slower than equivalent sequence
• High complexity
• Pipelining bottlenecks → lower clock rates
• Interrupt handling can complicate even more
• Marketing
• Prolonged design time and frequent microcode
errors hurt competitiveness
More about CISC
• Wired logic → microcode control
• Temptingly easy extensibility
• Performance tuning
• HW implementation of some high-level functions
• Marketing
• Add successful instructions of competitors
• “New feature” hype
• Compatibility: only extensions are possible
RISC
• RISC: reduced instruction set computer
• return to simpler design
• general purpose instructions with small number of
common features
• less circuitry/power
• execute in single cycle
• code size grew
• performance improved
• e.g. ARM, MIPS
RISC Features
• Low complexity
• Generally results in overall speedup
• Less error-prone implementation by hardwired
logic or simple microcodes
• VLSI implementation advantages
• Less transistors
• Extra space: more registers, cache
• Marketing
• Reduced design time, less errors, and more
options increase competitiveness
RISC Compiler Issues
• The compilers themselves
• Computationally more complex
• More portable

• The compiler writer


• Less instructions → probably easier job
• Simpler instructions → probably less bugs
• Can reuse optimization techniques
RISC vs. CISC misconceptions

• Arguments favoring RISC: simple design,


short design time, speed, price…

• Study of RISC should include


hardware/software tradeoffs, factors
influencing computer performance and
industry-side evaluation.
RISC vs. CISC misconceptions

• Incorrect implication from the two


acronyms: RISC and CISC.
• They are not bifurcations between which designers
have to choose

• Carelessly leaving out the ‘participation’


of Operating System
RISC vs. CISC misconceptions

• Reduced design time?


• academic <-> industrial

• Performance claims of RISC proponent


do not decouple design features like
MSRs (Model Specific Register).
• MRSs can have a remarkable effect on program
execution
Conclusion – RISC vs. CISC?
• CISC
• Effectively realizes one particular High Level
Language Computer System in HW - recurring
HW development costs when change needed

• RISC
• Allows effective realization of any High Level
Language Computer System in SW - recurring SW
development costs when change needed
Conclusion – Optimum?
• Hybrid solutions
• RISC core & CISC interface
• Still has specific performance tuning

• Optimal ISA
• Between RISC & CISC
• Few, carefully chosen, useful complex instructions
• Still has complexity handling problems
CISC vs RISC
CISC vs RISC
CISC vs RISC
CISC vs RISC
CISC vs RISC
CISC vs RISC
https://cs.stanford.edu/people/eroberts/cours
es/soco/projects/risc/risccisc/

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