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78 viewsCao Chapter 01 .
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© © All Rights Reserved
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/ 49
sz020:202
4% Semester
syllabus For BE IT
Computer Organization & Architecture
Unite: Basic structure of computer: Hardware & softwar,
program sequencing, Concept of memory locations
Fadress. Main memory operation. Instructions
instruction sequencing. Addressing. modes. Basic I/q
operations. Stacks. Queues & subroutines. }
[Refer Chapter 1
Unit-: Processing Unit: fundamental concepts. Execution
of a complete instruction, Hardwired control, performance
consideration. Micro-programmed control; |
microinstructions. [Refer Chapter 3]
Unit-tIl: /0 organization: Accessing I/O devices, interrupts, _
And direct memory access, bus arbitration: centralized and _
distributed. 1/0 hardware: processor bus (Synchronous & |
Asynchronous). [Refer Chapter 4]
@
Unit-4V: Memory Unit: Basic concepts, semiconductor Ra |
memories, internal organization, static & dynamic RAMs, |
ROMs. Speed, size & cost considerations. [Refer Chapter 2]
Unit-V: Cache memories: performance considerations
Virtual memories, address translation. Multiprocessor: The
Use of Multiprocessors, Symmetric Multiprocessor and
Clusters. [Refer Chapter 7]
Unie Arithmetic: Number representation. Design of fast
adders, signed addition and subtraction. Multiplication of
nt sequential multiplication, _ fast
nultiplication, Booths’ algorithm for multiplication, integer
Givson,restoringand non-restoring division.
[Refer Chapter 5]
2
Sr el | i, ie
Basic Structure of Computer
CHAPTER 1
Chapter One
1.1 Introduction
‘The word computer comes from the word
compute; to compute means to calculate. The
computer can be defined as an electronic device
that receives stores and processes data rapidly
according to the stored program.
‘The earliest computers had their programs
written as a series of binary instructions known
as machine language. But, the machine language
programs were difficult to understand for human
and hence percentage of errors in programs was
more. To avoid these problems the operations
and operand addresses were written in a
symbolic format instead of binary format.
1.2 Computer Types
In simple words, we can define computer as a
device that operates upon data. A computer can
store, process and retrieve data as and when
desired. In other words, a computer can be
‘defined as an electronic automatic device for
making calculations or controlling operations
that are expressible in numerical or logical terms.
‘The list of instructions is called a computer
program, and the internal storage is called
\computer memory.
‘There are different types of computers depending
on their size, cost, computational power and the
area where they are going to be used.
mputer Architecture & Organization yy sox, FA re
be
Chapter One
Computer Architecture & Organization
Basic Structure of Compute,
Mainframe Computer: It is traditional “large
computer system which contains thousands oj
ICs and its cost is very high. This type of
computers typically used by a University, q
factory or a bank in earlier stages of invention
of computers. This is room-sized machine
which is not accessible to the average user.
Minicomputer: It is the smaller (desk size)
and slower version of mainframe computers
with relatively low cost. It is useful for small
business.
Microcomputer: the combination of CPU,
memory and I/O circuit in one IC or small
number of ICs is called a microcomputer. It is”
again smaller, slower and cheaper’ that
packages all electronics of a computer into an
Personal Computer: Microcomputer
technology gave rise to the new class of
general purpose machines called as personal
computers. These are intended for single user.
It is widely used in homes, schools, «and
business offices. It is the most common form
. of desktop computers.
Desktop Computer: It has i
Computer: processing and
storage units, visual display and audio etait
units, and a keyboard that can all be located
a on A home or office desk. The storage
in 7
aan lude hard disks, CD-ROMs, and
Le Notebook Computer: These are a
oun ey een of the personal computer
oa , Llese components packaged into a
gle unit and it is the thin briefcase size.
NN
The program stored in the memory decides th
Computer Architecture & Organization
Chapter One Basic Structure of Computer
Draw a functional block diagram of a computer and
explain the function of each lock in brief.
: (S-15/19, W-15/17/19 for 6/7 marks)
Draw functional Glock, diagram of a computer.
Explain the function of each block in brief. What are
three most important aspects that count the
performance of computer? _(S-17 for 8 marks)
1.2.1 Functional Units
«A computer consists of five | fuinctionally
independent units:
1. Input Unit =—
2, Memory Unit
3. Arithmetic and Logical Unit
4, Output Unit and
8. Control Unit as shown in'Figure 1.1.
* The input unit accepts digital information
as keyboard, riouse, microphones étc.
‘The information received is‘ either stored ih
the memory for later use or immediately used
by the arithmetic and logic unit to perform the
desired operations.’ :
processing steps and output is either given (6°
the user with the, help of output devices such
‘as monitor, printer, speaker etc. or stored in
the memory for later use.
* All. the above mentioned activities are
coordinated and controlled by the control unit.
Wee
13
from user with the help of input devices such . v
Chapter One
The arithmetic and logical unit in combination
with control unit is called as Centra)
Processing Unit (CPU).
Basic Structure of Computer
Memory Unit
wm 7
hf
Arithmetic |
meet | ses uar arpa al
Control Unit! ti
Figure 1.1 Basic Functional Units of d Computer
1) Input Unit: ?
+ A. computer accepts digital information
through input unit using input devices.
* The most commonly used input’ devices
keyboard and mouse. =.” ie
* The keyboard is used for entering ext anc
e te
numeric information. , oe ee
* Whenever a key is pressed, the I igi
\ ' 7 letter or digit
is automatically translated into its binary
equivalent code and transmitted over a cable
either the memory or the processor.
Th :
peruse) is used to position the screen
and entering the information by
selecting options,
° Ay
input deme h@Yboard and mouse different
spaceball, are joysticks, _ trackballs,
digitizers and scanners,
Computer Archit
itecture & Organization ww 14
Basic Structure of Computer
Chapter One
2) ee Unit:
«the memory unit is used to store pro;
and data.
ams
«The memory unit is composed of two types of
memory devices: primary and secondary.
* The primary memory is commonly called as
| + These cells are read6r
in speed and used
and data, which is
main memory which is
for storing | program
currently ynder process.
« The mail memory is a semi conductor
memory.
« It consists of large number of semiconductor
storage cells, each capable of storing one bit of
information.
yritten by CPU in a
group of fixed size called Word.
° To ess data from particular’ word from
“main memory, each word is assigned a
distinct address. We can access the word by
specifying corresponding address.
© ‘The number of bits in each word is called as
word length of the computer. It varies from 8
to 64 bits. a= .
© The number of such. words in the main
memory is called as size or capacity of main
memory. :
e is the time required to access
ry. The access time
it is of the
* Access tim
one word from memo:
should be as small as possible. I
order 10 to 100 nanoseconds.
15
‘Computer Architecture & Organization
we Chapter One Basie Structure of Compute,
Access time depends on the type of memory.
For randomly accessed memories it is fixed fo,
any word while in sequentially accesseq
memories it is not fixed. ;
+ ‘The main memory consists of only randomly _
accessed memories, which is very fast but
small in size and expensive,, |
+ Therefore, the computel uses Secondary _
storage memories such as magnetic tapes,
magnetic disks for storing large amount of
lata. 4 %
3) Arithmetic and Logical Unit:
* It is responsible for performing arithmetic
operations such as add, subtract, division,
multiplication and logical operations such as
ANDing, ORing, Inverting etc,
To perform these operations, operands from
be ea memory are brought-into'the high
storage elements called regi ;
speed stor led registers of the
Each register can store one word of data and
they are
Gee used to store frequently used
* After performing operations, the result is
either stored i i
eeaton in the register or memory
ponies example: Suppose two numbers
ie nee dl the memeny are to be added. They
rar se
Addition i caried out Spygate etal
The is :
tei ee Stored in the ™memory or
an n the processor for immediate use/’
fer Architecture & Organization Wier 1.
FG
}
i
|
{
}
Chapter One Basic Structure of Computer
Any other arithmetic or logic operation, for
example, multiplication, ~ division - of
comparison of numbers is initiated by
bringing the required operands into the
processor where the operation is performed by
the ALU.
4) Output Unit:
j 2
« The output unit sends the processed results
| to the user using output devices’ such as video
| monitor, printer, plotter, etc.
2 The video monitors display output on the CRT
screen whereas printers and plotters give the
hard copy output. f
‘. Printers are classified according to their
printing methodology: impact printers and
non-impact printers. Y 2
5) Control Unit:
|. The control unit is called as supervisor of
computer because it supervises all the
activities amongst the functional units.”
«Control unit fetches the instuctions stored in
the main memory, identifies the operations
and devices involved’ in jt and accordingly
generate the ‘control signals to execute the
desired operations.
«It uses two types of signals i.e. control and
timing to determine when a given action is to
be take place.
«It controls input-output operations and data
transfer between processor, memory and 1/0
devices using timing signals.
Computer Architecture & Organization ¥3y// Ly a
Chapter One
‘The control and arithmetic and logical unit 9;
‘a computer are usually many times faste,
than other devices, conhected to compute;
hence; control unit can, control all the 1/9
devices.
‘After learning all the functional units of
computer system it is time to know what is
exactly the computer organization and computer
architecture. The key definitions are as follows:
Computer Organization: ’
The manner in which visible components of
the computer required to be interconnected so
that they can have necessary ‘synchronization is
called “computer organization”: :
Computer Architecture:
[ ame designing aspect of each components
computer is call “com
of a come led asi! “computer
Basic Structure of Compute,
t
F
1.3 Basic Operational Concepts
. oe fanctiis of computer ‘is to fetch the
ns from memo i:
and execute the ‘pobre F ne os i
After execution result is eit
user through output device
memory for later use.
ither given to the
or stored in the
All the functional uni
‘unit il a
program ae fa nits contribute to executela
h :
© Input Unit: accepts data and instructions
from user
© Memory Unit: )
\ in meee * stores data and instructions
mputer Architecture & Organization
Wen 18
dl
.
7
‘hapter One Basic Structure of Computer
Arithmetic and logical Unit: performs
arithmetic and logical operations
o Control Unit: supervises all the activities
o Output Unit: gives result back to the user
To execute the instruction, the processor
requires some general purpose registers for ©
temporary storage of data arid some special
purpose registers like PC, IR, MAR and MDR
as shown in figure 1.2 ie
Program Counter (PC):
+_Aprogram is’ set of instructions which are
J, to be executed. ~
© These instructions must be execute
proper sequence.” .
‘This execution’ sequignce
program counter. //
So, program counter is known as pointer
register which (points and keeps track-of the
address of next instruction which_is_to.be
exéeuted.
Instruction Register (IR):
It holds the instruction whi
being executed.
‘The content of IR are available to the control
unit which in turns generate the control
signals to control various ‘processing
elements involved in instruction executién
| Memory Address Register (MAR) and Memory
Data Register (MDR):
© These registers are used to handle the data
transfer between the main memgry andthe
. Yo 2?
‘d in a
is monitored by
E ich is currently
4
/ processor...
"Computer Architecture & Organization Basic Structure of Compute,
js the address of the maj,
which processor j,
Chapter One
The MAR holds the
memory location with
currently.communicating.
so called as MBR (Memory Buffe,
the MDa cles MO in ae
Regine addressed word of the main memory.
, %
Figure 1.2 Connections between the Processor & Memory
General Purpose Registers (GPRs):
These are the registers used to store.necessary
. data for an ALU and the. result after
computation, ae
they are used to store frequently used data.
Execution of instruction ADD LOCA, Ro:
* PC will point to the Instruction ADD LOCA Ro,
The content of PC will be
transferred to the
ec ed of abut is connected to. the
and simultaneously
t to the mi
Computer Architecture & Organization yt
eS
Access time of these registers is too small so |
Chapter One Basic Structure of Computer
+ Then, address word is received from memory
and stored in MDR. Then content of MDR will
be transferred to IR tp decode and execute.
¢ Fetch the second operand from memory
location LOCA and add the contents of
register Ro with the help of ALU. Store the
result in Ro,
1.4 Bus Structure
¢ The CPU, Memory unit and I/O unit are the
hardware components of the computer.
° For performing various operations "they
require | connection and, communication
between them. nk
* The collection of paths connecting these
components is called '4s interconnection
structure. ee
"+ A group of wires used to provide necessary
| signals for - communication _ between
componenits is called as bus;
eA bus that connects major components of a
_ ‘computer like CPU, memory and 1/0 is called
as a system bus. a
¢ The bus interconnection scheme is as shown
Figure 1.3 Bus Interconnection Scheme.
rent
mputer Architecture & Organization ee
chaperone Basie Structure of Commute
ae bus is separated into three functiona,
groups:
1. Data Bus
2. Address Bus
3. Control Bus
1, Data Bus:
* ‘The data bus consists of/8, 16, 32 or more
parallel lines. i
‘The data bus lines are bi-directional ic
used to receive data from memory and ~ «
input unit and to give data to memory and
output unit. ‘ t
‘The data bus is connected in parallel
the componénts.
2. Address Bus:
* The address bus consists of 16, 20, 24 or
more parallel lines. :
* The address bus is unidirectional.
. cru. sends the .address of the memory
location or 1/O port which is it
arenes! | Port which is to be written
3. Control Bus:
* The o i
the bart?! lines regulate the activity on
fo all
we
* The CPU send
to enable the
devices or
Is signals: on the control bus
outputs of ax
Dor aenuts of addressed memory
Computer Architecture & Organizatio
n
Wet?
Chapter One Basic Structure of Computer
‘Typical control lines include the following:
Memory Write: data is written’ ‘to
addressed memory location.
the
Memory Read: data is placed on the bus from
the addressed memory lccation.
1/O Write: data is given to the addressed 1/0
port.
1/O Read: data is placed on the bus from the
addressed 1/0.
‘Transfer ACK: indicates that data have been
from or placed on the bus.
Bus Request: module needs to gain control of
the bus.
Bus grant: requesting module has been
granted control of the bus.
Interrupt Request: an interrupt is pending.
Interrupt ACK: pending interrupt has been
recognized.
‘Clock: synchronize operations.
Reset: initializes all modules,
1.4.1 Single Bus Structure
Another way to represent bus interconnection
“scheme is shown in figure 1.4. Here, address
bus, data bus and control bus are shown by
single bus called as system bus hence called
_as single bus structure.
Computer Architecture & Organization wv
a ——~2M pu
Chapter One Basic Structure of Computer
1.4.2 Multiple-Bus Hierarchies
* Now-a-days data transfer rates for video
controllers and network interfaces are growing
eT
; rapidly. —=
Figure 1.4 Single-Bus Structure «Therefore, to fulfil the need of high speed bus
g i i t computer systems use multiple bus
« In this, only two units can communicate ,,. M05 u
time ie. only one transfer can take place ae structure.
time. bi ; * Blements of Bus Design:
+ The bus control lines are used to jug, Bus Type
multiple requests for use of the bus. |. Dedicated
{ . The complexity of bus control logic depeng, © Separate data and address lines
on the translation time betw i . . ki
\| and CPU. between system bu; 2, multiplexed
| Advantages: iy ¢ Shared lines
1. Its cost is low. f © Address valid or data valid control line
| a Advantages:
| 2. Itis flexible to attach peripheral devices. : “
Disadvantages: «| Fewer lines — saves space, lower cost
1. As j Disadvantage: *
the more devices are attached to the bus, 5 a ‘ ‘i \
Propagation delay increases. lore complex contro!
2. As data transfer demand of all the devices . Potential reduction in performance “
Performances ,'© the bus capacity, the
ce
Because of these eo poem gets degraded. 1.5 Software
tems are Sparawbacks, most compute For running any application program, the
Ss, ed on multiple bus computer must already contain some system
‘software in its memory. System software is a
Collection of programs that are executed to
rform following functions-
|* Receiving and interpreting user commands.
puter Architecture & Organization Wy, se 1-15
Wie 4-14 Chapter One
« Entering and ¢
and storing them as
devices. f
Managing the ‘storage and retrieval of files in
secondary storage devices. /
Running standard application programs such
Runnint processors, spreadsheets, oF games,
with data supplied by theuser.
Controlling I/O units! to receive
information and produce output result.
‘Translating programs from j source form
prepared by the user into/ object form
consisting of machine instructions.
g application program
files in secondary storage
Linking and running user-written application
programs with existing standard library
routines, such as numerical computation
packages. : :
System software is thus responsible ‘for the
coordination of all. activities in a computing
system. The purpose of this ‘section is to
introduce some basic aspects of system software.
Explain “memory locations and’ addves
a 8,
ascribe tee methods to represent negation nine
16 for. 9 marks)
1.6 Memory Locations and Addre:
° The memory of
7 n computer tain:
instructions, number and character o perands.
The memory ie
cells, eat
sses
input ’
ihapterOne___ Basic Structure of Computer
(6.1 Byte Addressability
» A byte is always 8, bits, but the word length
typically ranggs from 16 to 64 bits. It is
necessary to assign continuous addresses to
individual bit locations in the memary.
+ Normally, memory assignment
instructions is done successively.
to the
The term byte-addressable memory is used for
this assignment. Byte locations have
addresses 0, 1, 2, ., . Thus, if the word length
of the machine is 32 bits, successive words
are located at addresses 0,4, 8, ... with each
word consisting of four bytes.
be tie as
(a) A Signed Integer
iter Architecture & Organization y
Chapter One Basic Structure of Computer
Example 1: The data word “OA OB OC OD” and
four memory locations with addresses a, a+ 1,4
‘Asc ASCII +2, a+ 3; then figure 1.6 indicates how the word
Sa, Bide det tater t!'be stored in memory.
(b) Four Characters Memory Address | Big-Endian | Little Endton |
Figure 1.5 Memor, Words » a 0A oD |
L atl on oc |
Eeplain Big Endian and Little Endian, with suitable a+2 0c OB ]
IC i fey 14 OB env |
Data Structure examples. 2 3 OD on 1
(6-16/17/18/19, W-18/19 for 7/6 Marky -_—**=___|__0D | __ UA
Lean Bi and. Little. Endia, Figure 1.6 Byte and word addressing
z indian
a Example 2:
Endianness’ is the convention used 1,
interpret the bytes making up a data w
when those bytes are stored in comput:
memory.
‘There are two ways that byte addresses can b:
assigned across words, as shown
Figure 1.6.
Each byte of data in memory has its own
address.
Big-endian system stores the most, significan:
byte of a word in the smallest address ané
east significant bytes is stored in the largest
endian big end is
aie little endian litle
e
reg Organtation
fee 8
ing
Data List- WORD 1020 H, 3040 H, 5060 H.
) Data List- DWORD 10203040 H, 50607080 H
iii) Data List- BYTE data 10, 20, 30, 40, 50, 60
For Data List (Word data)
| Memory Address | Big-Endian | LittleEndian |
a 10 60 |
atl 20 50 |
‘ at2 30 40 |
i a+3 40 30
: at4 50 20
: ats 60 10
,4) For Data List (Double Word data)
Memory Address | Big-Endian | LittleEndian
a 10 20
atl 20 70
Computer Architecture & Organization we? structure of
F chapter One Basie or COMP,
60 “apter One Basic Structure of Computer
30
at2
is 40 50 | aligned words begin at byte addresses 0, 8,
| S| 116, et
ata 50 0 | .
60 30 There is no fundamental reason why words
| ats 29 | cannot begin at an arbitrary byte address. In
at7 70 that case, words are said to have unaligned
a+8 80 10 addresses.
ii) For Data List (Byte data)
| ‘Memory Address | Big-Endian Little Endien, |'-6-4 Accessing Numbers, Characters and
nt
| 10 60 |
| - = 50 |" A umber usually occupies one word. It can
atl | “be accessed in the memory by specifying its
ate 30 40 | word address.
ats 40 30 | In many applications, it is necessary to handle
ata 50 20, character strings of variable length. The
ats 6 1o__| | beginning of the string is indicated by giving
“the address of the byte containing its first
i “character. Successive byte locations contain
1.6.3 Word Alignment \ _ successive characters of the string.
. i case of a 32-bit word length, natural wor’ There are two ways to indicate the length of
undaries occur at addresses 0, 4,8, ..., asthe string. A special control character with the
shown in Figure 1.5, We say that ‘the word | meaning "end of string’ can be used as the
locations have associated addresses., | _last character in the string, or a separate
In general, word ; ; “memory word location or processor register
! memory if they begin tate ae ated it indicating length ofthe string in bytes.
5 at is]
Fonullipe of the number of bytes if @ word
A " Teasons it t
manipulating binary-code dade will’ Memory Operations
of bytes in a word is a power of 3, |, Both instructions and data are stored in the
+ Hence, if the word length i 1. ...,| Memory. To execute an instruction, the
aligned words begin at brie gioj20..2 bytes) processor control circuits must coritain the
vv and for @ word length addresses 0, 2, 4, word (or words) containing the instruction to
of 64 (2 3 bytes ‘be transferred from the memory to the
Computer Architecture & Organization | processor.
Wien. 1-202omputer Architecture & Organization Wem 1-24 Chapter One
© Operands and results must also
transferred between the memory and \,
processor. Thus, two basic operatio,,
involving the memory are needed, name), Y
Load (or Read or Fetch) and Store (or Write)
© The Load operation transfers a copy of th,
contents of a specific memory location to ty,
processor without modifying the contents ,
the memory.
* For loading the content from memory, th,
processor sends the address of the desire,
location to’ the memory and requests {o,
reading the content at that location. Afte:
reading the-content memory sends the data to
the processor.
* The Store operation transfers an item of
information from the processor to a specific
memory location. The content at that memory
location is overwritten.
* For storing purpose, \the processor sends the
address of the desired location and'data to be
written to the memory. \ i
+ A single operation transfers’ one word or one
byte between the processor and the memory.
1.8 Instructions an
Sequencing
The tasks carried out n
consist of a sequence oe ee
performing any mathe:
Instructions
aE
rogram
of small steps such’ as
matical operation of two
a character to be dis; m
played on.
Computer Architecture & Org ee
ganization Wis 122
Basic Structure of Compy,,
Chapter One Basic Structure of Computer
ty A computer must have instructions capable/of
performing four types of operations: ,-
processor registers
Arithmetic and logic operations on data
) Program sequencing and control
«1/0 transfers.
‘These following are the two types of notations:
1, Register Transfer Notation
2. Assembly Language Notation.
1. Register Transfer Notation
We need to describe the transfer of information
from one location in the computer to another.
Possible locations that may be involved in such
transfers are memory locations, processor
registers, or registers in the YO subsystem.
For, example, names for the addresses of
memory locations may be LOC, PLACE, A, VAR2;
Processor register names may be RO, RS; and
1/O_ register names may _-be.., DATAIN,
OUTSTATUS, and so on.
The contents of a location are denoted by placing
square brackets around the name of the location.
‘Thus the expression
“Rv € [noc}
means that the contents of memory location LOC
are transferred into processor register R1.
As another example, consider the operation that
add8 ‘the contents of registers RI and R2, and
then places their sum into register RI This action
is indicated as,
Computer Architecture & Organization Wr 14
‘Data‘transfers between the memory and ‘the
|
alll ic Structur
Chapter One
RL € (R1] + (R2]
This type of notation is known @s Regint,,
‘Transfer Notation (RT),
2. Assembly Language Notation:
jon to repres
We need another type of notation I
machine instructions and programs. For this, \.
use an assembly language format.
For example, an instruction that causes 1h)
transfer described above, from memory location,
LOC to processor register RI, is specified by th:
statement. x
Move Loc, RL
The contents of LOC are unchanged by the
execution of this instruction, but the old:contents
of register RI are overwritten.
‘The second example of adding two numbers
contained in processor registers R1 and R2 and
placing their sum in-R3 can be specified by the
assembly language statement
Add RI, R2, R3
4.8.1 Basic Instructions Types
« The operation of adding two\numbers
fundamental lity i i .
statement copebility in any upputer, 7
C=a+B
4-26
Chapter One Basic Structure of Computer
« When the program containing this statement
is compiled, the three variables, A, B, and C,
are assigned to distinct locations in the
memory.
« Let us first assume that this action is to be
accomplished by a single machine Instruction.
Furthermore, assume that this instruction
contains the memory addresses of the three
' operands - A, B, and C. This three-address
instruction can be represented symbolically
as,
Add A, B, C
©! Operands A and B are called the source
operands, C is called the destination operand
‘and Add is the operation :0 be performed on
the operands. A general instruction of this
type has the format.
‘Operation Source 1, Source 2, Destination
+ If'k bits are needed to specify the memory
address of each operand, the encoded form of
the above instruction must contain 3k bits for
addressing purposes in addition to the bits
" needed to denote the Add operation.
For a modern processor with a 32-bit address
space, a 3-address instruction is too large to
_ fit in one word for a reasonable word length.
Thus, a format that allows multiple words to
be used for a single instruction would be
needed to represent an instruction of this
| type.
An alternative approach is to use a sequence
Ee simpler instructions to perform the same
oa
Computer Architecture & Organization we soe 1-25
| a — —— 0.
* During each pass through this loop, th
address of the next list entry is determinec|
and that entry is fetched and added to RO.
4
* Assume that the number of entries in the lis!|
n, is stored in memory location N, as shown.
© Register R1 is used as a counter to determin
the number of times the: loop is execute!
Hence, the contents of location N are loaded
into register Rl at the beginning of th},
program,
* Then, within the bod; t
instruction by onthe Steep
Computer Architecture & Organization
‘Chapter One Basic Structure of Computer
Decrement R1
reduces the contents of R1 by 1 cach time
through the loop. (A similar type of operation
is performed by an Increment instruction,
which adds 1 to its operand.)
« Execution of the loop is repeated as long as
the result of the decrement operation is
greater than zero.
sum
name
nue
unte
pa |
Figure 1.8 (b) Using a Loop to Add n Numbers
(A) Branch Instructions:
The branch instruction breaks the sequence of
"the program execution and transfers the
‘control to the other segment of the same
program or other sub program. Chapter One
«Therefore, Pr .
i ction al instruction at 4)
oe 3
titer follows the branch instruction;
tio!
Sucatial ‘address order.
This can be done
unconditional way-
! i m causes ,
tional branch instruction ee
A _eanation if a specified condition is met
ay t, the
‘ondition is not met, i
pecemented in the normal way, and the ney,
jnstruction in sequential address order jg
fetched and executed:
In the program in figure 1.8(b), the instruction
Branch > 0 LOOP
hes and execu
in conditional ,, ,
{branch if greater than 0) is a conditional
branch instruction that causes a branch to ~
location LOOP if the result of the immediately
preceding instruction, which is the 3
decremented value in register R1, is greater
than zero. This means that the loop is
repeated as long as there are entries in the list
that are yet to be added to RO.
At the end of the nth pass through the loop, ig
the Decrement instruction produces a value 0!
zero, and, hence, branching does not occu.
Instead, the Move instruction is fetched an‘
executed. It moves the final result from R0*
into memory location SUM,
The capability conditions and) |
just loop control,
Computer Architecture & Organization
ie
1-37Computer Architecture & Organization
japter O! Basle Structure of Computer
.s, called the br; ny, (B) Condition Code:
The supplement ALU circuit in the processor
with a status register status bit conditions
can be stored for further analysis.
‘These status bits are called as condition-
code bits or flag bits.
Following are the four status bits that are set
or cleared as a result of an arithmetic
operation performed in the ALU.
1. S (sign) - Set to 1 if the result is negative;
otherwise, cleared to 0
2. Z (zero) - Set to 1 if the result is 0;
otherwise, cleared to 0
V (overflow) - Set to 1 if arithmetic
overflow occurs; otherwise, cleared to 0
4. C (carry) -Set to 1 if a carry out results
from the operation; otherwise, cleared to 0.
The S and Z flags indicate whether the result
of an arithmetic or logic operation is negative
or zero and affected by instructions that
’ transfer data, such as Move, Load, or Store.
Overflow occurs when the result of en
arithmetic operation is outside the range of
"values that can be represented by the number
of bits available for the operands.
The C flag makes it possible to perform
arithmetic operations on operands that are
longer than the word length of the processor.
Such operations are used in multiple-
precision.
Wirz 1.33 asic Structure of Comp,
Chapter Formats Chapter One _ Basic Structure of Computer
1.9 Instruction
function of the processing ,,,.
interpret the instructigy
‘and carry out ,°
instructions. Pr fe i
a specified number af inet
Bach instruction is a string of binary digi,
All processors have input/output. instruction,
arithmetic: instructions, logic” instruction;,
branch instruction and instruction to manipulay,
characters. The number and type of instruction,
vaiy from processor to processor. The list o
spetific instruction supported by the CPU jx
called its instruction set.
A computer instruction
language consists of a fixed number of bits stored
in computer words. If an instruction has n-bits
then these bit positions are divided into two or
more. section called fields. One fieid in an
instruction has to be an Operation Code field
usually called OP-Code that specifies the
operation to be performed. The remaining part of
the instruction word may be divided into Mod
field and one or more parts each Seeing
addres ie
ss of a particular memory location.
L_ opcode Mode ‘Address
= 5
‘gure 19 Instruction format with Mode Field
Thus an_ instruction
consists of the following
i
truction codes.
in machine languagt
Parts, ee
wy. 134
in__machine ©
iii, A mode ficld that specifies the way the
operand or the effective address is
determined
tt
ee are designed to inter i), Operation Code: The operation code of an
instruction consists of a group of bits that
define certain arithmetic or some other
operations such as addition, subtraction,
multiplication, division _— shifting or
complementation. The number of bits required
for an op-code depends upon the total number
of operations to be performed by the
computer. If the op-code has k-bits then the
computer is capable of performing 2* distinct
operations. For example, if 16 distinct
“operations are to be performed by a computer
then op-code must have at least 4 bits (as 24 =
16). The control unit fetches an instruction
form the memory and decodes the operation
code part of it. This control unit then issues a
sequence of control signals that perform
certain appropriate operation on the data
stored in its internal registers. The operations
performed in the internal register of a
computer are called micro-operations. Thus
the operation stated in the op-code is a
| macro-operation and the operations that
“result in achieving the macro-operation are
called micro-operation. For every macro-
operation the control unit issues a sequence
of control signals to perform the micro-
operations.
Address: The op-code of an_ instruction
specifies the operation to be performed. Since
the operation is to be performed on data or on
‘a set of data, the instruction must also tell
Wee 135
i)
Computer Architecture & Organization =
S data is store The data ma, ‘chapter One Basic Structure of Computer
fored in a register or iN @ MEMOTY loca,;, “1.9.1 Type of Instructions
| " t ig ation
_ hich the aa 18 to \There are various instruction formats depending
‘performed is called an operand. Thus, "upon the architecture of the computer. The types
~ Fhstruction must specify ens en to ,of commonly used instructions are:
e
performed along with address | 4. Three address instruction
i o
.sses of the operand or register where ,," : 2
weet of an operation is to be ston’ 2+ Two address instruction
Moreover, as a computer program consist, 7 8. One address instruction
a set of instructions, the computer instructs, 4, Zero address instruction (Stack instruction)
must also tell ‘explicitly or implicitly 4,
peril aaa ‘where the next instruction i 1.9.3.1 Three-Address Instruction Format
itymode: The bits that define’ the mode fj In a computer memory the program is
; ; , eld of stored in the form of instructions and these
rakscaatnes tub oe specify a variety ofinstructions are stored sequentially. A register
| i a the operands form called Program Counter (PC) is used to compute
| a Bie ee ma ess. The various addressing the address of next instruction. When an
(oe Sven in next section. instruction is fetched from the memory, the
us a computer instruction i address of this location is copied into program
ce : contain: : “ eres
following information: 's the Counter. As this instruction is being executed by
&. Operation to the ALU, the program counter is incremented ty
b. Mode f be performed 1 which is the address of the next instruction.
eld. However, if the current instruction is a JUMP
instruction, the PC is updated with the memory
‘address to which the jump has taken place.
‘The general form of a three address instruction
Address of
“Op-Codes | Address 1 | Address 2 Rennercn
ie Figure 1.10 Three Address Instruction
|This three address instruction has the following
v
[DBfOpcration code
-_o Wie: 1.37 on Basic Structure of Com, or
Chapter 8
ii) Address of two operands called address ,°
adarest & location wi
\dress of the memory location where 4
. ort of the operation is to be stored j,
address of the destination.
| For example let us evaluate the’ arithme;,
statement given in assembly languay.
X= (A +B) x (C + D) Using three addre,,
instruction.
App, MUL denote addition and multiplication
operations.
app RL, A,B ORI, € MIA] + MIB]
ADD R2,C,D R2 «¢ MIC] + MID]
MUL X, BL, R2 Mix] © RI x R2
It is assumed that the computer has two
soeesor registers, Rl and R2. The symbol MA}
seas ihe oped at memory «address
oe Advantages of the three address, format is
evaluate ee? 2. the ‘short “programa ‘when
a arithmetic expressions,
i disadvantages is that the binary code
tives adage too many bits to specify
€,
4.9.1.2 Two-
‘Address Instruction Format
Two-address. j
common in eames, tutions are ‘the most
instruction, one ope COmPUtCTS. In this type of
register such a5 an aut’ Placed in a specified
“Scumulator and the address
Computer Architecture @ Organ:
lation Ye 8
Chapter One Basic Structure of Computer
of the next instruction is obtained from another
register called Program Counter (PC) or Sequence
Control Register (SCR). This implies that such as
instruction should have the following parts:
i, Operation code
fi Address of one of the operands, say
address 1
fii, Address of the storage location where the
result is to be stored. This address is
denoted by address 2.
The general form of a two address instruction is:
OP-Code | Address | Address 2
Figure 1.11 Two Address instruction
For example, the program to evaluate
X= (A + B) x (C + D) using two address
instruction is as follows:
Mov RL,A RL «© Mal
ADD R1,B RL «© Rl + MIB]
MoV R2,C R20 © MIC]
ADD R2,D RZ < = R2 + MID]
MUL R1,R2 RI «© RL x R2
Mov. X, Rl MIX] < RL
Add denotes addition and the MUL
instruction multiplication. The MOV instruction
loves’ or transfers the operands to and from
Hetty and processor registers. The first symbol
ited in the instruction is assumed to be both a
and the destination where the result of
he operation is transferred.
Computer Architecture & Organization
jee, 139 r Fe 1,3 one-Address eee Y
gg the name sugBests, this instr... chapterOne Basic Stru
aaress of one operand only, the other o, "nzequired in a program, increases a great deal,
ed ia lator. The results Of o,,{%: making the program quite lengthy.
= Teft in the accumulator (AC) itself, j,,.°"
{ are can be moved to main memory jy,” "
= ‘The address of next ing,” 1, 19:14 Zero-Address Instruction Format
‘ained from the program counter tion ‘The zero address instructions consists of
NOP-CODE only. The addresses of operand and
re of Computer
Shera form of single address instruc,
Nis: destination are implied. The general form of a
OP-Code Address 1 zero address instruction i:
OP-Code
» Figure 1.13 Zero Address Instruction
The PUSH and POP instructions, however, need
“an address field to specify the operant that
communicates with the stack.
Figure 1.12 One Address Instruction
For example, the program to ea)
X= (A438) x (C + D) using sin,
| instruction is as follows: nea
= (A+
ww A ace May
wD oB For example, the program to evaluate % =
aC © ac f F
+ MIB] B) x (C + D) using zero address instruction is
STORE
T MIT] © ac as follows: (TOS stands for top of stack)
uD cc a iG ste PUSH A m0S « A
ADD
D ac © ac + MID) PUSH OB tos < B
My, oe ae « dachnee ADD, Tos < (A+B)
x i
Store = Mix) © -ac or 2 c mos + c
(a All operations ard D tos «+ D
inthe die per and s meas et Ne Se
Storis a
adie the inte (empo memory location {| MOL mos < (C+D) x (A+B)
Instron’, M8truction “t© Tesult, Obviously, o™ x s
ction ‘On provid sti ' aS
Address the Ct and le more exhaust?) 7)
1e my @ greater capability | |/To evaluate arithmetic expressing in a
k computer, it is necessary to convert the
advantage. ye locati
ression into reverse polish notation (Post fix}.
ions, ter |
= i no doubt a gre
PH Architecture gn Umber of instructio™® |
& e
Organization 4 é puter Architecture & Organization Wi 141
a I Basic See SOM pu
Chapter One .
The name “zero-address” iS GIVE to th
computer beca'
field in the computational instructions.
1.9.1.5 RISC Instructions
instruction set of a typical Rig
aT d to the use of load a
referring to memory.
One Basic Structure of Computer
{Ype
use of the absence of an addr, without accessing memory. Finally the result of
the computations is stored in memory using a
store instruction.
What is addressing mode? Explain different
addressing mode with example.
( (S-15/16/17/19, W-15/16/18/19 for 7 marks)
Why do we need addressing mode? Explain Auto
increment and Auto decrement addressing mode by
giving example, (5-18 for 7 marks)
A program for a RISC-Type CPU consists ¢; ¥.10 Generating Memory Addresses
LOAD end STORE instruction that have onOnce we know the
memory and one register address,
number of addresses
andcontained in an instruction, we should know how
computational-type instructions that have thr.ememory location is specified by an address field.
addresses with all three specifying “processo:,
registers. For example, the program to evaluate;
X= (+B) x (C + D) using RISC instruction,
is as follows:
Rl,
aa A Rl <¢ MIA]
LOAD 2, B R2 < MIB] f
ma eS R3< MIC}
LOAD
ap eae Ra © MID] q
RL RL, R20 Rl & RL + RZ
we Pkg ge Re RA |
MUL RL
8703 BRS ORL ce Rix 83
aoe MIX] © RL
The load ii ‘.
to Chg ens tansfer the operands form :
ta in the registers ,
re & Organization i = 1-42
‘omputer Architecture & Organization
Want the ability to reference a large range of
address locations
‘Trade off between
o Addressing range and flexibility.
© Complexity of the address calculation.
The different ways that a processor can access
data are called the addressing modes:
_Addressing modes differ in the way the
| address information of operands is specified.
An address computed by processor when
executing a memory access or branch
instruction or when fetching the next
sequential instruction is known as Effective
Address (EA).
‘An effective address is made up of three
elements: base, index and displacement.
1-43 pSo
g modes are
Chapter One
Types of addressint
a) Immediate Mode:
« The operand
instruction itself.
00, Ri
« For example, LOAD £10 3
‘This instruction copies operand 1000 into y
register Ri-
. ‘The sign # in front of the value of an oper:
indicates that this value is an immedia)
operand.
© The use of immediate addressing leads to po-;
programming practice. This is because
change in the value of an operand requires
change in every instruction that uses t
immediate value of such operand.
‘{B) Direct (Absolute) Mode:
* The address of the location of the operand is
given explicitly as part of the instruction.
For example: LOAD 1000, Ri.
This instruction copies content of memory
location 1000 into the register Ri.
* As 1000 is not prefixed with an ial
aeoeee y speci
characters, indicating that it is the direct 0°
ldress of the source operand
Figure 1.14 shows an i i i
oddressing eae illustration of the direct
+ Direct (abso! ‘
more ncaa) addressing mode provides
mode. ‘
incl it i :
inclusion of ™ requires the explicit
instruction ‘© Perand address in. the
Computer Architecture @, Organization
is given explicitly in 4,
However qPared to the immediate
One asic Structure of Computer
Operation Address Memory
Cc
| Operand
Figure 1,14 Illustration of the Direct Addressing Made
(C) Indirect Addressing Mode:
* In this addressing mode, the instruction
contains the address of memory which refers
the address of the operand.
° Forexample, LOAD (1000), Fi-
* This instruction copies the content of memory
location pointed by location 1000 into register
Ri.
Memory
penton net Adres (1000) |
j—--—
b L___+10| 2m
108 |Zoeel
1
Memory indirect addressing
Register (R))
acter
Register (R) .
3300]
i Register iaduect addres
Figure 1.15 Illustration of the Indirect Addressing Mode
ae
4-04 Computer Architecture & Organization Wy. ns 145 a
addressing. : a rar)
In register indirect addressing a registe, r a
+ Im sreihold the address ofthe operand, ©” °
eee Lom,
i i an be made 4,
indirection © 7
ee register OF | a memory |
therelore we can identify two types of
er “t
yy, ShapterOne __Basic structure of Computer
level of complexity over register indirect
addressing.
in
ig
emory indirect addressing mey, : mamas} ot
: Soation is used to hold the address of i) [ton
operand, The two types are illustrate, il
Figure 1.15.
Figure 1.16 Illustration of the Indexed Addressing Mode.
Modes:
(D) Indexed Mode: Other Modes:
* The addressing modes presented above
represent the most commonly used modes in
th, most — processors. They provide the
Positiy . programmer with sufficient means to handle
most general programming tasks.
« In this addressing mode, the address fig,
references the main memory and
referenced register contains a
displacement from that address.
EA= memory address+(1) «However, a number of other addressing modes
‘The indexing is a technique that allow ave been used in a number of processors to
Programmer to point oF refer the data sion tl? execution of specific programming tasks.
in sequential memory locations one by onc. * {These additional addressing modes arc more
For example; Loap X(Rind), Ri a as compared to those presented
emis a ae loads register Ri with the Among these addressing modes the relative,
address ia et, Memory location whee’ auto-increment, and the auto-decrement
Rind and the dinner, contents of regis") modes represent the most well-known ones
isplacement x, | “These are explained below.
‘ting i8 indicated in the|
register in perenatding the name of the ind (B) Relative Mode:
ba i { ‘ ;
X to indicate the near 4nd using the sym 6 Inindexed addressing, an index register, Rind,
* Figure 1.16 ith Stant to be added. “Was used, Relative addressing is the same as
can be acer Met Ales indexed addressing. A® indexed addressing but program counter (PC)
Computer Archhecture eve edulres an addition® Work as the index Tepieet
1 ization tame 1°47
e & Organization Si 146 ‘Computer Architecture & Organi: Yi |
|
|
|
BasieStructure of Com,
Chapter One
For example:
: roan x(PC), RE
japter One Basic Structure of Computer
* After loading the operand into register Ri, the
content of register Rauto is incremented,
: contents of inti 4
inetmyction loads the cont Of (), pointing for example to the next item in a list
: Ti oan whose address is the sur, |, . :
m
my of items.
the contents of the program counter (PC) j,
i “Figure 1.18 illustrates the auto-increment
Ri. ‘:
the displacement X into register addressing mode.
+ Figure 1.17 illustrates the relative address, Onin | Ancraen ccm | | Neneny
mode.
Memory
=
Opation | ViloeX Boo se |
sale ee)
7c =
Coun FO) ‘penal A (@) Before Execution
pore = rier,
Rowe
Figure 1.17 Illustration of Relative Addressing Mode = sot Mecey
(F| Auto-Increment Mode: e iS
* The effective address of the operand is the’ oie ee
contents of the register specified in the -— e {3301
instruction, ee
: (b) After Execution
* After accessing the operand, the contents of
this regis
ister are increment: the Figure 1.18 riustration of the Auto-Tnerement Addressing Mode
next location, d to address :
As before, indirection is ini __, @) Auto-D t Mode:
tremor; indirection is indicated by including“) ae
‘crement register in parentheses.
For example:
| The: contents of the register specified in the
| instruction are decremented and then they are
zon used as an. effective address to access a
Lag (auto) +, Ri, memory location,
is instructi f
operand whee O82 register sa with th | For example
register Rauto, "'°*® i8 the content
Computer Architecture &, Organtzatioy
n
LOAD - (Rauto), Ri.
ihe
4g Omputer Architecture & Organization yyy ron 449 \ = —ny
Chapter One ts the content ¢.
n decremen ENt oF 5
This instruct then uses the new co,,,|'Shapter One Basic Structure of Computer
Rauto and ONte, f 2
register Raut 2 cess of the operand (j,,"toP of some end of these locations, generally
as the effectiv vo register Ri- known as the top of stack. Stack addressing is
to be loaded in similar to register indirect addressing is depicted
g modes presented aboy,, in figure 1.20. Stack pointer maintained in a
dressin, ede
‘The seven, ae Table given below. In each cq,register
summple shows the name of the address, FA=[R]
| mode, its definition, and a. generic. cxamy,
| itlustrating the use of such mode. oy
[om | Avvoecree REGIE! Rey on Imei Top ot Stack
Figure 1.20 Stack Addressing
j Fave Stack mode of a addressing is a form of implied
scm 3300 addressing. The machine instructions do not
| = TE ]x» include a memory reference. The top of the stack
| |3%0 _is the implied address.
(@) Before Execution SEE eusepteereton_eaig Woes
epee Fagen a Fon RR, Se
= al, ammecie aa 8 Tae Bee 4) 3 os
= Memory Sa wa Seat, Sea
Regen aect RA A, CA) ew le ey Ag ese re
aad Re
in Tehmasishseyn
| RE ee
| Se }9°° ayant Aa eB) Top alee
(©) After Execution — ae oa
i is 7 in
Figure 1,19 rilustration of the Auto-Decrement Addressing Most) oh Rage ae Rage
0 Stack Adresng —— Se
Stack is speci aia aa meine
‘Pecial block of contiguous memo" ere Ee
locations. A
rel Tegister, known as stat
end of these locatie tt the address at ont
Ceations, generally known as tH!
Computer Architecture & Organisti
ion
Figure 1.21 Summary of Addressing Modes
ter Architecture & Organization w= 151 dL
joutput Operation GhapterOne___basie Structure of Computer
1
Chapter One
1.11 Basic Input.
want to read a character from,
@ produce @ character)"
To perform this Input-Ouip,
isplay screen.
ih help of program-controlled 1/o.
of data transfer from the keyboary
meni to eet
user, which is not more than few characte,
per second. The rate of output transfers frog
the computer to the display is much higher .
compared to input.
It is determined by the rate at whic
characters can be transmitted over the inj
between the computer and the display device
‘Typically it is several thousand characters pe;
second.
© Consider we
keyboard an
«However, this is still much slower than thy
speed of a processor that can execute many»
millions of instructions per second. So, i
requires synchronization between. processo:
and 1/0 devices, e
coed brvoesaor cea the first charactet
for a signal from the displey
ah the character has been received, It the?
nds the second character, and so on.
Input i |
pales i jan from the keyboard in a similar) 4
indicating (poets Waits for a signs!
struck ne fa tine buacter key has beet
buffer register agi'®,CO4 is available in somé
* associated with the keyboard. |
Computer Architecture @, Organization
Wer.
Figure 1.22 Bus Connections for Processor,
Keyboard, and Display
Then the processor proceeds to read that
code. The keyboard and the display are
‘separate devices as shown in Figure 1.22. The
action of striking a key on the keyboard does
not automatically cause the corresponding
character to be displayed on the screen.
One block of instructions in the I/O program
transfers the character into the processor, and
another associated block of instructions
causes the character to be displayed.
A solution to this problem is as follows: O»Illustration with Example:
© ‘Consider the problem of moving a character
‘code from the keyboard to the processor.
Striking key-stores the _ corresponding
character code in an 8-bit buffer register
associated with the keyboard.
A call to register DATAIN, as shown in
‘igure 1.22 is made to tell the processor that
@-valid character is in DATAIN, a status
control flag, SIN is set to 1 and processor
Teads the contents of DATAIN.
7 fomputer Architecture & Organization fase. 83
1 =. — Rt,
Chapter One character is transferred to }) Ghapter One Basic Structure of Computer
When the js automatically set to 9 i READWAIT Branch to READWAIT if SIN = 0
rocessoh sracter is entered at the keybo,, Input from DATAIN to RL
second characte’ 't and the Process repeg,,”
SIN is again The Branch operation is usually
h ae
A similar process tS plier ree tera implemented by two machine instructions.
are transferred from the Pew rts {© ti, The first instruction tests the status flag and
buffer register, » and the second performs the branch.
display. A SOUT, are used for 1:
status control flag, ti eabin simple words, processor checks SIN: if
transfer. ( { SIN=1 then transfer data and again make
When SOUT=I, the display is ready to rece, SIN=O.
rogram control, ;;
a character. Under progr » tt. 4 similar sequence of operations is used for
yr monitors SOUT, and when SOUT j i ‘
ar the processor transfers a charact:, transferring output to the display.
code to DATAOUT. ‘An example is
‘The transfer of a character to DATAOUT clea, WRITEWAIT Branch to WRITEWAIT if SOUT = 0
SOUT to 0; when the display device is ready) output from R1 to DATAOUT
oe character, SOUTs"egnin se@e i the Branch operation’ ‘is’ normially
ae implemented by two machine instructions.
* The buffer registers DATAIN and DATAOU! The wait loop is executed repeatedly until the
and the status flags SIN and SOUT an status flag SOUT=1 by the display. ‘The
commonly known as a device interface. Th: Output operation transfers a character from
cireuitry for each device is connected to tht Rl to DATAOUT to be displayed, and it sets
Processor via a bus, as shown in Figure 1.22. SOUT=0.
* In order to perform data transfers, we nee! Initially SIN-O and SOUT=1. This initialization
machine instructions to check the state of th is’ normally performed by the device control
Status flags and to transfer data between tht circuits when the devices are placed under
Processor and the I/O device. computer control before program execution
* GBs instructions are similar in format | PeBins-
presses’ fr moving data between tht| Until now, we have assumed that the
processor ad the memory. For’example, ti| addresses issued by the processor to access
monito i ds always refer to
fag gSIN and transfer av the keyboard status) instructions and operands yy
aister RI : |
operations: °Y *e following sequence 0
Computer Ar =
Ichitecture & Organization 1-54 OmMputer Architecture & Organization Fe
eae 4
455 Basic Structure of Com,
Chapter One rangement tet er One Basic Structure of Computer
||» Many computers youn’ ‘shieh some myclsove #20c, Ro Initialize pointer
Memory-mapped HO eter ton register RO to point
address values are ust such as Dele to the address of the
registers of peripheral i ATHY first. location in
and DATAOUT. memory where the
jal instructions are needeq ’ characters are to be
‘ Ce cenieal of these registers; da ; stored.
can be transferred between these Tegiste,READ TestBit #3, INstATUS Wait for a character
and the processor using instructions such , to be entered
Move, Load, or Store. Branch = 0 READ in the keyboard
| © For examp! tents of the | buffer DATAIN.
| ce eer DATA can be pee icine (HoveByte DATAIN, (RO) Transfer the
i register Rl in the processor by thy character from
DATAIN into the
| instruction, memory (this clears
Move-Byte DATAIN, R1 SIN to 0).
* Similarly, the contents of register R1 can piCHO TestBit #3, UTSTATUS Wait for the display
transferred to DATAOUT by the instruction, to become _ ready.
Branch = 0 ECHO
Move-Byte ,
Byte: iy DatnOoE foveByte (RO), DATAOUT Move the character
* The status flags SIN and. SOUT ar just read to display
automatically cleared when, the buffer buffer register (this
registers DATAIN and DATAOUT: att clears SOUT to 0).
teferenced, respectively. The | Move-Bytez i
need, respectively. -Byttiompare #CR, (RO) + Check if _the
operation code signifies that the operand size character just read
Sg. lvte: to distinguish it from the operation is CR (carriage
i The return). If it is not
operat "chown below uses these tw CR, then
a keybourd 24 4 line of characters typed at}anch != 0 READ branch back
| and send them out to a displa! |” - & read another
| A a : 7 character. Also,
ose cnaaetere i : increment _the
| are stored in a data 2°27 i8, one by one, the) | pointer to store the,
Yoel “rea in the memory ant next character.
Computer, ‘Architecture & Organtzati ‘omputer Architecture & Organization Yr 1-57
lon os
we 156 |
|
chapter One ——— te
Cha a = ack ands queue? Eaplain the differen.
Geeween stack and
nue.
yori /7 marks,
7 . WUEVE with reference to basic|y
Epis STICK Md (6-17 for 6 marty |
Te penth dagram the PUSH DOWN. stack, |
‘pointer and frame pointer. le
Compare sac (5-18 for 7 mark) |
1.12 Stacks and Queue
* A computer program frequently needs
perform a particular subtask using the know,
Subroutine structure. In order to organize the
control and information linkage between th.
main program and the subroutine, a datz
structure called a stack is used.
© We will also study one closely related data
structure to stack which is called @ queue
Data operated on by a program can be
organized in a variety of ways. We have
already encountered data structure as lists.
1.12.1 Stack
* A stack is a list of data eleme: |
nts, usually
words or bytes, with some access restriction
that elements can be
end of the list only. added or removed at on¢
. ile ond is called the “TOS Le. top of the)
eon the other end is called the
« structure is sometimes referred
to as a pushdc ; :
trays in Peandown stuck. Imagine a pile 0!
Computer Architecture & Organization
Qi.
» We-use a stack that
"ia; we pick up new trays fro! _
tO
4-56 Omputer Architecture & Organization
Chapter One Basic Structure of Computer
the top of the pile as well as clean trays are
added to the top of the pile.
A, stack work on the last-in-first-out (LIFO)
principle ie, the last data item placed on the
stack is the first to be removed.
‘The push and pop are the primitive operations
of the stack. Push places the new item on the
stack and pop removes the top item from the
stack.
Data stored in the memory of a computer can
be organized as a stack such as successive
elements occupying successive memory
locations. Assume that the first element is
placed in location BOTTOM, and when new
elements are pushed onto the stack, they are
placed in successively lower address locations.
grows in opposite
direction of memory addresses.
Figure 1.23 shows a stack of word data items
in the memory of a computer. It contains
numerical values, with 43 at the bottom and -
28 at the top.
‘A processor register known as stack pointer
(SP) is used to keep track of the address of the
element of the stack that is at the top of the
_ stack.
Tt could be one of the general-purpose
registers or a register dedicated to this
function. If we assume a byte-addressable
memory with a 32-bit word length, the push
operation can be implemented as,
he Subtract #4, SP
Qi 1-59 chopterOnt —————T vont, (52)
ove weNaTEM, (SP)
GhupterOne _______ Basle structure of Computer
!
the Subtract instruction uber ||, increment the stack pointer by 4 90 that it
where para from Cestinay,, points to the new top element. Figure 1.24
sour Oeiained in SP and pIGCES the re, hows the effect of each of theye operations on
iB sp. These two instructions Move the y, the in Figure 1.23,
iP ae NEWITEM onto the top of eee i
from location NEWT ‘stack pointer j\'* Hf the processor has the Auto-increment and
stack, decrementing [0 ¥\ Auto-decrement addressing modes, then the
before the move. push operation can be performed by the single
instruction,
Move NEWITEM, - (3P)
and the pop operation can be performed by
Move (SP) + ITEM
Cree
‘upeiser » When a stack is used in a program, ‘it is
usually allocated a fixed amount of space in
the memory. In this case, we must stop
stack is full; this error is called as stack
overflow.
» Also, we should not attempt to pop an item
from an empty stck; this error is called es
stack underflow.
Suppose that a stack runs from location 2000
(BOTTOM) down no further than location
‘1500. The stack pointer is loaded initially with
ae ingerting an item onto the stack when the
NA |
4 the address value 2004,
Recall that SP is decremented by 4 before new
Figure 12: nae
: = SA Sack of Word inthe MemorY Gta ave stored on the sack: Hone, a ial
Pop operation can be implemented as value of 2004 means that the first item
Move (SP), rmmy
Add 4,
‘The two instructi
the stack into 1
Compute Architecture & org
pushed onto the stack will be at location
2000,
7 To prevent either pushing an item on a full
ions Move the top value {| stack or popping an item off an empty stack,
location ITEM and the? the single-instruction push and pop
nleation We slomputerArciecture & Organization yy, 62 pasic Structure of Com, SL
Chapter be replaced by the instr, ‘chapter One Basic Structure of Computer
s can 2: FEPUSIL Compare #1000,5? 0 see if the stack pointer
operations shown in Figure oe Dario Futtiawon — Ccatues teats mle
tor las than 1500, If it does, the
stacks fall Beasch to the rontive
» aes] Mow NEWTTEe(OP) Ones eae bccoy
- s-[ 7 | OY Oe ria titens teat
[oma foe Figure 1.26 (b): Routine For a Safe Push Operation
1.12.2 Queue
Another useful data structure same as that of
Cs _| = the stack is called a queue.
mex * In queue data are stored in and retrieved out
re [2 ea]
in a first-in-first-out (FIFO) basis.
» We assume that the queue grows in the
K operations onthe Stack direction of increasing addresses in the
Figure 124 Effect of Stack Operations on the Steck To new data are added at the back-end
(eatery to EVEL (2) Ate pop et TEM
* The Compare instruction and retrieved irom the front-end of the queue.
Compare src, dst ‘Stack Queue
performs the operation 5 It works on last-in- | It works on first-in-first-
[dst] - [sre] first-out {LIFO) | out (FIFO) principie.
2 Principle.
| and sets the condition code flags according t
resul: i] It has two ends; one |It also has two ends;
aS It does not change the value © is fixed i.e. bottom | but both ends move as
Sperand. and’ other end moves | data are added at the
SAPO? Gore HS hes, - a8 per the insertion | back and removed from
to see if the stack oc .
Baio BIPTEIOR malties uic pate tants J+ | ANA deletion of data | the front.
doe the sacks empl. Bem 10 | OCCUTS.
See DerrveRne be sero A ‘single pointer is|As both ends move in
TE Odervie, 7 heeded to point to the | queue so two pointers |
ma eeepdiieet= top of the stack ic.jare needed to keep
. IS track of the two ends of
Figure 125 (a): Routine for a Safe Pog Operation ges. o
the queue.
Computer Architecture & Organization ef omputer Architecture & Organization ey
Wy. continuously i
through the meng,"
computer in the fy,"
memory direction,"
eo
or deletion ue oy lie
whether the oe ael ct TEND the!
impty. | back pointer is, reyoy
stackiofulloremPtYs | 2 “beginning
‘ ‘and
process continues,
‘What & subroutine? Explain it By example, es
(5-16, W-16/17 for 7/5 marty)
1,13 Subroutines
‘Subroutine is the block of instructions whic,
is repeating again and again in the giver
program.
So, instead of writing that code again ant
again we call it as subroutine and directly cal
that subroutine whenever required.
This helps us to save space,
For exanple, a subroutine may evaluate t
sine function or sort a list of values int
increasing or
ind
When a ‘
say that tee emanches to a subroutine ¥
instruction that ee a
instruction
Peration is named a Call instr ag
Computer Arclecture& Organ ma
lzation Woe
wy Ghapter One
ke
« The
easing order. It is possible *
Danie Siructuca of Cormnuter
Aller a subroutine has been executed, the
calling program =munt resume cullon,
continuing linmediately after the Instruction
that called the subroutine,
‘The subroutine is said to return to. the
program that called it by exceuting a Return
instruction, Since the subroutine may be
called from different places in a calling
program, provision must be made for
returning to the appropriate location.
location where the calling program
resumes execution is the location pointed to
by the updated PC while the Call instruction
is being executed.
Hence, the contents of the PC must be saved
by the Call instruction to enable correct
return to the calling program.
The way in which a computer makes it
possible to call and return from subroutines is
referred to as its subroutine linkage method.
‘The siinplest subroutine linkage method is to
save the return address in a specific location,
which may be a register dedicated to this
~ function.
Such a register is called the Unk register.
When the subroutine completes its task, the
Return instruction returns to the calling
program by branching indirectly through the
link register.
+ The Call instruction is just a special branch
| instruction
| operations:
that performs the _ following
1-6 Computer Architecture & Organization Wy, scx, ¥67 T
Chapter One Steuctere ob Compury
© Store the contents of the PC in the jj, x
register
© Branch to the target address specified j,
the instruction
‘The Retum instruction is a special brang,
instruction that performs the operation:
© Branch to the address contained in the lin,
register.
ad BEE scene sun
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mo SB > om et insoustion
2 cetiomsen ra
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eee PREPS TT}
1000
4
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ere
—
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Figure 1.27 css Linkages ae a Link Register
1.14 Subroutine
Processor Stack
* A common
Subroutine nesting, mine
ting, is to hi
call another. In this case, the return
Computer Architecture a, Organizati as
ion
Nesting
and. the
\, Chapter One Basic Structure of Computer
of the second call is also stored in the link
register, destroying its previous contents.
« Hence, it is essential to save the contents of
the link register in some other location before
calling another subroutine. Otherwise, the
return address of the first subroutine will be
lost.
¢ Subroutine nesting can be carried out to any
depth. Eventually, the last subroutine called
completes its computations and returns to the
subroutine that called it.
e The return address needed for this first return
is the last one generated in the nested call
sequence. That is, return addresses are
generated and used in a last-in-first-out order.
° This suggests that the return addresses
associated with subroutine calls should be
| pushed onto a stack. A particular register is
_ designated as the stack pointer, SP, to be
used in this operation.
The stack pointer points to a stack called the
processor stack. The Call instruction pushes
the contents of the PC onto the processor
stack and loads the subroutine address into
the PC. The Return instruction pops the
return address from the processor stack into
"the PC.
|1.14.1 Parameter Passing
When calling a subroutine, a program
‘must Bravide to the subroutine the parameters,
Qian 1-67
[Computer architecture & Organization Chapter One ee.
cir addres; ?
that is, the operands = . C8 tg
used inthe computation d lc Structure of Computer
the subroutine retums 4, he sum computed by the subroutine is passed
Later, - th
ters, in this case, the ae of back to the calling program through register RO.
Thi eof i
computation. ‘This oe < sub ti ‘The first four instructions in fi 1.28
between a calling Lwacaent Uline constitute the relevant part of the calling
referred to as parameter passing. program. The first two instructions load n and
Parameter passing may be accomplis}. NUM! into RI and R2. The call inst
cereal ways. The parameters may be plac, ‘branches to the subroutine stating at LSSTADD.
registers or in memory locations, where they . ‘This instruction also pushed the return address,
be eccessed by the subroutine, Alternatively, ont the | processor stack, The subroutine
parameters may be placed on the processor «,, computes the sum and places it in RO. After the
ahs Processor stax. Sturn operation is performed by the subroutine,
oe a ea the sum is stored in memory location SUM by the
a calling program,
ae
on foe, ere 4.14.2 Parameter Passing by Value and by
oe RSI Serene Reference
.
