L02 - A - Transistors To Logic Gates
L02 - A - Transistors To Logic Gates
&
Microprocessor System
Dennis A. N. Gookyi
CONTENTS
2
BIG PICTURE: BUILDING A
PROCESSOR
❖ Single cycle processor
3
WHAT IS THIS?
❖ How does it work?
#include <stdio.h>
int main() {
printf("Hello world!\n");
return 0;
}
4
COMPILERS AND ASSEMBLERS
❖ From high level language to machine language
int x = 10;
C x = 2 * x + 15;
compiler r0 = 0
6
INSTRUCTION SET ARCHITECTURE
(ISA)
❖ Abstract interface between hardware and the lowest level
software
7
BASIC COMPUTER SYSTEM
❖ Three key components
□ Computation
□ Communication
□ Storage/memory
8
BASIC COMPUTER SYSTEM
❖ A processor executes instructions
□ Processor has some internal state in storage elements (registers)
9
OVERVIEW
❖ Covered in this course
Problem
Algorithm
Program/Language
Runtime System
(VM, OS, MM)
ISA (Architecture)
Microarchitecture
Logic
Devices
Electrons
10
WHERE DID IT BEGIN:
❖ Electrical Switch
□ On/Off
□ Binary
❖ Transistor
11
TRANSISTORS
❖ Computers are built from very large numbers of very small
(and relatively simple) structures: transistors
□ Intel 4004, in 1971, had 2300 MOS transistors
□ Intel’s Pentium IV microprocessor, 2000, was made up of more
than 42 Million MOS transistors
□ Apple’s M2 Max, offered for sale in 2022, is made up of more
than 67 Billion MOS transistors
12
MOS TRANSISTOR
❖ By combining
□ Conductors (Metal)
□ Insulators (Oxide)
□ Semiconductors
14
MOS TRANSISTOR
Wall Switch
Power Supply
0 Volt
3
Gate
Power Supply
Shorthand notation
❖ The p-type transistor works in exactly the opposite fashion
from the n-type transistor
Drain Drain
The circuit is closed The circuit is closed
when the gate is when the gate is
supplied with 3V Gate Gate
supplied with 0V
17 n-type p-type
Source Source
LOGIC GATES
❖ We know how a MOS transistor works
□ How do we build logic structures out of MOS transistors?
18
LOGIC GATES
❖ Modern computers use both n-type and p-type transistors,
i.e. Complementary MOS (CMOS) technology
nMOS + pMOS = CMOS
p-type
0V
19
LOGIC GATES
❖ Functionality of CMOS circuits
3V 3V
p-type transistor
pulls the output up
0V Out (Y) Y = 3V
0V 0V
20
LOGIC GATES
❖ Functionality of CMOS circuits
3V 3V
A= 3V Out (Y) Y = 0V
0V 0V
21
LOGIC GATES
❖ Functionality of CMOS circuits
❖ This is actually the CMOS NOT Gate
❖ Why do we call it NOT?
□ If A = 0V then Y = 3V
□ If A = 3V then Y = 0V
❖ Digital circuit: one possible interpretation
□ Interpret 0V as logical (binary) 0 value
□ Interpret 3V as logical (binary) 1 value
A P N Y
0 ON OFF 1 𝑌 = 𝐴ҧ
1 OFF ON 0
22
LOGIC GATES
❖ Functionality of CMOS circuits
❖ This is actually the CMOS NOT Gate
❖ Why do we call it NOT?
□ If A = 0V then Y = 3V
□ If A = 3V then Y = 0V
❖ Digital circuit: one possible interpretation NOT
□ Interpret 0V as logical (binary) 0 value
□ Interpret 3V as logical (binary) 1 value A Y 𝐴ҧ
𝑌=
Truth table: shows
Y = what
A is the logical
A Y output of the circuit for each possible input
A Y
We call this a NOT gate 0 1
or an inverter 1 0
23 (bubble indicates inversion)
LOGIC GATES
❖ More complex gates
3V
P1 P2
Out (Y)
In (A) N1
In (B) N2
0V
24
LOGIC GATES
❖ More complex gates (CMOS NAND gate)
3V
P1 P2 𝑌 = 𝐴 ∙ 𝐵 = 𝐴𝐵
Out (Y)
In (A) N1 A B P1 P2 N1 N2 Y
In (B) N2 0 0 ON ON OFF OFF 1
0 1 ON OFF OFF ON 1
0V
1 0 OFF ON ON OFF 1
1 1 OFF OFF ON ON 0
❖ P1 and P2 are in parallel; only one must be ON to pull up the
output to 3V
❖ N1 and N2 are connected in series; both must be ON to pull
down the output to 0V
25
LOGIC GATES
❖ More complex gates (CMOS NAND gate)
3V
P1 P2 𝑌 = 𝐴 NAND
∙ 𝐵 = 𝐴𝐵
Out (Y)
A
In (A) N1 Y
B
In (B) N2
Y = AB
0V
A B Y
0 0 1
A 0 1 1
Y 1 0 1
B 1 1 0
We call this a NAND gate
26 (bubble indicates inversion)
LOGIC GATES
❖ More complex gates (CMOS AND gate)
𝑌 = 𝐴 ∙ 𝐵 = 𝐴𝐵
A B Y A
0 0 0 Y
0 1 0 B
1 0 0
1 1 1
3V 3V
We make an AND gate using
one NAND gate and P1 P2 P3
one NOT gate Out (Y)
In (A) N1 N3
In (B) N2
0V
Food for thought: Can we not use fewer
27 transistors for the AND gate? 0V
LOGIC GATES
NOT
❖A CMOS NOT,
Y NAND, AND gates
A A
A Y Y Y
Y=A B B
A Y A B Y A B Y
0 1 0 0 1 0 0 0
1 0 0 1 1 0 1 0
1 0 1 1 0 0
1 1 0 1 1 1
3V
3V 3V 3V
P1 P2 P1 P2 P3
P Out (Y)
Out (Y)
In (A) Out (Y) In (A) N1 In (A) N1 N3
N
In (B) N2 In (B) N2
0V
28
0V 0V 0V
MOORE’S LAW
❖ 1965
❖ # of transistors integrated on a die doubles every 18-24
months (i.e., grows exponentially with time)
❖ Amazingly visionary
□ 2300 transistors, 1 MHz clock (Intel 4004) - 1971
□ 16 Million transistors (Ultra Sparc III)
□ 42 Million transistors, 2 GHz clock (Intel Xeon) – 2001
□ 55 Million transistors, 3 GHz, 130nm technology, 250mm2 die
(Intel Pentium 4) – 2004
□ 290+ Million transistors, 3 GHz (Intel Core 2 Duo) – 2007
□ 721 Million transistors, 2 GHz (Nehalem) - 2009
□ 1.4 Billion transistors, 3.4 GHz Intel Haswell (Quad core) – 2013
□ 7.2 Billion transistors, 3-3.9 GHz Intel Broadwell (22-core) – 2016
29
MOORE’S LAW
❖ # of transistors integrated on a die doubles every 18-24
months (i.e., grows exponentially with time)
30