1.

Write a note on evolution of Integrated era and transistor technologies

● Transistors are switches controlled by voltage or current applied to a control

terminal.
● Bipolar junction transistors were more reliable and power-efficient
than earlier models.
● Early integrated circuits mainly used bipolar transistors, requiring a small
base current to switch larger currents.
● However, power dissipation limited the number of integrated
transistors on a single die.
● In the 1960s, Metal Oxide Semiconductor Field Effect Transistors (MOSFETs)
were introduced.
● They drew minimal control current while idle and were available in
nMOS and pMOS forms.
● In 1963, Fairchild introduced the first logic gates using MOSFETs, giving rise
to CMOS (Complementary Metal Oxide Semiconductor) technology.
● CMOS circuits consumed much less power compared to bipolar
transistors.
● MOS ICs became popular due to their low cost, smaller footprint, and simpler
fabrication process.
● Early commercial processes mainly used pMOS transistors but faced
performance and reliability issues.
● Although nMOS process was less expensive, nMOS logic gates consumed
power while idle.
● As power consumption became a major concern, CMOS processes
replaced nMOS and bipolar processes.
● In 1965, Gordon Moore observed the doubling of transistor count every 18
months, known as Moore’s Law.
● It was based on scaling down transistor size and, to some extent,
building larger chips.
● The process of integration can be classified as small, medium, large, very
large. 1. Small-Scale Integration (SSI): The number of components is less
than 10 in every package. Logic Gates like inverters, AND gate, OR gate and
etc. are products of SSI. 2. Medium Scale Integration (MSI): MSI devices has
a complexity of 10 to 100 electronic components in a single package. Ex:
decoders, adders, counters, multiplexers, and demultiplexers. 3. Large Scale
Integration (LSI): Products of LSI contain between 100 and 10,000 electronic
components in a single package. Ex: memory modules, I/O controllers, and
4-bit microprocessor systems. 4. Very Large Scale Integration (VLSI):
Devices that are results of VLSI contain between 10,000 and 300,000
electronic components. Ex: 8bit, 16-bit, and 32-bit microprocessor systems
2. Bring out the differences between pMOSFET and nMOSFET.
3. With the help of neat diagrams, explain the structure of nMOSFET.
5. Explain the different regions of operations of n-MOSFET with relevant diagrams and
expressions.
6. Derive an expression for drain current for a n-MOSFET in its linear and saturation region
of characteristics
7. Explain the CMOS n-well fabrication with neat diagrams, the following processing
technologies.
Write a note on the following second order effects and explain how do they influence drain
characteristics with relevant expressions and graphs. i. Velocity Saturation & Mobility
degradation ii. Channel length modulation iii. Body effect iv. Subthreshold conduction v.
Tunneling & Junction Leakage vi. Temperature and Geometry Dependence
Explain the following fabrication processes involved in fabrication of CMOS ICs.

i. Wafer preparation ii. Photolithography iii. Oxidation iv. Contacts and Metallization v. Source
and drain formation vi. Isolation

. Wafer preparation: This process involves preparing the silicon wafer, which serves as the base
material for the CMOS IC. The wafer is cleaned and polished to remove any impurities and
defects. I

ii. Photolithography: In this process, a series of masks are used to define the patterns on the
wafer. A photosensitive material called photoresist is applied to the wafer, and then exposed to
UV light through a mask. The exposed areas of the photoresist become soluble and are removed,
leaving behind the desired pattern.
iii. Oxidation: Oxidation is the process of growing a thin layer of silicon dioxide (oxide) on the
wafer's surface. This layer acts as an insulator and protects the underlying silicon. It is typically
grown by exposing the wafer to oxygen or steam at high temperatures.

iv. Contacts and Metallization: Contacts are small openings made in the oxide layer to allow
electrical connections to be made to the underlying silicon. Metallization involves depositing a
layer of metal (usually aluminum or copper) on the wafer's surface to form interconnects
between different components of the IC.

v. Source and drain formation: The source and drain regions are formed by selectively doping the
silicon substrate with impurities. These regions are responsible for controlling the flow of current
in the CMOS transistors. The doping process is typically done using a technique called diffusion
or ion implantation.

vi. Isolation: Isolation is the process of electrically isolating different components on the IC to
prevent unwanted interactions. This is achieved by creating a barrier between components using
techniques such as shallow trench isolation (STI) or local oxidation of silicon (LOCOS).

10 Differentiate between i. Diffusion and Ion implantation ii. Positive Photoresist and negative
photoresist iii. Projection printing and contact printing iv. OPC and No OPC

i. Diffusion and Ion implantation: - Diffusion is a process in which impurities are introduced into a
semiconductor material by heating the material in the presence of the impurity source. The
impurities diffuse into the material and create regions with different electrical properties. - Ion
implantation, on the other hand, is a process in which high-energy ions are accelerated and then
implanted into the semiconductor material. This process allows for precise control over the
depth and concentration of the implanted ions.

ii. Positive Photoresist and negative photoresist: - Positive photoresist is a type of photoresist
that becomes soluble in a developer solution when exposed to light. When the resist is exposed
to light, the exposed areas become soluble and can be removed, leaving behind the desired
pattern. - Negative photoresist, on the other hand, is a type of photoresist that becomes insoluble
in a developer solution when exposed to light. When the resist is exposed to light, the exposed
areas become cross-linked and cannot be removed by the developer solution, leaving behind the
desired pattern.
iii. Projection printing and contact printing: - Projection printing is a lithography technique in
which a mask pattern is projected onto the wafer using lenses or mirrors. This allows for
high-resolution patterning over a large area. - Contact printing, on the other hand, is a lithography
technique in which the mask pattern is in direct contact with the wafer surface. This technique is
typically used for small-scale patterning and may result in lower resolution compared to
projection printing.

iv. OPC and No OPC: - OPC stands for Optical Proximity Correction, which is a technique used in
lithography to compensate for the optical and process effects that can distort the printed
pattern. OPC involves modifying the mask pattern to account for these effects and improve the
final pattern fidelity. - No OPC refers to the absence of Optical Proximity Correction. In this case,
the mask pattern is not modified to compensate for the optical and process effects, which may
result in reduced pattern fidelity and increased process variations.

11. What are Pass transistors and what is their limitation?

Pass transistors are transistors that are used to pass or transmit signals from one point to
another in a circuit. They can be either nMOS or pMOS transistors. The limitation of pass
transistors is that they have different characteristics when passing 1s and 0s. nMOS transistors
pass 0s well but 1s poorly, while pMOS transistors pass 1s well but 0s poorly. If the source
voltage of an nMOS transistor drops below a certain threshold, the transistor cuts off. Similarly, if
the source voltage of a pMOS transistor drops below a certain threshold, the transistor cuts off.
This means that nMOS transistors can only pull up to within a threshold voltage of the power
supply voltage, while pMOS transistors can only pull down to within a threshold voltage above
ground. This limitation can be overcome by using a transmission gate, which is a combination of
an nMOS and a pMOS transistor connected in parallel. The transmission gate can transmit both
strong 0s and strong 1s without any signal degradation. It can be used as a multiplexing element,
an analog switch, or a latch element.

12. Show how a Transmission gate overcomes the limitation of Pass transistors.
13. Consider an nMOS in a 180nm process with W/L =4/2λ (i.e., 0.36/0.18 µm. In this process,
the gate oxide thickness is 40 Å and mobility of electrons is 180 cm2/Vs at 70oC . The threshold
voltage is 0.4 V. Plot Ids vs Vds for Vgs= 0, 0.3, 0.6, 0.9, 1.2, 1,5 & 1.8V) Given: 180nm process,
µn = 180 cm2/Vs at 70oC , Vt= 0.4V, tox= 40 Å .
16. Explain the following terms with respects MOSFETs: i. Channel length modulation ii. Body
effect iii. Velocity saturation iv. Mobility degradation v. Subthreshold conduction vi. Tunneling vii.
Junction leakage

I. Channel Length Modulation:

● Definition: Channel length modulation refers to the phenomenon where the effective
channel length of a MOSFET is reduced as the drain-to-source voltage (Vds) is increased.
This occurs due to the formation of a depletion region near the drain, which reduces the
length of the channel. As a result, the current flowing through the transistor increases
with increasing Vds in the saturation region.

II. Body Effect:

● Definition: The body effect, also known as the back-gate effect, refers to the change in
threshold voltage (Vt) of a MOSFET due to the voltage applied to the body or substrate.
When a voltage is applied to the body, it creates an electric field that affects the channel
region, altering the threshold voltage. The body effect can impact the performance and
characteristics of the MOSFET.

III. Velocity Saturation:

● Definition: Velocity saturation occurs when the velocity of charge carriers (electrons or
holes) in the channel region of a MOSFET reaches a maximum value and does not
increase further with increasing electric field. This saturation of carrier velocity is due to
scattering mechanisms within the semiconductor material. Velocity saturation limits the
maximum achievable current in a MOSFET and affects its overall performance.

IV. Mobility Degradation:

● Definition: Mobility degradation refers to the reduction in carrier mobility (the ability of
charge carriers to move through a material) in the channel region of a MOSFET. This
degradation occurs when the charge carriers bounce against the surface of the channel
due to the vertical electric field created by the gate voltage. The reduced mobility leads to
a decrease in current flowing through the transistor and can impact its I-V
characteristics.

V. Subthreshold Conduction:

● Definition: Subthreshold conduction refers to the conduction of current in a MOSFET

when the gate voltage is below the threshold voltage (Vt). In this region, the transistor is
in the off-state, but there is still a small leakage current flowing through the channel due
 to the presence of minority carriers. Subthreshold conduction is important for low-power
applications and can affect the overall power consumption of the MOSFET.

VI. Tunneling:

● Definition: Tunneling is a quantum mechanical phenomenon where charge carriers can

pass through a potential barrier even if they do not have sufficient energy to overcome it
classically. In the context of MOSFETs, tunneling refers to the leakage of charge carriers
through the thin gate oxide layer. This can result in increased leakage current and affect
the performance and reliability of the transistor.

VII. Junction Leakage:

● Definition: Junction leakage refers to the leakage current that occurs at the pn junctions
in a MOSFET. This leakage current is caused by the reverse biasing of the pn junctions
and can increase with temperature. Junction leakage can contribute to the overall
leakage current of the transistor and affect its power consumption and performance.

17. Draw the circuit for the following using i. 2 input NAND gate ii. 2 input XOR gate iii. 2 input
XNOR gate
18. Explain general logic gate using pullup and pull-down networks being in series and parallel.
21. Implement 4:1 mux using pass transistors and transmission gates.
22. Write the transistor level circuit for the tristate inverter and explain the operation with the
help of the truth table.
23. Explain VLSI Design flow with the help of neat flow chart.