MP3924

Quad-Port, IEEE 802.3af/at

PSE Controller for Power over Ethernet

DESCRIPTION FEATURES
The MP3924 is a quad-port power source  IEEE802.3af/at Compliant
equipment (PSE) power controller for IEEE  Quad-Port and 4-Bit Configurable I2C
802.3af/at compliant power over Ethernet (PoE) Address
applications.  0.25Ω Current-Sense Resistor
The device has all the functions of IEEE  Automatic Mode and I2C Command Control
802.3af/at, including detection, single-event and Mode
two-event classification, current limiting, and  Automatic Input Over-Power Shutdown
disconnected load detection. All of the functions  Internal VCC Power Supply
can be configured to work in automatic  Three-Wire I2C Interface for Isolated
operation mode or software program mode via Applications
the I2C.  Two INT Pins for Interrupt Priority Selection
The MP3924 features a 9-bit analog-to-digital  Disconnected DC Load Detection
converter (ADC) to monitor the current and  Instantaneous Current/Voltage Readout
voltage, a special I2C interface for isolated  Thermal Protection
controller communication, adjustable current  Available in a QFN-32 (5mmx5mm)
limits, and configurable system functions. Package
These features provide flexibility for PoE
applications.
APPLICATIONS
 PSE Switches/Routers
The MP3924 is available in a QFN-32  PSE Midspan Power Injectors
(5mmx5mm) package.  Surveillance NVR and DVRs
All MPS parts are lead-free, halogen-free, and adhere to the RoHS
directive. For MPS green status, please visit the MPS website under
Quality Assurance. “MPS”, the MPS logo, and “Simple, Easy Solutions” are
trademarks of Monolithic Power Systems, Inc. or its subsidiaries.

TYPICAL APPLICATION

C2 D1 Output
Start-Up for Class 4 PD
VIN = 54V
VIN Port x4
C1 OUTn
VCC
C3
EN
GATEn Q1
AUTO CH1: VOUTx -
MID MP3924 SENSEn VVIN
PMAX
R1 20V/div.
SGNDx
A3
R2 SCL
A2
A1 SDAO
A0 SDAI
INT1
CLS5
DGND PGND INT2 Note: Only One Port
is Shown Here
100ms/div.

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 MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER

ORDERING INFORMATION
Part Number Package Top Marking MSL Rating
MP3924GU* QFN-32 (5mmx5mm) See Below 2
EVKT-MP3924 Evaluation kit -
* For Tape & Reel, add suffix -Z (e.g. MP3924GU-Z).

TOP MARKING

MPS: MPS prefix

YY: Year code
WW: Week code
MP3924: Part number
LLLLLLL: Lot number

EVALUATION KIT EVKT-MP3924

EVKT-MP3924 kit contents (items listed below can be ordered separately, and the GUI installation file and
supplemental documents can be downloaded from the MPS website):
# Part Number Item Quantity
1 EV3924-U-00A MP3924 evaluation board 1
Includes one USB to I2C communication interface device, one USB
2 EVKT-USBI2C-02 1
cable, and one ribbon cable
3 MP3924GU MP3924 controller IC 2
Order directly from MonolithicPower.com or our distributors.

Input Power Supply

Input

USB to PMBus Ribbon Cable

USB Cable
Communication
Interface
Evaluation Board
(EVKT-USBI2C-02)

Output

Load

Figure 1: EVKT-MP3924 Evaluation Kit Set-Up

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 MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER

PACKAGE REFERENCE
TOP VIEW
SENSE1 OUT2 GATE2 SENSE2 OUT3 GATE3 SENSE3 OUT4
32 31 30 29 28 27 26 25

GATE1 1 24 GATE4

OUT1 2 23 SENSE4

INT2 3 22 VIN

SGND1 4 21 PMAX

CLS5 5 20 VCC

AUTO 6 19 PGND

MID 7 18 SGND2

INT1 8 17 DGND

9 10 11 12 13 14 15 16

SCL SDAO SDAI EN A0 A1 A2 A3

QFN-32 (5mmx5mm)

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PIN FUNCTIONS
Pin # Name Description
1 GATE1 MOSFET gate driver for port 1. Float the GATE1 pin if not used.
Output voltage sense pin for port 1. Connect OUT1 to the output interface return for
2 OUT1 detecting, classifying, voltage sensing, and current limit foldback control. Float the OUT1
pin if not used.
High-priority interrupt request pin. INT2 pulls low when the selected high-priority
3 INT2 interrupt source register is set and the interrupt is enabled. INT2 is an open-drain output.
Connect INT2 to DGND if the interrupt function is not used.
Current sense negative input for port 1 and port 2. Connect SGND1 to the low-side
4 SGND1 terminal of the sense resistor. For an accurate current sense, use a Kelvin connection
when connecting SGND1 to the PCB. Connect SGND1 to DGND if not used.
Class 5 enable input. CLS5 is internally pulled down to DGND through a 50kΩ resistor.
Leave CLS5 disconnected to disable the classification for Class 5 devices (IEEE 802.3at-
5 CLS5 compliant mode). Connect CLS5 to VCC to enable the classification of Class 5 devices.
CLS5’s status is latched when the device starts up, or after a reset condition. If CLS5’s
status changes after start-up, there is no effect.
Automatic mode setting pin. AUTO is internally pulled up to VCC through a 50kΩ resistor
(an external 10kΩ resistor can be added). Float the AUTO pin to make automatic mode the
6 AUTO default. Connect the AUTO pin to DGND to make shutdown mode the default. AUTO’s
status is latched when the device starts up, or after a reset condition. If AUTO’s status
changes after start-up, there is no effect.
Midspan mode setting. MID is internally pulled up to VCC through a 50kΩ resistor (an
external 10kΩ resistor can be added). Float the MID pin for midspan mode, then wait 2.8s
7 MID to reinitiate detection. Connect the MID pin to DGND to disable midspan mode. MID’s
status is latched when the device starts up, or after a reset condition. If MID’s status
changes after start-up, there is no effect.
Interrupt request pin for all interrupt source events. INT1 pulls low when the interrupt
8 INT1 register is set and the interrupt function is enabled. INT1 is an open-drain output. Connect
INT1 to DGND if the interrupt function is not used.
I2C clock input pin. Connect SCL to VCC using an external pull-up resistor (typically
9 SCL
4.7kΩ). Connect SCL to VCC if the I2C interface is not used.
I2C serial data output pin. SDAO is an open-drain output. Connect SDAO to VCC using
10 SDAO an external pull-up resistor (typically 4.7kΩ). Connect SDAO to SDAI for non-isolated
applications. Connect SDAO to DGND if the I2C interface is not used.
I2C serial data input pin. Connect SDAI to VCC using an external pull-up resistor
11 SDAI (typically 4.7kΩ). Connect SDAI to SDAO for non-isolated applications. Connect SDAI to
DGND if the I2C interface is not used.
Enable input. EN turns all internal circuits and four ports (except the VCC regulator) on
12 EN
and off. To turn on the device automatically, externally connect EN to VCC.
MP3924 address setting pin. Connect A0 to VCC or DGND to set the lower 4-bit address
bits (address = 010 A3 A2 A1 A0). The address signal is latched when the device starts up
13 A0
or is reset. A0 is internally pulled up to VCC through a 50kΩ resistor (an external 10kΩ
resistor can also be added).
MP3924 address setting pin. Connect A1 to VCC or DGND to set the lower 4-bit address
bits (Address = 010 A3 A2 A1 A0). The address signal is latched when the device starts up
14 A1
or is reset A1 is internally pulled up to VCC through a 50kΩ resistor (an external 10kΩ
resistor can also be added).

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 MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER

PIN FUNCTIONS (continued)

Pin # Name Description
MP3924 address setting pin. Connect A2 to VCC or DGND to set the lower 4-bit address
bits (Address = 010 A3 A2 A1 A0). The address signal is latched when the device starts up
15 A2
or is reset. A2 is internally pulled up to VCC through a 50kΩ resistor (an external 10kΩ
resistor can be added).
MP3924 address setting pin. Connect A3 to VCC or DGND to set the lower 4-bit address
bits (Address = 010 A3 A2 A1 A0). The address signal is latched when the device starts up
16 A3
or is reset. A3 is internally pulled up to VCC through a 50kΩ resistor (an external 10kΩ
resistor can also be added).
17 DGND Ground of the internal digital and analog circuit.
Current sense negative input for port 3 and port 4. Connect SGND2 to the low-side
18 SGND2 terminal of the sense resistor. For an accurate current sense, use a Kelvin connection
when connecting SGND2 to the PCB. Connect SGND2 to DGND if not used.
19 PGND Ground of input power supply.
3.3V internal regulator output for analog and digital circuit supply. A minimum 1µF
20 VCC
ceramic capacitor must be placed between VCC and DGND.
Maximum loading power setting pin. Connect one resistor from the PMAX pin to DGND
to set the total power capability on all four output ports. The MP3924 limits the total power
21 PMAX
on all four ports below this set limit. The PMAX setting signal is latched when the device
starts up or is reset.
Power supply input for both VCC and output ports. Bypass VIN with at least one
22 VIN
0.1µF/100V ceramic capacitor, placed between VIN and PGND.
Current-sense pin from the high-side sense resistor terminal for port 4. It is
recommended to use a 0.25Ω sense resistor for all applications. For an accurate current
23 SENSE4
sense, use a Kelvin connection when connecting SENSE4 during PCB layout. Connect
SENSE4 to DGND if not used.
24 GATE4 MOSFET gate driver for port 4. Float the GATE4 pin if not used.
Output voltage sense pin for port 4. Connect OUT4 to the return of the output interface
25 OUT4 for detecting, classifying, voltage sensing, and current limit foldback control. Float the
OUT4 pin if not used.
Current-sense pin from the high-side sense resistor terminal for port 3. It is
recommended to use a 0.25Ω sense resistor for all applications. For an accurate current
26 SENSE3
sense, use a Kelvin connection when connecting SENSE3 during PCB layout. Connect
SENSE3 to DGND if not used.
27 GATE3 MOSFET gate driver for port 3. Float the GATE3 pin if not used.
Output voltage sense pin for port 3. Connect OUT3 to the return of the output interface
28 OUT3 for detecting, classifying, voltage sensing, and current limit foldback control. Float the
OUT3 pin if it is not used.
Current-sense pin from the high-side sense resistor terminal for port 2. It is
recommended to use a 0.25Ω sense resistor for all applications. For an accurate current
29 SENSE2
sense, use a Kelvin connection when connecting SENSE1 during PCB layout. Connect
SENSE1 to DGND if not used.
30 GATE2 MOSFET gate driver for port 2. Float the GATE2 pin if not used.
Output voltage sense pin for port 2. Connect OUT2 to the return of the output interface
31 OUT2 for detecting, classifying, voltage sensing, and current limit foldback control. Float the
OUT2 pin if it is not used.
Current-sense pin from the high-side sense resistor terminal for port 1. It is
recommended to use a 0.25Ω sense resistor for all applications. For an accurate current
32 SENSE1
sense, use a Kelvin connection when connecting SENSE1 during PCB layout. Connect
SENSE1 to DGND if not used.

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 MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER

ABSOLUTE MAXIMUM RATINGS (1) Thermal Resistance θJA θJC

(4)
VIN .............................................. -0.3V to +80V EV3924-U-00A ................. 32 ......... 2 .. °C/W
OUT1~4 ................................ -0.3V to VIN + 0.3V JESD51-7 (5) ......................... 36 ......... 8 .. °C/W
GATE1~4, SENSE1~4 ................. -0.3V to +22V
DGND, SGND1, SGND2............. -0.3V to +0.3V Notes:
1) Exceeding these ratings may damage the device.
All other pins ............................... -0.3V to +6.5V 2) The maximum allowable power dissipation is a function of the
INT1, INT2, SDAO maximum sink current……... maximum junction temperature, TJ (MAX), the junction-to-
………………………………………………..20mA ambient thermal resistance, θJA, and the ambient
temperature, TA. The maximum allowable continuous power
Continuous power dissipation (TA = 25°C) dissipation at any ambient temperature is calculated by P D
…………………………………………...3.9W (2) (4) (MAX) = (TJ (MAX) - TA) / θJA. Exceeding the maximum
Junction temperature ............................... 150°C allowable power dissipation can cause excessive die
temperature, and the regulator may go into thermal shutdown.
Lead temperature .................................... 260°C Internal thermal shutdown circuitry protects the device from
Storage temperature ................ -65°C to +150°C permanent damage.
3) The device is not guaranteed to function outside of its
Recommended Operating Conditions (3) operating conditions.
4) Measured on EV3924-U-00A, 2-layer, 88mmx106mm PCB.
Supply voltage (VIN) ......................... 44V to 57V 5) The value of θJA given in this table is only valid for comparison
INT1, INT2, SDAO maximum sink current……... with other packages and cannot be used for design purposes.
These values were calculated in accordance with JESD51-7,
…………………………………………………5mA and simulated on a specified JEDEC board. They do not
Operating junction temp (TJ). ... -40°C to +125°C represent the performance obtained in an actual application.

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ELECTRICAL CHARACTERISTICS
VIN = 54V, PGND, DGND, SGND1, and SGND2 are connected together, RSENSE = 0.25Ω,
TJ = -40°C to +125°C (6), typical value is tested at TJ = 25°C, unless otherwise noted.
Parameter Symbol Condition Min Typ Max Units
Power Supply
Input under-voltage lockout
VIN_UVLO VIN rising 28 29.5 31 V
(UVLO)
Input UVLO hysteresis VIN_UVLO_HYS 2.7 V
Input over-voltage lockout
VIN_OVP VIN rising 62 65 68 V
(OVLO)
Input OVLO hysteresis VIN_OVP_HYS 2.8 V
Input OVP lockout delay (7) 100 µs
Input power okay threshold VIN_OK VIN rising 38 40 42 V
Input power okay hysteresis VIN_OK_HYS 0.7 V
EN logic high voltage VHI 2.5 V
EN logic low voltage VLI 0.4 V
EN input current Pull EN to 0V, 3.3V 0 µA
tEN_ON EN pin high pulse duration 150
EN turn on/off delay for start-up or low-pulse µs
tEN_OFF duration for shutdown 120
Logic pin is floating, no
Supply current IIN connection for all output 2 4 mA
ports, AUTO = low
Shutdown current ISD EN = 0V 150 µA
Load = 0mA 3.3
VCC regulation VCC V
Load = 15mA 3.2
VCC UVLO VCC_UVLO VCC rising 2.3 2.5 2.7 V
VCC UVLO hysteresis VCC_UV_HYS 170 mV
VCC current limit VCC = DGND 17 mA
Power-on reset (POR) delay tPOR From VCC on to detection 0.5 ms
Detection
First detection voltage VDET1 Test the VIN to OUTx pins 3.6 4 V
Second detection voltage VDET2 Test the VIN to OUTx pins 7.2 8 V
Detection voltage slew rate VSLEW CDET = 0.1µF 0.02 V/µs
Detection current limit IDET_LIMIT Short VIN to OUTx 1 1.2 1.5 mA
Short-circuit detection
VSC First detection voltage 1 1.5 1.8 V
threshold
Open-circuit current
IOPEN 10 15 25 µA
threshold

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ELECTRICAL CHARACTERISTICS (continued)

VIN = 54V, PGND, DGND, SGND1, and SGND2 are connected together, RSENSE = 0.25Ω,
TJ = -40°C to +125°C (6), typical value is tested at TJ = 25°C, unless otherwise noted.
Parameter Symbol Condition Min Typ Max Units
Minimum valid detection
RGOODL 15 17 19 kΩ
resistance
Maximum valid detection
RGOODH 26.5 30 33 kΩ
resistance
Maximum valid capacitance CGOOD_MAX 1 9 µF
Detection time tDET Second detection phase 280 310 ms
Port reset by internal
Detection reset time tRESET discharge between VIN and 80 100 ms
OUTx before detection starts
Midspan mode detection
tMIDDLY Re-detection interval, MID = 1 2.8 sec
delay
Re-detection after one power
removal event due to error
Power removal detection condition (ICUT, ILIM,
tREMDLY 0.8 0.96 1.12 sec
delay INRUSH), fault timer = 60ms
MID = 0, automatic and semi-
automatic mode
Classification
Test VIN to OUTx pins during
Classification output voltage VCLS 16 18 20 V
classification, load < 60mA
Classification current limit ICLS_ILIM Short VIN to OUTx 70 mA
Class event time tCLE 8 15 22 ms
Mark event voltage VMARK Test VIN to OUTx pins 7.6 8.8 9.8 V
Mark event current limit IMARK_ILIM Short VIN to OUTx 6 10 14 mA
Mark event time tME 6.5 9 11 ms
Class 0 to 1 5.5 6.5 7.5 mA
Class 1 to 2 13.5 14.5 15.5 mA
Classification current Class 2 to 3 21.5 23 24.5 mA
ICLS
threshold Class 3 to 4 31.5 33 34.5 mA
Class 4 to over-current (OC)
45.5 48 50.5 mA
condition (or Class 5 (8))
Automatic mode from
detection ending to power 100 ms
Port start-up delay tPON port above 21V
Manual mode, from command
3 ms
to output port above 21V
From command off to gate <
Port shutdown delay 0.5 ms
1V
From one channel detection
to the next channel detection
Start-up sequence delay (9) 0.5 sec
if the first channel powers up
in automatic mode

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ELECTRICAL CHARACTERISTICS (continued)

VIN = 54V, PGND, DGND, SGND1, and SGND2 are connected together, RSENSE = 0.25Ω,
TJ = -40°C to +125°C (6), typical value is tested at TJ = 25°C, unless otherwise noted.
Parameter Symbol Condition Min Typ Max Units
Gate Driver
GATE source capability ISOURCE Port start-up, VGATE = GND -43 µA
Port shutdown, VGATE = 10V 60 µA
Port shutdown, VGATE < 1V 9 mA
GATE sink capability ISINK Trigger SCP,
VSENSE = 450mV, 100 mA
VGATE = 5V (7)
GATE clamp voltage VGS_MAX Float GATE pin 10 V
OUT Pin
Between VIN and OUTx, pull
OUTx high in idle state
OUT pin resistance ROUT 0.2 MΩ
(detection/classification off,
port shutdown)
OUTx = 0V, port start-up -270 µA
OUT pin bias current IOUT
OUTx = 54V, port shutdown 1 µA
Protection
Output power good (PG)
VPG OUTx pin voltage decrease 1.5 2 2.5 V
rising threshold
Output PG hysteresis VPG_HYS 400 mV
Low to high deglitch 3 ms
PG delay
High to low deglitch 10 µs
Class 0~3, ILIMx bit = 0 101 106.25 111.5 mV
Current limit threshold VILIM Class 4, ILIMx bit = 1 201 212.5 224 mV
Class 5, ILIMx bit = 1 251.75 265 278.25 mV
Class 0~3 (ICUTx = 000) 89.06 93.75 98.44 mV
Over-current (OC) detection
VCUT Class 4 (ICUTx = 100) 154.38 162.5 170.63 mV
threshold
Class 5 (ICUTx = 101) 218.5 230 241.5 mV
Current limit timer tILIM TILIM = 11 50 60 70 ms
OC timer tICUT TCUT = 10 50 60 70 ms
Start inrush current limit
tINRUSH TINRUSH = 10 50 60 70 ms
timer
OUTx pin voltage when ILIM
32 V
decreases, ILIMx bit = 0
Foldback initial voltage VFOLD_ST
OUTx pin voltage when ILIM
18 V
decreases, ILIMx bit = 1
OUTx pin voltage when ILIM
Foldback end voltage VFOLD_END 46 V
decreases to minimum value
Short VIN to OUTx, FBLIMT
40 mV
Foldback minimum current bit = 1, Class 4
VLIM_MIN
limit Short VIN to OUTx, FBLIMT
22 mV
bit = 0, Class 4

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ELECTRICAL CHARACTERISTICS (continued)

VIN = 54V, PGND, DGND, SGND1, and SGND2 are connected together, RSENSE = 0.25Ω,
TJ = -40°C to +125°C (6), typical value is tested at TJ = 25°C, unless otherwise noted.
Parameter Symbol Condition Min Typ Max Units
Short circuit fast-off ILIMx bit = 0 212 mV
VSCP
threshold ILIMx bit = 1 425 mV
Sense pin bias current -1 +1 µA
Thermal shutdown (7) 150 °C
Thermal shutdown
25 °C
hysteresis (7)
Total Load Power Limit
Load power limit on all four RMAX = 49.9kΩ 49.9 W
PMAX
ports RMAX = 120kΩ 120 W
Maximum load capability on
PMAX_LIMT Float the PMAX pin 204.8 W
all four ports
TPMAX bit = 10
Maximum load power 100% x PMAX < load < 150% x 60 ms
tMAX_DLY PMAX
protection delay
Load > 150% x PMAX 2 ms
DC Load Disconnection
DC disconnect hold Decrease output load until
VDCHOLD 1.25 1.875 2.5 mV
threshold output port power off
DC connect power time tDCON Load time to reset tDCOFF timer 37.5 43.75 50 ms
DC disconnect power Time from load < VDCHOLD to
tDCOFF 300 350 400 ms
remove time gate off
Analog-to-Digital Converter (ADC)
ADC resolution 9 bits
ADC results = 1 1111 1111
Max ADC current range 1.216 A
(2.4mA/count)
ADC results = 1 1111 1111
Max ADC voltage range 76.65 V
(0.15V/count)
ADC results = 0 0000 0000 to
ADC junction temperature
1 1111 1111 -40 +164.4 °C
range
(0.4°C/count)
Max ADC PMAX setting ADC results = 1 1111 1111
204.8 W
range (0.4W/count)
Current conversion I = 600mA 254 count
V = 44V 293 count
Voltage conversion
V = 57V 380 count
TJ = 25°C 163 count
Temperature conversion (7)
TJ = 125°C 413 count
RMAX = 49.9kΩ 125 count
PMAX setting conversion
RMAX = 120kΩ 300 count

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 MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER

ELECTRICAL CHARACTERISTICS (continued)

VIN = 54V, PGND, DGND, SGND1, and SGND2 are connected together, RSENSE = 0.25Ω,
TJ = -40°C to +125°C (6), typical value is tested at TJ = 25°C, unless otherwise noted.
Parameter Symbol Condition Min Typ Max Units
Logic Interface (SCL, SDAI, SDAO, INT1, INT2, MID, A0, A1, A2, A3, AUTO, CLS5)
Input logic low voltage VLI 0.4 V
Input logic high voltage VHI 2 V
Logic input current For SCL, SDAI -1 +1 µA
Open-drain output logic low Sink current = 3mA,
VLO 0.4 V
voltage SDAO, INT1, INT2
Open-drain output logic high
Open drain to 3.3V 1 µA
leakage
Internal pull-up/down A0, A1, A2, A3, AUTO, MID
RUP 50 kΩ
Resistance to VCC, CLS5 to DGND
Notes:
6) Guaranteed by over-temperature correlation.
7) Guaranteed by engineering sample characterization.
8) If CLS5 is enabled, the MP3924 treats the classification current range from the upper of class 4 to the classification current limit as class 5.
9) Guaranteed by detection time, classification time, and start-up delay time.

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TYPICAL CHARACTERISTICS
VIN = 54V, TA = 25°C, unless otherwise noted.

VIN Shutdown Current vs. Input VIN Supply Current vs. Input
Voltage Voltage
SHUTDOWN CURRENT (μA)

200 2.4

SUPPLY CURRENT (mA)

180
2.2
160
140 2
120 1.8
100
80 1.6
60 1.4
40
1.2
20
0 1
25 30 35 40 45 50 55 60 25 30 35 40 45 50 55 60
INPUT VOLTAGE (V) INPUT VOLTAGE (V)

VIN Shutdown Current vs. VIN Supply Current vs. Junction

Junction Temperature VIN SUPPLY CURRENT (mA) Temperature
SHUTDOWN CURRENT (μA)

250 2.4
2.2
200
2
150 1.8

100 1.6
1.4
50
1.2
0 1
-50 0 50 100 150 -50 0 50 100 150
JUNCTION TEMPERATURE (℃) JUNCTION TEMPERATURE (℃)

VIN UVLO vs. Junction VIN OVP vs. Junction

Temperature Temperature
32 67
VIN OVP THRESHOLD (V)

30 65
VIN UVLO (V)

28 63

26 61
Rising Rising
24 59
Falling Falling
22 57

20 55
-50 0 50 100 150 -50 0 50 100 150
JUNCTION TEMPERATURE (℃) JUNCTION TEMPERATURE (℃)

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TYPICAL CHARACTERISTICS (continued)

VIN = 54V, TA = 25°C, unless otherwise noted.

EN UVLO vs. Junction VCC UVLO vs. Junction

Temperature Temperature
2.5 2.6

2 2.5
EN UVLO (V)

VCC UVLO (V)

2.4
1.5 Rising
2.3
Falling
1 Rising
2.2
0.5 Falling
2.1

0 2
-50 0 50 100 150 -50 0 50 100 150
JUNCTION TEMPERATURE (℃) JUNCTION TEMPERATURE (℃)

VCC Voltage vs. Junction

Temperature Detection Voltage vs. Junction
VCC load = 15mA Temperature
3.4 10
DETECTION VOLTAGE (V)

3.3
VCC VOLTAGE (V)

8
3.2
3.1 6

3 4
2.9 Second Detection
2
2.8
First Detection
2.7 0
-50 0 50 100 150 -50 0 50 100 150
JUNCTION TEMPERATURE ( C) JUNCTION TEMPERATURE (℃)

Valid Detection Resistance vs. Class Voltage vs. Junction

Junction Temperature Temperature
35 20
VALID DETECTION RESISTANCE

30
CLASS VOLTAGE (V)

18
25
20 16
(kΩ)

15 Maximum Resistance 14
10
12
5 Minmum Resistance
0 10
-50 0 50 100 150 -50 0 50 100 150
JUNCTION TEMPERATURE (℃) JUNCTION TEMPERATURE (℃)

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 MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER

TYPICAL CHARACTERISTICS (continued)

VIN = 54V, TA = 25°C, unless otherwise noted.

Mark Voltage vs. Junction Class Current vs. Junction

Temperature Temperature
11 80

CLASS CURRENT (mA)

70 Class 4 to OCP Class 3 to 4
MARK VOLTAGE (V)

10 Class 2 to 3 Class 1 to 2
60 Class 0 to 1
9 50
8 40
30
7
20
6 10
5 0
-50 0 50 100 150 -50 0 50 100 150
JUNCTION TEMPERATURE (℃) JUNCTION TEMPERATURE (℃)

ICUT Limit vs. Junction ILIM Limit vs. Junction

Temperature Temperature
250 250

200 200
ICUT LIMIT (mV)

ILIM LIMIT (mV)

150 150
Class 4
100 100
Class 0 Class 4
50 50
Class 0
0 0
-50 0 50 100 150 -50 0 50 100 150
JUNCTION TEMPERATURE (℃) JUNCTION TEMPERATURE (℃)

DC Hold Threshold vs. Junction Inrush Current Limit vs.

Temperature Junction Temperature
INRUSH CURRENT LIMIT (mV)
DC HOLD THRESHOLD (mV)

2.1 115

2 110
1.9
105
1.8
100
1.7

1.6 95

1.5 90
-50 0 50 100 150 -50 0 50 100 150
JUNCTION TEMPERATURE (℃) JUNCTION TEMPERATURE (℃)

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 MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER

TYPICAL PERFORMANCE CHARACTERISTICS

VIN = 54V, set with a Class 4 PD load, TA = 25°C, unless otherwise noted.

No PD Connection Class 0~3 PD Connection

CH1: VOUTx CH1: VOUTx

- VVIN - VVIN
2V/div. 20V/div.

100ms/div. 100ms/div.

Start-Up through VIN

Class 4 PD Connection No PD connection

R1: VIN
CH1: VOUTx 50V/div.
- VVIN
20V/div. CH4: OUT4
50V/div.

CH3: OUT3
50V/div.
CH2: OUT2
50V/div.
CH1: OUT1
50V/div.
100ms/div. 400ms/div.

Start-Up through VIN Shutdown through VIN

Class 4 PD connection No PD connection

R1: VIN R1: VIN

50V/div. 50V/div.

CH4: OUT4 CH4: OUT4

50V/div. 50V/div.

CH3: OUT3 CH3: OUT3

50V/div. 50V/div.
CH2: OUT2 CH2: OUT2
50V/div. 50V/div.
CH1: OUT1 CH1: OUT1
50V/div. 50V/div.
400ms/div. 400ms/div.

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 MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

VIN = 54V, set with a Class 4 PD load, TA = 25°C, unless otherwise noted.

Shutdown through VIN Start-Up through EN

Class 4 PD connection No PD connection

R1: VIN R1: VEN

50V/div. 2V/div.

CH4: OUT4 CH4: OUT4

50V/div. 50V/div.

CH3: OUT3 CH3: OUT3

50V/div. 50V/div.
CH2: OUT2 CH2: OUT2
50V/div. 50V/div.
CH1: OUT1 CH1: OUT1
50V/div. 50V/div.
400ms/div. 400ms/div.

Start-Up through EN Shutdown through EN

Class 4 PD connection No PD connection

R1: VEN R1: VEN

2V/div. 2V/div.

CH4: OUT4 CH4: OUT4

50V/div. 50V/div.

CH3: OUT3 CH3: OUT3

50V/div. 50V/div.
CH2: OUT2 CH2: OUT2
50V/div. 50V/div.
CH1: OUT1 CH1: OUT1
50V/div. 50V/div.
400ms/div. 400ms/div.

Shutdown through EN
Class 4 PD connection PMAX Limit Triggered (10)

R1: VEN
2V/div.
R1: IIN
CH4: OUT4 500mA/div.
50V/div. CH4: OUT4
50V/div.
CH3: OUT3 CH3: OUT3
50V/div. 50V/div.
CH2: OUT2 CH2: OUT2
50V/div. 50V/div.
CH1: OUT1 CH1: OUT1
50V/div. 50V/div.
400ms/div. 400ms/div.

Note:
10) The maximum power (PMAX) is set to 50W. If the load’s power exceeds 50W, port 4 shuts down with default priority.

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 MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

VIN = 54V, set with a Class 4 PD load, TA = 25°C, unless otherwise noted.

ICUT Triggered ILIM Triggered

CH2: VIN CH2: VIN

20V/div. 20V/div.
CH1: OUT1 CH1: OUT1
20V/div. 20V/div.

CH4: IOUT1 CH4: IOUT1

500mA/div. 500mA/div.

20ms/div. 20ms/div.

Output SCP Triggered Inrush Current Limit Triggered

CH2: VIN CH2: VIN

20V/div. 20V/div.
CH1: OUT1
20V/div.
CH1: OUT1
20V/div.
CH4: IOUT1 CH4: IOUT1
1A/div. 1A/div.

100ms/div. 100ms/div.

Output Disconnection Triggered

CH2: VIN
20V/div.
CH1: OUT1
20V/div.

CH4: IOUT1
100mA/div.

200ms/div.

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 MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER

FUNCTIONAL BLOCK DIAGRAM

VCC
VIN
VIN
VIN
VCC LDO Output
4V, 8V
8.8V, 18V
Port x4
Detection
Classification
UVLO Enable OUT 1~4
EN OVP
Current
Sense
AUTO PSE Interface
Logic Control
MID
GATE Driver
CLS5
Control
GATE 1~4
PMAX
Register
Memory ADC VIN, Temp, PMAX SENSE 1~4

A3~A0 ICUT, ILIM, Inrush,

INT1 I2 C Watchdog Disconnect.
INT2 Control
SGND 1~2

SCL SDAI SDAO PGND DGND

Figure 2: Functional Block Diagram

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 MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER

OPERATION MP3924 outputs can restart with a new

detection cycle after OVP recovery.
The MP3924 is a quad-output power source
equipment (PSE) power controller for IEEE PD Detection
802.3af/at power over Ethernet (PoE) In normal idle operation, the MP3924 detects
applications. The device establishes a method the output port for a valid PD connection, which
of communication between the powered device typically has a 24.9kΩ resistance (see Figure 3).
(PD) and PSE with detection, classification, and
marked events. The MP3924 also provides OUTx
functions for current and voltage protections in Pin
VIN
automatic mode as well as I2C command 80ms

control mode. VIN (4V)

140ms
VIN (8V)
Power Supply 140ms

The MP3924 is designed for PoE applications Detection for 24.9kΩ

Discharge Classify
that require a 44V to 57V input. The MP3924
powers the output port from this input source, t
then generates an internal 3.3V for the digital
and analog circuits. The VCC regulator is Figure 3: PD Detection Process
enabled after VIN powers on. When VIN During this detection process, the MP3924
exceeds VIN_UVLO, the part is enabled after a generates a two-phase voltage (4V/8V) through
delay (tPOR). All functions can be enabled or the OUTx pin. Meanwhile, the external
disabled by both VCC and EN going above or MOSFET is off (see Figure 4).
below the under-voltage lockout (UVLO) value,
respectively. VIN

The MP3924 uses the PORT_ENABLE register

to disable functions related to all ports, as well 4V/8V
as functions related to individual ports. The
OUTx
PORT_ENABLE register does not include VIN,
Current
VCC, or EN UVLO. Sense

The device can be reset by any of the below

conditions: Figure 4: PD Detection Block Diagram

 VIN or VCC UVLO The OUTx pin sinking current capability is

limited to about 1.2mA. The current and voltage
 EN turning off
through the OUTx pin are measured. If the
 Writing 0 to the ENAL bit effective resistance with the two-point test is
After the MP3924 resets, all internal register are valid, this means that one PD device is
set to their default values. The following pins connected to the PSE port. The MP3924
are read and latched into the internal registers: integrates a filter to avoid 50Hz/60Hz power line
noise.
 AUTO
 MID After the detection cycle, the DETCx bit is set,
 CLS5 and an interrupt signal is generated to report
that detection has completed. The host can
 PMAX
read each port’s DET/CLS_RESULT register to
 A3~A0
obtain the detection results. After one detection
During normal operation, changes to these pins cycle, the MP3924 enters classification mode if
do not affect the registers. the PD connection is valid.
The MP3924 includes one VIN over-voltage If the output port is shorted or the detected
protection (OVP) threshold at about 65V. All capacitance is too high, the OUTx pin limits the
ports shut down if input OVP is triggered. The

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 MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER

sink current to about 1.2mA. Then the detection method to enable Class 5 is to use the enable
cycle ends. the CLS5_ENx bits on a port.
If the output port has an open circuit in the first During classification, the MP3924 outputs a
phase detection period, the MP3924 ends the 18V voltage on the OUTx pin (see Figure 5).
detection cycle. If the OUTx pin has a low The device then measures the current though
impedance to PGND, detection ends the OUTx pin to determine the classification
immediately. level. After classification is complete, the status
bits (CLSCx) and interrupt are set. The
For other invalid resistance signatures, the
classification result is stored in the DET/CLS
MP3924 ends detection after two-phase
Result register.
detection. After one invalid detection result, the
MP3924 stays in idle mode and re-enables VIN
detection within an 80ms port reset time. In
midspan mode, there is one delay time (about
2.8s) before the 80ms reset time. 18V

Midspan Mode OUTx

If a port is set to midspan mode, the device Current
Sense
waits about 2.8s before attempting to detect a
PD connection. This can avoid detection
collision. Midspan mode can be set or reset by Figure 5: Classification Block Diagram
the MID pin before the MP3924 starts up. Classification is based on the IEEE802.3at
Midspan mode can also be configured via the standards. If a classification result is in Class
MIDx bits via the I2C interface during normal 0~3, the MP3924 only performs one-time
operation. If the detection is valid, the device classification in accordance with IEEE 802.3af.
exits midspan mode. If Class 4 or Class 5 is detected in the first
PD Classification classification event, the MP3924 performs a
If the PD detection resistance is valid, the second classification event when the voltages
on VIN and OUTx are the same. 2-event
device enters classification mode to measure
classification can be enabled by 2EVNTENx
the power level of the connected PD. Different
classifications support 4W, 7W, 15.4W, or 30W (see Figure 6).
of power to the port. Based on the OUTx
IEEE802.3af/at standard, the MP3924 provides Pin
one additional class: Class 5 (see Figure 5). VIN

Class 5 classification has a 40W load capability, 2-Event for Class 4/5
which is valid when the CLS5_EN bit is enabled
and the classification current exceeds the Class
4 upper current threshold. If Class 5 is not Valid
Class 1~3
enabled, a classification current that exceeds Detection
50.5mA results in an over-current (OC) t
condition and a classification failure. If Class 5
is enabled, a classification current that exceeds Figure 6: 1-Event and 2-Event Classification
50.5mA results in a Class 5 classification level.
In this scenario, an OC condition refers to when Between the two classifications, the MP3924
the current has triggered the current limit performs two time mark events between VIN
threshold. OC conditions can occur with all and OUTx with an 8.8V mark voltage. The
classes. second classification result must be equal to the
first classification result, or the classification is
The CLS5 pin is internally pulled down to considered invalid.
DGND to disable Class 5 classification. Pull the
CLS5 pin high during a power-on reset (POR) After each 2-event classification, the output port
to enable Class 5 classification. Another generates an 8.8V voltage to perform the mark

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 MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER

event. During a classification mark event, the OUT

OUTx pins have sink and source current Pin
VIN
capability. This means that the output port
OUT3 OUT4
voltage can use a 0.1µF capacitor to follow the OUT1 OUT2 OUT1 OUT3

OUTx pin’s regulated voltage. 80ms

160ms
The classification circuit is disabled when the
classification result is valid and the port output t
is powered up.
Figure 8: PD Plug into Port 2
Start-Up
If the detection and classification results are If one of the ports has a PD load and the port
valid, the MP3924 ramps up the port’s output starts up, then the other ports repeat the
power. This power is delivered to the PD circuit. detection cycle, from channel one to channel
The PENx and PECx bits are then set to four. After one channel shuts down, it returns to
indicate the port status. When the power supply its place in the queue (see Figure 9).
(VIN) is between 44V and 57V, the MP3924 can OUT
operate from 31V and report over-voltage (OV) Pin
conditions at 65V. If the OUTx pin voltage drops VIN
below 2V, the PGx and PGCx bits are set to OUT3 OUT4 OUT1 OUT2 OUT3 OUT4 OUT1 OUT2

indicate the power good (PG) result. Wait for the

next cycle
Internal
If the detection is valid but the port does not Discharge
start up within 400ms in automatic or semi-
t
automatic mode, then the port initializes a new
detection cycle.
Figure 9: PD Plug Out from Port 2
Four-Channel Sequence
Over-Current Protection (OCP)
The MP3924 detects, classifies, and starts up
the ports one at a time. Port one is first, When the port is powered up, the MP3924
followed by the second, third, and fourth ports. controls the inrush current. As a result, the
output port voltage ramps up smoothly until the
If no PD is plugged in, the detection process connected PD capacitor charges up to the
goes one by one (see Figure 7). power source voltage. In this scenario, the
GATE pin voltage is controlled to limit the input
OUT
Pin
current (IIN) below 106.25mV / RSENSE.
VIN If the PD capacitor value is too large or the
OUT1 OUT2 OUT3 OUT4 OUT1 OUT2 output port is shorted, the inrush current lasts
for a set time (tINRUSH). After tINRUSH, the port
80ms output power turns off. tINRUSH can be configured
Detection ends
due to open port
via the TINRUSH bit.

t If 106.25mV / RSENSE exceeds ICUT during the

inrush period, the ICUT timer (tICUT) begins
counting. After tICUT, the output turns off. It is
Figure 7: No PD on an Output Port recommended for RSENSE to be 0.25Ω for all
The next port starts detecting within the 80ms applications. If one port shuts down due to the
discharge time after the previous port’s start-up inrush current, then the STFx bits are
detection cycle ends. Within this 80ms delay, set to indicate a start failure event.
the port can be discharged below 4V before After start-up, the PGx bits are set to high to
detection starts (see Figure 8). indicate the port’s output power status. If the
load current exceeds VCUT / RSENSE (VCUT is

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 MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER

controlled by the ICUTx bits), then a timer (tICUT) OUTx

Pin
VIN
is enabled to record the OC condition.
>0.96s

8The port turns once this timer finishes Detect.

t
counting. If the load current exceeds VCUT and Current
triggers VILIM / RSENSE, then the GATE pin ILIM
ICUT

regulates the load at the current limit level. An <60ms

t
additional timer (tILIM) is enabled to record the
60ms
current limit event. tILIM is counted even if the
MP3924 is in current foldback mode. tCUT
SR2 SR1 OCP

SR1 = 16 x SR2 t
VCUT detects the OC threshold, which is below
the VILIM threshold. tICUT starts counting when Figure 10: ICUT Over-Current Detection
the OC condition begins. If the load current
drops below VCUT, tICUT does not reset The GATE pin typically has a 43µA source
immediately. Instead, tICUT counts down at a current capability for current limit regulation,
rate that is 1/16 of how quickly is counts up. which means that the output voltage maximum
The tICUT timer records for a total of 60ms for start-up slew rate can be controlled by IGATE /
every 0.96s + 0.06s detection window. CGD (CGD is the capacitance between the
external MOSFET’s gate and drain). When the
If the port shuts down due to an OC condition, GATE pin’s voltage is pulled down to 1V by a
the port can be re-enabled only after tICUT weak discharge current, the voltage is latched
counts down to 0. This logic can detect a short to 0V with a strong pull-down current until the
or repeated OC condition. The logic also next start-up event. If the load current ramps up
protects the external MOSFET from quickly and triggers the VSCP fast-off voltage
overheating. tILIM and tNRUSH operate with the threshold, the MP3924 shuts down port power
same logic. quickly to protect the MOSFET. The load at the
The over-current protection (OCP) timer does current limit level is regulated until the timer
not reset even if the device shuts down or the (tILIM) counts down.
EN bit turns off. This means that the port cannot The MP3924 shuts down the corresponding
be re-enabled until the timer counts to 0 again. output port if an ICUT or ILIM event occurs, and
In manual mode, the host should read the Read the related fault bits are set. The following
and Clear register address continuously until registers are also affected:
the register is reset to 0. Then the port is re-
enabled. In automatic mode, the MP3924  The PGx and PENx bits in the
automatically restarts after the timer counts POWER_STATUS register are cleared.
down to 0.  The DET/CLS_RESULTx register and
When tICUT is completed, the related OUT port PORTx_VOLTAGE/CURRENT register are
shuts down (see Figure 10). At the same time, cleared.
the POWER_STATUS and
 The PGCx and PECx bits in the
OVER_LOAD_STATUS registers are set to
POWER_STATUS_CHANGE register are
indicate the power condition.
set.
The default VCUT is different for Classes 0~3
 The ICUTx and ILIMx bits are cleared.
than Class 4 and Class 5. VCUT can also be
configured. VILIM has three fixed values for Current Foldback
Classes 0~3, Class 4, and Class 5. During an overload or short-circuit condition,
the MP3924 limits the current through the
sense resistor by controlling the external
MOSFET. The MOSFET loses power due to the
rising drain voltage. To reduce power loss and
protect the MOSFET, reduce the current limit
when the drain voltage rises.

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 MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER

For Class 0~3 applications, the current limit 16 times the value set by the TPMAX register
drops when the OUTx pin’s voltage (VOUTx) (see Figure 12).
exceeds 32V. Meanwhile, the current limit Load Power

threshold linearly falls to 40mV when VOUTx Port 4

Re-Detect
rises to 46V. For Class 4 and Class 5 13W Load

60ms 0.96s 60ms

applications, the current limit drops when VOUTx Port 3

15W Load
10W Load
exceeds 18V. The current limit eventually falls Port 2
to 40mV when VOUTx rises to 46V. 25W Load

Port 1
Figure 11 shows current limit foldback. The Time

current limit is calculated using a 0.25Ω sense

Figure 12: PMAX Power Management at 50W
resistor.
DC Disconnect Detection
265mV
Current (1060mA) The MP3924 monitors the load current after the
Class 5 port is powered up. If the port load current
212.5mV Class 4
(850mA) drops below 7.5mA (assuming RSENSE = 0.25Ω)
for longer than 350ms, then the MP3924
106.25mV Class 0~3
(425mA)
About considers the load disconnected and turns off
40mV (160mA)
the port’s output power. The MP3924 considers
V_OUT PIN
the load connected to the port if the current
18V 32V 46V exceeds 7.5mA (assuming RSENSE = 0.25Ω), or
Figure 11: Current Limit Foldback exceeds the current load from the PSE output,
for longer than 43.75ms in every 393.75ms
Automatic Maximum Power Protection window.
The MP3924 has the classification ability to
allocate power to each port based on The DC disconnect detection function is
IEEE802.3at. The MP3924 can monitor the total enabled by default after the device starts up in
loading power and automatically shut down the automatic mode. If the AUTO pin is low during
lower priority port if the total load power start-up or after the IC resets, the DC
exceeds the expected power rating. Set the disconnect detection function is disabled by
PMAXEN bit high to enable this function. Then default. Each port can enable/disable the DC
the MP3924 compares the total load power with disconnect detection function via the DISENx
the power reference set by the PMAX pin. bits. After a shut down due to DC disconnect
detection, one DCDISx bit is set to indicate the
If the total load exceeds the configured power status. The following registers are also affected:
level for longer than the overload time (tPMAX),
the MP3924 shuts down the lowest priority port  The PGx and PENx bits in the
among the powered ports. If the total load POWER_STATUS register are cleared.
power exceeds 50% of the configured limit, the  The DET/CLS_RESULTx register and
lowest priority port shuts down after a 2ms PORTx_VOLTAGE/CURRENT register are
delay. Port priority is arranged via the PRTYx cleared.
bits. By default, port 1 has the highest priority
and port 4 has the lowest priority.  The PGCx and PECx bits in the
POWER_STATUS_CHANGE register are
If the AUTO pin is high after start-up or after the set.
device resets, then the PMAXEN bit is set to 1
by default. If the AUTO pin is low after start-up  the ICUTx and ILIMx bits are cleared.
or after the device resets, then the PMAXEN bit Interrupt Control
is set to 0 by default. Maximum power
The MP3924 features two interrupt pins that
protection is enabled when the PMAXEN bit is
can be used for different priority interrupt
high. If the total load power is below the
sources. The priority can be configured via the
configured PMAX level, the maximum power on
Interrupt Priority register. INT2 responds to the
each port does not exceed the classified current
limit. The PMAX cooling time before recovery is

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 MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER

selected interrupt sources, while INT1 responds After the host controller receives the interrupt
to all interrupt sources. By default, INT2 signal, it can check the status register to
responds to VIN power failures and OC events. diagnose the issues. The host can read the
read and clear address to reset the interrupt
The MP3924 pulls the INT1 and INT2 pins low if
event register, as well as the INT1 and INT2
a fault condition occurs in the Interrupt Priority
pins. If the host controller reads the status
register while the interrupt is not masked. The
register through the read-only address, neither
interrupt signal is asserted to notify the host
the interrupt event register nor the INT1 and
controller that certain fault conditions have been
INT2 pins are reset. For more details, see the
detected. If the interrupt source is masked, the
Register Map section on page 29.
interrupt event bits are set, but the INT1 and
INT2 pins do not respond to the fault event. The INT1 and INT2 pins can be reset by the
CLRAINT bit or the interrupt disable bit (INTEN)
INT1 and INT2 go low if a fault occurs. If a
(see Figure 14).
second fault occurs before the host resets the
interrupt signal, the MP3924 keeps the INT1 The INTx pin should be triggered at the edge of
and INT2 pins low until the host controller the fault event. If two fault events occur
resets the fault condition (see Figure 13). simultaneously, then the INTx pin does not
reset until all fault events are cleared.
First Fault

Second Fault

INTn

Figure 13: Interrupt Sequence

Read R/C Address or set
Each bit can be masked
CLRAINT to 1 to reset it

VIN UVLO VINUV Bit

VIN OVP VINOV Bit

VCC UVLO VCCUV Bit OR

VINF Bit
OTP OTP Bit

Portx FET Fail FETFx Bits

Set CLRPIN to 1 to
Total Power Overload OVPMAX Bit reset it. Does not affect
the register
Portx Start-Up Failure STFx Bits STF Bit

Portx Trigger ICUT or ILIM OCUTx or OLIMx OCP Bit OR

INTEN bit INTx Pin
Portx Classification Done CLSCx Bits CLSC Bit

Portx Detection Done DETCx Bits DETC Bit

Portx DC Disconnect DCDISx Bits DCDIS Bit

Portx PG Change PGCx Bits PGC Bit

Portx Start-Up Change PECx Bits PEC Bit

Figure 14: Interrupt Logic Diagram

Legacy Detection lists the detection parameters. Legacy detection
The DET/CLS_RESULTx registers return to returns the results of the
010 (if CDET > 5µF) if the cable is connected to a LEGACY_DETECT_RESULTx registers.
legacy PD with a high input capacitor. The The MP3924 starts legacy detection after the
LEGENx bits enable legacy detection mode. By PD input voltage is discharged below 2.4V. If
default, the LEGENx bits are set to 00 to
disable legacy detection. Table 1 on page 25

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 MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER

the PD input voltage is high, a 250ms discharge the standard resistance detection result is not
timer works with a 100kΩ load between the valid and legacy detection is valid, the MP3924
OUTx pin and VIN. If the PD input exceeds does not start the classification process, even if
2.4V, a secondary 500ms discharge timer the CLSENx bit is set. In this scenario, a
begins. If the PD input voltage does not fall software command is required to trigger the
below 2.4V after the two discharge times, then classification process.
the MP3924 is set to 0010 in the
If the following conditions are met, then PON
LEGACY_DETECT_RESULTx registers.
automatically powers the port (even if the
After legacy detection starts, a fixed current is classification result does not match, or there is
charged to the PD input. The voltage difference an OC condition):
between two points is used to calculate the
 PON is enabled by the software after the
effective capacitance.
legacy detection is determined to be valid.
If the capacitance is too great and the
measured voltage difference is below 0.5V,  The MP3924 is in automatic or semi-
then the MP3924 reports 0110. If the automatic mode.
capacitance is too low and the measured If the LEGENx bit is enabled in automatic or
voltage reaches 18.5V, then the MP3924 semi-automatic mode, the legacy detection
reports 0100 or 0101. All of these results are result repeats and refreshes the
invalid in legacy detection. LEGACY_DETECT_RESULTx registers. This
Table 1: Legacy Detection Measurements process repeats until the LEGENx bit is
disabled. In manual mode, legacy detection
Parameter Value Units occurs once, then the LEGENx bits resets
Minimum measurable automatically. It is recommended to use manual
5 µF
capacitance mode.
Maximum measurable
capacitance
100 µF Operation Modes
Capacitance test charge The MP3924 provides four operation modes to
500 µA flexibly control PoE communication and start-up:
current
automatic mode, semi-automatic mode, manual
Nominal measurement time 150 ms
mode, and shutdown mode. The AUTO pin and
Maximum voltage before the MODEx bits set the different modes, which
2.4 V
start measurement
are described below in greater detail.
Duration of first port
250 ms Automatic Mode
discharge period
Duration of second port In automatic mode, the MP3924 automatically
500 ms
discharge period controls and responds to all detection,
Maximum voltage during classification, and start-up functions. The
18.5 V MP3924 handles these processes for each port
measurement
independently and without external I2C control.
If legacy detection is enabled and a legacy Float the AUTO pin to force the MP3924 to
device is detected in automatic mode, then the work in automatic mode.
detection status is reported in the
LEGACY_DETECT_RESULTx registers. In automatic mode, the MODEx bits are set to
However, the device does not start up 11 when device turns on. The AUTO pin status
immediately, as it requires a host command is only read once when the device turns on or
through the I2C. the MP3924 is reset. If a master is connected to
the MP3924 via the I2C, then the master can
If LEGENx is set to 01 or 10 in automatic or change the MODEx bits to change the
semi-automatic mode, there is initially one operation mode. If there is no valid PD on the
standard detecting cycle. If the standard port in automatic mode, then the MP3924
resistance detection result is valid, then the
MP3924 does not continue legacy detection
and the classification process begins instead. If

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 MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER

repeats the detection cycle until a valid PD is simultaneously, then the MP3924 executes a
connected. detection cycle first. If the DETENx and
CLSENx bits are set after the port starts up, the
If the MP3924 runs in automatic mode after
MPM3924 ignores the DETENx and CLSENx
start-up or reset, the DETENx and CLSENx bits
commands. The RDETx and RCLSx bits follow
are set high based on the AUTO pin. If a port is
the same logic.
set to automatic mode via the I2C, the DETENx
and CLSENx bits do not change. If a PONx command is received while the
device recovers from a protection, then the
Semi-Automatic Mode
MP3924 does not turn on and the failure is
In semi-automatic mode, the MP3924 reported to the STFx bit.
automatically detects and classifies the
connected PD. However, the port does not start Shutdown Mode
up until an I2C command is issued. Set the In shutdown mode, all detection, classification,
MODEx bits to 10 to force the MP3924 to and port power output functions are off. To
operate in semi-automatic mode. force the MP3924 to operate in shutdown mode,
pull the AUTO pin to DGND before the device
When the port is set to semi-automatic mode,
starts up or resets. Set the MODEx bits to 00 to
the DETENx and CLSENx bits to not change. If
set a port to shutdown mode.
the DETENx and CLSENx bits are high in semi-
automatic mode, the port repeats the detection Once a port is in shutdown mode, the power is
(and classification if the PD detection result is turned off and the corresponding port
valid) continuously. However, the port does not event/status registers are cleared, except for
start up until an I2C command is issued. If the the PECx and PGCx bits. The I2C interface still
detection and classification are valid, the port operates in shutdown mode, but the ports do
power can be turned on by a PONx bit. If the not respond to any detection, classification, or
port is powered off in semiautomatic mode, the port start-up commands.
DETENx and CLSENx bits are reset to 0.
In certain AUTO pin configurations, the MODE
If the detection is valid and the port does not bits are set to 00 or 11 after start-up (or after a
turn on within 400ms in automatic or semi- reset). After start-up, all ports can switch
automatic mode, then the port initiates a new between the four modes. The registers and port
detection sequence. If the final detection and states are not changed by these bits unless
classification sequences are determined to be shutdown mode is selected.
invalid before the start-up command is received,
9-Bit ADC
the device fails to turn on. At the same time, the
STFx bit is set and the MP3924 resets the The MP3924 integrates a 9-bit analog-to-digital
command. If the detection and classification converter (ADC) to continuously measure the
sequences are valid but a start-up command is input voltage, output voltage, load current, and
not issued after 400ms, then the STFx bit is set. junction temperature. The ADC also measures
PMAX once following start-up, or if the device is
Manual Mode reset. When any ADC information is required,
In manual mode, all functions are controlled via the host controller can read the corresponding
the I2C interface. Manual mode is data registers. ADC conversion only works
recommended for system diagnostics. Set the when the port is enabled and if there is no data
MODEx bits to 01 to force the ports to operate update for the corresponding port when the port
in manual mode. is shut down. The register cannot be updated
while it is read, even if ADC conversion is
In manual mode, the DETENx and CLSENx bits
complete for that segment of data.
are set to 0. Set these bits to 1 to enable one-
time detection or classification. These bits reset I2C Interface
to 0 automatically. The MP3924 features an I2C interface. The 7-bit
The PONx bits power the port in manual mode. device address is defined as 010 xxxx, where
The port turns on any time the PONx bit is set.
If the DETENx, CLSENx, and PONx bits are set
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 MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER

the lower 4 bits are set by A3~A0 pins. When the address set by host 1 can respond to host 2,
the master sends an 8-bit address value, the 7- if host 1 does not have data to read/write in that
bit I2C address should be followed by a 0 or 1 to address. If different registers must be read or
indicate a write or read operation, respectively. written, one address information is required to
The MP3924 works as a slave and supports set the correct register address.
standard mode (100kbps) and fast mode
I2C Data Validity
(400kbps) communication.
One clock pulse is generated for each
The I2C is a two-wire, bidirectional serial transferred data bit. The data on the SDA line
interface consisting of a data line (SDA) and a must be stable during the high period of the
clock line (SCL). The lines are externally pulled clock. The high or low state of the data line can
to a bus voltage when they are idle. When only change when the clock signal on the SCL
connecting to the line, a master device line is low (see Figure 15).
generates the SCL signal and device address,
then arranges the communication sequence. To
support communication with an isolated host
controller, the data interface is split into two
ports: SDAI and SDAO. For non-isolated
applications, SDAI and SDAO can be
connected to on another.
The MP3924 includes one alert response Figure 15: Bit Transfer on the I2C Bus
address for MP3924 devices that are connected
The start (S) and stop (P) commands are
through the address 0x0C (000 1100). If the
signaled by the master device, which signifies
bus master controller sends the alert response
the beginning and the end of the I2C transfer. A
address when INT1 is low during an interrupt
start command is defined as the SDA signal
event, then the MP3924 with the interrupt
transitioning from high to low while the SCL
request responds with its device address on the
signal is high. A stop command is defined as
SDAI line before releasing the INT1 line.
the SDA signal transitioning from low to high
If two MP3924 devices respond simultaneously, while the SCL signal is high (see Figure 16).
then the device with the lower address
succeeds in transmitting to the master via the
SDAI and SDAO lines. The device that attempts
to send a 1 but detects a 0 on the SDAI line
does not respond. After this, the MP3924 with Start Condition Stop Condition

the higher address finishes responding. Its INT1 Figure 16: Start and Stop Conditions
pin remains low until it receives the host
controller’s next alert response address read. Start and stop commands are always generated
by the master. The bus is considered to be
The MP3924 has one global address: 0110000. busy after a start command. The bus is
This means that the host controller can write to considered to be free again a minimum of 4.7μs
multiple MP3924 devices through the address after the stop condition. The bus remains busy
0x60 (01100000). If the host controller reads if a repeated start (Sr) command is generated
multiple MP3924 through the address 0x61 instead of a stop command. The start (S) and
(01100001), it works as an alert response repeated start (Sr) commands are functionally
address. identical.
While reading or writing, the MP3924 register I2C Transfer Data
address is determined by the host command. Every byte put on the SDA line must be 8 bits
After each read/write data byte operation, the long. Each byte has to be followed by an
register address automatically increases by 1 acknowledge (ACK) bit. The acknowledge clock
byte, and the host can read/write the next byte pulse is generated by the master. The
without the new address command information. transmitter releases the SDA line (high) during
If the system works with several host controllers,

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 MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER

the acknowledgement clock pulse. The receiver

must pull down the SDA line during the
acknowledge clock pulse so that it remains low
during the high period of this clock pulse.
Figure 17 shows the data transfer sequence. Start Address Data Data Stop
After the start condition (S), a slave address is Condition Condition

sent. This address is 7 bits long followed by an Figure 17: Complete Data Transfer
8th data direction bit (R/W). A 0 indicates a The MP3924 includes a full I2C slave controller.
transmission (write), while a 1 indicates a The I2C slave fully complies with I2C
request for data (read). A data transfer is specification requirements. It requires a start
always terminated by a stop condition (P) condition, a valid I2C address, a register
generated by the master. However, if a master address byte, and a data byte for a single data
must communicate on the bus, it can generate update. The MP3924 acknowledges that it has
a repeated start condition (Sr) and address received each byte by pulling the SDA line low
another slave without first generating a stop during the high period of a single clock pulse. A
condition. valid I2C address selects the MP3924. The
MP3924 performs an update on the falling edge
of the LSB byte.
Figure 18 shows an I2C write example.

8 Bits 8 Bits 8 Bits

S Slave Address Wr A Register Address K A Write Data A P

Master to Slave A = Acknowledge (SDA = Low) S = Start Condition Write (Wr) = 0

Slave to Master NA = Not Acknowledge (SDA = High) P = Stop Condition Read (Rd) = 1

Figure 18: I2C Write Example

Figure 19 shows an I2C write example.
8 Bits 8 Bits 8 Bits 8 Bits

S Slave Address Wr A Register Address K A Sr Slave Address Rd A Read Data K NA P

Register address to read specified Read register data from current register location

Master to Slave A = Acknowledge (SDA = Low) S = Start Condition Sr = Repeat Write (Wr) = 0
Start Condition
Slave to Master NA = Not Acknowledge (SDA = High) P = Stop Condition Read (Rd) = 1

Figure 19: I2C Read Example

Figure 20 shows that the 0x00C address has a different read command from the standard I2C.
8 Bits 8 Bits

S 0x0C Rd A Interrupted Device Address NA P

Read device address data by alert response address

Master to Slave A = Acknowledge (SDA = Low) S = Start Condition Sr = Repeat Write (Wr) = 0
Start Condition
Slave to Master NA = Not Acknowledge (SDA = High) P = Stop Condition Read (Rd) = 1

Figure 20: 0x0C Read Example

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 MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER

Watchdog Over-Temperature Protection (OTP)

The MP3924 implements a watchdog to monitor Over-temperature protection (OTP) is
the SCL line for I2C activity. If there is no implemented to prevent the chip from thermal
transition on the SCL line for about 2.5s during runaway. When the junction temperature
I2C communication, then the I2C port and all exceeds its upper threshold, the MP3924 shuts
power output ports shut down. The WDS bit is down all ports (the I2C and registers still work).
set to 1 to indicate the error condition. WDS Once the temperature drops below its recovery
must be reset before any port can be re- threshold, the ports are enabled again with a
enabled. After watchdog protection is triggered, new detection cycle. The OTP bit is set to 1
the port shuts down until the host re-enables after OTP recovery.
the ENx bits.
By default, the watchdog is off after start-up. To
enable the watchdog function, set the WDEN bit
to 1.

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 MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER

REGISTER DESCRIPTION
Register Map
Addr Register Type D7 D6 D5 D4 D3 D2 D1 D0 Reset State
Interrupt Register
00h INTERRUPT R VINF STF OCP CLSC DETC DCDIS PGC PEC 1000 0000
INTERRUPT_ VINF_ STF_ OCP_ CLSC_ DETC_ DCDIS_ PGC_ PEC_
01h R/W 1A A0 0A00 (11)
MASK M M M M M M M M
INTERRUPT_ VINF_ STF_ OCP_ CLSC_ DETC_ DCDIS_ PGC_ PEC_
02h R/W 1010 0000
PRIORITY P P P P P P P P
Configuration Register
03h MODE_SETTING R/W MODE4 MODE3 MODE2 MODE1 AAAA AAAA (11)
MIDSPAN_
04h R/W - - - - MID4 MID3 MID2 MID1 0000 MMMM (11)
SETTING
05h PORT_ENABLE R/W - - - ENAL EN4 EN3 EN2 EN1 0001 1111
CLSEN LCSEN CLSEN CLSEN DETEN DETEN DETEN
06h DET/CLS_ENABLE R/W DETEN3 AAAA AAAA (11)
4 3 2 1 4 2 1
DISCONNECT_ DISEN DISEN
07h R/W - - - - DISEN3 DISEN1 0000 AAAA (11)
ENABLE 4 2
08h FAULT_TIMER R/W TPMAX TINRUSH TILIM TCUT 1010 1110
09h RESERVED - - - - - - - - - 0000 0000
0Ah RESERVED - - - - - - - 0000 0000
0Bh FOLDBACK_ILIM R/W - - - - - - - FBLIMT 0000 0001
2-EVENT_CLASS_ CLS5_ CLS5_ CLS5_ CLS5_ 2EVNT 2EVNT 2EVNT
0Ch R/W 2EVNTEN3 CCCC AAAA (11)
5_ENABLE EN4 EN3 EN2 EN1 EN4 EN2 EN1
PMAX_
0Dh SHUTDOWN_ R/W PRTY4 PRTY3 PRTY3 PRTY1 1110 0100
PRIORITY
INTERRUPT_ CLRAI
0Eh R/W - - - - - CLRPIN INTEN 0000 0001
ENABLE NT
GENERAL_
0Fh R/W - - - - - PMAXEN ADCEN WDEN 0000 0A 10 (11)
CONTROL
Manual Control Register
DET/CLS_
10h R/W RCLS4 RCLS3 RCLS2 RCLS1 RDET4 RDET3 RDET2 RDET1 0000 0000
TRIGGER
POWER_ON/OFF_
11h R/W POFF4 POFF3 POFF2 POFF1 PON4 PON3 PON2 PON1 0000 0000
TRIGGER
12h LEGACY_ENABLE R/W LEGEN4 LEGEN3 LEGEN2 LEGEN1 0000 0000
Current Limit Configuration Register
ICUT1_
13h R/W - - - - - ICUT1 0000 0000
THRESHOLD
ICUT2_
14h R/W - - - - - ICUT2 0000 0000
THRESHOLD
ICUT3_
15h R/W - - - - - ICUT3 0000 0000
THRESHOLD
ICUT4_
16h R/W - - - - - ICUT4 0000 0000
THRESHOLD
ILIM1_
17h R/W - - - - - - - ILIM1 0000 0000
THRESHOLD
ILIM2_
18h R/W - - - - - - - ILIM2 0000 0000
THRESHOLD
ILIM3_
19h R/W - - - - - - - ILIM3 0000 0000
THRESHOLD
ILIM4_
1Ah R/W - - - - - - - ILIM4 0000 0000
THRESHOLD
Status Register
20h POWER_ R
SOURCE_ FETF4 FETF3 FETF2 FETF1 VCCUV OTP VINOV VINUV 0000 1001
21h R/C (12)
STATUS1
22h POWER_ R
OVP
SOURCE_ - - - - - - VINOK 0000 0000
23h R/C (12) MAX
STATUS2
24h DET/CLS_
R
COMPLETE_ CLSC4 CLSC3 CLSC2 CLSC1 DETC4 DETC3 DETC2 DETC1 0000 0000
25h R/C (12)
STATUS
DET/CLS_ 2EVNT
26h R CLSR1 DETR1 0000 0000
RESULT_1 C1
DET/CLS_ 2EVNT
27h R CLSR2 DETR2 0000 0000
RESULT_2 C2
DET/CLS_ 2EVNT
28h R CLSR3 DETR3 0000 0000
RESULT_3 C3
DET/CLS_ 2EVNT
29h R CLSR4 DETR4 0000 0000
RESULT_4 C4
2Ah POWER_STATUS R PG4 PG3 PG2 PG1 PEN4 PEN3 PEN2 PEN1 0000 0000
2Bh POWER_ R
STATUS_ (12) PGC4 PGC3 PGC2 PGC1 PEC4 PEC3 PEC2 PEC1 0000 0000
2Ch R/C
CHANGE

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 MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER

Addr Register Type D7 D6 D5 D4 D3 D2 D1 D0 Reset State

2Dh OVER_LOAD_ R
OCUT4 OCUT3 OCUT2 OCUT1 STF4 STF3 STF2 STF1 0000 0000
2Eh STATUS R/C (12)
2Fh CURRENT_LIMIT_ R
- - - - OLIM4 OLIM3 OLIM2 OLIM1 0000 0000
30h STATUS R/C (12)
31h DISCONNECT_ R DCDIS
- - - - DCDIS3 DCDIS2 DCDIS1 0000 0000
32h STATUS R/C (12) 4
WATCHDOG_
33h R - - - - - - - WDS 0000 0000
STATUS
34h PIN_STATUS R - - - AUTO A3 A2 A1 A0 000A DDDD (11)
LEGACY_
35h DETECT_ R LEGDET2 LEGDET1 0000 0000
RESULT1
LEGACY_
36h DETECT_ R LEGDET4 LEGDET3 0000 0000
RESULT2
ADC Results Register
40h PORT_1_ R - - - - - - - Bit [0] 0000 0000
41h CURRENT R Bit[8] Bit [7] Bit [6] Bit [5] Bit [4] Bit [3] Bit [2] Bit [1] 0000 0000
42h OUT1_PIN_ R - - - - - - - Bit [0] 0000 0000
43h VOLTAGE R Bit[8] Bit [7] Bit [6] Bit [5] Bit [4] Bit [3] Bit [2] Bit [1] 0000 0000
44h PORT_2_ R - - - - - - - Bit [0] 0000 0000
45h CURRENT R Bit[8] Bit [7] Bit [6] Bit [5] Bit [4] Bit [3] Bit [2] Bit [1] 0000 0000
46h OUT2_PIN_ R - - - - - - - Bit [0] 0000 0000
47h VOLTAGE R Bit[8] Bit [7] Bit [6] Bit [5] Bit [4] Bit [3] Bit [2] Bit [1] 0000 0000
48h PORT_3_ R - - - - - - - Bit [0] 0000 0000
49h CURRENT R Bit[8] Bit [7] Bit [6] Bit [5] Bit [4] Bit [3] Bit [2] Bit [1] 0000 0000
4Ah OUT3_PIN_ R - - - - - - - Bit [0] 0000 0000
4Bh VOLTAGE R Bit [8] Bit [7] Bit [6] Bit [5] Bit [4] Bit [3] Bit [2] Bit [1] 0000 0000
4Ch PORT_4_ R - - - - - - - Bit [0] 0000 0000
4Dh CURRENT R Bit [8] Bit [7] Bit [6] Bit [5] Bit [4] Bit [3] Bit [2] Bit [1] 0000 0000
4Eh OUT4_PIN_ R - - - - - - - Bit [0] 0000 0000
4Fh VOLTAGE R Bit [8] Bit [7] Bit [6] Bit [5] Bit [4] Bit [3] Bit [2] Bit [1] 0000 0000
50h R - - - - - - - Bit [0] 0000 0000
INPUT_VOLTAGE
51h R Bit [8] Bit [7] Bit [6] Bit [5] Bit [4] Bit [3] Bit [2] Bit [1] 0000 0000
52h JUNCTION_ R - - - - - - - Bit [0] 0000 0000
53h TEMPERATURE R Bit [8] Bit [7] Bit [6] Bit [5] Bit [4] Bit [3] Bit [2] Bit [1] 0000 0000
54h PMAX_POWER_ R/W - - - - - - - Bit [0] 0000 000P
55h SETTING R/W Bit [8] Bit [7] Bit [6] Bit [5] Bit [4] Bit [3] Bit [2] Bit [1] PPPP PPPP (11)
MAJOR MINOR VENDO 0000
60h DIE_ID R FAB - - - -
_REV _REV R_ID 0000

Notes:
11) “A” represents the AUTO pin’s status during start-up. “M” represents the MID pin’s status during start-up. “C” represents CLS5 pin’s status
during start-up. “D” represents the A3~A0 address pin statuses during start-up. “P” represents the PMAX pin setting ADC results during
start-up.
12) R/C is read and clear address. Reading R/C clears the bit status after reading is complete.

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 MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER

INTERRUPT REGISTERS
INTERRUPT (00h)
Read-only
Bits Bit Name Default Value Description
Interrupt signal for VIN power failure. If this bit is set to 1, one of the following
scenarios has occurred:
 The power on VIN is below 29.5V
D[7] VINF 1  VIN over-voltage protection (OVP)
 VCC is under the under-voltage lockout (UVLO) threshold
 Thermal shutdown
 A power MOSFET failure
 A PMAX event
Interrupt signal for a start-up failure. If this bit is set to 1, at least one of the ports has
D[6] STF 0 experienced a start-up failure, or if a port shuts down due to the start-up inrush
current.
Interrupt signal for over-current (OC) conditions. If this bit is set to 1, at least one of
D[5] OCP 0
the ports has met the ILIMT current limit timer or the ICUT OC timeout condition.
Interrupt signal for classification completion. This bit is set to 1 if at least one port
D[4] CLSC 0
has completed its classification process.
Interrupt signal for detection completion. This bit is set to 1 if at least one port has
D[3] DETC 0
completed its detection process.
Interrupt signal for a disconnected DC load. This bit is set to 1 if at least one port
D[2] DCDIS 0
has had its DC load disconnected (load < 7.5mA).
Interrupt signal for power good (PG) status change. This bit is set to 1 if at least one
D[1] PGC 0
port has a new PG status.
Interrupt signal for power enable status change. This bit is set to 1 if at least one
D[0] PEC 0
port has changed its enable or disable status.

Read the register address with an R/C byte, or write 1 to CLRAIN to reset the corresponding bit. The
IN1 and INT2 pins go low to report if an interrupt bit is set to 1. These pins do not go low if the interrupt
signal is masked.
INTERRUPT_MASK (01h)
Read/write
Bits Bit Name Default Value Description
Masks the interrupt signal for VIN power failures. Set this bit to 0 to disable the
D[7] VINF_M 1
interrupt function.
Masks the interrupt signal for start-up failures. Set this bit to 0 to disable the
D[6] STF_M A
interrupt function.
Masks the interrupt signal for over-current (OC) conditions. Set this bit to 0 to
D[5] OCP_M A
disable the interrupt function.
Masks the interrupt signal for classification completion. Set this bit to 0 to disable the
D[4] CLSC_M 0
interrupt function.
Masks the interrupt signal for detection completion. Set this bit to 0 to disable the
D[3] DETC_M 0
interrupt function.
Masks the interrupt signal for DC load disconnection. Set this bit to 0 to disable the
D[2] DCDIS_M A
interrupt function.
Masks the interrupt signal for power good (PG) status change interrupt. Set this bit
D[1] PGC_M 0
to 0 to disable the interrupt function.

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Masks the interrupt signal for power enable status change interrupt. Set this bit to 0
D[0] PEC_M 0
to disable the interrupt function.

Write 1 to enable the interrupt function; write 0 to disable the interrupt function. “A” is “1” if the AUTO
pin is set high during start-up or a reset. “A” is “0” if the AUTO pin is set low.
These bits only disable the response from the INT1 and INT2 pins. The corresponding interrupt bit
always changes. The device cannot mask certain interruptions during start-up or a reset event,
including VIN under-voltage lockout (UVLO) and VCC UVLO.
INTERRUPT PRIORITY (02h)
Read/write
Bits Bit Name Default Value Description
D[7] VINF_P 1 Selects if the INT2 pin responds to a VIN power failure interrupt signal.
D[6] STF_P 0 Selects if the INT2 pin responds to a start-up failure interrupt signal.
D[5] OCP_P 1 Selects if the INT2 pin responds to an over-current (OC) interrupt signal.
D[4] CLSC_P 0 Selects if the INT2 pin responds to a classification completion interrupt signal.
D[3] DETC_P 0 Selects if the INT2 pin responds to a detection completion interrupt signal.
D[2] DCDIS_P 0 Selects if the INT2 pin responds to a DC load disconnect interrupt signal.
Selects if the INT2 pin responds to a power good (PG) status change interrupt
D[1] PGC_P 0
signal.
D[0] PEC_P 0 Selects if the INT2 pin responds to a power enable status change interrupt signal.

If a bit is set to 1, the INT2 pin pulls low in response to the corresponding interrupt signal. The INT1 pin
responds to all interrupt sources, as long as they are not masked. INT2 only responds to the interrupt
sources that are not masked.

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CONFIGURATION AND CONTROL REGISTERS

OPERATION_MODE_SETTING (03h)
Read/write
Bits Bit Name Default Value Description
Sets the operation mode for ports 1 through 4. “A” is 1 if the AUTO pin is set high
D[7:6] MODE4 AA
during start-up or a reset. “A” is 0 if the AUTO pin is set low. The status is latched
only during start-up or a reset. This can be changed via the I2C.
D[5:4] MODE3 AA 00: Shutdown mode. The port is off, and there is no detection or classification
process
01: Manual mode. There is no automatic state change
D[3:2] MODE2 AA 10: Semi-automatic mode. The detection and classification processes are
automated, but the port does not turn on automatically
11: Automatic mode. Start-up, as well as detection and classification processes,
D[1:0] MODE1 AA
are automated

MIDSPAN_SETTING (04h)
Read/write
Bits Bit Name Default Value Description
D[7:4] RESERVED - Reserved.
D[3] MID4 M
Sets the midspan mode for ports 1 through 4. “M” is “1” if the MID pin is high
D[2] MID3 M during start-up or a reset. “M” is “0” if MID pin is low. These changes can be
configured by writing to the I2C. Set this bit to 1 to enable midspan mode for the
D[1] MID2 M
corresponding port.
D[0] MID1 M

PORT_ENABLE (05h)
Read/write
Bits Bit Name Default Value Description
D[7:5] RESERVED - Reserved.
Enables the MP3924. If this bit is set to 1, all internal IC circuits are enabled.
D[4] ENAL 1 Each port is enabled if the ENAL and ENx bits are set to 1. If ENAL is disabled,
the I2C continues to operate, but the ports are shut down.
D[3] EN4 1 Enables ports 1 through 4. These bits can disable the corresponding port, which
includes detection and classification processes, resets the port and status
D[2] EN3 1 registers, and shuts down the port. If a port is already turned off and these bits
are set to 0, then there is no change.
D[1] EN2 1
1: Enabled
D[0] EN1 1 0: Disabled

DET/CLS_ENABLE (06h)
Read/write
Bits Bit Name Default Value Description
D[7] CLSEN4 A
D[6] CLSEN3 A Enables the classification process for the corresponding port. Set these bits to 1 to
D[5] CLSEN2 A enable classification.
D[4] CLSEN1 A
D[3] DETEN4 A
D[2] DETEN3 A Enables the detection process for the corresponding port. Set these bits to 1 to
D[1] DETEN2 A enable detection.
D[0] DETEN1 A

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“A” is “1” if the AUTO pin is set high during start-up or a reset. “A” is “0” if the AUTO pin is set low. In
automatic and semi-automatic mode, the detection and classification processes are enabled when the
bit is set to 1. In manual made, set the bit to 1 for one-time detection or classification. Then the bit is
reset to 0.
DISCONNECT_ENABLE (07h)
Read/write
Bits Bit Name Default Value Description
D[7:4] RESERVED - Reserved.
D[3] DISEN4 A Enables DC load disconnection for ports 1 through 4. “A” is 1 if the AUTO pin is
D[2] DISEN3 A set high during start-up or a reset. “A” is 0 if the AUTO pin is set low. If these bits
D[1] DISEN2 A are set to 1, the DC load disconnection function is enabled on the corresponding
D[0] DISEN1 A port.

FAULT_TIMER (08h)
Read/write
Bits Bit Name Default Value Description
Sets the total power overload timer after start-up.
00: 15ms
D[7:6] TPMAX 10 01: 30ms
10: 60ms
11: 120ms
Sets the start-up inrush current timer for all ports.
00: 15ms
D[5:4] TINRUSH 10 01: 30ms
10: 60ms
11: 120ms
Sets the current limit trigger timer after start-up for all ports.
00: 7.5ms
D[3:2] TILIM 11 01: 15ms
10: 30ms
11: 60ms
Set the over-current (OC) timer after start-up for all ports.
00: 15ms
D[1:0] TCUT 10 01: 30ms
10: 60ms
11: 120ms

The timer begins counting up after a load triggers the threshold. If the current drops below the
threshold, the timer begins counting down at 1/16 of the rising rate. If it times out, the port shuts down.
The port cannot be redetected once the timer counts down to 0.
FOLDBACK_ILIM (0Bh)
Read/write
Bits Bit Name Default Value Description
D[7:1] RESERVED - Reserved.
Sets the foldback over-current (OC) threshold when the OUTx pin exceeds 46V.
D[0] FBLIMT 1 0: The foldback current limit is 22mV (88mA if RSENSE = 0.25Ω).
1: The foldback current limit is 40mV (160mA RSENSE = 0.25Ω).

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2-EVENT_AND_CLASS_5_ENABLE (0Ch)
Read/write
Bits Bit Name Default Value Description
D[7] CLS5_EN4 C
D[6] CLS5_EN3 C Enables Class 5 classification for all ports. If these bits are set to 1, Class 5
classification is enabled on the corresponding port, and the default current limit
D[5] CLS5_EN2 C can support up to 40W of power.
D[4] CLS5_EN1 C
D[3] 2EVNTEN4 A
D[2] 2EVNTEN3 A Enables two-event classification for all ports. If these bits are set to 1, two-event
classification is enabled when the first classification result on the port is Class 4 or
D[1] 2EVNTEN2 A Class 5.
D[0] 2EVNTEN1 A

“A” is “1” if the AUTO pin is set high during start-up or a reset. “A” is “0” if the AUTO pin is set low. “C” is
“1” if the CLS5 pin is set high during start-up or a reset. “C” is “0” if the CLS5 pin is set low. The CLS5
pin has a high power level under the IEEE802.3 at classification, but it is not a standard class level that
is compatible with IEEE802.3.
PMAX_SHUTDOWN_PORT_PRIORITY (0Dh)
Read/write
Bits Bit Name Default Value Description
D[7:6] PRTY4 11 Sets the shutdown priority for all ports after the PMAX limit is triggered. If the value
is the same on several ports, priority is arranged based on the default priority. For
D[5:4] PRTY3 10 example, if both port 1 and port 2 are 00, then port 2 shuts down first.
11: The lowest priority port, which shuts down first if the PMAX limit is triggered
D[3:2] PRTY2 01 10: The third level priority port if the PMAX limit is triggered
01: The second level priority port if the PMAX limit is triggered
D[1:0] PRTY1 00 00: The highest priority port, which shuts down last if the PMAX limit is triggered

INTERRUPT_ENABLE_CONTROL (0Eh)
Read/write
Bits Bit Name Default Value Description
D[7:3] RESERVED - Reserved.
Controls the reset function for the INT1 and INT2 pins. If this bit is set to 1,
D[2] CLRPIN 0 resetting the INT1 and INT2 pins does not affect the registers. This bit is
automatically set to 0 after the INT1 and INT2 pins are reset.
Controls the reset function for the interrupt source. If this bit is set to 1, all
D[1] CLRAINT 0 registers and the INT1 and INT2 bit are reset. This bit is automatically set to 0
after the INT1 and INT2 pins are reset.
Enables the interrupt function. This bit does not affect the event register. If this bit
D[0] INTEN 1
is set to 1, the interrupt function is enabled.

GENERAL_ENABLE_CONTROL (0Fh)
Read/write
Bits Bit Name Default Value Description
D[7:3] RESERVED - Reserved.
Enables the maximum total load power limit. If this bit = 1, automatic shutdown is
D[2] PMAXEN A
triggered when the PMAX pin reaches its maximum input power setting.
D[1] ADCEN 1 Enables the ADC. If this bit = 1, the ADC is enabled.
D[0] WDEN 0 Enables the I2C watchdog. If this bit is set to 0, the watchdog is disabled.

“A” is “1” if the AUTO pin is set high during start-up or a reset. “A” is “0” if the AUTO pin is set low.

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MANUAL MODE AND LEGACY DETECTION CONTROL REGISTERS

DET/CLS_TRIGGER (10h)
Read/write
Bits Bit Name Default Value Description
D[7] RCLS4 0
D[6] RCLS3 0 Re-enables the classification function on all ports. If these bits are set to 1, a one-
time classification event is enabled on the corresponding port. These bits are reset
D[5] RCLS2 0 after classification is complete.
D[4] RCLS1 0
D[3] RDET4 0
D[2] RDET3 0 Re-enables the detection function on all ports. If these bits are set to 1, a one-time
detection event is enabled on the corresponding port. These bits are reset after
D[1] RDET2 0 detection is complete.
D[0] RDET1 0

In manual mode, one-time detection or classification occurs after the corresponding bit is set. In semi-
automatic or automatic mode, detection and classification are controlled by the DETENx and CLSENx
bits. These processes are repeated once they are enabled.
POWER_ON/OFF_TRIGGER (11h)
Read/write
Bits Bit Name Default Value Description
D[7] POFF4 0
D[6] POFF3 0 Triggers a shutdown on the corresponding port. If these bits are set to 1, the port
D[5] POFF2 0 powers off. The bit automatically resets afterward.
D[4] POFF1 0
Triggers start-up on the corresponding port. If these bits are set to 1, the
D[3] PON4 0 corresponding port powers on. These bits are reset after start-up is complete. The
device performs a detection cycle first if the DETENx and PONx bits are set
simultaneously.

D[2] PON3 0 The PONx bits are operational in manual mode. If the port is powered on or in
shutdown mode, the port does not respond to these bits.
The PONx bits are operational in semi-automatic mode. The port responds to
these bits if the detection and classification results are valid.
D[1] PON2 0
The PONx bits are only functional during legacy detection if the device is set to
automatic mode.
D[0] PON1 0 For all modes, the PONx bits may be cleared by DET/CLS/LEGACY_DET failures,
start-up failures, or if the PON signal lasts for 400ms when the port is operational.

LEGACY_ENABLE (12h)
Read/write
Bits Bit Name Default Value Description
D[7:6] LEGEN4 00 Enables legacy detection mode for all ports.
D[5:4] LEGEN3 00 00: Legacy detection is disabled
D[3:2] LEGEN2 00 01: Legacy detection is enabled while standard detection is disabled
10: Legacy detection is enabled after standard detection is complete
D[1:0] LEGEN1 00 11: Reserved

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CURRENT LIMIT CONFIGURATION REGISTER

ICUT1_THRESHOLD (13h)
Read/write
Bits Bit Name Default Value Description
D[7:3] RESERVED - Reserved.
Sets port 1’s over-current (OC) threshold. The default value is 000. In automatic
mode, the bits are set to 000 for Class 0~3 results, 100 for Class 4 results, and
101 for Class 5 results. In semi-automatic mode or manual mode, the bits do not
change unless changes are made via the I2C.
000 = 93.75mV (375mA with RSENSE = 0.25Ω)
D[2:0] ICUT1 000 001 = 27.5mV (110mA with RSENSE = 0.25Ω)
010 = 47mV (188mA with RSENSE = 0.25Ω)
011 = 93.75mV (375mA with RSENSE = 0.25Ω)
100 = 162.5mV (650mA with RSENSE = 0.25Ω)
101 = 230mV (920mA with RSENSE = 0.25Ω)
110 = 125mV (500mA with RSENSE = 0.25Ω)
111 = 156.25mV (625mA with RSENSE = 0.25Ω)

ICUT2_THRESHOLD (14h)
Read/write
Bits Bit Name Default Value Description
D[7:3] RESERVED - Reserved.
Sets port 2’s over-current (OC) threshold. The default value is 000. In automatic
mode, the bits are set to 000 for Class 0~3 results, 100 for Class 4 results, and
101 for Class 5 results. In semi-automatic mode or manual mode, the bits do not
change unless changes are made via the I2C.
000 = 93.75mV (375mA with RSENSE = 0.25Ω)
D[2:0] ICUT2 000 001 = 27.5mV (110mA with RSENSE = 0.25Ω)
010 = 47mV (188mA with RSENSE = 0.25Ω)
011 = 93.75mV (375mA with RSENSE = 0.25Ω)
100 = 162.5mV (650mA with RSENSE = 0.25Ω)
101 = 230mV (920mA with RSENSE = 0.25Ω)
110 = 125mV (500mA with RSENSE = 0.25Ω)
111 = 156.25mV (625mA with RSENSE = 0.25Ω)

ICUT3_THRESHOLD (15h)
Read/write
Bits Bit Name Default Value Description
D[7:3] RESERVED - Reserved.
Sets port 3’s over-current (OC) threshold. The default value is 000. In automatic
mode, the bits are set to 000 for Class 0~3 results, 100 for Class 4 results, and
101 for Class 5 results. In semi-automatic mode or manual mode, the bits do not
change unless changes are made via the I2C.
000 = 93.75mV (375mA with RSENSE = 0.25Ω)
D[2:0] ICUT3 000 001 = 27.5mV (110mA with RSENSE = 0.25Ω)
010 = 47mV (188mA with RSENSE = 0.25Ω)
011 = 93.75mV (375mA with RSENSE = 0.25Ω)
100 = 162.5mV (650mA with RSENSE = 0.25Ω)
101 = 230mV (920mA with RSENSE = 0.25Ω)
110 = 125mV (500mA with RSENSE = 0.25Ω)
111 = 156.25mV (625mA with RSENSE = 0.25Ω)

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ICUT4_THRESHOLD (16h)
Read/write
Bits Bit Name Default Value Description
D[7:3] RESERVED - Reserved.
Sets port 4’s over-current (OC) threshold. The default value is 000. In automatic
mode, the bits are set to 000 for Class 0~3 results, 100 for Class 4 results, and
101 for Class 5 results. In semi-automatic mode or manual mode, the bits do not
change unless changes are made via the I2C.
000 = 93.75mV (375mA with RSENSE = 0.25Ω)
D[2:0] ICUT4 000 001 = 27.5mV (110mA with RSENSE = 0.25Ω)
010 = 47mV (188mA with RSENSE = 0.25Ω)
011 = 93.75mV (375mA with RSENSE = 0.25Ω)
100 = 162.5mV (650mA with RSENSE = 0.25Ω)
101 = 230mV (920mA with RSENSE = 0.25Ω)
110 = 125mV (500mA with RSENSE = 0.25Ω)
111 = 156.25mV (625mA with RSENSE = 0.25Ω)

ILIM1_THRESHOLD (17h)
Read/write
Bits Bit Name Default Value Description
D[7:1] RESERVED - Reserved.
Sets port 1’s over-current (OC) limit. The default value is 0. In automatic mode, the
bits are set to 0 for Class 0~3, and set to 1 for Class 4 or Class 5 results. In semi-
automatic mode and manual mode, the bits do not change unless changes are
D[0] ILIM1 0 made via the I2C.
0: 106.25mV (425mA if RSENSE = 0.25Ω)
1: 212.5mV. The current limit is 265mV under Class 5 conditions

ILIM2_THRESHOLD (18h)
Read/write
Bits Bit Name Default Value Description
D[7:1] RESERVED - Reserved.
Sets port 2’s over-current (OC) limit. The default value is 0. In automatic mode, the
bits are set to 0 for Class 0~3, and set to 1 for Class 4 or Class 5 results. In semi-
automatic mode and manual mode, the bits do not change unless changes are
D[0] ILIM2 0 made via the I2C.
0: 106.25mV (425mA if RSENSE = 0.25Ω)
1: 212.5mV. The current limit is 265mV under Class 5 conditions

ILIM3_THRESHOLD (19h)
Read/write
Bits Bit Name Default Value Description
D[7:1] RESERVED - Reserved.
Sets port 3’s over-current (OC) limit. The default value is 0. In automatic mode, the
bits are set to 0 for Class 0~3, and set to 1 for Class 4 or Class 5 results. In semi-
automatic mode and manual mode, the bits do not change unless changes are
D[0] ILIM3 0 made via the I2C.
0: 106.25mV (425mA if RSENSE = 0.25Ω)
1: 212.5mV. The current limit is 265mV under Class 5 conditions

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ILIM4_THRESHOLD (1Ah)
Read/write
Bits Bit Name Default Value Description
D[7:1] RESERVED - Reserved.
Sets port 4’s over-current (OC) limit. The default value is 0. In automatic mode, the
bits are set to 0 for Class 0~3, and set to 1 for Class 4 or Class 5 results. In semi-
automatic mode and manual mode, the bits do not change unless changes are
D[0] ILIM4 0 made via the I2C.
0: 106.25mV (425mA if RSENSE = 0.25Ω)
1: 212.5mV. The current limit is 265mV under Class 5 conditions

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STATUS REGISTERS
POWER_SOURCE_STATUS1 (20h and 21h)
(20h) Read-only
(21h) Read and clear
Bits Bit Name Default Value Description
D[7] FETF4 0
D[6] FETF3 0 Indicates whether an external power MOSFET failure has occurred. This bit is set
to 1 if the external MOSFET on the corresponding port has failed. If this occurs, the
D[5] FETF2 0 current limit cannot be reached, or the OUTx pin is high after start-up.
D[4] FETF1 0
Indicates whether a VCC under-voltage condition has occurred. This bit is set to 1
D[3] VCCUV 1
if VCC has recovered from a shutdown or reset condition.
Indicates whether an over-temperature (OT) condition has occurred. This bit is set
D[2] OTP 0 to 1 if the junction temperature exceeds 150°C. For more details, see the Over-
Temperature Protection (OTP) section on page 28.
Indicates whether a VIN over-voltage (OV) condition has occurred. This bit is set to
D[1] VINOV 0
1 if VIN exceeds 65V.
Indicates whether a VIN under-voltage (UV) condition has occurred. This bit is set
D[0] VINUV 1
to 1 if VIN drops below 29.5V.

Read and Clear (0x21h) means that the bit is reset after a read operation. If read on 0x20h, the bits are not
cleared.
POWER_SOURCE_STATUS2 (22h and 23h)
(22h) Read-only
(23h) Read and clear
Bits Bit Name Default Value Description
D[7:2] RESERVED - Reserved.
Indicates whether the VIN source power is working normally. This bit is set to 1 if
D[1] VINOK 0
VIN exceeds 40V.
Indicates whether a power overload condition has occurred. This bit is set to 1 if
D[0] OVPMAX 0
the total power load on all ports exceeds the PMAX threshold set by the PMAX pin.

DET/CLS_COMPLETE_STATUS (24h and 25h)

(24h) Read-only
(25h) Read and clear
Bits Bit Name Default Value Description
D[7] CLSC4 0
D[6] CLSC3 0 Indicates whether a port has completed its classification process. These bits are
D[5] CLSC2 0 set to 1 if classification has completed on the corresponding bit.
D[4] CLSC1 0
D[3] DETC4 0
D[2] DETC3 0 Indicates whether a port has completed its detection process. These bits are set to
D[1] DETC2 0 1 if detection has completed on the corresponding bit.
D[0] DETC1 0

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DET/CLS_RESULT1 (26h)
Read-only
Bits Bit Name Default Value Description
Returns the classification result for port 1.
0000: Classification is not done
0001: Class 1
0010: Class 2
0011: Class 3
0100: Class 4
D[7:4] CLSR1 0000 0101: Class 5
0110: Class 0
0111: Over-current (OC) condition
1000: The first and secondary class results do not match
If Class 5 is enabled, any current that exceeds Class 4’s upper limit is considered a
Class 5 result. An OC condition triggers a current limit. If Class 5 is disabled, any
current exceeding Class 4’s upper limit is considered an OC condition.
Indicates whether two-event classification has been completed on port 1. This bit is
D[3] 2EVNTC1 0 set to 1 if two-event classification has been completed. This bit is only set once
Class 4 and Class 5 are successfully detected.
Indicates port 1’s detection result.
000: Detection has not completed (default after a power-on reset)
001: The port is shorted (VIN - OUT < 1.5V)
010: CDET too high (exceeds 5µF)
D[2:0] DETR1 000 011: RDET is too low (below 19kΩ)
100: Detection is valid (19kΩ < RDET < 26.5kΩ)
101: RDET is too high (exceeds 26.5kΩ)
110: The port is open (<15µA load current)
111: Low impedance to PGND (OUT - PGND < 2V)

DET/CLS_RESULT2 (27h)
Read-only
Bits Bit Name Default Value Description
Returns the classification result for port 2.
0000: Classification is not done
0001: Class 1
0010: Class 2
0011: Class 3
0100: Class 4
D[7:4] CLSR2 0000 0101: Class 5
0110: Class 0
0111: Over-current (OC) condition
1000: The first and secondary class results do not match
If Class 5 is enabled, any current that exceeds Class 4’s upper limit is considered a
Class 5 result. An OC condition triggers a current limit. If Class 5 is disabled, any
current exceeding Class 4’s upper limit is considered an OC condition.
Indicates whether two-event classification has been completed on port 2. This bit is
D[3] 2EVNTC2 0 set to 1 if two-event classification has been completed. This bit is only set once
Class 4 and Class 5 are successfully detected.

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Indicates port 2’s detection result.

000: Detection has not completed (default after a power-on reset)
001: The port is shorted (VIN - OUT < 1.5V)
010: CDET too high (exceeds 5µF)
D[2:0] DETR2 000 011: RDET is too low (below 19kΩ)
100: Detection is valid (19kΩ < RDET < 26.5kΩ)
101: RDET is too high (exceeds 26.5kΩ)
110: The port is open (<15µA load current)
111: Low impedance to PGND (OUT - PGND < 2V)

DET/CLS_RESULT3 (28h)
Read-only
Bits Bit Name Default Value Description
Returns the classification result for port 3.
0000: Classification is not done
0001: Class 1
0010: Class 2
0011: Class 3
0100: Class 4
D[7:4] CLSR3 0000 0101: Class 5
0110: Class 0
0111: Over-current (OC) condition
1000: The first and secondary class results do not match
If Class 5 is enabled, any current that exceeds Class 4’s upper limit is considered a
Class 5 result. An OC condition triggers a current limit. If Class 5 is disabled, any
current exceeding Class 4’s upper limit is considered an OC condition.
Indicates whether two-event classification has been completed on port 3. This bit is
D[3] 2EVNTC3 0 set to 1 if two-event classification has been completed. This bit is only set once
Class 4 and Class 5 are successfully detected.
Indicates port 3’s detection result.
000: Detection has not completed (default after a power-on reset)
001: The port is shorted (VIN - OUT < 1.5V)
010: CDET too high (exceeds 5µF)
D[2:0] DETR3 000 011: RDET is too low (below 19kΩ)
100: Detection is valid (19kΩ < RDET < 26.5kΩ)
101: RDET is too high (exceeds 26.5kΩ)
110: The port is open (<15µA load current)
111: Low impedance to PGND (OUT - PGND < 2V)

DET/CLS_RESULT4 (29h)
Read-only
Bits Bit Name Default Value Description
Returns the classification result for port 4.
0000: Classification is not done
0001: Class 1
0010: Class 2
0011: Class 3
0100: Class 4
D[7:4] CLSR4 0000 0101: Class 5
0110: Class 0
0111: Over-current (OC) condition
1000: The first and secondary class results do not match
If Class 5 is enabled, any current that exceeds Class 4’s upper limit is considered a
Class 5 result. An OC condition triggers a current limit. If Class 5 is disabled, any
current exceeding Class 4’s upper limit is considered an OC condition.

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Indicates whether two-event classification has been completed on port 4. This bit is
D[3] 2EVNTC4 0 set to 1 if two-event classification has been completed. This bit is only set once
Class 4 and Class 5 are successfully detected.
Indicates port 4’s detection result.
000: Detection has not completed (default after a power-on reset)
001: The port is shorted (VIN - OUT < 1.5V)
010: CDET too high (exceeds 5µF)
D[2:0] DETR4 000 011: RDET is too low (below 19kΩ)
100: Detection is valid (19kΩ < RDET < 26.5kΩ)
101: RDET is too high (exceeds 26.5kΩ)
110: The port is open (<15µA load current)
111: Low impedance to PGND (OUT - PGND < 2V)

POWER_STATUS (2Ah)
Read-only
Bits Bit Name Default Value Description
D[7] PG4 0 Indicates the power good (PG) status for all ports. This bit is set to 1 if the
D[6] PG3 0 corresponding port’s power is on, and if the OUTx pin’s voltage is below VPG.
D[5] PG2 0 The PG bit resets once the OUTx pin’s voltage exceeds the VPG threshold with a
D[4] PG1 0 short deglitch time.
D[3] PEN4 0
D[2] PEN3 0 Indicates whether power has been enabled on a port. These bits are set to 1 if the
D[1] PEN2 0 corresponding port is powered on.
D[0] PEN1 0

POWER_STATUS_CHANGE (2Bh and 2Ch)

(2Bh) Read-only
(2Ch) Read and clear
Bits Bit Name Default Value Description
D[7] PGC4 0
D[6] PGC3 0 Indicates whether the power good (PG) status has changed on the ports. This bit is
D[5] PGC2 0 set to 1 if the PG status changes on the corresponding port.
D[4] PGC1 0
D[3] PEC4 0
D[2] PEC3 0 Indicates whether the power status has been enabled or disabled on the ports.
This bit is set 1 if the power status changes (disabled or enabled) on the
D[1] PEC2 0 corresponding port.
D[0] PEC1 0

OVER_LOAD_STATUS (2Dh and 2Eh)

(2Dh) Read-only
(2Eh) Read and clear
Bits Bit Name Default Value Description
D[7] OCUT4 0
D[6] OCUT3 0 Indicates whether the ICUT1~4 timer (tICUT) has finished counting after ICUTx
D[5] OCUT2 0 exceeds the over-current (OC) threshold. This bit is set to 1 if tICUT times out.
D[4] OCUT1 0
D[3] STF4 0
D[2] STF3 0 Indicates a start-up failure for all ports. This bit is set to 1 if start-up inrush timer
D[1] STF2 0 times out, or if there is a power-on command failure.
D[0] STF1 0

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CURRENT_LIMIT_STATUS (2Fh and 30h)

(2Fh) Read-only
(30h) Read and clear
Bits Bit Name Default Value Description
D[7:4] RESERVED - Reserved.
D[3] OLIM4 0
D[2] OLIM3 0 Indicates whether a hardware current limit has been triggered on the ports. These
D[1] OLIM2 0 bits are set to 1 if a current limit is triggered on a corresponding port.
D[0] OLIM1 0

DISCONNECT_STATUS (31h and 32h)

(31h) Read-only
(32h) Read and clear
Bits Bit Name Default Value Description
D[7:5] RESERVED - Reserved.
D[3] DCDIS4 0
D[2] DCDIS3 0 Indicates whether a disconnected DC load event has occurred on the ports.
These bits are set to 1 if a disconnected DC load event occurs on the
D[1] DCDIS2 0 corresponding port.
D[0] DCDIS1 0

WATCHDOG_STATUS (33h)
Read-only
Bits Bit Name Default Value Description
D[7:1] RESERVED - Reserved.
Indicates the watchdog status. This bit is set to 0 if the watchdog times out
D[0] WDS 0
without an active CLK signal.

PIN_STATUS (34h)
Read-only
Bits Bit Name Default Value Description
D[7:5] RESERVED - Reserved.
Returns the AUTO pin’s status during start-up. “A” is “1” if the AUTO pin is set
D[4] AUTO A high during start-up or a reset. “A” is “0” if the AUTO pin is set low. This bit is set
to 1 if the AUTO pin is pulled high.
D[3] A4A3 D
D[2] A3A2 D Returns the A3~A0 pins’ statuses during start-up. “D” is “1” if the corresponding
pin is set high during start-up or a reset. “D” is “0” if the corresponding pin is set
D[1] A2A1 D low. These bits are set to 1 if the corresponding pin’s voltage is high.
D[0] A1A0 D

LEGACY_DETECT_RESULT1 (35h)
Read-only
Bits Bit Name Default Value Description
Returns the legacy detection results for port 2.
0000: No legacy detection
0001: Valid (5µF < PD input capacitor < 100µF)
D[7:4] LEGDET2 0000 0010: Unable to discharge the PD input capacitance to 2.4V
0100: The first measurement exceeds the 18.5V maximum voltage
0101: The second measurement exceeds the 18.5V maximum voltage
0110: The difference between the measured voltages is below 0.5V

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Returns the legacy detection results for port 1.

0000: No legacy detection
0001: Valid (5µF < PD input capacitor < 100µF)
D[3:0] LEGDET1 0000 0010: Unable to discharge the PD input capacitance to 2.4V
0100: The first measurement exceeds the 18.5V maximum voltage
0101: The second measurement exceeds the 18.5V maximum voltage
0110: The difference between the measured voltages is below 0.5V

LEGACY_DETECT_RESULT2 (36h)
Read-only
Bits Bit Name Default Value Description
Returns the legacy detection results for port 4.
0000: No legacy detection
0001: Valid (5µF < PD input capacitor < 100µF)
D[7:4] LEGDET4 0000 0010: Unable to discharge the PD input capacitance to 2.4V
0100: The first measurement exceeds the 18.5V maximum voltage
0101: The second measurement exceeds the 18.5V maximum voltage
0110: The difference between the measured voltages is below 0.5V
Returns the legacy detection results for port 3.
0000: No legacy detection
0001: Valid (5µF < PD input capacitor < 100µF)
D[3:0] LEGDET3 0000 0010: Unable to discharge the PD input capacitance to 2.4V
0100: The first measurement exceeds the 18.5V maximum voltage
0101: The second measurement exceeds the 18.5V maximum voltage
0110: The difference between the measured voltages is below 0.5V

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ADC RESULT REGISTERS

PORT_1_CURRENT (40h and 41h)
Read-only
Bits Bit Name Default Value Description
(40h)
0 Returns the lower bit of port 1’s ADC current result.
D[0]
Returns the higher bits of port 1’s ADC current result.
PORT_1_
41h CURRENT_DATA The output current can be calculated with the following equation:
0000 0000
D[7:0] Output current = 2.4mA x COUNT - 10mA
Where COUNT is the unsigned binary integer of the ADC result.

PORT_1_VOLTAGE (42h and 43h)

Read-only
Bits Bit Name Default Value Description
42h
0 Returns the lower bit of port 1’s ADC voltage result.
D[0]
OUT1_ Returns the higher bits of port 1’s ADC voltage result.
PIN_ The sum of these two registers is the OUT1 pin voltage. The port output voltage
43h VOLTAGE can be calculated with the following equation:
0000 0000
D[7:0] _DATA
Output voltage = 0.15V x (VIN COUNT - OUT1 COUNT)
Where COUNT is the unsigned binary integer of the ADC result.

PORT_2_CURRENT (44h and 45h)

Read-only
Bits Bit Name Default Value Description
44h
0 Returns the lower bit of port 2’s ADC current result.
D[0]
PORT_2_ Returns the higher bits of port 2’s ADC current result.
CURRENT_ The output current can be calculated with the following equation:
45h
DATA 0000 0000
D[7:0] Output current = 2.4mA x COUNT - 10mA
Where COUNT is the unsigned binary integer of the ADC result.

PORT_2_VOLTAGE (46h and 47h)

Read-only
Bits Bit Name Default Value Description
46h
0 Returns the lower bit of port 2’s ADC voltage result.
D[0]
Returns the higher bits of port 2’s ADC voltage result.
OUT2_PIN_
VOLTAGE_ The sum of these two registers is the OUT2 pin voltage. The port output voltage
47h can be calculated with the following equation:
DATA 0000 0000
D[7:0]
Output voltage = 0.15V x (VIN COUNT - OUT2 COUNT)
Where COUNT is the unsigned binary integer of the ADC result.

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PORT_3_CURRENT (48h and 49h)

Read-only
Bits Bit Name Default Value Description
48h
0 Returns the lower bit of port 3’s ADC current result.
D[0]
PORT_3_ Returns the higher bits of port 3’s ADC current result.
CURRENT_ The output current can be calculated with the following equation:
49h
DATA 0000 0000
D[7:0] Output current = 2.4mA x COUNT - 10mA
Where COUNT is the unsigned binary integer of the ADC result.

PORT_3_VOLTAGE (4Ah and 4Bh)

Read-only
Bits Bit Name Default Value Description
4Ah
0 Returns the lower bit of port 3’s ADC voltage result.
D[0]
Returns the higher bits of port 3’s ADC voltage result.
OUT3_PIN_
VOLTAGE_ The sum of these two registers is the OUT3 pin voltage. The port output voltage
4Bh can be calculated with the following equation:
DATA 0000 0000
D[7:0]
Output voltage = 0.15V x (VIN COUNT - OUT3 COUNT)
Where COUNT is the unsigned binary integer of the ADC result.

PORT_4_CURRENT (4Ch and 4Dh)

Read-only
Bits Bit Name Default Value Description
4Ch
0 Returns the lower bit of port 4’s ADC current result.
D[0]
PORT_4_ Returns the higher bits of port 4’s ADC current result.
CURRENT_ The output current can be calculated with the following equation:
4Dh
DATA 0000 0000
D[7:0] Output current = 2.4mA x COUNT - 10mA
Where COUNT is the unsigned binary integer of the ADC result.

PORT_4_VOLTAGE (4Eh and 4Fh)

Read-only
Bits Bit Name Default Value Description
4Eh
0 Returns the lower bit of port 4’s ADC voltage result.
D[0]
Returns the higher bits of port 4’s ADC voltage result.
OUT4_PIN_
VOLTAGE_ The sum of these two registers is the OUT4 pin voltage. The port output voltage
4Fh can be calculated with the following equation:
DATA 0000 0000
D[7:0]
Output voltage = 0.15V x (VIN COUNT - OUT4 COUNT)
Where COUNT is the unsigned binary integer of the ADC result.

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INPUT_VOLTAGE (50h and 51h)

Read-only
Bits Bit Name Default Value Description
50h
0 Returns the lower bit of the ADC VIN result.
D[0]
INPUT_ Returns the higher bits of the ADC VIN result.
VOLTAGE_ VIN can be calculated with the following equation:
51h
DATA 0000 0000
D[7:0] VIN = 0.15V x COUNT
Where COUNT is the unsigned binary integer of the ADC result.

JUNCTION_TEMPERATURE (52h and 53h)

Read-only
Bits Bit Name Default Value Description
52h
0 Returns the lower bit of the ADC die temperature result.
D[0]
JUNCTION_
Returns the higher bits of the ADC die temperature result.
TEMP
53h ERATURE_ The junction temperature can be calculated with the following equation:
0000 0000
D[7:0] DATA Junction temperature = 0.4°C x COUNT - 40°C
Where COUNT is the unsigned binary integer of the ADC result.

PMAX_POWER_SETTING (54h and 55h)

Read/write
Bits Bit Name Default Value Description
54h
0 Returns the lower bit of the ADC PMAX setting data result.
D[0]
Returns the higher bits of the ADC PMAX setting data result.
PMAX_
The maximum power load can be calculated with the following equation:
SETTING_
55h Max power load = 0.4W x COUNT
DATA 0000 0000
D[7:0]
Where COUNT is the unsigned binary integer of the ADC result. The PMAX
power result is latched when the MP3924 starts up or is reset. The PMAX power
rating is in a decimal value as a multiple 0.4W.

DIE_ID (60h)
Read-only
Bits Bit Name Default Value Description
D[7:6] FAB 00 Returns the fab location.
D[5:4] MAJOR_REV 00 Returns the major revision.
D[3:2] MINOR_REV 00 Returns the minor revision.
D[1:0] VENDOR_ID 00 Returns the vendor ID.

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APPLICATION INFORMATION
Selecting the Input Capacitor  The gate voltage should be 20V to establish
The supply voltage (VIN) must be between 44V a sufficient margin while GATEx is about
and 57V. The input capacitor (CIN) maintains 10V.
the DC input voltage. The system input The FDMC3612 is recommended for most
capacitor(s) must be rated for 100V, and they applications.
can be aluminum electrolytic capacitors. Place
a 0.1μF decoupling ceramic capacitor close to Selecting the SENSE Resistor for Each Port
VIN and PGND to bypass VIN. The load current in each PSE port is sensed as
the voltage across a current-sense resistor
Selecting the VCC Capacitor
(RSENSE, which is about 250mΩ). For more
The MP3924 integrates the VCC (about 3.3V) accurate current sensing, a Kelvin sense at the
to power the internal control circuit. The internal low end of the current-sense resistor is
regulator requires a minimum 1μF ceramic provided through pins SGND1 for ports 1 and 2,
bypass capacitor to be connected from VCC to and SGND2 for ports 3 and 4 (see Figure 21).
DGND. The VCC current limit is typically 17mA.
Do not connect a heavy external load to VCC, COUT DTVS
Port 1~4
VIN = 54V
as the VCC voltage may drop. This can result in VIN Output

a high VIN to VCC LDO power loss. CIN OUTn

MP3924
Selecting the Output Capacitor for Each Port GATEn QMAIN

An output capacitor must be placed from VIN to SENSEn

OUTx for the MP3924’s output. It is RSENSE
recommended to use a 0.1µF, 100V ceramic SGNDx

capacitor. PGND

Output Transient Voltage Suppression (TVS)

Figure 21: Typical Output Components
The port transient voltage suppression (TVS)
should be rated for the expected port surge Maximum Power Supply Setting
environment. DTVS should have a minimum Connect one resistor from the PMAX pin to
reverse standoff voltage of 58V, as well as a DGND to set the total power capability for all
maximum clamping voltage of 95V at the four output ports. The maximum output power is
expected peak surge current. equal to the PMAX resistor value (in kΩ). For
example, if 120W power is required for all for
Selecting the Output MOSFET for Each Port output, connect a 120kΩ resistor from PMAX to
The port’s MOSFET can be a small, DGND.
inexpensive device with average performance
characteristics as long as it meets the following Selecting the Digital I/O Pull-Up Resistors
conditions: EN
 The voltage rating should be 100V minimum EN is the enable input pin that can turn all
for high-voltage surge environments. internal circuits and ports on and off (except for
the VCC regulator). Connect EN to VCC
 RDS(ON) should be below 150mΩ for power through a 100kΩ resistor to automatically turn
dissipation. on the MP3924.
 The power dissipation for the power AUTO
MOSFET (Q1) when RDS(ON) = 100mΩ at the The AUTO pin sets automatic mode. AUTO is
maximum ICUT is about 85mW. internally pulled up to VCC through a 50kΩ
 The gate charge (QG) when VGATE = 10V resistor (an external 10kΩ resistor can also be
should be below 50nC to satisfy faster added). Float the AUTO pin for automatic
response times under overload conditions. mode. Connect the AUTO pin to DGND for
shutdown mode.

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MID Over-Current Protection (OCP) and Overload

The MID pin sets the midspan mode. MID is Protection (OLP)
internally pulled up to VCC through a 50kΩ Inrush Current Limit
resistor (an external 10kΩ resistor can also be The MP3924 provides a 425mA inrush current
added). Float the MID pin for midspan mode, limit for inrush protection. When the external
and wait 2.8s before reinitiating detection. MOSFET begins to operate, inrush current
Connect MID to DGND to disable midspan protection is enabled. This protection allows the
mode. input capacitance of the PD to charge to the full
A0~A3 VIN on the power interface. It also ensures the
pass FET remains within its safe operating
The A0~A3 pins set the MP3924’s address.
range.
These pins are internally pulled up to VCC
through a 50kΩ resistor (an external 10kΩ If IINRUSCH exceeds ICUT during the inrush, the
resistor can also be added). Connect these pins ICUT timer (tICUT) begins working. If tICUT times
to VCC or DGND to set the lower 4 bits of the out, the output turns off.
address (Address = 010 A3 A2 A1 A0).
ICUT
CLS5 Following the end of start-up, a two current-limit
The CLS5 enables Class 5. CLS5 is internally protection scheme is applied to the ports. The
pulled down to DGND through a 50kΩ resistor. first level is the ICUT current limit, which
Leave CLS5 disconnected to disable the includes an ICUT timer (tICUT). If tICUT times out
classification for Class 5 devices. (This is a because the ICUT current threshold is
high power level with the same classification as exceeded, the port shuts down. The ICUT
IEEE802.3 at. This is not standard class level current limit threshold is configured by the
that is compatible with IEEE802.3). Connect ICUTx bits (see Table 2).
CLS5 to VCC to enable the classification of Table 2: ICUT Threshold
Class 5 devices.
ICUT Register Value ICUT (mA)
SCL and SDAI
000 375
SCL and SDAI are the I2C input pins. They 001 110
must be connected to VCC through an external
010 188
pull-up resistor (typically 4.7kΩ). If the I2C
interface is not used, connect SCL to VCC and 011 375
connect SDAI to DGND. 100 650
SDAO 101 920
110 500
SDAO is open-drain output pin as well as the
I2C serial data output pin. Connect SDAO to 111 625
VCC through an external pull-up resistor In automatic mode, the bits are set to 000 for
(typically 4.7kΩ). Connect SDAO to SDAI for Class 0~3 results, set to 100 for Class 4 result,
non-isolated applications. If the I2C interface is and set to 101 for Class 5 result automatically
not used, connect SDAO to DGND. based on classification result.
INT1 and INT2 ILIM
INT1 and INT2 are open-drain outputs that act The second level of current-limit protection is
as the interrupt request pins for all interrupt the ILIM current limit. The ILIM current limit is a
source events. These pins are set low when the hard limit. The GATE pin regulates the load at
interrupt register is set and the interrupt function the current limit level, and one additional timer
is enabled. Connect these pins to VCC through (tILIM) is enabled to record the current limit event.
an external pull-up resistor (typically 4.7kΩ). If When tILIM completes, the port shuts down. The
the interrupt function is not used, connect these ILIM current limit threshold can be configured
pins to DGND. via the ILIMx threshold register (see Table 3 on
page 52).

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Table 3: ILIM Threshold minimizes the impact of the PCB trace

ILIM Register Value ICUT (mA) resistance.
0 425 2. Kelvin connect the top of R1A–R1D to the
850 for Class 4 SENSE1~4 pins. Kelvin connect the bottom
1 of R1A and R1B to SGND1, then Kelvin
1060 for Class 5
connect R1C and R1D to SGND2.
In automatic mode, the bits are set to 0 for
3. Place the input capacitor (C1B) as close to
Class 0~3 results, or they are set to 1 for Class
the VIN and PGND pins as possible.
4 and Class 5 based on the classification result.
4. Place the VCC capacitor (C3) as close to
Design Example
the VCC and DGND pins as possible.
Table 4 shows a design example following the
application guidelines. 5. Place the PMAX resistor (R2) as close to
the PMAX and DGND pins as possible.
Table 4: Design Example
VIN 44V to 57V 6. Place a sufficient number of GND vias
VOUT 0V to 57V under the MP3924 to provide good thermal
POUT 4 x 0W to 30W dissipation. This also lowers the PCB trace
resistance from the bottom of the current-
Figure 23 on page 53 shows the detailed sense resistor to PGND.
application schematic. The Typical
Performance Characteristics section on page 7. Use a separated DGND and PGND layout.
15 shows the typical performance and circuit Connect DGND and PGND under the
waveforms. For more device applications, refer package, and between the DGND and
to the related evaluation board datasheet(s). PGND pins.
PCB Layout Guidelines GND
Top Layer
Bottom Layer

Efficient PCB layout is critical, as poor layout C1A C1B

R2 C3 U1 Vias

can result in reduced performance, resistive

loss, and system instability. For the best results,
VIN
refer to Figure 22 and follow the guidelines 2 R1D 1 1 R1A 2

2 R1C 1 1 R1B 2
below:
1. Place the current-sense resistor close to the
IC. To optimize accuracy, place the D1D D1C D1B D1A

SENSE1~4 pins and the SGND1~2 pins C2D

Q1D

OUT4 C2C
Q1C

OUT3 2 C2B
Q1B

OUT2 C2A
Q1A

OUT1
close to the current-sense resistor. This
Figure 22: Recommended PCB Layout

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TYPICAL APPLICATION CIRCUIT

VIN C1A C1B

22
220µF 0.1µF Port 1
C2A D1A
Output

VIN
0.1µF SMBJ58A
GND 2
OUT1
PGND PGND
20
VCC GATE1
1 Q1A
C3 FDMC3612
R3
12
1µF EN
100kΩ R1A
32
SENSE1
D1B Port 2
C2B
DGND 0.25Ω SMBJ58A Output
31 0.1µF
OUT2
13
A0
GATE2
30 Q1B
14
A1 FDMC3612
15
A2
R1B
16 29
A3 SENSE2
6 U1 0.25Ω
AUTO
4
SGND1 Port 3
7
MID MP3924 C2C D1C
5 28 PGND 0.1µF SMBJ58A Output
CLS5 OUT3

GATE3
27 Q1C
9 FDMC3612
SCL

R1C
11 26
SDAI SENSE3 Port 4
C2D D1D
0.25Ω
25 0.1µF SMBJ58A Output
OUT4
8
INT1
GATE4
24 Q1D
3 FDMC3612
INT2
R1D
10 23
SDAO SENSE4
0.25Ω
21 18
DGND

PGND

PMAX SGND2

R2 PGND
17

19

120kΩ

DGND PGND

Figure 23: Typical Application Circuit without I2C Control

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 MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER
PACKAGE OUTLINE DRAWING FOR 32L QFN (5X5mm)
PACKAGE INFORMATION MF-PO-D-0052 revision 1.0
QFN-32 (5mmx5mm)

PIN 1 ID PIN 1 ID
MARKING 0.30x45°TYP.

PIN 1 ID
INDEX AREA

TOP VIEW BOTTOM VIEW

SIDE VIEW

0.10x45°
NOTE:

1) ALL DIMENSIONS ARE IN MILLIMETERS.

2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD
FLASH.
3) LEAD COPLANARITY SHALL BE 0.08 MILLIMETERS MAX.
4) DRAWING CONFIRMS TO JEDEC MO-220, VARIATION
WHHE-1.
5) DRAWING IS NOT TO SCALE.

RECOMMENDED LAND PATTERN

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CARRIER INFORMATION

Carrier
Package Quantity/ Quantity/ Reel Carrier Tape
Part Number Tape
Description Reel Tube Diameter Width
Pitch
QFN-32
MP3924GU-Z 5000 N/A 13in 12mm 8mm
(5mmx5mm)

MP3924 Rev. 1.0 MonolithicPower.com 55

7/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2021 MPS. All Rights Reserved.
 MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER

REVISION HISTORY
Revision # Revision Date Description Pages Updated
1.0 07/16/2021 Initial Release -

Notice: The information in this document is subject to change without notice. Users should warrant and guarantee that third-
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.

MP3924 Rev. 1.0 MonolithicPower.com 56

7/16/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2021 MPS. All Rights Reserved.