TSMC Libraries

Advanced Technology Standard Cells

Industry Standard I/Os

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Library Features
Standard cells
z 9 tracks, 600 cells
z Multiple Vt, ECO cells, low power architectures
z All major EDA views

General purpose I/Os

z Latch-up characterized to 200 milliamps
z Pad- and core-limited varieties available
z ESD characterized to 2kV/200V model (HBM/MM)

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 TSMC Library Distribution and Support

z Developed and validated by TSMC

z Distributed by <Distributor>
„ Standard cells
„ General purpose digital I/O’s

z Support provided by <Distributor>

„ Hotline and AE service in the excellent tradition of
<Distributor>
„ Library updates and bug fixes are done by TSMC
„ If customized characterization or library elements are
required, <Distributor> will direct those requests to TSMC

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Why is TSMC Creating Libraries?

z To create a comprehensive choice of industry-leading standard
cell, I/O and memory libraries in the leading process
technologies, complementing internal offerings with 3rd party
partner offerings
z To productize the cells used in wafer process development,
and test them in real-world EDA flows, to provide process-
tuned design architectures that fully utilize TSMC’s silicon
technology
z To set the industry standard for quality with TSMC 9000
compliant products
z To fulfill increasing demand for segment-targeted building
blocks
z To utilize distribution partners with strong, global field
organizations to serve designers throughout the design cycle

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 Who is Using TSMC Libraries?

z I/Os: In production, in hundreds of products

z Standard cells: Rapid customer adoption in
„ communications segment
„ consumer segment
z All geographic regions The advanced
„ Americas
technology
„ Japan
„ Europe
libraries for
„ Asia TSMC design
z All leading processes
„ 0.15 µm
„ 0.13 µm
„ 90 nm

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TSMC Standard Cell

Libraries

The advanced
technology
libraries for
TSMC design
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 TSMC Standard Cell Roadmap
0.13um CL013
Datapath

CL013G
Hvt-Nvt-Lvt

CL013LV (OD) CL013LP

Hvt-Nvt Nvt-Lvt

90nm CLN90LP CLN90G

CLN90G
Hvt-Nvt-Lvt UHvt-Hvt-Nvt Back-bias

CLN90GOD CLN90G
Hvt-Nvt-Lvt Multi-Vdd

CLN90 CLN90G
Datapath ECO Cells

Q3 2003 Q4 2003 2004 Q2 Q3 Q4 2005

Left edge of each box represents first release schedule, when design kits are ready
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Advanced Technology Library Features

z Ready for market

z Power
z Timing
z DFM

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 Advanced Technology Library Features

z Ready for market

Competitive cell density, 9 track architecture
Pre-tested with advanced design flows
Commercial and industry specs available
Tested in silicon

z Power
z Timing
z DFM

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Advanced Technology Library Features

z Ready for market

z Power
Decoupling capacitors available in filler cells
Comprehensive libraries with standard, overdrive and
multi-Vt cells
‹ Overdrive 0.13µm LV
‹ Multi-Vt all 0.13µm, all 90nm
Signal current characterization methodology for
electromigration (EM) and wide wire routing
New in Q4’03 !! Added corners for advanced leakage characterization
(90nm, 0.13µm)

z Timing
z DFM
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 Advanced Technology Library Features

z Ready for market

z Power
z Timing
Most popular timing features
‹ Industry-standard 30-70 slew rate transition
New in Q4’03 !! model
‹ Setup/hold time uses “CLK-to-Q 10% push out”
constraint

z DFM

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Advanced Technology Library Features

z Ready for market

z Power
z Timing
z DFM
Built-in antenna diodes in clock buffer cells
Advanced TSMC-tuned DFM features
„ unidirectional gate poly
„ contact/metal overlap DFM guidelines used

New in Q4’03 !!
Compliant with advanced TSMC “LOD” Spice
model (90nm, Q4’03)
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Multiple Threshold (Multi-Vt) for Both
Power and Performance

z Best of both worlds

„ shorter delay (Low
- Vt)
„ lower power (Std- and Hi- Vt) Unique to TSMC

z Interchangeable footprints:
„ Freely swap cells from Hi- ,Std
- , or Low
- V
t
„ Vertical and horizontal abutment allowed

z Fully tested in TSMC Unique to TSMC

Reference Flow
The advanced
technology libraries
for TSMC design Empowering Innovation
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New for Power Efficiency

The World’s Most Advanced Power Architectures

z Back bias cells

„ Standby mode in addition to normal mode
„ Exponential decrease in leakage
z Multiple Vdd
„ Block
- based Vdd assignment
„ Lower switching current

z Pre-release in Q2’04 Unique to TSMC

The advanced
technology libraries
for TSMC design Empowering Innovation
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 ECO Change for Design Flexibility
Advanced technology for faster time-to-market
z Allows respin of chip with simple Filler Cell

logic patches
„ Logic elements to patch a circuit, in filler
cell footprint
„ 30 different cells available
„ Modify contact, M1 (and above) to patch
the logic for ECO De-cap Cell
„ Decoupling caps may be placed in unused
filler cells

z Pre-release in Q2’04
ECO Cell
The advanced
Unique to TSMC technology libraries
for TSMC design

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Std Cell Design Kit Deliverables

Abbreviation Design Kits Description
rln Release note
syn Synopsys sdb, lib and clf for Apollo/Astro and
Cadence tlf for Silicon Ensemble/SoC Encounter
pc Physical synthesis

vlg Verilog simulation model

vit VHDL/Vital simulation model

mdt Mentor DFT advisor and Fastscan model

apf/apt Apollo frame view, cell view, timing view and power view
sef Silicon Ensemble lef and technology files

cdb Celtic SI
New in Q4’03 !! pgv Voltage Storm Cadence DSM views
ecsm Signal Strom

gds GDSII layout views

spi LVS netlist in CDL format
lpe LPE Layout parasitic Extraction

doc Datasheets and application notes

Notes: 1. Zero timing Verilog model for back-annotation

2. 7x7 Look-Up Table for Synopsys model
3. Composer symbol view design kits available upon request

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 Standard Cell Categories
Drive
Cell Family 0.15um 0.13um 90nm
Strength

(AND/NAND) / (OR/NOR) / (XOR/XNOR) 3 each 3 each 3 each 5 / 6 / 4 each

BUFFER / 3-STATE BUFFER: w/ & w/o enable/inverter 1 each 1 each 1 each 11 each

AOI / OAI / AO / OA / MAO / MOAI 12 each 39 39 4 each

ADDER: half/full adder 1 each 3 3 3/2 each

MUX: w & w/o inverted output 3 each 6 6 4 each

CLK BUFFER / Inverted CLK BUFFER / Gated CLK LATCH 1 each 1 each 1 each 11 / 11 / 10 each

DFF: pos-edge, neg-edge, async/sync R/S, w/o R/S 15 15 15 3 each

ENABLE DFF; async/sync R, w/o R flip-flop 6 6 6 3 each

SCAN DFF: all version of scan flip-flop 21 23 23 3 each

LATCH: active high/low enable, async R/S 8 8 8 3 each

INV/NAND/AND/MUX/XOR (balanced rise/fall) 1 each 5 5 4 each

DELAY/TIE-HIGH/TIE-LOW cell 1 each 4 4 4 / 1 / 1 (7/1/1)

ANTENNA/DECOUPLING cell 2, 7 7 7 N/A

Total Cell Number 514 600* 600*

New in Q4’03 !! *90nm and 0.13um libraries include over 30 datapath cells
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TSMC Std Cell Library Comparison

Raw Gate Internal
TECHNOLOGY Leakage Speed
PRODUCT NAME Density Power Voltage
(PROCESS) (nW) (ns)
(Kgates/mm 2) (nW/MHz)
TCBN90G 4.11 2.25 0.031
TCBN90GHVT 2.2 2.1 0.041 1.0V
TCBN90GLVT 61.8 2.75 0.028
CLN90G
TCBN90GOD 7.62 3.85 0.026
NEW 413
TCBN90GODHVT 4.84 3.2 0.0327
TCBN90GODLVT NEW 114.9 5.15 0.0237
1.2V
TCBN90LP 0.13 2.45 0.04
CLN90LP TCBN90LPHVT NEW 0.02 2.4 0.05
TCBN90LPUHVT NEW 0.01 2.55 0.07
TCB013GHP 0.76 5.5 0.052
CL013G TCB013GHPHVT 0.2 5.3 0.067 1.2V
TCB013GHPLVT 8.16 6.3 0.04
TCB013LVHP 7.19 3.7 0.04
1.0V
TCB013LVHPHVT 196 1.19 3.3 0.044
CL013LV
TCB013LVHPOD 12.5 6.2 0.0329
1.2V
TCB013LVHPODHVT NEW 2.42 5.05 0.0351
TCB013LPHP 0.008 8.5 0.067
CL013LP 1.5V
TCB013LPHPLVT 0.171 7.4 0.042
CL015G TCB015G 0.058 9.8 0.055 1.5V
131
CL015LV TCB015LV 0.51 6.1 0.05 1.2V

* All libraries use 9-track height cells; raw gates use ND2D1 area as 1 gate
NEW Added in 2H03
* OD, HVT and LVT: Over Drive, High Vt and Low Vt nodes
* Leakage/Power/Performance data are based on 2-input NAND gate (ND2D1)
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 New for 0.15 µm

z 8 track architecture
New in Q4’03 !!

z High density
z Tuned for consumer applications
z Q4’03

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Standard Cell Timing Characterization

Conditions
Conditions
Type
Voltage Temperature Process

Low Temperature
VDD + 10% -40o C Fast-Fast
(LTCOM)

Best Case
VDD + 10% 0o C Fast-Fast
(BCCOM)

Typical Case
VDD 25o C Typical-Typical
(NCCOM)

Worst Case
VDD - 10% 125o C Slow-Slow
(WCCOM)

Some processes such as Overdrive have different conditions; check with TSMC

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 TSMC Standard Cell Characterization
Sets the industry standard

z Extensive Characterization:
„ Input pin capacitance
„ Propagation Delay, Transition Time
„ Setup/Hold Time
„ Recovery/Removal Time/Minimum Pulse Width
„ Leakage, Internal Power
z High Accuracy:
„ 7 X 7 Lookup Table for timing & power calculation
z Advanced Power Parameters:
„ Pin-to-Pin Power Table supported
„ State-dependent delay, internal power (selected cells)
„ Input pin state-dependent leakage
Unique to TSMC
„ Cell output Irms characterized for EM at 500MHz

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Widespread Adoption, Working Silicon

„ Customer #1: network
Taped out MPW in February 2003, silicon functional
z 90 nm „ Customer #2: programmable logic
Taped out MPW in June 2003, silicon functional
„ Customer #3: major IDM
Multiple tape-outs planned

„ Customer #1: handset

Taped out 0.13G multi-Vt in April 2003, silicon functional
z 0.13 µm „ Customer #2: wireless
Taped out 0.13G multi-Vt in July 2003 , silicon functional
„ Customer #3: computer
Will tape out 0.13LV-OD in Q4/2003
„ Customer #4: storage
Will tape out 0.13G in Q4/2003

„ Customer #1: communication

In pilot production now (0.15G)
z 0.15 µm „ Customer #2: consumer
Will tape out in Q4/2003 (0.15G)
„ Customer #3: consumer
Will tape out in Q4/2003 (0.15LV)

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 Standard Cell Library
TSMC 9000 Validation Status
z Level 1
Level 1 All cells reviewed
0.15 µm All Design kit complete
0.13 µm All
90 nm All Level 3 Test chip validation
Silicon report available

z Level 3 Level 5 Production

0.13 µm All
0.15 µm All

z Level 5

0.15 µm G New in Q4’03 !!

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N90 Success Story – Processor Core

z Design specification: Silicon Status: In progress

Process: TSMC 90nm logic 1P6M Low-K
Gate count: 1M gates
Memory: 140KB (20 memory instances)
Chip size: 3x3 mm square
Target Frequency: 350+MHz

z Library & Flow:

TSMC 90um multi-Vt Std. Cell library
TSMC digital I/O cells
Multi-Vt power/performance optimization
TSMC Reference Flow 4.0
Hierarchical partition and physical P&R implementation

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 CL013 Success Story – Cellular Phone
Chip
z Design specification: First time silicon success!
Process: TSMC 0.13 µm 1.2V/3.3V 1P6M FSG
Gate count: 1.44M gates
Memory: 485KB
Chip size: 9x9 mm square
Frequency Target: 122.5MHz
Package: 504 pins BGA

z Library & Flow:

TSMC 0.13 µm multi-Vt Std. cell library
TSMC digital & analog I/O cells
Multi-Vt script design methodology
Precise leakage cell modeling for leakage
and speed trade-off
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Summary
z Advanced DFM features
z Advanced power features
z Advanced ECO flexibility
z Most extensive characterization
z Flow proven and silicon validated
z Rapid market adoption

The advanced
technology
libraries for
TSMC design
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 TSMC Standard I/O
Libraries

The most widely

used I/O libraries
for TSMC design

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TSMC Std I/O Portfolio Summary

Technology Process Voltage Name
1.0/2.5V TPDN90G2
CLN90G
1.0/3.3V TPDN90G3
90 nm
1.2/2.5V TPDN90LPN2 NEW
CLN90LP
1.2/3.3V TPDN90LPN3 NEW

1.2V/3.3V, 5V tol TPZ013G3

CL013G
1.2V/2.5V, 3.3V tol TPZ013G2
1.0V/3.3V, 5V tol TPZ013LG3
CL013LV
0.13µm 1.0V/2.5V, 3.3V tol TPZ013LG2
1.0V/3.3V, 5V tol TPZ013LODG3 NEW
CL013LVOD
1.0V/2.5V, 3.3V tol TPZ013LODG2 NEW

CL013LP 1.5V/3.3V TPD013LPN3

CL015G 1.5V/3.3V, 5V tol TPZ015G
0.15µm
CL015LV 1.2V/3.3V, 5V tol TPZ015LG

* tol = tolerant
NEW Added in 2H03

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 CL013 I/O Library Features
z Process: 0.13 µm logic salicide, from 4 to 8 metals
z Voltage combinations

* tol = tolerant

z Cells: z Bonding type: staggered or linear

„ 123 I/O cells z Body cell width/height:
„ 2 corner cells 35µm x 246µm (tpz013g2/g3/lg2)
„ 6 bond pads 35µm x 276µm (tpz013lg3)
„ 7 filler pads 60µm x 150µm (tpd013lpn3)

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CLN90 I/O Library Features

z Process: 90 nm logic salicide, from 5 to 9 metal layers
z Voltage combinations

z Cells: z Bonding type: linear

„ 18 I/O cells, z Body cell width/height:
programmable to over
35µm x 210µm
75 configurations
„ 1 corner cell
„ 6 bond pads
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 CL015 I/O Library Features
z Process: 0.15 µm logic salicide, from 4 to 7 metals
z Voltage combinations

* tol = tolerant

z Cells: z Bonding type: staggered

„ 123 I/O cells
z Body cell width/height:
„ 1 corner cell
40µm x 230µm (tpz015lg/g)
„ 2 bond pads
„ 7 filler pads

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I/O Library
TSMC 9000 Validation Status
z Level 1

0.15 µm All Level 1 All cells reviewed

0.13 µm All Design kit complete
90 nm All
Level 3 Test chip validation
Silicon report available
z Level 3
Level 5 Production
0.13 µm G

z Level 5

0.13 µm Formal status underway

Production of 2.5V + 3.3V :
over 20,000 wafers!
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 Summary
z Available for production in TSMC
processes
z Used in hundreds of products, tens of
thousands of wafers
z Packaged by all leading backend houses

The most widely

used I/O libraries
for TSMC design

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