UNIT – III: I/O and Memory Interface: LCD, Keyboard, External Memory RAM, ROM Interface,

ADC, DAC Interface to 8051. Serial Communication and Bus Interface: Serial Communication
Standards, Serial Data Transfer Scheme, On board Communication Interfaces-I2C Bus, SPI Bus,
UART; External Communication Interfaces-RS232, USB.
LCD INTERFACING
LCD Operation:

LCD is finding widespread use replacing LEDs

 The declining prices of LCD
 The ability to display numbers, characters, and graphics
 Incorporation of a refreshing controller into the LCD, thereby relieving the CPU of the task of
refreshing the LCD
 Ease of programming for characters and graphics
LCD INTERFACING LCD Pin Descriptions
Pin Descriptions for LCD
Pin Symbol I/O Descriptions
1 VSS -- Ground
2 VCC -- +5V power supply
3 VEE -- Power supply to control contrast
4 RS I RS=0 to select command register,
RS=1 to select data register
5 R/W I R/W=0 for write,
R/W=1 for read
6 E I/O Enable
7 DB0 I/O The 8-bit data bus
8 DB1 I/O The 8-bit data bus
9 DB2 I/O The 8-bit data bus
10 DB3 I/O The 8-bit data bus
11 DB4 I/O The 8-bit data bus
12 DB5 I/O The 8-bit data bus
13 DB6 I/O The 8-bit data bus
14 DB7 I/O The 8-bit data bus

E – Enable is used by the LCD to latch information presented to its data bus.
Pin no. 7 – 14 are the 8-bit data bus, which sends displayed information or instruction command codes
to the LCD - Read the contents of the LCD’s internal registers.

1
LCD Command Codes
Code Command to LCD Instruction Register Code Command to LCD Instruction
(Hex) (Hex) Register
1 Clear display screen F Display on, cursor blinking
2 Return home 10 Shift cursor position to left
4 Decrement cursor (shift cursor to left) 14 Shift cursor position to right
6 Increment cursor (shift cursor to right) 18 Shift the entire display to the left
5 Shift display right 1C Shift the entire display to the right
7 Shift display left 80 Force cursor to beginning to 1st line
8 Display off, cursor off C0 Force cursor to beginning to 2nd line
A Display off, cursor on 38 2 lines and 5x7 matrix
C Display on, cursor off
E Display on, cursor blinking

Sending Data/Commands to LCDs with/Time Delay:

2
To send any of the commands to the LCD, make pin RS=0. For data, make RS=1. Then send a high-
to-low pulse to the E pin to enable the internal latch of the LCD. This is shown in the code below.
;calls a time delay before sending next data/command
;P1.0-P1.7 are connected to LCD data pins D0-D7
;P2.0 is connected to RS pin of LCD
;P2.1 is connected to R/W pin of LCD
;P2.2 is connected to E pin of LCD

ORG 0H
MOV A,#38H ;INIT. LCD 2 LINES, 5X7 MATRIX
ACALL COMNWRT ;call command subroutine
ACALL DELAY ;give LCD some time
MOV A,#0EH ;display on, cursor on
ACALL COMNWRT ;call command subroutine
ACALL DELAY ;give LCD some time
MOV A,#01 ;clear LCD
ACALL COMNWRT ;call command subroutine
ACALL DELAY ;give LCD some time
MOV A,#06H ;shift cursor right
ACALL COMNWRT ;call command subroutine
ACALL DELAY ;give LCD some time
MOV A,#84H ;cursor at line 1, pos. 4
ACALL COMNWRT ;call command subroutine
ACALL DELAY ;give LCD some time
MOV A,#’N’ ;display letter N
ACALL DATAWRT ;call display subroutine
ACALL DELAY ;give LCD some time
MOV A,#’O’ ;display letter O
ACALL DATAWRT ;call display subroutine
AGAIN: SJMP AGAIN ;stay here
COMNWRT: ;send command to LCD
MOV P1,A ;copy reg A to port 1
CLR P2.0 ;RS=0 for command
CLR P2.1 ;R/W=0 for write
SETB P2.2 ;E=1 for high pulse
ACALL DELAY ;give LCD some time
CLR P2.2 ;E=0 for H-to-L pulse
RET
DATAWRT: ;write data to LCD
MOV P1,A ;copy reg A to port 1
SETB P2.0 ;RS=1 for data
CLR P2.1 ;R/W=0 for write
SETB P2.2 ;E=1 for high pulse
ACALL DELAY ;give LCD some time
CLR P2.2 ;E=0 for H-to-L pulse
RET
DELAY: MOV R3,#50 ;50 or higher for fast CPUs

3
HERE2: MOV R4,#255 ;R4 = 255
HERE: DJNZ R4,HERE ;stay until R4 becomes 0
DJNZ R3,HERE2
RET
END
LCD Timing for Read

Read requires an L-to-H pulse for the E pin

LCD Timing for Write

4
KEYBOARD INTERFACING

 Keyboards are organized in a matrix of rows and columns

 The CPU accesses both rows and columns through ports
 Therefore, with two 8-bit ports, an 8 x 8 matrix of keys can be
connected to a microprocessor
 When a key is pressed, a row and a column make a contact
 Otherwise, there is no connection between rows and columns
 In IBM PC keyboards, a single microcontroller takes care of
hardware and software interfacing
 A 4x4 matrix connected to two ports

 The rows are connected to an output port and the columns are
connected to an input port
 It is the function of the microcontroller to scan the keyboard
continuously to detect and identify the key pressed
 To detect a pressed key, the microcontroller grounds all rows by
providing 0 to the output latch, then it reads the columns
 If the data read from columns is D3 – D0 = 1111, no key has been
pressed and the process continues till key press is detected
 If one of the column bits has a zero, this means that a key press
has occurred
 For example, if D3 – D0 = 1101, this means that a key in the D1
column has been pressed
 After detecting a key press, microcontroller will go through the
process of identifying the key

5
  Starting with the top row, the microcontroller grounds it by
providing a low to row D0 only
 It reads the columns, if the data read is all 1s, no key in that
row is activated and the process is moved to the next row
 It grounds the next row, reads the columns, and checks for any
zero
 This process continues until the row is identified
 After identification of the row in which the key has been pressed
 Find out which column the pressed key belongs to
Program for detection and identification of key activation goes
through the following stages:
1. To make sure that the preceding key has been released, 0s are
output to all rows at once, and the columns are read and checked
repeatedly until all the columns are high.
 When all columns are found to be high, the program waits for a
short amount of time before it goes to the next stage of waiting
for a key to be pressed.
2. To see if any key is pressed, the columns are scanned over and
over in an infinite loop until one of them has a 0 on it.
 Remember that the output latches connected to rows still have
their initial zeros (provided in stage 1), making them grounded.
 After the key press detection, it waits 20 ms for the bounce and
then scans the columns again.
(a) it ensures that the first key press detection was not an
erroneous one due a spike noise.
(b) the key press. If after the 20-ms delay the key is still pressed,
it goes back into the loop to detect a real key press.
3. To detect which row key press belongs to, it grounds one row at
a time, reading the columns each time.
 If it finds that all columns are high, this means that the key
press cannot belong to that row.
 Therefore, it grounds the next row and continues until it finds
the row the key press belongs to
 Upon finding the row that the key press belongs to, it sets up
the starting address for the look-up table holding the scan codes
(or ASCII) for that row.
4. To identify the key press, it rotates the column bits, one bit
at a time, into the carry flag and checks to see if it is low.
 Upon finding the zero, it pulls out the ASCII code for that key
from the look-up table.
 Otherwise, it increments the pointer to point to the next element
of the look-up table.

6
7
Keyboard Program
;keyboard subroutine. This program sends the ASCII
;code for pressed key to P0.1
;P1.0-P1.3 connected to rows, P2.0-P2.3 to column

MOV P2,#0FFH ;make P2 an input port

K1: MOV P1,#0 ;ground all rows at once
MOV A,P2 ;read all col
;(ensure keys open)
ANL A,00001111B ;masked unused bits
CJNE A,#00001111B,K1 ;till all keys release
K2: ACALL DELAY ;call 20 msec delay
MOV A,P2 ;see if any key is pressed
ANL A,00001111B ;mask unused bits
CJNE A,#00001111B,OVER ;key pressed, find row
SJMP K2 ;check till key pressed
OVER: ACALL DELAY ;wait 20 msec debounce time
MOV A,P2 ;check key closure
ANL A,00001111B ;mask unused bits
CJNE A,#00001111B,OVER1 ;key pressed, find row
SJMP K2 ;if none, keep polling
OVER1: MOV P1, #11111110B ;ground row 0
MOV A,P2 ;read all columns
ANL A,#00001111B ;mask unused bits
CJNE A,#00001111B,ROW_0 ;key row 0, find col.
MOV P1,#11111101B ;ground row 1
MOV A,P2 ;read all columns
ANL A,#00001111B ;mask unused bits
CJNE A,#00001111B,ROW_1 ;key row 1, find col.
MOV P1,#11111011B ;ground row 2
MOV A,P2 ;read all columns
ANL A,#00001111B ;mask unused bits
CJNE A,#00001111B,ROW_2 ;key row 2, find col.
MOV P1,#11110111B ;ground row 3
MOV A,P2 ;read all columns
ANL A,#00001111B ;mask unused bits
CJNE A,#00001111B,ROW_3 ;key row 3, find col.
LJMP K2 ;if none, false input,
;repeat
ROW_0: MOV DPTR,#KCODE0 ;set DPTR=start of row 0
SJMP FIND ;find col.Key belongs to
ROW_1: MOV DPTR,#KCODE1 ;set DPTR=start of row
SJMP FIND ;find col. Key belongs to

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ROW_2: MOV DPTR,#KCODE2 ;set DPTR=start of row 2
SJMP FIND ;find col. Key belongs to
ROW_3: MOV DPTR,#KCODE3 ;set DPTR=start of row 3
FIND: RRC A ;see if any CY bit low
JNC MATCH ;if zero, get ASCII code
INC DPTR ;point to next col. addr
SJMP FIND ;keep searching
MATCH: CLR A ;set A=0 (match is found)
MOVC A,@A+DPTR ;get ASCII from table
MOV P0,A ;display pressed key
LJMP K1
;ASCII LOOK-UP TABLE FOR EACH ROW
ORG 300H
KCODE0: DB ‘0’,’1’,’2’,’3’ ;ROW 0
KCODE1: DB ‘4’,’5’,’6’,’7’ ;ROW 1
KCODE2: DB ‘8’,’9’,’A’,’B’ ;ROW 2
KCODE3: DB ‘C’,’D’,’E’,’F’ ;ROW 3
END

8051 connection to DAC 0808:

The digital inputs are converted to current I out and by connecting a

resistor to the Iout pin. The total current I out is a function of the
binary numbers at the D0-D7 inputs of the DAC 0808. The reference
current can be found out as follows.

9
Usually reference current is 2mA. Ideally the output pin is connected
to a resistor for converting the current into voltage, which can be
monitored with an oscilloscope. But this can cause inaccuracy; hence
an opamp is used to convert the current into voltage. The 8051-
connection diagram to DAC0808 is shown in the figure above.
Example: Write an ALP to generate a triangular waveform.

MOV A, #00H
INCR: MOV P1,A
INC A
CJNE A, #255, INCR
DECR: MOV P1, A
DEC A
CJNE A, #00, DECR
SJMP INCR
END

ADC INTERFACING

ADC are among the most widely used devices for data acquisition. The
digital computers use binary (discrete) values, but in the physical
world everything is analog(continuous). Temperature, pressure,
humidity, and velocities are few examples of physical quantities that
we deal with every day.

ADC interfaced with 8051 microcontroller

10
ADC Details: ADC808/809 chip has 8 analog channels, which can monitor
8 different transducers. The ADC804 has only one analog input; Vin(+).
The ALE is the address latch enable which is used to latch the address.
The start of conversion pin needs to be activated for start of
conversion process. The output enable needs to be enabled for the
output to be made available. The end of conversion (EOC) is to stop
the conversion process.
Steps for data conversion using 0804 Chip:
1. Make the CS=0 and send low to high pulse to pin WR to start the
conversion process.
2. Keep monitoring the INTR pin, if it is low, then the conversion
is completed and then go to the next step, else keep polling the
INTR until it becomes low.
3. If INTR is low, make CS=0 and send a high to low pulse to RD pin
to get the data out of the ADC0804.

Assembly Language Program for Analog to Digital Conversion

ADC_IO:
MOV P1, #0XFF ; To configure as input
AGAIN
AGAIN: CLR P3.7 ; Chip Select
SETB P3.6 ; RD=1
CLR P3.5 ; WR=0
SETB P3.5 ; WR=1 – LOW TO HIGH TRANSITION
WAIT: JB P3.4, WAIT ; Wait for INTR
CLR P3.7 ; Generates CS for ADC
CLR P3.6 ; RD=0, High to Low Transition
MOV A, P1 ; Read digital Output
SJMP AGAIN

For External Memory RAM, ROM Interface refer Unit - 2

11
BASICS OF SERIAL COMMUNICATION:
Computers transfer data in two ways:
Parallel: Often 8 or more lines (wire conductors) are used to transfer data to a device that is only
a few feet away.
Serial: To transfer to a device located many meters away, the serial method is used. The data is
sent one bit at a time.

 At the transmitting end, the byte of data must be converted to serial bits using parallel-in-
serial-out shift register.
 At the receiving end, there is a serial- in-parallel-out shift register to receive the serial
data and pack them into byte.
 When the distance is short, the digital signal can be transferred as it is on a simple wire
and requires no modulation.
 If data is to be transferred on the telephone line, it must be converted from 0s and 1s to
audio tones.
 This conversion is performed by a device called a modem, “Modulator/demodulator”.

Serial data communication uses two methods;

 Synchronous method transfers a block of data at a time.
 Asynchronous method transfers a single byte at a time.
It is possible to write software to use either of these methods, but the programs can be tedious and
long. There are special IC chips made by many manufacturers for serial communications. UART
(universal asynchronous Receiver- transmitter). USART (universal synchronous-asynchronous
Receiver-transmitter).
 If data can be transmitted and received, it is a duplex transmission.
 If data transmitted one way a time, it is referred to as half duplex.
 If data can go both ways at a time, it is full duplex.
 This is contrast to simplex transmission, in which communication takes place only in one
direction.
A protocol is a set of rules agreed by both the sender and receiver on;
 How the data is packed.
 How many bits constitute a character?
 When the data begins and ends.
Asynchronous serial data communication is widely used for character-oriented transmissions
 Each character is placed in between start and stop bits, this is called framing
 Block-oriented data transfers use the synchronous method
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The start bit is always one bit, but the stop bit can be one or two bits. The start bit is always a 0
(low) and the stop bit(s) is 1 (high).

Due to the extended ASCII characters, 8-bit ASCII data is common. In older systems, ASCII
characters were 7- bit. In modern PCs the use of one stop bit is standard. In older systems, due to
the slowness of the receiving mechanical device, two stop bits were used to give the device
sufficient time to organize itself before transmission of the next byte. Assuming that we are
transferring a text file of ASCII characters using 1 stop bit, we have a total of 10 bits for each
character.
 This gives 25% overhead, i.e. each 8-bit character with an extra 2 bits.
 In some systems in order to maintain data integrity, the parity bit of the character byte is
included in the data frame.
 UART chips allow programming of the parity bit for odd-, even-, and no-parity options.
The rate of data transfer in serial data communication is stated in bps (bits per second). Another
widely used terminology for bps is baud rate. It is modem terminology and is defined as the number
of signal changes per second. In modems, there are occasions when a single change of signal
13
transfers several bits of data. As far as the conductor wire is concerned, the baud rate and bps are
the same, and can be used interchangeably. The data transfer rate of given computer system
depends on communication ports incorporated into that system. IBM PC/XT could transfer data at
the rate of 100 to 9600 bps. Pentium-based PCs transfer data at rates as high as 56K bps. In
asynchronous serial data communication, the baud rate is limited to 100K bps.

Serial data standards:

The first of the RS standards was RS232, or more correctly RS-232. This was developed in 1962
when the need for forms of transmitting data from modems attached telephone lines to remote
communications equipments became apparent.

The 'RS' stands for Recommended Standard, although later these standards were formally adopted
by the EIA / TIA in the USA.

The EIA is the Electrical Industries Association and the TIA is the Telecommunications Industries
Association. Once RS-232 was established an equivalent standard was written for the ITU
(International Telecommunications Union) to provide a more international standard. This would
enable the same standards to be used worldwide and also give manufacturers access to a global
market using just one product. This standard was known as V.24 and is totally compatible with
RS-232.

With RS232 well established and the need for faster communications and over longer distances,
further standards beyond RS232 were introduced. Although a number of standards were
introduced, the most widely used are RS-422 and RS485.

The standard was set long before the advent of the TTL logic family, its input and output voltage
levels are not TTL compatible. In RS232, a 1 is represented by -3 ~ -25 V, while a 0 bit is +3 ~
+25 V, making -3 to +3 is undefined.

RS232 DB-25 Pins

Pin Description Pin Description

1 Protective ground 14 Secondary transmitted data
2 Transmitted data (TxD) 15 Transmitted signal element timing
3 Received data (RxD) 16 Secondary receive data
4 Request to send (-RTS) 17 Receive signal element timing
5 Clear to send (-CTS) 18 Unassigned
6 Data set ready (-DSR) 19 Secondary receive data
7 Signal ground (GND) 20 Data terminal ready (-DTR)
8 Data carrier detect (-DCD) 21 Signal quality detector
9/10 Reserved for data testing 22 Ring indicator (RI)
11 Unassigned 23 Data signal rate select
12 Secondary data carrier detect 24 Transmit signal element timing
13 Secondary clear to send 25 Unassigned
14
RS232 Connector DB-25

Since not all pins are used in PC cables, IBM introduced the DB-9 version of the serial I/O
standard.
RS232 DB-9 Pins:

Pin Description
1 Data carrier detect (-DCD)
2 Received data (RxD)
3 Transmitted data (TxD)
4 Data terminal ready (DTR)
5 Signal ground (GND)
6 Data set ready (-DSR)
7 Request to send (-RTS)
8 Clear to send (-CTS)
9 Ring indicator (RI)

Current terminology classifies data communication equipment as:

 DTE (data terminal equipment) refers to terminal and computers that send and receive data.
 DCE (data communication equipment) refers to communication equipment, such as
modems.
 The simplest connection between a PC and microcontroller requires a minimum of three
pins, TxD, RxD, and ground.

15
DTR (data terminal ready): When terminal is turned on, it sends out signal DTR to indicate that
it is ready for communication.
DTR (data terminal ready): When terminal is turned on, it sends out signal DTR to indicate that
it is ready for communication.
DSR (data set ready): When DCE is turned on and has gone through the self-test, it asserts DSR
to indicate that it is ready to communicate.
RTS (request to send): When the DTE device has byte to transmit, it asserts RTS to signal the
modem that it has a byte of data to transmit.
CTS (clear to send): When the modem has room for storing the data it is to receive, it sends out
signal CTS to DTE to indicate that it can receive the data now.
DCD (data carrier detect): The modem asserts signal DCD to inform the DTE that a valid carrier
has been detected and that contact between it and the other modem is established.
RI (ring indicator): An output from the modem and an input to a PC indicates that the telephone
is ringing. It goes on and off in synchronous with the ringing sound.
A line driver such as the MAX232 chip is required to convert RS232 voltage levels to TTL
levels, and vice versa. 8051 has two pins that are used specifically for transferring and receiving
data serially. These two pins are called TxD and RxD and are part of the port 3 group (P3.0 and
P3.1). These pins are TTL compatible; therefore, they require a line driver to make them RS232
compatible.
We need a line driver (voltage converter) to convert the R232’s signals to TTL voltage
levels that will be acceptable to 8051’s TxD and RxD pins.

8051 CONNECTION TO RS232

16
PC Baud Rates:

110
150
300
600
1200
2400
4800
9600
19200

Baud rates supported by 486/Pentium IBM PC BIOS

17
Communication Interface

Communication interface is essential for communicating with various subsystems of the

embedded system and with the external world. For an embedded product, the
communication interface can be viewed in two different perspectives; namely; Device/board
level communication interface (Onboard Communication Interface) and Product level
communication interface (External Communication Interface). Embedded product is a
combination of different types of components (chips/devices) arranged on a printed circuit
board (PCB) The communication channel which interconnects the various components
within an embedded product is referred as device/board level communication interface
(onboard communication interface). Serial interfaces like I2C, SPI. UART, 1-Wire, etc. and
parallel bus interface are examples of' ‘Onboard Communication Interface’.

Some embedded systems arc self-contained units and they don't require any interaction
and data transfer with other sub-systems or external world. On the other hand, certain
embedded systems may be a part of a large distributed system and they require interaction
and data transfer between various devices and sub-modules. The ‘Product level
communication interface’ (External Communication Interface) is responsible for data
transfer between the embedded system and other devices or modules. The external
communication interface can be either a wired media or a wireless media and it can be a
serial or a parallel interface. Infrared (IR), Bluetooth (BT), Wireless LAN (Wi-Fi), Radio
Frequency waves (RF), GPRS/3G/4GLTE, etc. are examples for wireless communication
interface. RS-232C/RS-422/RS-485, USB, Ethernet, IEEE 1394 port. Parallel port, CF-II
interface. SDIO. PCMCIA/PCIex, etc. are examples for wired interfaces. It is not mandatory
that an embedded system should contain an external communication interface. Mobile
communication equipment is an example for embedded system with external
communication interface.

Onboard Communication Interfaces

Onboard Communication Interface refers to the different communication channels/buses

for interconnecting the various integrated circuits and other peripherals within the embedded
system. The following section gives an overview of the various interfaces for onboard
communication.
Inter Integrated Circuit (12C) Bus: The Inter Integrated Circuit Bus (I2C-Pronounced ‘I
square C’) is a synchronous bi-directional half duplex (one-directional communication at a
given point of time) two wire serial interface bus. The concept of I2C bus was developed by
‘Philips semiconductors’ in the early 1980s. The original intention of I2C was to provide an
easy way of connection between a microprocessor/microcontroller system and the peripheral
chips in television sets. The I2C bus comprise of two bus lines, namely; Serial Clock-SCL
and Serial Data-SDA. SCL line is responsible for generating synchronization clock, pulses
and SDA is responsible for transmitting the serial data across devices. I2C bus is a shared
bus system to which many number of I2C devices can be connected. Devices connected to
the I2C bus can act as either ‘Master’ device or ‘Slave’ device. The ‘Master’ device is
responsible for controlling the communication by initiating/terminating data transfer,
sending data and generating necessary synchronization clock pulses ‘Slave’ devices wait for
the commands from the master and respond upon receiving the commands. ‘Master’ and
‘Slave’ devices can act as either transmitter or receiver. Regardless whether a master is
acting as transmitter or receiver, the synchronization clock signal is generated by the
‘Master’ device only. I2C supports multi masters on the same bus. The bus interface diagram
shown in figure below illustrates the connection of master and slave devices on the I2C bus.

18
 Figure: I2C Bus Interfacing

The I2C bus interface is built around an input buffer and an open drain or collector
transistor. When the bus is in the idle state, the open drain/collector transistor will be in
the floating state and the output lines (SDA and SCL) switch to the 'High Impedance' state.
For proper operation of the bus. both the bus lines should be pulled to the supply voltage
(+5V for TTL family and +3.3V for CMOS family devices) using pull-up resistors. The
typical value of resistors used in pull-up is 2.2K. With pull-up resistors, the output lines
of the bus in the idle state will be ‘HIGH’.
The address of a I2C device is assigned by hardwiring the address lines of the device to
the desired logic level. The address to various I2C devices in an embedded device is
assigned and hardwired at the time of designing the embedded hardware. The sequence
of operations for communicating with an I2C slave device is listed below:
1. The master device pulls the clock line (SCL) of the bus to 'HIGH'
2. The master device pulls the data line (SDA) ‘LOW’, when the SCL line is at logic
‘HIGH’ (This is the ‘Start’ condition for data transfer)
3. The master device sends the address (7 bit or 10 bit wide) of the ‘slave’ device to
which it wants to communicate, over the SDA line. Clock pulses arc generated at the
SCL line for synchronizing the bit reception by the slave device. The MSB of the data
is always transmitted first. The data in the bus is valid during the ‘HIGH’ period of
the clock signal
4. The master device sends the Read or Write bit (Bit value = 1 Read operation; Bit
value 0 Write operation) according to the requirement
5. The master device waits for the acknowledgement bit from the slave device whose
address is sent on the bus along with the Read/Write operation command. Slave
devices connected to the bus compares the address received with the address assigned
to them
6. The slave device with the address requested by the master device responds by sending
an acknowledge bit (Bit value = 1) over the SDA line
7. Upon receiving the acknowledge bit. the Master device sends the 8bit data to the slave
device over SDA line, if the requested operation is ‘Write to device’. If the requested
operation is ‘Read from device’, the slave device sends data to the master over the
SDA line
8. The master device waits for the acknowledgement bit from the device upon byte
transfer complete for a write operation and sends an acknowledge hit to the Slave
device for a read operation
9. The master device terminates the transfer by pulling the SDA line ‘HIGH’ when the
19
 clock line SCL is at logic ‘HIGH’ (Indicating the ’STOP' condition)
10. I2Cbus supports three different data rates. They are: Standard mode (Sm - Data rate
up to 100kbps), Fast mode (Fm - Data rate up to 400kbps sec), Fast mode Plus (Fm+
- Data rate up to 1Mbit/sec) and High speed mode (Hs-mode - Data rate up to
3.4Mbits/sec and an Ultra-Fast-mode (UFM), with a bit rate up to 5 Mbps)

Serial Peripheral Interface (SPI) Bus: The Serial Peripheral Interface Bus (SPI) is a
synchronous bi-directional full duplex four-wire serial interface bus. The concept of SPI
was introduced by Motorola. SPI is a single master multi-slave system. It is possible to
have a system where more than one SPI device can be master, provided the condition
only one master device is active at any given point of time, is satisfied. SPI requires four
signal lines for communication. They are:

Master Out Slave In (MOSI): Signal line carrying the data from master to slave
device. It is also known as Slave Input/Slave Data
In (SI/SDI)

Master In Slave Out (MISO): Signal line carrying the data from slave to master
device. It is also known as Slave Output
(SO/SDO)

Serial Clock (SCLK): Signal line carrying the clock signals

Slave Select (SS): Signal line for slave device select. It is an active
low signal

The bus interface diagram shown in figure below illustrates the connection of master
and slave devices on the SPI bus.

Figure: SPI Bus Interfacing

The master device is responsible for generating the clock signal. It selects the required
slave device by asserting the corresponding slave device’s slave select signal ‘LOW’.
The data out line (MISO) of all the slave devices when not selected floats at high
impedance state.

The serial data transmission through SPI bus is fully configurable. SPI devices
contain a certain set of registers for holding these configurations. The serial peripheral

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control register holds the various configuration parameters like master slave selection
for the device, baud rate selection for communication, clock signal control, etc. The
status register holds the status of various conditions for transmission and reception.

SPI works on the principle of 'Shift Register’. The master and slave devices contain
a special shift register for the data to transmit or receive. The size of the shirt register is
device dependent. Normally it is a multiple of 8. During transmission from the master
to slave, the data in the master’s shift register is shifted out to the MOSI pin and it enters
the shift register of the slave device through the MOSI pin of the slave device. At the
same time the shifted-out data bit from the slave device’s shift register enters the shift
register of the master device through MISO pin. In summary, the shift registers of
‘master’ and ‘slave’ devices form a circular buffer. For some devices, the decision on
whether the LS/MS bit of data needs to be sent out first is configurable through
configuration register (e.g. LSBF bit of the SPI control register for Motorola’s 68HCI2
controller).
When compared to I2C, SPI bus is most suitable for applications requiring transfer
of data in 'streams’. The only limitation is SPI doesn't support an acknowledgement
mechanism.
Universal Asynchronous Receiver Transmitter (UART): Universal Asynchronous Re-
ceiver Transmitter (UART) based data transmission is an asynchronous form of serial
data transmission. UART based serial data transmission doesn't require a clock signal to
synchronize the transmitting end and receiving end for transmission, instead it relies
upon the pre-defined agreement between the transmitting device and receiving device.
The serial communication settings (Baud rate, number of bits per byte, parity, number
of start bits and stop bit and flow control) for both transmitter and receiver should be set
as identical. The start and stop of communication are indicated through inserting special
bits in the data stream. While sending a byte of data, a start bit is added first, and a stop
bit is added at the end of the bit stream. The least significant bit of the data byte follow's
the ‘start’ bit.
The ‘start’ bit informs the receiver that a data byte is about to arrive. The receiver
device starts polling its ‘receive line' as per the baud rate settings. If the baud rate is 'x'
bits per second, the time slot available for one bit is 1/x seconds. The receiver unit polls
the receiver line at exactly half of the time slot available for the bit. If parity is enabled
for communication, the UART of the transmitting device adds a parity bit (bit value is 1
for odd number of 1s in the transmitted bit stream and 0 for even number of 1s). The
UART of the receiving device calculates the parity of the bits received and compares it
with the received parity bit for error checking. The UART of the receiving device discards
the ‘Start', ‘Stop' and ‘Parity' bit from the received bit stream and converts the received
serial bit data to a word (In the case of 8 bits/byte, the byte is formed with the received 8
bits with the first received bit as the LSB and last received data bit as MSB).

For proper communication, the ‘Transmit line' of the sending device should be con-
nected to the ‘Receive line’ of the receiving device. Figure below illustrates the same.

Figure: UART Interfacing

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 In addition to the serial data transmission function, UART provides hardware handshak-
ing signal support for controlling the serial data flow. UART chips are available from dif-
ferent semiconductor manufacturers. National Semiconductor's 8250 UART chip is
considered as the standard setting UART. It was used in the original IBM PC.
Nowadays most of the microprocessors/controllers are available with integrated UART
functionality and they provide built-in instruction support for serial data transmission and
reception.
1-Wire Interface: 1-wire interface is an asynchronous half-duplex communication protocol
developed by Maxim Dallas Semiconductor. It is also known as Dallas l-Wire® protocol. It
makes use of only a single signal line (wire) called DQ for communication and follows the
master-slave communication model. One of the key feature of 1-wire bus is that it allows
power to be sent along the signal wire as well. The 1-Wire slave devices incorporate internal
capacitor (typically of the order of 800 pF) to power the device from the signal line. The l-
wire interface supports a single master and one or more slave devices on the bus. The bus
interface diagram shown in Figure below illustrates the connection of master and slave
devices on the l-wire bus.

Figure: 1-Wire Interface Bus

Every 1-wire device contains a globally unique 64bit identification number stored within it.
This unique identification number can be used for addressing individual devices present on
the bus in case there are multiple slave devices connected to the 1-wire bus. The identifier
has three parts: an 8bit family code, a 48bit serial number and an 8bit CRC computed from
the first 56 bits. The sequence of operation for communicating with a l-wire slave device is
listed below.

1. The master device sends a ‘Reset’ pulse on the 1-wire bus.

2. The slave device(s) present on the bus respond with a ‘Presence’ pulse.
3. The master device sends a ROM command (Net Address Command followed by
the 64bit address of the device). This addresses the slave device(s) to which it
wants to initiate a communication.
4. The master device sends a read/write function command to read/write the internal
memory or register of the slave device.
5. The master initiates a Read data/Write data from the device or to the device.

All communication over the 1-wire bus is master initiated. The communication over the
1-wire bus is divided into timeslots of 60 microseconds. The ‘Reset’ pulse occupies 8 time
slots. For starting a communication, the master asserts the reset pulse by pulling the l-wire
bus ‘LOW’ for at least 8 time slots (480ps). If a ‘slave’ device is present on the bus and is

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ready for communication it should respond to the master with a ’Presence’ pulse, within 60
micro seconds of the release of the ‘Reset’ pulse by the master. The slave device(s) responds
with a ’Presence’ pulse by pulling the 1-wire bus ‘LOW for a minimum of I time slot (60
micro seconds). For writing a bit value of 1 on the 1-wire bus, the bus master pulls the bus
for 1 to 15 micro seconds and then releases the bus for the rest of the time slot. A bit value
of ‘0’ is written on the bus by master pulling the bus for a minimum of 1 time slot (60 micro
seconds) and a maximum of 2 time slots (120 micro seconds). To Read a bit from the slave
device, the master pulls the bus ‘LOW for 1 to 15 micro seconds. If the slave wants to send
a bit value ‘1’ in response to the read request from the master, it simply releases the bus for
the rest of the time slot. If the slave wants to send a bit value ‘0’, it pulls the bus ‘LOW’ for
the rest of the time slot.
Parallel Interface: The on-board parallel interface is normally used for communicating
with peripheral devices which are memory mapped to the host of the system. The host
processor/controller of the embedded system contains a parallel bus and the device
which supports parallel bus can directly connect to this bus system. The communication
through the parallel bus is controlled by the control signal interface between the device
und the host. The ‘Control Signals’ for communication includes ‘Read/Write’ signal and
device select signal. The device normally contains a device select line and the device
becomes active only when this line is asserted by the host processor. The direction of
data transfer (Host to Device or Device to Host) can be controlled through the control
signal lines for ‘Read’ and ‘Write’. Only the host processor has control over the ‘Read’
and ‘Write’ control signals. The device is normally memory mapped to the host
processor and a range of address is assigned to it. An address decoder circuit is used for
generating the chip select signal for the device. When the address selected by the
processor is within the range assigned for the device, the decoder circuit activates the
chip select line and thereby the device becomes active. The processor then can read or
write from or to the device by asserting the corresponding control line (RD\ and WR\
respectively). Strict timing characteristics are followed for parallel communication. As
mentioned earlier, parallel communication is host processor initiated. If a device wants
to initiate the communication, it can inform the same to the processor through interrupts.
For this, the interrupt line of the device is connected to the interrupt line of the processor
and the corresponding interrupt is enabled in the host processor. The width of the parallel
interface is determined by the data bus width of the host processor. It can be 4bit, 8bit,
16bit, 32bit or 64bit etc. The bus width supported by the device should be same as that
of the host processor. The bus interface diagram shown in figure below illustrates the
interfacing of devices through parallel interface.

Figure: Parallel Interface Bus

External Communication Interfaces
The External Communication Interface refers to live different communication
channels/buses used by the embedded system to communicate with the external world.
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RS-232 C & RS-485: RS-232 C (Recommended Standard number 232, revision C from
the Electronic Industry Association) is a legacy, full duplex, wired, asynchronous serial
communication interface. The RS-232 interface is developed by the Electronics Industries
Association (EIA) during the early 1960s. RS-232 extends the UART communication
signals for external data communication.
UART uses the standard TTL/CMOS logic (Logic ‘High’ corresponds to bit value 1 and
Logic ‘Low’ corresponds to bit value 0) for bit transmission whereas RS-232 follows the
EIA standard for bit transmission. As per the EIA standard, a logic ‘0’ is represented with
voltage between +3 and +25V and a logic ‘1’ is represented with voltage between -3 and -
25 V. In EIA standard, logic ‘0’ is known as ‘Space’ and logic ‘1’ as 'Mark'. The RS-232
interface defines various handshaking and control signals for communication apart from
the ‘Transmit’ and 'Receive' signal lines for data communication. RS-232 supports two
different types of connectors, namely; DB-9: 9-Pin connector and DB-25: 25-Pin
connector. Figure below illustrates the connector details for DB-9 and DB-25.

Figure: DB-9 and DB-25 RS-232 Connector Interface

The pin details for the two connectors are explained in the following table:

Pin Pin no: Pin no: (For Description

Name (For DB-9 DB-25
Connector) Connector)
TXD 3 2 Transmit Pin for Transmitting Serial Data
RXD 2 3 Receive Pin for Receiving Serial Data
RTS 7 4 Request to send
CTS 8 5 Clear to Send
DSR 6 6 Data Set Ready
GND 5 7 Signal Ground
DCD 1 8 Data Carrier Detect
DTR 4 20 Data Terminal Ready
RI 9 22 Ring Indicator
FG 1 Frame Ground
SDCD 12 Secondary DCD
SCTS 13 Secondary CTS
STXD 14 Secondary TXD
TC 15 Transmission Signal Element Timing
SRXD 16 Secondary RXD
RC 17 Receiver Signal Element Timing
SRTS 19 Secondary RTS
SQ 21 Signal Quality Detector
NC 9 No Connection
NC 10 No Connection
NC 11 No Connection
NC 18 No Connection
NC 23 No Connection
NC 24 No Connection
NC 25 No Connection

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 RS-232 is a point-to-point communication interface and the devices involved in RS-232
communication are called 'Data Terminal Equipment (DTE)' and ‘Data Communication
Equipment (DCE)’. If no data flow control is required, only TXD and RXD signal lines and
ground line (GND) are required for data transmission and reception. The RXD pin of DCE
should be connected to the TXD pin of DTE and vice versa for proper data transmission.

If hardware data flow control is required for serial transmission, various control signal
lines of the RS-232 connection are used appropriately. The control signals are implemented
mainly for modem communication and some of them may not be irrelevant for other type of
devices. The Request To Send (RTS) and Clear To Send (CTS) signals co-ordinate the
communication between DTE and DCE. Whenever the DTE has a data to send, it activates
the RTS line and if the DCE is ready to accept the data, it activates the CTS line.
The Data Terminal Ready (DTR) signal is activated by DTE when it is ready to accept
data. The Data Set Ready (DSR) is activated by DCE when it is ready for establishing a
communication link. DTR should be in the activated state before the activation of DSR.
The Data Carrier Detect (DCD) control signal is used by the DCE to indicate the DTE
that a good signal is being received.
Ring Indicator (RI) is a modem specific signal line for indicating an incoming call on the
telephone line.
The 25 pin DB connector contains two sets of signal lines for transmit, receive and control
lines. Nowadays DB-25 connector is obsolete and most of the desktop systems are available
with DB-9 connectors only.
As per the EIA standard RS-232 C supports baud rates up to 20Kbps (Upper limit 19.2
Kbps). The commonly used baud rates by devices are 300bps. 1200bps. 2400bps. 9600bps.
11.52Kbps and 19.2Kbps. 9600 is the popular baud rate setting used for PC communication.
The maximum operating distance supported by RS-232 is 50 feet at the highest supported
baud rate.
Embedded devices contain a UART for serial communication and they generate signal
levels conforming to TTL/CMOS logic. A level translator IC like MAX 232 from Maxim
Dallas semiconductor is used for convening the signal lines from the UART to RS-232
signal lines for communication. On the receiving side the received data is convened back to
digital logic level by a converter IC. Converter chips contain converters for both transmitter
and receiver.
Though RS-232 was the most popular communication interface during the olden days,
the advent of other communication techniques like Bluetooth, USB. Firewire, etc. are
pushing down RS-232 from the scenes. Still RS-232 is popular in certain legacy industrial
applications.
RS-232 supports only point-to-point communication and not suitable for multi-drop
communication. It uses single ended data transfer technique for signal transmission and
thereby more susceptible to noise and it greatly reduces the operating distance.
RS-422 is another serial interface standard from EIA for differential data communication.
It supports data rates up to 100Kbps and distance up to 400 ft. The same RS-232 connector
is used at the device end and an RS-232 to RS-422 converter is plugged in the transmission
line. At the receiver end the conversion from RS-422 to RS-232 is performed. RS-422
supports multi-drop communication with one transmitter device and receiver devices up to
10.
RS-485 is the enhanced version of RS-422 and it supports multi-drop communication
with up to 32 transmitting devices (drivers) and 32 receiving devices on the bus. The
communication between devices in the bus uses the ‘addressing’ mechanism to identify
slave devices.

Universal Serial Bus (USB): Universal Serial Bus (USB) is a wired high-speed serial bus
for data communication. The first version of USB (USD 1.0) was released in 1995 and was
created by the USB core group members consisting of Intel, Microsoft, IBM, Compaq,

25
Digital and Northern Telecom. The USB communication system follows a star topology
with a USB host at the center and one or more USB peripheral devices/USB hosts connected
to it. A USB 2.0 host can support connection up to 127, including slave peripheral devices
and other USB hosts. Figure below illustrates the star topology for USB device connection.
USB transmits data in packet format. Each data packet has a standard format. The USB
communication is a host initiated one. Tire USB host contains a host controller which is
responsible for controlling the data communication, including establishing connectivity with
USB slave devices, packetizing and formatting the data packet. There are different standards
for implementing the USB Host Control interface; namely Open Host Control Interface
(OHCI) and Universal Host Control Interface (UHCI).

Figure: USB Device Connection Topology

The physical connection between a USB peripheral device and master device is
established with a USB cable. The USB cable supports communication distance of up to 5
meters. The USB standard uses two different types of connector at the ends of the USB cable
for connecting the USB peripheral device and host device. ‘Type A’ connector is used for
upstream connection (connection with host) and Type B connector is used for downstream
connection (connection with slave device). The USB connector present in desktop PCs or
laptops are examples for ‘Type A’ USB connector. Both Type A and Type B connectors
contain 4 pins for communication. The Pin details for the connectors arc listed in the table
given below.

Pin no. Pin name Description

1 VBUS Carries power (5V)
2 D- Differential data carrier line
3 D+ Differential data carrier line
4 GND Ground signal line

USB uses differential signals for data transmission. It improves the noise immunity. USB
interface has the ability to supply power to the connecting devices. Two connection lines
(Ground and Power) of the USB interface are dedicated for carrying power. It can supply
power up to 500 mA at 5 V. It is sufficient to operate low power devices. Mini and Micro
USB connectors are available for small form factor devices like portable media players.

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 Each USB device contains a Product ID (PID) and a Vendor ID (VID). The PID and VID
are embedded into the USB chip by the USB device manufacturer. The VID for a device is
supplied by the USB standards forum. PID and VID are essential for loading the drivers
corresponding to a USB device for communication.
USB supports four different types of data transfers, namely: Control, Bulk, Isochronous
and Interrupt. Control transfer is used by USB system software to query, configure and issue
commands to the USB device. Bulk transfer is used for sending a block of data to a device.
Bulk transfer supports error checking and correction. Transferring data to a printer is on
example for bulk transfer. Isochronous data transfer is used for real-time data
communication. In Isochronous transfer, data is transmitted as streams in real-time.
Isochronous transfer doesn’t support error checking and re-transmission of data in case of
any transmission loss. All streaming devices like audio devices and medical equipment for
data collection make use of the isochronous transfer. Interrupt transfer is used for
transferring small amount of data. Interrupt transfer mechanism makes use of polling
technique to see whether the USB device has any data to send. The frequency of polling is
determined by the USB device and it varies from 1 to 255 milliseconds. Devices like Mouse
and Keyboard, which transmits fewer amounts of data, uses Interrupt transfer.

USB.ORG (www.usb.org) is the standards body for defining and controlling the
standards for USB communication. Presently USB supports four different data rates namely;
Low Speed (1.5Mbps). Full Speed (12Mbps), High Speed (480Mbps) and Super Speed
(4.8Gbps). The Low Speed and Full Speed specifications are defined by USB 1.0 and the
High-Speed specification is defined by USB 2.0. USB 3.0 defines the specifications for
Super Speed. USB 3.0 is expected to be in action by year 2020. There is a move happening
towards wireless USB for data transmission using Ultra Wide Band (UWB) technology.
Some laptops are already available in the market with wireless USB support.

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