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Solution of Numerical Problem Week 7

This document contains solutions to 10 numerical problems from a VLSI design flow course. Problem 7 calculates arrival times and output slew for an AND gate using graph-based analysis. Problem 8 does the same but uses path-based analysis. Problem 9 calculates setup slack at a timing endpoint for a synchronous circuit. Problem 10 calculates hold slack for the same circuit.

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Shrinidhi Mohan
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310 views

Solution of Numerical Problem Week 7

This document contains solutions to 10 numerical problems from a VLSI design flow course. Problem 7 calculates arrival times and output slew for an AND gate using graph-based analysis. Problem 8 does the same but uses path-based analysis. Problem 9 calculates setup slack at a timing endpoint for a synchronous circuit. Problem 10 calculates hold slack for the same circuit.

Uploaded by

Shrinidhi Mohan
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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VLSI Design Flow: RTL To GDS (NPTEL Course)

Solution of numerical problem for Week 7

7. Consider the AND gate shown below:

The delay and the output slew of different arcs are shown below:
Arc Delay (ps) Output Slew at pin Z (ps)
A→Z 10 20
B→Z 20 5
C→Z 30 10

The arrival time at different input pins are as follows:


Pin Arrival Time (ps)
A 5
B 6
C 12

What will be the arrival time and the output slew at the pin Z when Graph Based Analysis
(GBA) is performed for the setup check or late-mode check?

Solution:

Arrival time from A to Z=10+5=15 ps


Arrival time from B to Z=6+20=26 ps
Arrival time from C to Z=12+30=42 ps

For setup or late check, maximum arrival time should be taken. Hence, arrival time at Z = 42
ps

For GBA, the maximum slew from any path is taken. The maximum slew is from A to Z. Its
value is 20 ps.
Hence, the correct answer is (c) Arrival Time = 42 ps Output Slew = 20 ps

8. For PBA, for B to Z path:


Arrival time = 6+20=26 ps
Slew = 5 ps. Hence, the correct answer is (b) Arrival Time = 26 ps Output Slew = 5 ps

9. Consider the following synchronous circuit.


The following attributes are valid for the flip-flops FF1 and FF2: setup time=45 ps, hold
time=10 ps, and CLK-to-Q delay=20 ps. The delay of each inverter is 50 ps. Ignore the wire
delay.
Assume that the period of the clock is 1000 ps. What is the setup slack at the timing end-
point FF2/D?

Here, T_capture=T_launch=0 ps [Since, delay on clock path is only the wire delay, which must
be ignored, according to the question]

Arrival time at FF2/D = CLK-to-Q delay of FF1 + delay of inverter G2 = 20 + 50 = 70 ps


Required time = Clock period – setup time of FF2 = 1000 – 45 ps = 955 ps
Setup Slack = Required time – Arrival time = 955-70= 885 ps
Hence, correct answer is (a) 885 ps

10. For the same question above, what is the hold slack at the timing end-point FF2/D?
Arrival time at FF2/D = CLK-to-Q delay of FF1 + delay of inverter G2 = 20 + 50 = 70 ps
Required time = hold time of FF2=10 ps
Hold Slack = Arrival time – Required time = 70 -10=60 ps.
Hence, the correct answer is (b) 60 ps.

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