AN1470

Manchester Decoder Using the CLC and NCO

It has no DC component, which means that it may be
Authors: Jatinder Gharoo coupled inductively or capacitively. A typical application
Brian Bailey requires a Manchester data encoder used to transmit
Microchip Technology Inc. data, and a receiver on the other end that decodes
data. The objective of this document is to demonstrate
how the NCO and CLC peripherals found on PIC16F
ABSTRACT
devices can be used as a Manchester Decoder.
A Manchester decoder can be built using Microchip’s Traditional algorithms can be firmware intensive and
award winning CLC (Configurable Logic Cell) blocks leave very small amount of CPU cycles to service other
and NCO (Numerically Controlled Oscillator) available application needs. The following approach involves
in the PIC16F150x devices. The PIC16F150x devices using blocks that operate independently of the CPU
are Microchip’s new enhanced core devices featuring clock and have zero CPU utilization, allowing designers
low-power XLP technology. The decoder requires little to service their applications along with data encoding
firmware support and, therefore, requires very few CPU and decoding.
cycles after the modules are initialized. Data and clock Depending on the encoding standard, data is available
can be directed to the internal SPI module for data during the first or second half of bit time. There are two
capture at rates of up to 500 kbps. standards of Manchester encoded signals used in the
INTRODUCTION industry. Manchester encoded signal as per G.E.
Thomas (Figure 1), a ‘0’ is transmitted by low-to-high
Manchester encoding is used in a wide range of transition and a ‘1’ is expressed by high-to-low
applications in telecommunication and data storage. It transition:
is used in systems for its simplicity and synchronization
benefits. A transition is ensured at least once every bit,
allowing the receiving device to recover clock and data.

FIGURE 1: MANCHESTER ENCODED DATA (AS PER G.E. THOMAS)

Manchester encoded signal as per IEEE 802.3

(Figure 2) is the opposite of G.E. Thomas, where a ‘0’
is transmitted by high-to-low transition:

FIGURE 2: MANCHESTER ENCODED DATA (AS PER IEEE 802.3)

 2012 Microchip Technology Inc. DS01470A-page 1

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CONFIGURABLE LOGIC CELL
This section describes a Manchester decoding
implementation using the CLC blocks of PIC16F150x
microcontrollers. The Configurable Logic Cell (CLC)
provides programmable logic that operates outside the
limitation of CPU execution. The logic cell allows signal
multiplexing from other peripherals, input pins or
register bits through the use of configurable gates that
drive selectable single-output logic functions. The
output of each CLC block can be directed internally to
peripherals, other CLC blocks and to an output pin.
Possible configurations include eight logic functions:
• AND-OR
• OR-XOR
• AND
• S-R Latch
• D Flip-flop with Set and Reset
• D Flip-flop with Reset
• J-K flip-flop with Reset
• Transparent Latch with Set and Reset
Logic functions are shown in Figure 3. Each logic
function has four inputs and one output. The four inputs
are the four data gate outputs of the previous stage.

CLC CONFIGURATION TOOL

The CLC is a complex peripheral with multiple
combinations and sequential circuits that can be
pre-programmed or configured dynamically. This
allows flexibility, but also makes configuration and
setup very complex. The CLC configuration tool
provided by Microchip makes the setup process of the
CLC module easier to implement and understand. It is
worthwhile mentioning that any gate with an
unconnected input will be read as a logic zero. To input
a logic one as an input to a gate or latch, the zero can
be inverted. See “Appendix A ” for configuration
snapshots of the tool.

DS01470A-page 2  2012 Microchip Technology Inc.

 AN1470
FIGURE 3: CLC FUNCTIONS
AND - OR OR - XOR

lcxg1 lcxg1
lcxg2 lcxg2
lcxq lcxq
lcxg3 lcxg3
lcxg4 lcxg4

LCxMODE<2:0>= 000 LCxMODE<2:0>= 001

4-Input AND S-R Latch

lcxg1 lcxg1
S Q lcxq
lcxg2 lcxg2
lcxq
lcxg3 lcxg3
R
lcxg4 lcxg4

LCxMODE<2:0>= 010 LCxMODE<2:0>= 011

1-Input D Flip-Flop with S and R 2-Input D Flip-Flop with R

lcxg4
lcxg4
S D Q lcxq
lcxg2 D Q lcxq lcxg2

lcxg1
lcxg1 R
R
lcxg3
lcxg3

LCxMODE<2:0>= 100 LCxMODE<2:0>= 101

J-K Flip-Flop with R 1-Input Transparent Latch with S and R

lcxg4
lcxg2 J Q lcxq
S
lcxg1 lcxg2 D Q lcxq

lcxg4 K
R
lcxg1 LE
R
lcxg3
lcxg3
LCxMODE<2:0>= 110 LCxMODE<2:0>= 111

 2012 Microchip Technology Inc. DS01470A-page 3

AN1470
NUMERICALLY CONTROLLED • 16-bit increment function
OSCILLATOR • Fixed Duty Cycle (FDC) mode
• Pulse Frequency (PF) mode
The NCO module as shown in Figure 4 is a timer that
• Output pulse width control
uses a 16-bit increment register to add to a 20-bit
accumulator to divide the input frequency. The NCO is • Multiple clock input sources
most useful in applications that require frequency • Output polarity control
accuracy and fine resolution at a fixed duty cycle. • Interrupt capability
Some features of the NCO include:

FIGURE 4: NCO BLOCK DIAGRAM

Increment
16
(1)
Buffer
16
Interrupt event
Set NCOxIF flag

6
NCOxOUT
20 D To CLC, CWG
NCO1CLK 11 Q
LC1OUT 10 Overflow NxOE
Accumulator
FOSC 01 NCOx Clock Q TRIS Control
0
20
HFINTOSC 00 NxEN
1 NCOx
2

NxCKS<2:0> NxPFM
Overflow S Q
NxPOL

R Q

3
NxPWS<2:0>

NCOx Clock Reset

Ripple Counter

Note 1: The increment registers are double-buffered to allow for value changes to be made without first disabling the NCOx
module. They are shown here for reference. The buffers are not user-accessible.

One of the key features of the NCO is the ability to

generate a pulsed output every time the accumulator
overflows. The output becomes active for specified
clock periods. The output returns to an inactive state
once the clock period expires.

DS01470A-page 4  2012 Microchip Technology Inc.

 AN1470
MANCHESTER DECODER The CLC modules are very flexible and can be easily
applied to a wide range of scenarios by inverting the
The approach described in this section and hereafter is input or output polarities of each individual blocks. The
based on Manchester encoding as per G.E.Thomas NCO module’s Idle state can also be controlled in the
described in Figure 1. The method is flexible and can software. The methods discussed below assume that
be easily ported to IEEE 802.3. There are several data is available during the first half of each bit time.
variations and considerations required for the first
Let’s take an example of the following encoded
transition based on the Idle states of modules,
bit-stream as per G.E. Thomas encoding (Figure 5).
power-up configuration of microcontroller pins and the
first bit received (transition based on encoding This signal will be decoded into its clock and data line,
method). Start-up and Idle states will be discussed in as shown in Figure 6.
the Section “Synchronization” of this document.

FIGURE 5: ENCODED BIT STREAM

FIGURE 6: DATA AND CLOCK LINE

Two key points to note from this bit stream are that the mid-bit transition as a trigger for NCO and use ¾ bit
bit value is present in the first half of each bit time, time to overflow and capture the next bit value
before the mid-bit transition. There is a transition in the (Figure 7). This ¾ bit time allows up to +/- ¼ bit time of
middle of each bit period. This allows us to use the error.

FIGURE 7: DATA CAPTURE

 2012 Microchip Technology Inc. DS01470A-page 5

AN1470
CLC block in OR-XOR configuration is used to extract
clock out of this configuration (Figure 8).

FIGURE 8: CLOCK EXTRACTION

This essentially is our Manchester decoder, where notice that every bit except the first one is decoded.
CLC OR-XOR is clock and D is data. If we use the The issue can be resolved in several ways, which will
rising edge of a clock signal to capture data from D, we be discussed in the Section “Synchronization”.

FIGURE 9: MANCHESTER DECODER

The timing diagram above (Figure 9) is decoded into • Stage 3 – XOR gate to provide start time for NCO
the following block diagram (Figure 10). There are five • Stage 4 – AND-OR gate to supply clock to NCO,
stages in this diagram: and to ensure that it clocks for full ¾ bit time
• Stage 1 – Incoming Manchester Signal • Stage 5 – NCO to generate ¾ bit time, started in
• Stage 2 – D flip-flop that captures input data when mid-bit transition of previous bit
NCO is triggered

DS01470A-page 6  2012 Microchip Technology Inc.

 AN1470
FIGURE 10: FULL DECODER BLOCK DIAGRAM
CLC4 CLC2 CLC1

Data Out
Data In S
D Q1

R FOSC

NCO
Clock Out
CLK OUT

PIC16F1509 IMPLEMENTATION These two blocks together are the most important in
the decoder. They create a fixed length pulse for each
The device chosen for this implementation is rising edge coming out of Stage 2. The output of the
PIC16F1509. It has four CLC blocks to implement NCO is fed back into the AND-OR gate, so that when
combinational logic along with NCO to generate the output of Stage 2 goes to zero, the NCO will
specific bit time. The following section covers the continue clocking until it overflows.
implementation of these blocks using the available
When the part is first configured, it will output a single
resources in this device.
¾ bit length pulse. This is needed to put the NCO in its
active-low state. When it is active, the NCO is waiting
Stage 1 – D Flip-Flop (CLC4) on the output pulse width clocks configured in the
This stage latches in the Manchester data on the falling NCOCLK register.* Once a clock source is supplied, it
edge of the clock signal. This output is the recovered will finish its active pulse and start counting again.
data that will be fed into the microcontroller. The data is *Design Tip: By removing the clock source from the
sampled on the clock falling edge, and is stable to be NCO and holding it in its active state, you have
read on the clock rising edge, because the data line essentially created a way to control the duty cycle of
never changes on a rising clock edge. the NCO.

Stage 2 – XOR Gate (CLC2)

Because a transition is ensured in the middle of every
bit in Manchester encoding, we can use an XOR gate
to ensure that each mid-bit transition gives us a rising
edge for Stage 3. This means that we are
synchronizing our decoder in the middle of each bit.

Stage 3 – NCO + AND-OR (CLC1)

The PIC16F1509 has a NCO module that is used to
generate ¾ bit-time to capture data value. The NCO is
used in active-low Pulse Frequency mode to output a
pulse when ¾ bit time expires. The pulse width can be
controlled using a Special Function Register. The
module also requires a clock source that allows it to
repeatedly add a fixed value to an accumulator at the
specified clock rate, which will be supplied by CLC1.

 2012 Microchip Technology Inc. DS01470A-page 7

AN1470
Figure 11 uses the example of a 25 kHz Manchester
data input. 25 kHz gives us 40 µs bit time, which means
that we need to generate a ¾ bit time of 30 µs to
capture data and synchronize the NCO clock to the
rising edge of the extracted clock.

FIGURE 11: BIT TIMING

To configure the NCO, refer to Equation 25-1 in the

PIC16F1509 data sheet on the Microchip web site:

EQUATION 1:

NCO Clock Frequency * Increment Value 16 MHz  Internal Clock F osc  * Increment Value
- = -------------------------------------------------------------------------------------------------------------------------
F overflow = ----------------------------------------------------------------------------------------------------- -
2 n 2 20

n = accumulator width in bits

16 MHz * Increment Value

30us pulse = 33.33 kHz = ------------------------------------------------------------------  Increment Value = 2184 = 0x0888
2 20

We are using the NCO in Pulse Frequency mode,

where every time the accumulator overflows; the output
becomes active for pre-defined clock periods. Keep in
mind that these clocks are removed from the NCO to
hold it in its active (low) state. They will then be added
to the next pulse.

DS01470A-page 8  2012 Microchip Technology Inc.

 AN1470
SYNCHRONIZATION Another method is by first sending a Start bit. It needs
to occur a ½ bit length before the first bit is transmitted,
The assumption in the above analysis is that the first so the remaining data will synchronize with the mid-bit
edge was a mid-bit transition. The problem is that one transitions. A Stop bit may be necessary to return the
¾ bit length after the first mid-bit transition; you have encoded data line back to its default state. Figure 12
already missed your first bit of data. There are several again shows the waveform timings of the different
methods to overcome this problem. blocks in the decoder. Because there is a Start and
The first and easiest method is by receiving data with a Stop bit, the first clock and last clock do not contain
known first bit. That way you can just mask it in after the data and must be filtered out in the software. This can
data is read. be done using the interrupt-on-change feature (trigger
on the Start bit), then fed into the SPI or UART. Or, it
can easily be bit-banged.

FIGURE 12: MANCHESTER DECODER FINAL TIMING

 2012 Microchip Technology Inc. DS01470A-page 9

AN1470
HARDWARE APPLICATION
The CLC blocks have a variety of inputs and outputs.
Figure 13 shows how the three blocks can be wired up to
each other externally in order to make the decoder work
properly.

FIGURE 13: BLOCK DIAGRAM WITH EXTERNAL PIN CONNECTIONS

CONCLUSION
A Manchester decoder is implemented using Microchip’s
award winning CLC blocks. In the chosen
implementation, the NCO and three CLC blocks were
used. Serial data and clock can be fed into an SPI
module, UART, or bit-banged to recover data if needed.
The implementation chosen is using very few CPU cycles
for Manchester decoding, leaving it to process other
application tasks. The part can remain in Sleep mode
between bytes to save power.
There are plenty of other applications where CLC blocks
can be used very efficiently. Manchester encoding and
decoding is just one of them. The new enhanced
mid-range 8-bit core on PIC16F1509 features Microchip’s
Extreme Low-Power XLP technology, and is suitable for a
wide range of applications.

DS01470A-page 10  2012 Microchip Technology Inc.

 AN1470
REFERENCES
Wikipedia: http://en.wikipedia.org/wiki/Manchester_code
Device Data Sheet: http://www.microchip.com/wwwproducts/Devices.aspx?dDocName=en553474

 2012 Microchip Technology Inc. DS01470A-page 11

AN1470
APPENDIX A

FIGURE 14: CLC 1 (AND-OR)

FIGURE 15: CLC 2 (D FLIP-FLOP)

DS01470A-page 12  2012 Microchip Technology Inc.

 AN1470
FIGURE 16: CLC4 (D FLIP-FLOP)

 2012 Microchip Technology Inc. DS01470A-page 13

AN1470
FIGURE 17: DECODED DATA

DS01470A-page 14  2012 Microchip Technology Inc.

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