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Abstract—With the continuous advancement of technology, there is a growing demand
for designing devices with low power consumption. The development of smaller and
more portable devices has prompted designers to focus on minimizing power usage,
particularly in digital circuits where reducing clock power is a significant factor in
achieving low-power designs. A notable technique for achieving low-power designs is
the utilization of Multi-bit flip-flops, especially when sharing the clock signal among
multiple flip-flops.

This approach has been successfully applied to sequential circuits such as Shift Registers
and Finite State Machines (FSMs) to significantly reduce clock power consumption and
conserve overall power.In the course of this research, we have demonstrated the
effectiveness of the Multi-bit flip-flop approach in practice, using examples of Shift
Registers and FSMs. In both cases, it was empirically confirmed that circuits
implemented with Multi-bit flip-flops consume less clock power compared to traditional
flip-flops. Post-layout simulations of these circuits further validated these findings.The
entire research was conducted using Cadence® Virtuoso, Cadence® Layout Editor, and
Cadence® Assura, all implemented with 180nm technology.

Index Terms—Low power consumption, clock power, Multi- bit flip-flops (MBFFs),
Sequential circuits, Shift registers, Finite state Machine’s (FSM’s), Post-Layout simulation
Introduction In the realm of System-on-Chip (SoC) design, the com- plexity is on a
continuous upward trajectory with respect to power domains, gate count, and package
densities. The challenges intensify as physical design teams struggle with the intricate
task of balancing power consumption, performance, and die area. This becomes
especially critical as we migrate to ever-smaller technology nodes and increased
packaging densities.Clock power consumption emerges as a pivotal factor in
determining the overall power usage within a single chip.

To mitigate power-related concerns, various techniques have been introduced and are
currently applied in modern tech- nologies. Among these, clock power reduction
methods such as clock gating, Multi Vth concept, and Multi Supply Multi Voltage
(MSMV) have gained considerable popularity.When we consider designs employing
single-bit flip-flops, the total area tends to increase due to the larger number of
sequential and combinational cells involved.

In contrast, the same design can be implemented using multi-bit flip-flops, resulting in
reduced area and lower clock power consumption compared to _the single-bit flip-flop
design. Multi-bit flip-flops have proven to be an effective technique for achieving
low-power designs. These flip-flops amalgamate single-bit flip-flops, eliminating
redundant inverters that are typically shared among the flip- flops. This reduction in the
number of inverters translates to a decrease in power consumption, thereby reducing
dynamic power dissipation due to the decreased clock power consump- tion.

The literature survey showed some of the common tech- niques used by different
researchers in reducing power in digital circuits. In[1], the clock gating and MBFF
combined is used to reduce power conception in SoC platforms, without degrading the
delay aspect of the circuit. In this work, they have merged all the SBFF in the SOC to
obtain a set of MBFF that provide the same working with reduction in power. In[2], a
relatively new method for using the MBFF in the circuit.

Loosely Coupled MBFF (LC-MBFF), through this style of FFs the placement area and
delay of the circuit could be reduced. The main objective of the work was to reduce the
post placement power. here a algorithm was developed to efficiently place the blocks so
that power will be reduced. !n[3], an application perspective of MBFF in IoT systems is
done. It proposes the usage of MBFFs in IoT application to reduce the delay and power
consumption aspects so that portable IoT processing devices can be designed with
minimum latency and power dissipation.

They have used iterative insertion of MBFF in different stages of implementation. In[4],
the power consumption in different configurations of network switches are being
measured with respect to both SBFF and MBFF. They came to realise that the power
dissipation higher bit switches using MBFF was found to be decreasing. Even- though
for low number of bit it does not show any variation but as the number of bits increases
the power conception rapidly reduces compared with their SBFF counter parts.

Theoretical background Single Bit Flip Flop SBFF consist of a master and a slave latch.
The latches use two different clock phases to perform the operation. The clock signal
should use opposite phases, in order to have a better delay. To implement this property
cascaded pair of inverters are used. Fig 1 provides an example of SBFF.
//
Fig. 1. Single Bit Flip Flop Multi Bit Flip Flop In case of MBFF the master and slave latch
remains same but the major difference here is the number of master and slave latches
driven by the cascaded clock branch.

If more than one pair of master and slave latches are being driven by the clock branch
then it is referred to as MBFF. Here in Fig 2 an example of dual bit flip flop is given,
which has a cascaded clock driving 2 pairs of master and slave latches. When combining
Fig. 2. Dual Bit Flip Flop one or more Single-Bit Flip-Flop (SBFF) cells with Multi-Bit
Flip-Flop (MBFF) cells,the resulting circuit has the foillowing advantages compared to
the former circuit style: 1.Reduced Clock Sinks. 2.Lower Power Consumption. 3.Smaller
Area and Reduced Delay. 4.Reduced Clock Skew. As illustrated in Fig 3, a Dual-Bit
Flip-Flop includes two data input pins, two data output pins, one clock pin, and a reset
pin.

The truth table for the dual-bit flip-flop cell Table 1 demonstrates its behavior: at the
positive edge of the clock signal (ck), the values of Q1 and Q2 pass to D1 and D2, while
at the negative clock edge, Q1 and Q2 retain their original values. TABLE I Truth table of
DBFF _ Fig. 3. Dual Bit Flip Flop cell Shift Register A shift register is a fundamental digital
electronic circuit used for the temporary storage and sequential processing of binary
data. It consists of a series of flip-flops interconnected in a linear chain. Each flip-flop
can store a single bit of data, and the entire register can hold multiple bits. Shift
registers can perform two primary operations: shifting and loading.

In the shifting operation, data is moved from one flip-flop to the next in a synchronized
manner, either left or right. This allows for the serial transfer of data. In the loading
operation, new data can be loaded into the register, replacing the existing contents.
Sequence Detector A sequence detector is a digital circuit whose primary func- tion is to
continuously examine incoming data and generate an output signal when it detects the
desired sequence.

This output signal often serves as a trigger for subsequent actions, decision-making
processes, or further data processing. There in general two types of sequence
detectors:- Mealy sequence detector:- It is a type of sequence detector where the
output depends not only on the current input but also on the state of the machine. It
can generate output signals that change asynchronously with the input and internal
state changes, making it suitable for more complex sequences.

In a Moore sequence detector:- In this type of sequence detector the output depends
only on the current state of the machine and does not consider the current input. It’s a
simpler and more straightforward type of sequence detector compared to the Mealy
type. Delay Propagation Delay (tpd): Propagation delay (tpd) is a critical metric for
measuring the time it takes for a signal to traverse a digital circuit. For combinational
logic circuits, it’s the time taken for the output to transition from one logical state to
another when the input changes.

It is the sum of the low-to- high transition delay (tplh) and the high-to-low transition
delay (tphl):
tpd = tplh + tphl (1)
In sequential circuits like flip-flops and registers, tpd in- cludes the time taken for the
signal to pass through the combinational logic and the clock-to-Q delay, which is the
time it takes for the output to respond to a clock signal. Power Power Consumption (P):
Power consumption in digital circuits can be divided into two main components: static
power (Pstatic) and dynamic power (Pdynamic).

Static Power (Pstatic): represents the power consumed by an IC when it is in a quiescent

state, with no clock signal or input activity. It is primarily due to leakage currents in
transistors and is less dependent on switching activities. Dynamic Power (Pdynamic): is
the power consumed when signals transition between logic states and when there is
activity within the circuit. It is directly related to the switching frequency (f ) and the load
capacitance (Cload) of the circuit. The total power consumption (Ptotal) is the sum of
static and dynamic power: Ptotal = Pstatic + Pdynamic (2) The dynamic power
consumption can be further calcu- lated using the equation: Pdynamic = 0.5

· Cload · V 2 · f (3) Here, Cload represents the total load capacitance of the circuit, Vdd is
the supply voltage, and f is the switching frequency. Proposed work and methadology
Series In Series Out Shift Register(SISO) In this register the input is given serially bit by
bit and the output is collected one after the other serially.so at both the input and
output side transfer of bits is done serially.This data can be shifted towards left or right
that is only in one direction As the data is fed from left as bit by bit, the shift register
shifts the data bits to right as shown in Fig 4 A 4-bit SISO shift register consists of 4 flip
flops which clock as common input and Data In will given at the leftmost flip-flop.Shift
left registers are nothing but registers which will shift the bits towards left side.Shift
right registers are nothing but registers which will shift the bits towards right side.

Among all the four type of shift registers SISO is the simplest. Here the shift of bits will
be from left to right as all the 4 flip-flops are connected to each other in such a way that
output of present flop will be the input of next flop and the leftmost flip-flop is given
the input. In Fig 4 the feeding is done at the leftmost flip-flop.In this shift register serially
data is passed when clock signal is applied.It is used to make a temporary storage while
it is also used as delay element.

In the proposed shift register the same functionality is implemented using multi-bit
flip-flops as shown in Fig 4 where the two single bit flip-flops are replaced with a 2-bit
flip-flop so as to consume less power. _ / Fig. 4. Model OF SISO Series In Parallel Out
Shift Register(SIPO) The input is given serially and Output is collected paral- lel.An extra
signal called clear is connected in addition to clock to reset the registers.The output of
present flip-flop will be the input to next flip-flop and all flip-flops are sharing the clock
signal Fig 5 Model of Serial In Parallel Out.In SIPO the outputs are collected immediately
after the every flip- flop .This type of registers are used to covert serial data into parallel
data, which will be useful in de-multiplexing of a data line in communication lines.

In the proposed shift register the same functionality is implemented using multi-bit
flip-flops as shown Fig 5 where the two single bit flip-flops are replaced with a 2bit
flip-flop so as to consume less power. Fig. 5. Model OF SIPO Parallel In Series Out Shift
Register(PISO) The input to this register is given in parallel i.e. data is given separately to
each flip flop and the output is collected in serial at the output of the end flip flop. For
this type of shift registers the data is given in parallel individually to each register
through a multiplexer. The inputs are given parallel to each register and the data is
collected serially.

The parallel data input and the present flip-flop output is given as inputs to the
multiplexer and the output of multiplexer is connected to the next flip-flop. This type of
shift registers convert parallel data into serial data where number of data lines are
multiplexed into single serial data In the proposed shift register the same functionality is
implemented using multi-bit flip-flops as shown in Fig 6 where the two single bit
flip-flops are replaced with a 2-bit flip-flop so as to consume less power. Parallel In
Parallel Out Shift Register(PIPO) In this register, the input is given in parallel and the
output also collected in parallel.

The clear (CLR) signal and clock signals are connected to all the 4 flip flops. Data is given
as input separately for each flip flop and in the same way, output also collected
individually from each flip flop.The input is
/
 Fig. 6. Model of PISO given parallel and the output is also taken parallelly. The input
and output are taken individually for every flip-flop. The flip- flops are independent on
the previous or next flip-flops. The clock will be shared by all the flip-flops. In the below
Fig 7 the inputs are D1,D2,D3,D4 are inputs given in parallel and clock signal is given to
each flip-flop. The outputs are Q1,Q2,Q3,Q4 which are not dependent on previous
flip-flops. Fig. 7.

Model of PIPO Moore Sequence Detector (101) Designing a Moore sequence detector
for the sequence ”101” involves a systematic approach to recognizing this specific
pattern within a digital data stream. In this design, we create a state machine with three
distinct states: State 0 (initial state), State 1 (after detecting the first ”1”), and State 2
(after recognizing ”10”). Transitions between these states are determined by the
incoming data: a ”1” in State 0 transitions to State 1, a ”0” in State 1 leads to State 2, and
any other input resets the detector to the initial State 0.

State 2 serves as the accepting state, indicating the successful detection of the ”101”
sequence. The Moore machine’s output signal, which depends solely on the current
state, can be set to indicate a successful sequence detection. By implementing this
circuit with flip- flops and combinational logic, we can reliably identify and respond to
the ”101” sequence in the input. _Fig. 8. 101 sequence detector using Moore Results and
discussion In the context of working with a 180nm technology node in Cadence, our
research conducted a comprehensive compara- tive analysis between Single-Bit
Flip-Flops (SBFF) and Multi- Bit Flip-Flops (MBFF) for sequential circuits. This analysis
encompassed the evaluation of power consumption, delay, and Power-Delay Product
(PDP).Figure 9 illustrates the power consumption results, revealing a slight reduction in
power for 4-bit sequential circuits implemented with Dual Bit Flip- Flops compared to
SBFF. However, the difference becomes more pronounced when examining 8-bit
sequential circuits.

Notably, in Figure 10, a similar trend is observed in the delay characteristics of

sequential circuits employing SBFF and MBFF. An important finding is that the delay
remains consistent in both configurations, regardless of parallel input or output
operations. Figure 11 reinforces our observations on power consumption, showing that
4-bit Sequential Multi- Bit Flip-Flops (SMBFF) and Multi-Bit Flip-Flops (MBBF)
implementations exhibit relatively minor variations in their PDP. In contrast, their 8-bit
counterparts exhibit substantial differences, with MBFF implementations clearly
demonstrat- ing a distinct advantage in terms of lower power dissipation.

These findings underscore the potential of MBFF architecture, particularly in higher-bit

applications, as a highly favorable candidate for digital integrated circuits. This
technology holds promise for significantly reducing both power consumption and delay,
making it a compelling choice for future digital IC designs. Fig. 9. Power comparison
 / Fig. 10. Delay comparison Fig. 11. PDP comparison Conclusion and Future work In this
study, we conducted a thorough comparative analysis between Single-Bit Flip-Flops
(SBFF) and Multi-Bit Flip- Flops (MBFF) for sequential circuits in a 180nm technology
node using Cadence tools.

Our investigation encompassed the assessment of power consumption, delay, and

Power-Delay Product (PDP) for both 4-bit and 8-bit implementations. The results have
revealed compelling insights into the advantages of MBFFs, particularly in high-bit
applications. Our findings indicate that the use of MBFFs in sequential circuits can lead
to a significant reduction in power consumption and delay compared to traditional SBFF
implementations. This highlights the potential for MBFF architecture to be a favor- able
candidate for future digital integrated circuits, offering substantial improvements in
performance and efficiency.

Our research has opened up several promising avenues for future investigations in the
field of digital integrated circuits: Scaling to Advanced Technology Nodes: Extending
this study to advanced technology nodes (e.g., 45nm, 28nm, or beyond) is crucial to
assess how MBFFs perform in cutting-edge semiconductor processes. Low-Power
Architectures: Explor- ing the integration of MBFFs within low-power architectures and
assessing their effectiveness in energy-efficient digital ICs.

High-Performance Computing: Investigating the use of MBFFs in high-performance

computing systems, such as graphics processors and AI accelerators, to determine their
potential in demanding applications. .

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