Practical Workbook

Name: Ayush Kumar

Roll Number: 202211008
Branch: Computer Science and Engineering
Batch: 2022
Subject: EC261
Session: 2023-
24

1
 Certificate

This is to certify that Mr. Ayush Kumar of B.

Techof semesterIIIEnrolmentNumber 202211008
Branch Computer Science and Engineering (CSE)
has been found satisfactory in the continuous
internal evaluation of laboratory, practical and term
work in the subject EC261 for the academic year
2023-2024.

Date: Sign of Faculty:

2
 List of Experiments

S. Name of experiment Date of Date of Faculty

No. experime submissio ’ssign
nt n
1. Basic familiarity with logic 19/9/23 26/9/23
gate. Verify the truth table of
given 74-series IC

3
Experiment 1

Aim of The Experiment:-

Basic familiarity with logic gate. Verify the truth table

of given74-series IC.
(i) AND
(ii) NAND
(iii) NOT
(iv) NOR
(v) OR
(vi) Xor

Components Required:-

•
Breadboard
•
IC
•
LED
•
Wires
•
Voltage source (+5V)

4
Theory:-

A logic gate is a device either in theory or, in form that carries

out Boolean functions. These functions involve operations
performed on binary inputs resulting in a solitary binary
output.

Different Logic Gates are

:- AND Gate:-

An AND gate is a logic gate having two or more

inputsand a single output. An AND gate operates on
logicalmultiplication rules. In this gate, if either of
the inputsis low (0), then the output is also low. If all
of the inputs are high (1), then the output will also be
high.

NAND Gate:-
A NAND gate (“not AND gate”) is a logic gate that
produces a low output (0) only if all its inputs are
true,and high output (1) otherwise. Hence the NAND
gate is the inverse of an AND gate, and its circuit is
produced by connecting an AND gate to a NOT gate.
5
NOT Gate:-
A NOT gate, often called an inverter, is a nice digital
logic gate to start with because it has only a single
input with simple behavior. A NOT gate performs
logical negation on its input. In other words, if the
input is true, then the output will be false. Similarly,
afalse input results in a true output.

NOR Gate:-
A NOR gate (“not OR gate”) is a logic gate that
produces a high output (1) only if all its inputs are
false, and low output (0) otherwise. Hence the NOR
gate is the inverse of an OR gate, and its circuit is
produced by connecting an OR gate to a NOT gate.

OR Gate:-
An OR gate is a logic gate that performs logical OR
operation. A logical OR operation has a high output
(1) if one or both the inputs to the gate are high (1).
Ifneither input is high, a low output (0) results.

6
 XOR Gate:-

XOR” an abbreviation for “Exclusively-OR.” The

simplest XOR gate is a two-input digital circuit that
outputs a logical “1” if the two input values differ,
i.e.,its output is a logical “1” if either of its inputs are
1, but not at the same time (exclusively).

Observation:-

Nand Gate:-

Truth table:

A B NAND
0 0 1
0 1 1
1 0 1
1 1 0

7
NOT Gate:-

Truth table:

A NOT
0 1
1 0

8
 AND Gate:-

Truth table:

A B AND
0 0 0
0 1 0
1 0 0
1 1 1

9
 XOR Gate:-

Truth table:

A B XOR

0 0 0
0 1 1
1 0 1
1 1 0

10
 OR Gate:-

Truth table:

A B OR
0 0 1
0 1 1
1 0 1
1 1 0

11
 NOR Gate:-

Truth table:

A B NOR

0 0 1
0 1 0
1 0 0
1 1 0

12
Conclusion:-

We've double checked the truth table, for all types of logic gates,
such as NAND, NOT ,AND, XOR, NOR and OR gates.
*-*-*-*-*

13
Indian Institute of Information Technology,
Vadodara International Campus Diu IIITV-
ICD

Practical Work Book

Name:Ayush kumar
Roll: 202211008
Branch: CSE
Batch: 2022
Subject: EC261
Session: 2022-23
 Certificate
This is to certify that Mr. Ayush Kumar of B-Tech batch 2022
Semester 3 Enrollment No. 202211008 Branch CSE hasbeen
found satisfactory in the continuous internal evaluation of the
laboratory, practical and term work in the subject EC261 for
the academic year 2022– 2023.

Date: 27/09/2023 Sign of Faculty

 List of experiment

Sr Aim of Date of Date of Pag Teache

. experiment performance submission e rsign
N no
o

1 Verification of 27/9/2023 03/10/2023 4-9

truth table of all
logic gates and
adder, subtractor
circuit.
 Date: 27/9/2023

Aim:
(i) Make the different basic logic gates using the NAND gate.

(ii) Make half adder and subtractor using NAND gate.

Components required:
Breadboard, IC, LED, wires,voltage source(+5V)

Theory:
A logic gate is an idealized or physical device implementing a Boolean function,
alogicaloperation performed on one or more binary inputs that produces a single binary
output.

Different logic gates are:

NAND gate: The NAND gate operates as an AND gate followed by a NOT gate. It acts in
the manner of the logical operation "and" followed by negation. The output is"false" if
bothinputs are "true." Otherwise, the output is "true."

XOR gate: The XOR (exclusive-OR) gate acts in the same way as the logical "either/or."
The output is "true" if either, but not both, of the inputs are "true." The output is "false" if
both inputs are "false" or if both inputs are "true." Another way of looking at this circuit is
toobserve that the output is 1 if the inputs are different, but 0if the inputs are the same.

And gate: The output is "true" when both inputs are "true." Otherwise, the output
is"false."In other words, the output is 1 only when both inputs one AND two are
1.

Or gate :The output is "true" if either or both of the inputs are "true." If both inputs are
"false," then the output is "false." In other words, for the output to be 1, at leastinput one
OR two must be 1.
 NOT gate: A logical inverter is called a NOT gate. It has only one input. It reverses the
logicstate. If the input is 1, then the output is 0. If the input is 0, then the output is1.

XNOR gate: The XNOR (exclusive-NOR) gate is a combination XOR gate followed by an
inverter. Its output is "true" if the inputs are the same, and "false" if the inputsare different.

Adder and Subtracter Circuit

Adder circuit A logic circuit used for adding two 1-bit numbers or simply two bits is called
as a Half Adder circuit. This circuit has two inputs and two outputs. The inputsare the two 1-
bit binary numbers and the outputs are Sum and Carry.

Subtractor Circuit A Half Subtractor is a multiple output Combinational Logic Circuitthat

does the subtraction of two 1-bit binary numbers. It has two inputs and two outputs. The
twoinputs correspond to the two 1-bit binary numbers and the two outputs corresponds to
the Difference bit and Borrow bit.

Observations:
(a) NAND gate

Circuit and Truth table:

A B NAN
D
0 0 1
0 1 1
1 0 1
1 1 0
(b) NOT gate

Circuit and Truth table:

A NO
T
0 1
1 0

(C) AND gate

Circuit and Truth table:

A B AN
D
0 0 0
0 1 0
1 0 0
1 1 1
(d) XOR gate

A B XO
R
0 0 0
0 1 1
1 0 1
1 1 0
Circuit and Truth table:

e) XNOR gate

Circuit and Truth table:

A B XNO
R
0 0 1
0 1 0
1 0 0
1 1 1
f) OR gate

Circuit and Truth table:

A B O
R
0 0 1
0 1 1
1 0 1
1 1 0

g) Adder circuit
Circuit and Truth table:

A B A+ Carr
B y
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
h) Subtractor Circuit
Circuit and Truth table:

A B A- Borro
B w
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

Conclusion:
We have verified the truth table for all logic gates including NAND,
NOT, AND, XOR, XNOR, OR gates.

We have successfully created and verified half adder and subtractorcircuit.

**************
 Practical Workbook

Name: Ayush Kumar

Roll Number: 202211008
Branch: Computer Science and Engineering
Batch: 2022
Subject: EC261
Session: 2023-
24

1
 Certificate

This is to certify that Mr. Ayush Kumar of B. Tech

of semester III Enrolment Number 202211008
Branch Computer Science and Engineering (CSE)
has been found satisfactory in the continuous
internal evaluation of laboratory, practical and term
work in the subject EC261 for the academic year
2023-2024.

Date: Sign of Faculty:

2
 List of Experiments

S. No. Name of experiment Date of Date of Faculty’s

experiment submission sign
1. Basic familiarity with logic 19/9/23 26/9/23
gate. Verify the truth table of
given 74-series IC

2. (i) Make the different basic 27/9/23 3/10/23

logic gates using the universal
gate.
(ii) Make half adder and
subtractor using universal gate.
3. (i) Make full adder and full 4/10/23 10/10/23
subtractor.
(ii) Make BCD to grey code
convertor and vice versa.
(iii) Make 2 Bit Adder Circuit

3
Experiment 1

Aim of The Experiment:-

Basic familiarity with logic gate. Verify the truth table of

given 74-series IC.
(i) AND
(ii) NAND
(iii) NOT
(iv) NOR
(v) OR
(vi) Xor

Components Required:-

 Breadboard
 IC
 LED
 Wires
 Voltage source (+5V)

4
Theory:-

A logic gate is an idealized or physical device implementing a

Boolean function, a logical operation performed on one or
more binary inputs that produces a single binary output.

Different Logic Gates are :-

AND Gate:-

An AND gate is a logic gate having two or more

inputs and a single output. An AND gate operates on
logical multiplication rules. In this gate, if either of
the inputs is low (0), then the output is also low. If all
of the inputs are high (1), then the output will also be
high.

NAND Gate:-
A NAND gate (“not AND gate”) is a logic gate that
produces a low output (0) only if all its inputs are
true, and high output (1) otherwise. Hence the
NAND gate is the inverse of an AND gate, and its
circuit is produced by connecting an AND gate to a
NOT gate.

5
NOT Gate:-
A NOT gate, often called an inverter, is a nice digital
logic gate to start with because it has only a single
input with simple behavior. A NOT gate performs
logical negation on its input. In other words, if the
input is true, then the output will be false. Similarly,
a false input results in a true output.

NOR Gate:-
A NOR gate (“not OR gate”) is a logic gate that
produces a high output (1) only if all its inputs are
false, and low output (0) otherwise. Hence the NOR
gate is the inverse of an OR gate, and its circuit is
produced by connecting an OR gate to a NOT gate.

OR Gate:-
An OR gate is a logic gate that performs logical OR
operation. A logical OR operation has a high output
(1) if one or both the inputs to the gate are high (1). If
neither input is high, a low output (0) results.

6
XOR Gate:-

XOR” an abbreviation for “Exclusively-OR.” The

simplest XOR gate is a two-input digital circuit that
outputs a logical “1” if the two input values differ,
i.e., its output is a logical “1” if either of its inputs are
1, but not at the same time (exclusively).

Observation:-

Nand Gate:-

Truth table:

A B NAND
0 0 1

0 1 1

1 0 1
1 1 0

7
NOT Gate:-

Truth table:

A NOT
0 1

1 0

AND Gate:-

Truth table:

A B AND
0 0 0
0 1 0

1 0 0
1 1 1

8
XOR Gate:-

Truth table:

A B XOR
0 0 0

0 1 1
1 0 1

1 1 0

OR Gate:-

Truth table:

A B OR
0 0 1
0 1 1
1 0 1
1 1 0

9
NOR Gate:-

Truth table:

A B NOR
0 0 1
0 1 0
1 0 0
1 1 0

1
Conclusion:-

We have verified the truth table for all logic gates

including NAND, NOT, AND, XOR, NOR, OR
gates.
*-*-*-*-*

1
Experiment 2

Aim of The Experiment :-

Perform the following:

(i) Make the different basic logic gates using the universal gate.
(ii) Make half adder and subtractor using universal gate.

Components Required:-

 Breadboard
 IC
 LED
 Wires
 Voltage source (+5V)
 NAND GATE (7400)
 NOR GATE (7402)

Software :-
 Logisim

1
Theory:-

Universal Gates:-

 A universal gate is a gate which can implement any

Boolean function without need to use any other gate
type.
 The NAND and NOR gates are universal gates.
 In practice, this is advantageous since NAND and NOR
gates are economical and easier to fabricate and are the
basic gates used in all IC digital logic families.
 In fact, an AND gate is typically implemented as a
NAND gate followed by an inverter not the other way
around!!
 Likewise, an OR gate is typically implemented as a
NOR gate followed by an inverter not the other way
around!!

1
Half Adder Circuit :-

 A combinational logic circuit which is designed to add

two binary digits is called as a half adder.
 The half adder provides the output along with a carry
value (if any).
 The half adder circuit is designed by connecting an EX-
OR gate and one AND gate.
 It has two input terminals and two output terminals for
sum and carry.

1
Characteristics Equations of Half adder :-

The characteristic equations of half adder, i.e. equations of sum

(S) and carry (C) are obtained according to the rules of binary
addition. These equations are given below:-
The sum (S) of the half-adder is the XOR of A and B.
Sum, S=A⊕B=AB′+A′B
The carry (C) of the half-adder is the AND of A and B.
Carry, C=A⋅B

Truth Table:-

A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

1
Half Subtractor Circuit :-

 A half-subtractor is a combinational logic circuit that

have two inputs and two outputs (i.e. difference and
borrow).
 The half subtractor produces the difference between the
two binary bits at the input and also produces a borrow
output (if any).
 In the subtraction (A-B), A is called as Minuend bit and
B is called as Subtrahend bit.

1
Characteristics Equations of Half subtractor :-

The characteristic equations of the half subtractor, i.e.

equations of the difference bit (d) and the output borrow bit
(b) are obtained by following the rules of binary subtraction.
These equations are given as follows :-
The difference bit (d) of the half subtractor is given by XORing
the two inputs A and B.
Difference, d=A⊕B=A′B+AB′
The borrow (b) of the half subtractor is the AND of A’
(compliment of A) and B.
Borrow, b=A′B

Truth Table:-

A B Difference Borrow
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

1
Observations:-

1
1
2
Conclusion:-
We have verified the truth table of all gates using universal
gates. We have also verified the truth table of half adder and
half subtractor circuit using universal gates.

*-*-*-*-*

2
Experiment 3

Aim of The Experiment :-

Perform the following:

(i) Make full adder and full subtractor.
(ii) Make BCD to grey code convertor and vice versa.
(iii) Make 2 Bit Adder Circuit.

Components Required:-

 Breadboard
 IC
 LED
 Wires
 Voltage source (+5V)
 AND GATE (7408)
 OR GATE (7432)
 XOR GATE (7486)

Software :-
 Logisim

2
Theory:-

Full Adder:-

 A combinational logic circuit that can add two binary

digits (bits) and a carry bit, and produces a sum bit and a
carry bit as output is known as a full-adder.
 In other words, a combinational circuit which is designed
to add three binary digits and produces two outputs (sum
and carry) is known as a full adder. Thus, a full adder
circuit adds three binary digits, where two are the inputs
and one is the carry forwarded from the previous
addition.

2
Characteristic Equations of Full Adder

The characteristic equations of the full adder, i.e equations of

sum (S) and carry output (Cout) are obtained according to the

Sum, S=A⊕B⊕C=A′B′+A′BC′+AB′C′+ABC
Truth Table:-
Sum, S=A⊕B⊕C=A′B′C+A′BC′+AB′C′
+ABC Carry, Cout =AB+AC+BC
A B C Sum Carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

2
Full Subtractor:-

 A Full Subtractor is a combinational logic circuit which

performs a subtraction between the two 1-bit binary
numbers and it also considers the borrow of the previous
bit i.e., whether 1 has been borrowed by the previous
minuend bit.
 So, a Full Subtractor has three inputs, in which two
inputs corresponding to the two bits to be subtracted
(minuend A and subtrahend B), and a borrow bit, usually
represented as Bin, corresponding to the borrow
operation. There are two outputs, one corresponds to the
difference D output and the other Borrow output Bo.

2
Characteristic Equations of Full Subtractor

The characteristic equations of the full subtractor, i.e.

equations of the difference (d) and borrow output (b) are
obtained by following the rules of binary subtraction.

Difference, d=A⊕B⊕bin d=A′B

Truth Table:-
′bin+AB′b′in+A′Bb′in+ABbin
Borrow, b=A′B+(A⊕B)′bin
A B C Difference Borrow
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

2
Binary to Grey Code Convertor

Formula:-
𝐺𝑛−1 = 𝐵𝑛⊕𝐵𝑛−1

Grey Code to Binary Convertor

Formula:-
𝐵𝑛−1 = 𝐵𝑛⊕𝐺𝑛−1

Note:- In both the cases Most significant bit (MSB) will

remain same.

2
2 Bit Adder Circuit :-

Truth Table:-

2
Observation:-

2
3
Conclusion:-

We have verified the truth table of Full adder and Subtractor.

We have also verified the truth table of BCD to grey code
convertor and vice versa. We also made two bit adder circuit.

*-*-*-*-*

3
 Indian Institute of Information
Technology
Vadodara,International
Campus Diu

Name: Ayush kumar

Roll Number: 202211008
Batch: Computer Science and
EngineeringBatch: 2022
Session:
2023-24
Subject:EC26
1
Components
Required :-1] AND
gate(7408)
2. OR gate(7432)
3. XOR gate(7486)
4. NOT gate(7402)
5. Connecting wires
6. Breadbo
a rd
Theory:-

2 Bit Comparator
A magnitude comparator is a circuit that compares 2 binary
numbers in order tofind out whether those 2 numbers are equal
or first number is less than second number or second number is
less than first number.
We logically design a circuit that takes 2 input for A and 2 input
for B and givesone output for A<B or A=B or A>B.
Characteristic equation:-
A>B: A1(B1’)+A0(B1’B0’)
+A1A0(B0’)A<B:
A1’B1+B0’B1B0+A1’A0’B0
A=B: (A0 XOR B0)’(A1 XOR
B1)’

A1 A0 B1 B0 A>B A=B A<B

0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
 1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0

2*1 Multiplexer

In 2*1 MUX, there are only 2 inputs, 1 selection pin and a single
output on basis of the combination of input which are present at
selection line. So, one of these 2 input will be connected to
output. A 2-to-1 multiplexer consists of two inputs A0 and A1,
one select input S and one output Y. Depending on the select
signal, the output is connected to either of the inputs. Since
there are two input signals, only two ways are possible to
connect the inputs to the outputs, so one select is needed to do
these operations. When the select line is low, the output is
switched to the D0 input; when the select line is high, the output
is switched to the D1 input.

Logical
expressionY=
S0’A0+S0A1
4*1 Multiplexer
The 4x1 multiplexer has four data inputs I3, I2, I1 and I0, two
select lines s1 and s0 and one output Y. The block diagram
of the 4x1 multiplexer is shown in the following figure.

S1 S0 I1 I2 I3 I4 Output
0 0 0 x x x 0
0 0 1 x x x 1
0 1 x 0 x x 0
0 1 x 1 x x 1
1 0 x x 0 x 0
1 0 x x 1 x 1
1 1 x x x 0 0
1 1 x x x 1 1

Logical Expression:-
Y=S1ʹS0ʹI0+S1ʹS0I1+S1S0ʹI2
+S1S0I3
4*2 Encoder
An encoder is a digital circuit that converts a set of binary
inputs into a single binary code. Binary code represents the
position of an input and is used to identify the specific input
that is active.
The 4 to 2 encoder consists of four inputs Y3, Y2, Y1 and Y0
and two outputs A1 and A0. At any given time, only one of
these four inputs can be “1” to get the corresponding binary
code as output. The figure below shows the logic symbol of a 4
to 2 encoder.

INPUTS OUTPUTS

Y3 Y2 Y1 Y0 A1 A0

0 0 0 1 0 0

0 0 1 0 0 1

0 1 0 0 1 0

1 0 0 0 1 1

Logical
Expression:-A1
= Y3 + Y2
A0 = Y3 + Y1
2*4 Decoder
The 2*4 decoder has two inputs A1 and A0 and four outputs Y3,
Y2, Y1 and Y0. The functional diagram of 2 to 4 decoders is shown
in the following figure.

Enable Inputs Outputs

E A1 A0 Y3 Y2 Y1 Y0
0 x x 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0

Logical
expression:
-
Y3=EA1A0
Y2=EA1A0’
Y1=EA
A0’
Y0=EA1’
A0’
Conclusion: - Verified the truth table of a 2-bit comparator,
verified the truth table of a 4*1 MUX using a 2*1 MUX, and
also created a 4*2 encoder and a 2*4 decoder.
Indian Institute of Information Technology,
Vadodara International Campus Diu IIITV-
ICD

Practical Work Book

Name: Ayush
kumar Roll:
202211008
Branch: CSE
Batch: 2022
Subject: EC261
Session: 2022-23
 Certificate
This is to certify that Mr. Ayush Kumar of B-Tech batch 2022
Semester 3 Enrollment No. 202211008 Branch CSE hasbeen
found satisfactory in the continuous internal evaluation of the
laboratory, practical and term work in the subject EC261 for
the academic year 2022– 2023.

Date: 18/10/2023 Sign of Faculty

 List of
experiment

Sr Aim of Date of Date of Pa Teach

. experime performan submissio ge er
No nt ce n no sign
1 Design 18/10/2023 25/10/2023 4-9
(a)JK,SR, D
latch using
logic gate
(b) JK to SR
flip flop
conversio
n andvice
versa
(c) JK to D
andT flip
conversion
 Lab: 5
Date: 18/10/2022

Aim:
Design the following

(a) JK, SR, D latch using logic gate

(b) JK to SR flip flop conversion and vice versa

(c) JK to D and T flip

Components required:
Breadboard, IC, LED, wires,voltage source(+5V), Logisim software

Latch:

A Latch is a special type of logical circuit. The latches have low and high
two stablestates. Due to these states, latches also refer to as bistable-
multivibrators. A latchis a storage device that holds the data using the
feedback lane. The latch stores 1 - bit until the device set to 1. The latch
changes the stored data and constantly trials the inputs when the enable input
set to 1.

Jk Latch:

The JK Latch is the same as the SR Latch. In JK latch, the unclear states
are removed, and the output is toggled when the JK inputs are high. The
only difference between SR latch JK latches is that there is no output
feedback towards the inputs inthe SR latch, but it is present in the JK latch.

SR Latch:

The SR latch is a special type of asynchronous device which works

separately forcontrol signals. It depends on the S-states and R-inputs.
The SRlatch design by
connecting two NOR gates with a cross loop connection. The SR
latch canalso bedesigned using NAND gates

D Latch:
The D latch is the same as D flip flop. The only difference between these two
is theENABLE input. The output of the latch is the same as the input passed
tothe Data input when the ENABLE input set to 1. At that time, the latch is
open,and the path is transparent from input to output. If the ENABLE input is
set to 0, the D latch's output is the last value of the latch, i.e., independent from
the input D, and thelatch is closed.

Flip Flops:
Flip flop is a circuit that maintains a state until directed by input to change
the state.A basic flip flop can be constructed using four NAND or four NOR
gates.

JK Flip-flops:
The JK Flip Flop is a gated SR flip-flop having the addition of a clockinput
circuitry. The invalid or illegal output condition occurs when both of the
inputsare set to 1 and are prevented by the addition of a clock input circuit.
So, the JKflip- flop has four possible input combinations, i.e., 1, 0, "no
change" and "toggle".

SR Flip-flops:
The SR flip flop is a 1-bit memory bistable device having two inputs, i.e., SET
and RESET. The SET input 'S' set the device or produce the output 1, and the
RESET input 'R' reset the device or produce the output 0. The SR flip flop
stands for "Set-Reset" flip flop. The reset input is used to get back the flip flop
toits original state from the current state with an output 'Q'. This output depends
on the set and reset conditions, which is either at the logic level "0" or "1".

D Flip-flop:
It ensures that at the same time, both the inputs, i.e., S and R, are never equal to
1. The Delay flip-flop is designed using a gated SR flip-flop with an inverter
connected between the inputs allowing for a single input D(Data). This single
data input, which is labeled as "D" used in place of the "Set" input and for the
complementary "Reset" input, the inverter is used. Thus, the level-sensitive D-
type orD flip flop is constructed from a level-sensitive SR flip flop.

T Flip-flop:
The T flip-flop is also called toggle flip-flop. It is a change of the JK flip-
flop.The T flip flop is received by relating both inputs of a JK flip-flop. The
T flip-flop is received by relating the inputs 'J' and 'K'. When T = 0, both
AND gatesare disabled.
Observations:
(a) JK Latch

Truth Table:

J K Q Q’
0 0 Memory
0 1 0 1
1 0 1 0
1 1 Memory

(b) SR Latch

Truth table :

Enabl S R Q Q’
e
0 X X Memor
y
1 0 0 Memor
y
 1 0 1 0 1
1 1 0 1 0
1 1 1 0 0

(c) D Latch

Truth Table:

Enabl D Q Q’
e
0 X Memor
y
1 0 0 1
1 1 1 0

(d) JK to SR 9lip 9lop conversion:

Conversion Equation : J= S and
K=RCircuit Diagram:
Truth Table:

S R Qn Qn+1 J K
0 0 0 0 0 X
0 0 1 1 X 0
0 1 0 0 0 X
0 1 1 0 X 1
1 0 0 1 1 X
1 0 1 1 X 0
1 1 0 X X X
1 1 1 X X X

(e) JK to D 9lip 9lop conversion:

Conversion Equation: J= D and K=
D’Circuit Diagram:

Truth Table:

D Qn Qn+ J K
1
0 0 0 0 X
0 1 0 X 1
1 0 1 1 X
1 1 1 X 0

(f) JK to T 9lip 9lop conversion:

Conversion Equation : J=T and K=T
Circuit Diagram:

Truth Table:

T Qn Qn+ J K
1
0 0 0 0 X
0 1 1 X 0
1 0 1 1 X
1 1 0 X 1

Conclusion:
We have successfully created and verified the truth table of JK,SR
and D latch.
We have also converted JK flip flop to SR, D, T flip-flops and
viceversaand verified their respective truth table.

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