International Journal of

Electrical and Electronics Research (IJEER)

Open Access | Rapid and quality publishing Research Article | Volume 10, Issue 2 | Pages 341-346 | e-ISSN: 2347-470X

Design and Leakage Power Optimization of 6T Static

Random Access Memory Cell Using Cadence Virtuoso
Sufia Banu1 and Shweta Gupta2
1
Research Scholar, Department of ECE, Jain University, Bangalore, India, [email protected]
2
Associate Professor, Department of ECE, Jain University, Bangalore, India, [email protected]

*Correspondence: Sufia Banu; E-mail: [email protected]

░ ABSTRACT- Reduction of Leakage power at nano meter regime has become a challenging factor for VLSI designers. This
is owing to the need for low-power, battery-powered portable pads, high-end gadgets and various communication devices. Memories
are made up of Static RAM and Dynamic RAM. SRAM has had a tremendous impact on the global VLSI industry and is preferred
over DRAM because of its low read and write access time. This research study proposes a new method has been proposed of 6T
Static Random Access Memory cell to decrease the leakage current at various technologies. Three source biasing methods are used
to minimize the 6T SRAM cell leakage power. The three methods are NMOS diode clamping, PMOS diode clamping and NMOS-
PMOS diode clamping at 45 nm and 90 nm technology nodes. This paper also emphasizes on the implementation of 6T SRAM cell
using Multiple Threshold CMOS (MTCMOS) technique at 45nm technology. The simulation is achieved and various power
dissipations are analyzed at supply voltage of 0.9 V and 0.45 V for 90 nm and 45 nm technology respectively using cadence virtuoso
tool. PMOS clamping has shown the reduction in an average power by 82.19% than compared to other two proposed techniques.

Keywords: Clamping diode, Forward body bias, Low Power, MTCMOS, Reverse body bias, Source biasing.

ARTICLE INFORMATION An Integrated Circuit is made up off combinational devices,

Author(s): Sufia Banu and Shweta Gupta sequential devices, memory units and input-output devices.
Each circuit in an IC contributes to the total power dissipation.
Special Issue Editor: Dr. S. Muthubalaji
Received: 20/05/2022; Accepted: 16/06/2022; Published: 30/06/2022;
The portable battery-operated devices such as cell phones had a
e-ISSN: 2347-470X; single core processor. With advancement in technology
Paper Id: 0322SI-IJEER-2022-26; transistor density is increased with octa-core processors. Static
Citation: 10.37391/IJEER.100246 RAM used in portable battery powered devices needs lower
Webpage-link:
https://ijeer.forexjournal.co.in/archive/volume-10/ijeer-100246.html
area and parallel lower power consumption [1]. Static RAM
used in embedded controllers requires less read and write time.
This article belongs to the Special Issue on Intervention of Electrical,
Electronics & Communication Engineering in Sustainable Development
Due to the significant increase of lower power and lower
voltage memory systems in recent years, SRAM has been
Publisher’s Note: FOREX Publication stays neutral with regard to
jurisdictional claims in Published maps and institutional affiliations.
emphasized in the research sector. On-chip memory is built
utilizing arrays of tightly packed Static RAM cells to provide
increased quality. As a memory cell, a 6T Static Random
░ 1. INTRODUCTION Access Memory (SRAM) is commonly utilized. The two most
In the past, performance and miniaturization of an integrated common kinds of power dissipation in an electronic circuit
device was the major design concern of a VLSI designer. include Switching power and Static power dissipation. During
Technologies scaling from micro meter regime to nano meter the active mode of performance, when the device is under ON
regime yields in increased integration density referring to more state, the power dissipation is majorly because of both
number of semiconductor devices that are significantly smaller switching power and static components of the semiconductor.
and quicker are embedded onto a single tiny piece of chip. This While during the standby mode or sleep mode of operation,
scaling is done to provide quicker speed and a greater operating when the device is under OFF state, standby leakage current is
frequency, resulting in increased power dissipation. With the responsible for the power dissipation. With technology scaling
growing popularity of portable battery-operated gadgets, power the leakage power is dominating that the dynamic power and
dissipation has become a crucial concern as these devices spend hence is of major design concern to the VLSI designers as most
majority of the time in standby or sleep mode. Proper heat sinks of the portable devices are battery operated [2].
are also necessary to dissipate the power in right manner in a
circuit. Power dissipation also has an impact on packaging and
reliability. Earlier days these battery-operated handheld gadgets
░ 2. MAJOR LEAKAGE CURRENT
had lower computing performances yielding to reduced power COMPONENTS
dissipation, while technology scaling led to higher performance There are numerous origins of leakage current for nanometer
than the non-portable devices. It is the need of an hour to devices, which includes low threshold voltage causes
prolong the life of the battery of these battery-operated portable subthreshold leakage current, extremely thin gate oxides cause
gadgets and it’s challenging for the circuit designers. gate leakage current, and the heavily doped halo causes Band-
To-Band Tunneling (BTBT). [3].

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 International Journal of
Electrical and Electronics Research (IJEER)
Open Access | Rapid and quality publishing Research Article | Volume 10, Issue 2 | Pages 341-346 | e-ISSN: 2347-470X

2.1 Sub-threshold Leakage Current 3.1 Body Biasing Scheme

Subthreshold leakage occurs while the transistor is under weak The sub-threshold leakage current fluctuates exponentially as a
inversion region of operation i.e. when gate to source potential function of device’s threshold voltage (𝑉𝑡ℎ ). This is adopted to
of a semi-conductor is lesser than its threshold voltage i.e. decrease the propogation delay and leakage current to a greatly
𝑽𝒈𝒔 <𝑽𝒕𝒉 as well it is majorly comprised of diffusion current [4]. by varying the threshold voltage. Body bias alters the 𝑉𝑡ℎ by
The two major subthreshold paths in 6T SRAM cell are from applying the voltage across source and substrate terminal of a
VDD to the GND and bitlines (BL, BLB) to the GND. MOS device. The MOS transistor threshold voltage is related to
source to substrate voltage as shown in Eq. (1) [13].
2.2 Gate Leakage Current
In the nanoscale era, excessive technology scaling amplifies 𝑉𝑡ℎ = 𝑉𝑡𝑜 + 𝛾√∅𝑠 + 𝑉𝑠𝑏 − √∅𝑠 (1)
Short Channel Effects (SCE) which includes 𝑉𝑡ℎ roll-off and
Drain Induced Barrier Leakage (DIBL). Each technological Where 𝑉𝑡ℎ is the threshold potential of semiconductor device,
generation must scale the oxide thickness (Tox) to manage the 𝑉𝑡𝑜 is the threshold potential at zero body-bias, γ is the body
SCE. Excessive miniaturization of Tox results in a large electric effect factor, 𝑉𝑠𝑏 is the voltage across source and substrate and
field, which leads to a large direct-tunneling current along the 𝜑𝑠 is the surface potential.
semiconductor’s gate insulator [5]. Gate oxide tunneling current
Reducing the voltage between source and substrate (𝑉𝑠𝑏 ), 𝑉𝑡ℎ
refers to the tunneling of electrons or holes through a
voltage of the device decreases thereby increasing the
semiconductor's gate oxide. The three important gate leakage
performance of a device. By increasing the potential across
processes in semiconductor device are tunneling in the Electron
source and substrate ( 𝑉𝑠𝑏 ), 𝑉𝑡ℎ of device increases thereby
Conduction Band (ECB), Electron Valence Band (EVB), and
reducing the leakage current across OFF transistors [13].
Hole Valence Band (HVB). In ECB, electrons tunnel from the
substrate's conduction band to the gate's conduction band and In passive CMOS, the substrate terminal of PMOS is wired to
vice versa. In EVB, tunneling of electrons takes place from the VDD and substrate terminal of NMOS is wired to GND. Source
substrate's valence band to the gate's conduction band. In HVB, to substrate (bulk) potential can be a non-zero value by adopting
holes tunnel from the substrate's valence band to the gate's various body biasing schemes such as Forward Body Bias
valence band and vice versa. (FBB), Reverse Body Bias (RBB), DTMOS, VTMOS. Body
biasing scales the threshold voltage of the device while supply
2.3 Junction Leakage Current voltage is kept constant. Body biasing either increases or
The semiconductor Metal Oxide Semiconductor (MOS) device decreases the 𝑉𝑡ℎ of the device. The FBB enhances the
comprises of two PN junctions i.e. drain region to well and performance (decreases the delay) by decreasing the 𝑉𝑡ℎ of the
source region to well. PN junction leakage current occurs when device. The RBB minimizes the leakage current by boosting the
these junctions are reverse biased. When ‘P’ and ‘N’ junctions 𝑉𝑡ℎ of the device. Hence by smartly choosing both the delay and
are doped heavily results in BTBT tunneling while it also leakage current of the semiconductor can be decreased. The
dominates PN junction leakage current [6]. Junction leakage is body bias can also characterized as fixed, variable and dynamic
typically smaller than compared to other sources of leakage depending on the application [14]. A set forward or reverse bias
currents and it exists across the access transistors of SRAM cell voltage is placed across the transistor's substrate terminal in a
[7]. Fixed Body Bias configuration. Different bias voltages are used
in variable and dynamic body bias. Body bias voltages must be
░ 3. LEAKAGE CURRENT REDUCTION generated by an extra control circuitry called a Body Bias
TECHNIQUES Generator in variable and dynamic body bias systems (BBG).
Various leakage power reduction techniques have been
proposed by researchers at the device, circuit, and architectural 3.2 Source-biasing Scheme
levels. At device level the leakage power is reduced by scaling Source biasing approach is employed to reduce leakage by
the channel length, junction depth, oxide thickness [8-10]. utilizing an additional clamping circuitry in line with the pull
Researchers have come up with newer transistor structure such down NMOS semiconductor to accomplish data retention. In
as Fin-shaped FET (FINFET) having two or more gates between SRAM cell's source lines and GND, a high threshold
resulting in lower short channel effect and lower subthreshold voltage NMOS transistor is introduced. [15]. The gate terminal
leakage current. At circuit level various leakage reduction of NMOS transistor is latched to the WL (word line) as
techniques include DMOS, VTMOS, MTCMOS, STACKING illustrated in Figure 5.
(forced stack, sleep stack, lector, galore, sleepy keeper, and
During the active mode, WL goes logic high which tunes ON
zigzag keeper), source biasing, body biasing, drain gating and
NMOS transistor. The SRAM device functions conventionally
many more [2]. At architectural level techniques include
since resistance is very small thereby the virtual ground (VSL)
multiple modes management which puts the unutilized memory
more or less functions as normal ground. During the standby
in sleep mode or standby mode thereby reducing leakage
mode, the WL goes low which turns OFF the NMOS transistor,
current which allows only a small part of the memory to be ON
results in decreasing the gate leakage and sub threshold leakage
[11-12].
current. Drawback by using an extra NMOS transistor in the
pull down network is that it increases dynamic energy, delay

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 International Journal of
Electrical and Electronics Research (IJEER)
Open Access | Rapid and quality publishing Research Article | Volume 10, Issue 2 | Pages 341-346 | e-ISSN: 2347-470X

and area. The pull-down semiconductor is frequently shared

with a bank of SRAM cells to save space. During the standby
when NMOS pull down transistor is turned off results in virtual
ground where VSL charges up to floating positive potential. This
makes SRAM device more vulnerable to noise. To overcome
this problem, an additional PMOS semiconductor device is
introduced parallel to it, shorting the gate with drain terminals Figure 2: Cross Coupled Inverters (Basic bi stable element)
of PMOS makes a clamping diode as shown in figure 7.

3.3 Dynamic Threshold MOS (DTMOS)

Leakage reduction is attained by changing the threshold voltage
𝑉𝑡ℎ of a device dynamically called as DTMOS. In this, the gate
and substrate terminals are tied together [16]. Due to this
configuration, threshold voltage is dynamically changed as the
substrate voltage is varied with the input gate voltage V IN. Low
𝑉𝑡ℎ is used in active mode, resulting in improved speed,
whereas high 𝑉𝑡ℎ is used in standby mode, resulting in lower
static current. Figure 3: Conventional 6T SRAM Cell

This demonstrates that in any stable circumstance, the outputs

3.4 Multiple Threshold MOS (MTCMOS) of two inverters are complimentary. This attribute is used to
create Static Random Access Memory cell (SRAM) cell. Two
cross coupled inverters make up a traditional 6T SRAM
memory cell which forms four CMOS transistors
(M1,M2,M3,M4) which acts as memory and 2 access
transistors formed by M5 and M6 which serves to regulate the
cell while performing read and write operation as illustrated in
figure 3. The access transistors are controlled by the word line
WL, which is connected to the bit lines BL and BLB, providing
access to the cell. The bit lines are used to transport data to and
Figure 1: Multiple Threshold MOS Variation with Leakage Current from the memory during write and read operations.

This technique makes use of multiple threshold voltages high The cell's three phases of operation are as mentioned below
and low threshold voltages 𝑉𝑡ℎ to optimize power and delay as [19].
shown in figure 1. High threshold transistor switch slower
thereby reduces the leakage power. While low threshold Read Operation: During this, bit lines (BL and BLB) act as
transistors switch faster but have high leakage power. output lines and both are pre-charged with certain voltage
MTCMOS makes use of high threshold voltage transistors normally Vdd/2 (logic 1). When the word line is asserted, both
known as sleep transistors. During the active mode of operation, the access transistors M5 and M6 linked to the bit lines are
these are ON and the circuit will behave normally. While in enabled, causing the bit-line voltages to decrease slightly. The
sleep mode, these transistors are OFF thereby reducing the output of these bit line voltages is send to sense amplifier which
leakage power [17]. These sleep transistors aims in reduction of acts as an op amp comparator. It compares the difference
standby leakage power to larger extent during the OFF state of between BL and BLB. If voltage across BL>BLB, it outputs a
SRAM cell logic 1 and if voltage across BL<BLB, it outputs a logic 0. The
advantage of using a sense amplifier is that it sets the output
░ 4. CONVENTIONAL 6T SRAM CELL quickly without fully charging or discharging.
Static RAM memory cells are made up of two inverters that are Write Operation: Bit lines act as input lines during the write
cross coupled as seen in Figure 2 [18]. The inverter2’s output process. The value that is to be written into the cell is provided
(Q’) is connected to the inverte1’s input (A). When the voltage by these bit lines. The word line will be asserted to logic high
transfer characteristics of the first inverter (VoA v/s ViA) are to access the bitlines i.e. WL=1. If logic 1 is to be written, bit
compared with those of the second inverter (VoB v/s ViB), line bar is loaded to supply rail VDD while bit line is discharged
three alternative operating locations (A, B, and C) are obtained. to low potential, and Word line is asserted, resulting in
Because the loop gain is less than one, the operation points A successful data (logic 1) writing into the cell. If logic 0 is to be
and B are stable. Inverter one's output is high, while inverter written, BLB is discharged to ground potential, while BL is
two's output is low, as shown in point A. Inverter one's output loaded to VDD and Word line is asserted, resulting in successful
is low, but inverter two's output is high, as seen in point B. data (logic 0) writing into the cell.

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 International Journal of
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Open Access | Rapid and quality publishing Research Article | Volume 10, Issue 2 | Pages 341-346 | e-ISSN: 2347-470X

Hold Operation: During the hold or ideal state, the word line By adding an extra high 𝑉𝑡ℎ NMOS transistor between the
is not connected i.e. WL=0 which does not turn on the access SRAM cell's source line 𝑉𝑠𝐿 and Ground (GND), leakage current
cells M5 and M6. This open circuits the cross coupled inverter across a 6T SRAM cell is considerably decreased. During active
from the bit lines (BL, BLB) and thereby the data is held in the state, word line is activated (WL=1) which turns ON the NMOS
memory cell. Hence is it said to be in hold state or ideal state as transistor and the SRAM cell behaves normally, since the
data is held in the latch mode. As long as the semiconductor is resistance is smaller across the circuit. During the standby state,
connected to the power source, it will continue to store the data. word line is deactivated (WL=0) which turns OFF the NMOS
transistor thereby the source line (𝑉𝑠𝐿 ) will be raised to greater
░ 5. PROPOSED 6T SRAM CELL potential that results in decreasing the subthreshold leakage
6T SRAM cell is implemented employing Cadence virtuoso current and gate leakage.
software is as shown in figure 4 at 90vnm and 45 nm technology
nodes and various power parameters such as average power and
leakage power are calculated. The idea for this implementation
shows three different methods to minimize the leakage current
in 6T SRAM cell. The traditional 6T SRAM device is as
depicted in figure 4. The proposed work employs clamping of
a) one extra high 𝑉𝑡ℎ NMOS transistor as shown in figure 5, b)
one extra high 𝑉𝑡ℎ PMOS transistor as shown in figure 6 c) a
pair of high 𝑉𝑡ℎ NMOS-PMOS transistors in between the
source terminal and ground of SRAM cell as shown in figure 7.
The schematic of standard 6T SRAM cell is shown in figure. 4
that comprises of two cross coupled inverters along with two
access transistors thereby forming six transistors.

Figure 6: Conventional 6T SRAM Cell Schematic with PMOS

Clamping Diode

During the standby when NMOS pull down transistor is turned

off results in virtual ground where 𝑉𝑠𝐿 will be charges up to
floating positive potential. The SRAM cell becomes more
vulnerable to noise as a result of this. To overcome this issue,
an additional PMOS cell is introduced in parallel to it, shorting
the gate and drain terminals of PMOS makes a clamping diode
as given in figure 7. A high 𝑉𝑡ℎ PMOS cell is added between
the source terminal and ground terminal of SRAM cell instead
Figure 4: Conventional 6T SRAM Cell Schematic in Cadence of NMOS transistor as shown in figure 6.

Figure 5: Conventional 6T SRAM Cell Schematic with NMOS

Clamping Diode
Figure 7: Conventional 6T SRAM Cell Schematic with NMOS-
PMOS Clamping Diode

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A pair of NMOS and PMOS high threshold voltage transistors standby (Sleep) mode, these high 𝑉𝑡ℎ sleep devices are turned
inserted in parallel between the source terminal and ground OFF while the conduction path that may arise from low 𝑉𝑡ℎ
terminal of SRAM cell is as depicted in figure 7. The transient SRAM device is smartly cutoff thereby reducing the leakage
analysis of 6T SRAM device is as shown in figure 8. The test current.
schematic where the voltages are applied the inputs WL, BL and
BLB is as available in figure 9. The symbol of 6T SRAM cell
which is generated from the schematic is as shown in figure 10.

Figure 8: Transient Analysis of 6T SRAM Cell

Figure 11: 6T SRAM MTCMOS Test Schematic

░ 6. RESULTS AND DISCUSSION

Table 1 describes the average power of standard 6T Static
Random Access Memory cell with proposed techniques having
NMOS clamping, PMOS clamping and NMOS-PMOS
clamping. PMOS clamping has shown the reduction in an
average power by 82.19% than compared to other two proposed
techniques.

Table 2 describes the dynamic power of standard 6T Static

Random Access Memory cell with proposed techniques having
NMOS clamping, PMOS clamping and NMOS-PMOS
Figure 9: 6T SRAM Test Schematic clamping. Table 3 describes the leakage power of standard 6T
Static Random Access Memory cell with proposed techniques
having NMOS clamping, PMOS clamping and NMOS-PMOS
clamping. PMOS clamping shown the best results compared to
NMOS and NMOS-PMOS clamping. The leakage power
analysis of 6T SRAM cell obtained by applying MTCMOS
method is as given in table 4. The average power is reduced to
about 92% using MTCMOS technique, thereby reducing the
leakage power.

░Table 1: Average Power Analysis of 6T SRAM Cell

6T_SRAM
Figure 10: 6T SRAM Symbol 6T_SRAM 6T_SRAM
Technology 6T SRAM NMOS
NMOS PMOS
PMOS
Multiple Threshold CMOS (MTCMOS) of 6T SRAM cell is as
90nm 9.66E-08 4.99E-08 1.72E-08 5.36E-08
given in figure 11. Two additional high 𝑉𝑡ℎ transistors known
as sleep transistors are used. A high 𝑉𝑡ℎ PMOS cell is added 45nm 1.25E-10 5.43E-11 1.98E-11 5.39E-11
across the PUN and supply voltage and a high 𝑉𝑡ℎ NMOS cell
is placed across the PDN & ground terminal. MTCMOS makes ░Table2: Dynamic Power Analysis of 6T SRAM Cell
use of two threshold voltages in a circuit to obtain higher 6T_SRA 6T_SRAM
6T_SRAM
performance and lower leakage. During the active mode, these Technology 6T SRAM M NMOS
NMOS
PMOS PMOS
high 𝑉𝑡ℎ sleep transistors are turned ON and low 𝑉𝑡ℎ SRAM cell
90nm 8.01E-08 4.49E-08 1.72E-08 4.84E-08
operates normally with small propagation delay. During the 45nm 1.23E-10 5.29E-11 1.83E-11 5.23E-11

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Electrical and Electronics Research (IJEER)
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Website: www.ijeer.forexjournal.co.in Design and Leakage Power Optimization 346