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Data Acquisition Fundamentals

Chapter · January 2012

DOI: 10.1201/b11093-23

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 19 Data Acquisition Fundamentals
David Potter and Halit Eren

Partial List of Suppliers shows a simplified block diagram of a typical multifunc-

tion device commercially available from several vendors. It
Analog Devices (http://www.analog.com/en/index.html), includes one or more analog-to-digital converters (A/Ds or
Fairchild Semiconductors (http://www.fairchildsemi. ADC) with accompanying signal conditioning, one or more
com/), Intersil (http://www.intersil.com/cda/home/), Linear digital-to-analog converters (D/As or DAC), digital input/
Technology (http://www.linear.com/), Maxim Integrated output circuitry, and a timing controller.
Products (http://www.maxim-ic.com/), Microchip (http:// This chapter begins by explaining the basic concepts of
www.microchip.com/), (National Semiconductors (http:// A/D and D/A conversion and the circuits used to carry them
www.national.com/analog), Sony (http://www.sonyc- out. Also, in addition to A/D and D/A conversions, other
sbd.com/), Thaler Corp (http://www.thaler.com/), Texas indispensable operations, such as signal conditioning and
Instruments (http://www.ti.com/). timing controllers, as well as the extremely important soft-
ware, are required components of an effective DAQ system.

Introduction
A/D and D/A Signal Converters
Over the last several years, the use of computers and micro-
processor-based equipment to measure, control, and test At the heart of the DAQ system is data conversion, the pro-
processes and equipment have become the norm, including cess of converting analog signals into digital formats, and
process, manufacturing industries, and automation. One par- vice versa. The conversion is carried out in two steps: first the
ticular area that has been revolutionized by the rapid tech- signal is quantified and later it is codified. Quantifying means
nological evolution of the PC is the data acquisition (DAQ), representing the continuous values of the analog signal using
commonly also referred to as DAQ. Today, PC-based DAQ a set of discrete values, and codifying means representing
systems are able to tackle a much wider and broader range of these discrete values by bit sequences. The number of bits
applications as predicted by Moore’s Law on the continual of these sequences determines the number of possible values
increase in performance-to-price ratio of PC technologies. of the conversion: 2 n for n bits. As an example, Figure 19.3
This chapter reviews the fundamental concepts of DAQ both illustrates the digitization of a 10 V waveform with 3 bits of
from hardware and software technologies’ point of view. resolutions.
DAQ is defined as the general process by which phenom- A/D and D/A provide the interface between the analog
ena from the real world is captured and recorded in digital world (the real world) and the world of digital computation
format. The basic elements of a computer-based DAQ system and data processing. Many of the applications for analog–
are shown in Figure 19.1. The majority of process equipment, digital interfaces are quite evident as we use them in our
such as sensors and transducers and final control elements, daily lives. Temperature controllers, computers and related
are analog devices and they generate or operate on analog peripherals, electronic fuel injection, and compact disc music
electrical signals. Generally speaking, DAQ hardware per- systems are just a sample of the typical applications that
forms the conversion from analog-to-digital signals, and vice require analog–digital interfaces.
versa. More often than not, the DAQ device works in con- The electronic circuit of A/D carries out the quantifica-
junction with a computer, such as the standard PC. The com- tion and codification processes. The A/D operates with sig-
puter in this figure runs DAQ software that processes and nals of determined amplitude, for example, between −SV and
records the data. +SV. Another electronic circuit of D/A carries out the con-
The DAQ devices can take many different forms and version from digital signals into analog signals. This device
implementations. Most of these devices not only incorporate converts digital codes of n bits into a signal of 2n discrete
analog input capabilities, but also include provisions for gen- levels of voltage or current. We will look at D/A first as they
erating analog outputs, digital inputs and outputs, and vari- are typically simpler than A/Ds and are often utilized as a
ous counting and timing functions. Figure 19.2, for example, component within an A/D.

330

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 19 Data Acquisition Fundamentals 331

Physical Data aquisition Controller Data acquisition

Transducers
phenomena hardware (PC) software

Electrical Bus or
signal network

Fig. 19.1
Basic elements of a DAQ system.

Data acquisition hardware

Signal
conditioning A/D converter
Analog (ADC)
Input from and
sensors Digital multiplexing
(discrete)

Digital I/O Controller/

circuitry computer

D/A converter
Output to Analog (DAC)
controls Digital
(discrete)
Timing controller

Fig. 19.2
Block diagram of multifunction DAQ device.

3 Bit resolution
10.00
111
8.75
110
7.50
= 1 Code width
Amplitude (v)

101
6.25
100
5.00
011
3.75
010
2.50
001
1.25
000
0
0 50 100 150 200
Time (µs)

Fig. 19.3
Quantization of analog waveform with 3 and 16 bit converter.

Digital-to-Analog Converters For example, Figure 19.4 shows a typical design of a sim-
ple n-bit D/A, referred to as an R-2R ladder D/A. The set of
A D/A is an integrated circuit (IC) device, which converts latches holds the binary number, which is to be converted to
an n-bit digital word to an equivalent analog voltage. DAQ an analog voltage signal. The output of each latch controls
systems often include D/As in order to generate analog sig- a transistor switch, which is associated with a determined
nals for control, reference signals, stimulus signals, and so resistor in the resistor network. The voltage reference, which
on. Most D/As utilize some combination of a resistive or is connected to the resistor network, controls the range of the
capacitive network, a switching network, and a summing output voltage. The operational amplifier works as an adder
amplifier. circuit.

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 332 Digital Techniques and Data Handling

Latches R Because it is generally easier to sum currents using ana-

log circuitry, many D/As utilize current sources, rather than
Dn–1 2R a voltage reference, and generate a current output that is the
Vout weighted summation of currents.

D/A Characteristics

While there are many important specifications that charac-

D2 terize the performance of a D/A, the following are a few key
2n–2 R
parameters to consider:
Range: The output range of the D/A is the span of voltages,
D1 2 n–1 R or currents, over which the D/A can generate an output. For
example, typical ranges for a voltage output D/A are 0–5,
0–10, ±5, and ±10 V.
D0 2n R Resolution: This is the number of bits used in the digital cod-
ing of the value to be converted to an analog signal. The reso-
lution determines the dynamic range of the output signal. For
example, a 12 bit D/A can generate a total of 2 n = 212 = 4096
Vref
unique output values. If a 12 bit D/A is configured with an
output range of 0–5 V, then the D/A can generate a change in
voltage output as small as 5 V ÷ 4096 = 1.22 mV. Most com-
mercial DAQ products today utilize D/As with 8, 12, or 16
Fig. 19.4
Basic D/A design. bits of resolution.
Settling time: Settling time determines how rapidly a D/A can
change its output signal to a new value when the digital input
The operation of the D/A converter is as follows:
changes, as shown in Figure 19.5. Most D/As specify settling
time as a full-scale change in voltage, from the smallest out-
1. Switches set the digital word, that is, switch is closed
put value to the largest. A D/A with a small settling time can
for logic ONE and switch is grounded for logic ZERO.
generate high-frequency signals because an accurate voltage
2. The weighted resistors determine the amount of volt-
level can be obtained in a very small time.
age Vout at the output.
Linearity: Linearity specifies the maximum deviation of
For each one of the resistors in the network, when its corre- the D/A’s transfer curve from an ideal straight line, usually
sponding switch is on, the operational amplifier adds a volt- expressed as a fraction of the full-scale reading, as shown in
age to Vout, which is inversely proportional to the value of the Figure 19.5b.
resistor and directly proportional to the reference voltage and
Monotonicity: If a D/A is monotonic, the output always
the feedback resistor (R). For example, for the 2R resistor the
increases with an increase in the digital input. Conversely,
operational amplifier adds value to Vout as expressed in the
a non-monotonic D/A would actually decrease the output at
following equation:
specific code values, and its transfer curve would have a dip.

R Vref Analog-to-Digital Converters

Vout = Vref = (19.1)
2R 2
A/Ds, of course, perform the reverse operation of D/As,
The total value of Vout can be calculated by using the equation: converting analog input signals into a digital, binary repre-
sentation. The number of bits in this digital representation
determines the resolution. An A/D with n-bit resolution can
D D D D 
Vout = Vref  n −1 + n − 2 +  + n −11 + n0  (19.2) generate an output with one of 2 n distinct codes. When com-
 2 4 2 2  bined with the input range, or span, of the A/D, the resolu-
tion indicates the smallest change that can be detected in the
where Dn−1, Dn−2, etc., represent the values of the bits of the input signal or the value of one least significant bit (LSB).
binary number to be converted. Table 19.1 compares resolutions commonly available today
In this formula, each active bit contributes to Vout with a for some typical input ranges.
value proportional to its weight in the binary number, and There are many types of A/Ds in practical use and the
thus the output voltage generated by the D/A is proportional reason for this is that there are a diverse number of applica-
to the value of the input binary number. tions. Some of the popular A/Ds used in DAQ are as follows:

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 19 Data Acquisition Fundamentals 333

Analogue Analogue
output output

Actual

Ideal
Digital (linear)
input

t Digital input value

(a) Settling time (b)

Fig. 19.5
Key D/A characteristics include (a) settling time and (b) linearity.

TABLE 19.1
Comparison of Common A/D Resolutions
8 bit 12 bit 16 bit 18 bit 24 bit
Distinct levels, 2
n 256 4,096 65,536 262,144 16,777,216
Value of 1 LSB for 0–1 V input range 3.92 mV 244 μV 15.3 μV 3.81 μV 0.060 μV
Value of 1 LSB for ±10 V input range 78.4 mV 4.88 mV 305 μV 76.4 μV 1.19 μV
Dynamic range in dB 48.2 72.2 96.3 108.4 144.5

Flash A/D converters (parallel): The fastest type of A/D is An n-bit flash A/D utilizes 2 n reference voltage levels and
the flash or parallel converter, obtaining speeds in multiple 2 − 1 comparators, as shown in Figure 19.6. The input ana-
n

gigasamples per second. However, the parallel architecture log voltage is connected to the input of every comparator so
employed by the flash converters tends to limit practical that a comparison can be made with each of the reference
implements to 10 bits or less of resolution. voltages representing the quantization levels. The outputs of

Comparator 1
VIN

VR1 E
Comparator 2 n
c
o
d
VR2
Comparator 3 i Digital
n output
g

VR3 l
o
g
i
Comparator 2n–1 c

VR(2n–1)

Fig. 19.6
Flash A/D Converter.

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 334 Digital Techniques and Data Handling

Analog Comparator Full scale

input
Input
Successive-
voltage
approximation

DAC output
register
(SAR) ½FS
D/A
VOA
¼FS
Vref 1 0 1 1 0 1 0
Clock 0 1 2 3 4 5 6 7 8
(a) Output (b) Clock cycle

Fig. 19.7
(a) Scheme of a successive approximation A/D. (b) Output bit generation of the process.

the comparators then drive the encoding logic to generate the 4. This process of comparison is repeated for n bits until
equivalent digital output. the signal has been converted.
The conversion rate for flash A/D converters is very fast
because only one step is required for complete conversion. The Figure 19.7 also shows an example conversion process of a
main disadvantage of the flash converter is of course the num- value of an analog input. Only the calculation of the seven
ber of comparators and reference voltages required to imple- most significant bits of the digital output is shown.
ment large-scale converters. For every additional binary bit of
Delta-sigma A/D converter: The delta-sigma, or sigma-
resolution added to the converter, the number of comparators
delta, converters have become a very important technol-
required is essentially doubled. For instance, 255 comparators
ogy for DAQ applications in recent years. Delta-sigma A/
are required for an 8 bit converter. If 4 more bits were added,
Ds commonly provide 24 bits of resolution at sampling rates
4095 comparators are required for a 12 bit converter.
that now reach up to hundreds of thousands of samples per
Successive approximation converter: The successive second. Their combination of speed, high resolution, and
approximation register (SAR) A/D is the most popular archi- inherent anti-aliasing and noise filtering capabilities make
tecture for DAQ applications, with many options available the delta-sigma A/D reduce or even eliminate the need for
covering a wide range of resolution and speed at an afford- expensive instrumentation amplifiers and other signal pre-
able cost. Modern SAR A/Ds are available in resolutions of conditioning. As such, delta-sigma converters offer an attrac-
8–18 bits, with sampling rates up to tens of megasamples tive option for a wide range of applications ranging from
per second. low-level sensor measurements to dynamic vibration and
The basic architecture of a successive approximation audio analysis.
converter is shown in Figure 19.7. The analog input to this The basic concept of the delta-sigma converter is to
system is successively compared with the voltage generated greatly oversample the input signal with a 1 bit A/D (essen-
by a D/A. The digital input to the D/A, which is stored in the tially a comparator) and then use digital signal processing
SAR is adjusted according to the result of each comparison. (DSP) methods to reshape the quantization noise. Figure 19.8
If the converter is of n bits, the conversion process requires shows a simplified block diagram of a basic single-order
n comparisons, and the result of the conversion is the final delta-sigma converter.
value stored in the SAR. The single-bit modulator is comprised of a subtraction
The conversion process for this A/D converter is as node, a loop filter, a 1 bit A/D, and a 1 bit D/A in a feed-
follows: back loop. Both A/D and D/A are oversampled at rates much

1. The most significant bit of the SAR is set to logic ONE, Modulator DSP
causing the internal D/A output to go to midscale.
2. The output of the decoder is compared against the
input analog signal. If the analog signal is larger than + 1-Bit
Loopfilter Decimation
the D/A output VOA, then a logic ONE is registered for A/D
the most significant bit. If the signal is less than the D/A –
output, the bit value is replaced with a logic ZERO. 1-Bit
3. The successful approximation register then goes to the D/A
next bit and tries logic ONE for that bit, which sets
the D/A output to either ¼ scale or ¾ scale, which is Fig. 19.8
compared to the input signal. Topology for a simple single-bit sigma-delta A/D.

K10922_C019.indd 334 5/26/2011 3:36:42 PM

 19 Data Acquisition Fundamentals 335

higher than the desired sampling rate, often at rates 64 or 128 DAQ Systems
times the eventual sample rate. The modulator section of the
A/D generates a bitstream whose average level, thanks to the While the A/Ds and D/As are core components of the DAQ
negative feedback loop, approximating the input signal level. device or system, there are other critical functions required
The DSP section of the delta-sigma A/D consists of a low- to make useful measurements or effectively control a pro-
pass filter, which converts this high data-rate bitstream into a cess. Most DAQ devices are designed to handle more than
high-resolution signal value. one sensor inputs and so incorporate either a multiplexer or
additional circuitry to simultaneously acquire data from mul-
A/D Characteristics tiple inputs. Interfacing to real-world sensor outputs usually
requires some type of signal-conditioning circuitry that pre-
While resolution and speed of conversion are the fundamental conditions the signal, or sensor output, improving the quality
specifications, the following key parameters are particularly and reliability of the measurement. DAQ systems will also
important in characterizing the operation and performance require a system timing controller, which can generate the
of A/Ds. needed clock and timing signals to accurately and precisely
control the timing of the acquisition.
Input range: The input range of an A/D is the span of volt-
Additionally, many commercial DAQ products fall into
ages over which it can make a conversion. The end points
the class of multifunction I/O, meaning they combine analog
of the low and high end of the range are called −full scale
input functionality with analog output, digital input/output,
and +full scale (they are also referred to as rails). If the −full
counter, and timing input/output capabilities. The following
scale is equal to 0 V, then the range is referred to as unipolar,
sections will examine the different components that com-
and if the two full-scale values have the same magnitude, for
prise a typical DAQ device.
example, −5 to +5 V, then the range of the A/D is referred
to as bipolar. If an input voltage falls outside the range, the
converter is said to be overranged. In this case, most convert- Multiplexers and Multichannel Systems
ers will return a value of the end point closest to the sampled
A DAQ system typically involves multiple sensors or ana-
signal.
log inputs, sometimes reaching channel counts in hundreds
Linear errors: Linear errors, namely, DC offset errors and or even thousands. In order to efficiently and economically
gain errors, are the largest and most common errors in an address these multiple channel applications, DAQ products
A/D. However, they are easily corrected through simple cali- tend to employ either a multiplexed architecture or an A/D-
bration and linear correction. per-channel architecture.
A multiplexed DAQ system employs a switching device,
Nonlinear errors: Nonlinear errors are characterized by two
called a signal multiplexer, to sequentially connect analog
specifications: differential nonlinearity (DNL) and integral
signals to the A/D system, as shown in Figure 19.9. With the
nonlinearity (INL). DNL measures any irregularity in the
multiplexed system, one A/D device can be shared across
code width (smallest detectable change) by comparing the
many analog inputs, yielding a more economical and com-
actual change in value to the ideal value of one code width
pact system design. The signal-conditioning circuitry may be
(or 1 LSB). INL measures the deviation from an ideal transfer
located either before or after the multiplexer, depending on
line of the code transitions. Unlike linear errors, nonlinear
the application.
errors are more difficult to compensate for in either the ana-
One potential disadvantage of the multiplexed systems
log or digital signal. The best way to mitigate nonlinear error
is that the acquisition speed is limited to the rate at which
is to choose a well-designed, well-specified A/D.
the multiplexer can switch, including the time for the analog
Relative accuracy: Another way to express the nonlinearity input signal to settle to the correct value, the rate of the single
of the A/D is relative accuracy, which is the worst-case devi- A/D to sequentially convert the input signals. For example, a
ation from the ideal DAQ board transfer function, a straight system with a 16 channel multiplexer and a 200 kSamples/s
line. A relative accuracy test is run by linearly sweeping the (5 μs) converter would take a minimum of 80 μs to convert
input from minus full scale to plus full scale and compar- one sample from each channel, yielding a maximum sam-
ing the average of the digitized values to the values of an pling rate of 12.5 kS/s for each input. Additionally, a time
end-point-fit straight line, created from an endpoint fit of the skew, or delay, is present in the scanned data, which is
data. Relative accuracy includes all nonlinearity and quan- equal to the conversion rate (5 μs in this example). Some
tization errors but does not include offset and gain errors of devices will employ sample-and-hold amplifiers on each
the circuitry feeding the converter. The relative accuracy is channel to remove this time skew and obtain simultaneous
measured in LSBs. In practice, a good A/D will have a rela- measurements.
tive accuracy of less than ±1 LSB. The relative accuracy is a Alternatively, a DAQ device can be designed with a more
very important specification because it tells how accurately parallel architecture, as shown in Figure 19.10. This type
the continuous analog input range is converted to discrete of system uses a distinct A/D, along with any needed sig-
digital values. nal conditioning, for each input channel. This architecture,

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 336 Digital Techniques and Data Handling

Signal Analog
Analog input 1
conditioning multiplexer
Signal
Analog input 2 Digital data
conditioning
Signal
A/D
conditioning

Signal
Analog input n
conditioning

Fig. 19.9
Multiplexed analog inputs.

Signal
Analog input 1 A/D
conditioning

Signal
Analog input 2 A/D Digital data
conditioning

Signal
Analog input n A/D
conditioning

Fig. 19.10
Parallel A/D-per-channel DAQ system.

which avoids the performance bottleneck of the multiplexed interval (Ts). Additionally, the entire sequence can be initi-
architecture and can inherently provide simultaneous digiti- ated with an external trigger signal. An example of a timing
zation of all input channels, is popular on higher speed sys- diagram of this scenario is shown in Figure 19.11.
tems. The disadvantage of the A/D-per-channel architecture
is the added cost and space for the additional circuitry. Multifunction I/O Systems

System Timing Controller As mentioned earlier, a common type of DAQ device is the
multifunction I/O DAQ device that combines analog input,
High-speed DAQ applications require that the A/D conver- analog output, digital input, digital output, and counter/timer
sions occur automatically, at very precisely defined time inputs and outputs. In modular systems, individual mod-
intervals. Therefore, a DAQ device must be equipped with ules may be a single function system but can be mixed and
a system timing controller whose principal responsibility is matched to form a multifunction system.
to generate the timing signals that control the synchronized
Analog output: Many DAQ devices and systems include two
operation of the A/Ds, multiplexers, movement of digital
or more analog output channels that utilize D/As to gener-
data, as well as analog output D/As, digital I/O, and counter/
ate analog voltages to generate control signals. Typically, the
timer I/O.
analog outputs can generate voltages up to 5 or 10 V although
Timing controllers include a frequency source, or time-
some DAQ boards designed for more industrial applications
base, for example, a 10 MHz oscillator, and a system of divid-
can directly generate a 4–20 mA analog output. By adding a
ers and timing circuitry that can generate the various timing
timing controller and buffer memory to hold arrays of digital
signals required to control the DAQ system. For example, the
values to be converted, an analog output device can generate
timing controller may need to be able to generate a 1 s clock
dynamic waveform signals that can be used to simulate sig-
signal for slow-speed temperature monitoring or a 1 MHz
nals used as a stimulus or a reference in a test.
clock to time high-speed ultrasonic signals.
The system timing controller also typically generates a Digital I/O: Most DAQ devices include several general-pur-
number of different timing and triggering clock signals. For pose digital inputs and outputs or digital I/O. Digital I/O can
example, a multiplexed analog input device may require a be used for a wide variety of applications, including sensing
control signal to initiate a scan of all channels at one time the on/off state switches and other binary sensors, control-
interval (Tscan), but also multiplex through the individual ling external relays and actuators, generating test patterns,
input channels at a different rate, referred to as the sample and simple parallel I/O communication. Most digital I/O on

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 19 Data Acquisition Fundamentals 337

Start trigger

Timebase

Analog input sample clock 1 2 3 4 1 2 3 4

Ts
Tscan

AI channel #1
AI channel #2
AI channel #3
AI channel #4

Fig. 19.11
Timing diagram of scanned DAQ sequence.

computer-based DAQ works at 5 V and is transistor-transis- By combining one or more counters with a frequency
tor logic (TTL) compatible, which defines the low and high clock source, a counter/timer device can be configured for a
states of the digital signals, as illustrated in Figure 19.12. wide range of counting and timing operations:
Alternatively, some digital I/O devices designed for industrial
control and monitoring applications may implement digital • Event (pulse) counting
I/O that operates directly with 24 V sensors and actuators. • Pulse-width and period measurement
Counters/timers: Counters/timers are versatile devices used • Pulse-width modulated inputs and outputs
for a variety of counting, timing, and signal generation appli- • Frequency measurement
cations. Counter/timer functionality is accomplished through • Frequency generation
the use of one or more counters and one or more frequency • Pulse train generation
clock sources or timebases. The counter itself is a basic device
that consists of a count-register, GATE and SOURCE inputs,
and an OUT signal (Figure 19.13). The counter’s basic opera- Signal Conditioning
tion is to increment the count-register on every detected state
changes at the SOURCE INPUT. Counting is controlled, or Most sensors and transducer generate signals that cannot be,
gated, by the state of the GATE signal. The OUT can be con- or should not be, connected directly to the unconditioned
figured to generate a pulse, or a change of state, when the input of an A/D. The sensor signals may be very low and
count-register reaches a preprogrammed count value. vulnerable to noise corruption or very high and outside the
usable range of the A/D or even pose a safety issue. Many
+5.0 V popular sensors generate a resistive signal, which must
essentially be converted to a measurable voltage signal. A
High typical signal-conditioning circuitry provides (Figure 19.14)
the front-end analog preprocessing required to convert the
+2.0 V output from the sensor into conditioned signals, which can
Indeterminate be effectively digitized and acquired. Signal-conditioning
+0.8 V functions include amplification, filtering, isolation, sensor
Low
0V excitation, and other sensor-specific functions.
In commercial DAQ systems, signal conditioning may be
Fig. 19.12 provided as a front-end unit that attaches or cables to the
Voltage levels of digital TTL signal.
digitizing DAQ device. This modularity allows mixing and
matching the signal conditioning to match the application
as needed. Alternatively, an approach that is gaining popu-
Gate Out
larity as the size and cost of analog and digital IC technol-
ogy continues to decrease is to integrate signal-conditioning
Count register
capabilities into the DAQ device. An advantage to this inte-
Source grated approach is that the system design can be optimized,
(input) both in terms of cost and performance, for more specific
applications.
Fig. 19.13 More information on signal conditioning can be found
Basic counter device. in Chapter 18.

K10922_C019.indd 337 5/26/2011 3:36:44 PM

 338 Digital Techniques and Data Handling

Signal conditioning

A/D Bus/network
Amplifier Filter
converter interface

Sensor-specific conditioning Isolation Isolation

Sensors Sensor excitation (analog) (digital)
Bridge completion
Shunt calibration

Fig. 19.14
Signal conditioning includes amplification, filtering, isolation, and sensor-specific function for interfacing to popular industrial sensors
and transducers.

Amplification A second important application of filters is to remove

errors caused by aliasing. Aliasing is the phenomena whereby
Amplification is the most common signal-conditioning func- high frequency signals show up as low frequency signals
tion and is critical in effectively utilizing the resolution of the because of undersampling. Anti-aliasing filters reduce or
A/D subsystem. The converter in the DAQ system operates remove these aliased signals by implementing high-order low-
over a fixed input range, with a fixed resolution. For example, pass filters that sharply attenuate all signals above one-half
as we saw earlier that a 16 bit A/D with a ±10 V input range of the sampling rate, also known as the Nyquist frequency.
yields a signal resolution of 305 μV, which would be more As we saw earlier, sigma-delta A/Ds incorporate very effec-
than sufficient for voltage signals that operate over the full tive noise and anti-aliasing filtering as a useful by-product of
10 V input range. However, consider using this same system the digitization scheme. Alternatively, regardless of the type
to digitize a typical thermocouple that generates a signal that of converter, it is often very effective to oversample a noisy
varies with temperature at a rate of approximately 50 μV/°C signal at a higher rate and apply basic averaging, or digital
and will never exceed a maximum level of 100 mV. The 16 filters, in the software application. This approach does not
bit system, with a resolution of 305 μV, can detect changes provide true anti-aliasing, but it can reduce other noise and
no smaller than 6°C. However, by adding a low-noise signal increase the frequency at which aliasing would occur. In any
amplifier with a gain factor of 100, the resolution of the sys- case, many DAQ and signal condition products do incorpo-
tem is increased to 3.05 μV. With this amplification, tempera- rate some type of analog filtering to pre-filter the signal in the
ture changes of less than 0.1°C can be detected (neglecting analog domain, either as a precaution for anti-aliasing or to
other sources of error and noise, of course). Note that the clean up signals distorted with noise from the environment,
effective input range of the DAQ device is also reduced by a such as 50 or 60 Hz noise from power lines. Figure 19.15
factor of 100 to ±200 mV. illustrates the effect of a low-pass filter on a noisy strain gage
Another important function of amplification is to signal.
increase the signal-to-noise ratio, reducing the error caused
by noise imposed on the signal after being amplified. Noise
Isolation
that is coupled into the measurement signal path will have
a proportionately smaller effect if the analog signal has One of the most common causes of measurement problems
been amplified to a higher level. That is why it is often and failures is improper grounding of the signal wires. For
desirable to amplify the signal as close as possible to the example, if a sensor is electrically referenced to a local
source before the signal is transmitted through a noisy ground point that is not exactly at the same potential as the
environment. ground of the DAQ system, the difference in potential can
show up as an offset error or noise in the measurement. If the
Filtering ground potentials are far enough apart, they can cause dam-
age to the DAQ equipment. Signal conditioners with isolation
Filtering removes or decreases the unwanted noise from can prevent most of these problems. Such devices pass the
­signal measurements. Filters operate as a function of fre- signal from its source to the measurement device without a
quency, and can selectively attenuate signals above a cer- galvanic or physical connection, breaking the path for cur-
tain frequency (low-pass filters), below a certain frequency rents to flow between grounds at differing potentials. Besides
(high-pass filters), within a frequency range (notch filters), or breaking ground loops, isolation blocks high-voltage surges
all frequencies except a specified range (band-pass filters). and rejects high common-mode voltage and thus protects
­Low-pass filters are the most common in industrial applica- both the operators and expensive measurement equipment.
tions and are used to reduce the effects of higher frequency Isolation of analog signals is usually implemented using
noise from power lines, generators, motors, etc. capacitive or magnetic isolation techniques. Optical isolation is

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 19 Data Acquisition Fundamentals 339

Noisy signal

Amplitude Time

Filtered (lowpass) signal

Amplitude

Time

Fig. 19.15
Effect of low-pass filter on noisy signal.

Isolation
Isolation
barrier
barrier

I/O Connector
I/O Connector

Gain Gain Digital

Analog in ISO AI Data Analog in Amp. D/A AI FIFO AI Data
Amp. A/D AI FIFO isolators
Amp

Analog signal Digital signal

Analog signal Digital signal

(a) (b)

Fig. 19.16
Two approaches to isolate DAQ device. (a) analog isolation and (b) digital isolation.

primarily used for digital signals. A DAQ system that incorpo-

rates isolation can be implemented either with analog isolation TABLE 19.2
in the signal-conditioning front end or with digital isolation List of Common Industrial Sensors and Their Signal-
on the digital data path. These two approaches are illustrated Conditioning Requirements
in Figure 19.16. New higher speed digital isolators based on Sensor Signal-Conditioning Requirements
MEMS (Micro Electromechanical Systems) technology have Thermocouples Cold-junction sensing and compensation,
made the digital approach more feasible in recent years. signal amplification
RTDs Precision current source (excitation), lead-wire
Sensor and Transducer Interfacing resistance compensation (three-wire and four-wire
connections)
Another important function of signal conditioning is pro- Strain gages Wheatstone bridge completion, precision voltage or
viding the needed functions to interface a DAQ system to current source (excitation), signal amplification,
common sensors and transducers. The signal-conditioning offset nulling, shunt calibration
requirements of some of the most common industrial sensors Load cells Precision voltage or current source (excitation),
signal amplification, offset nulling,
are listed in Table 19.2. We will look at some sensors and the
shunt calibration
key signal-conditioning requirements.
Thermocouples: The most common sensor used to mea-
sure temperature in DAQ applications is the thermocouple. voltage, which varies with temperature. More specifically,
The thermocouple is inexpensive and easy to use, does not the generated voltage is a function of the difference between
require power or excitation, and can measure over a very this junction, called the hot junction, and the connection of
wide range of temperatures. the thermocouple wires to the measurement system, called
The thermocouple consists of two wires of dissimi- the cold junction. In order to determine the absolute tem-
lar metals. The junction of the two wires generates a small perature of the hot junction, the signal conditioner or DAQ

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 340 Digital Techniques and Data Handling

Signal Signal conditioner/data aquisition

connector
Thermocouple 1

Thermocouple 2
Digital data

Thermocouple 3 Analog A/D

multiplexer

Thermocouple 4

TCJ
CJ
temp
sensor

Fig. 19.17
Thermocouple instrumentation requires a cold junction sensor to measure the temperature of the cold junction, where the thermocouple
wire connects to the measurement system.

system must also sense the temperature of the cold junction. measurements. The most common type is the bonded resis-
DAQ systems designed for thermocouples often embed a tance foil strain gage whose electrical resistance, typically
single temperature sensor in the connector block to measure 120 or 350 Ω nominally, varies linearly with the strain applied
the cold junction (CJ) temperature as accurately as possible, to the device. Because the DAQ system must be able to effec-
as shown in Figure 19.17. tively measure very small changes in resistance, strain gages
The ability of the cold junction temperature sensor to are invariably used in a Wheatstone bridge circuit, shown in
accurately sense the temperature at the actual connection of Figure 19.18. The Wheatstone bridge circuit consists of four
the thermocouple wire to the terminals has a direct impact of resistive elements with a voltage excitation supply applied to
the overall measurement accuracy. Therefore, signal condi- the ends of the bridge. When the ratios R1/R2 and R3/R4 are
tioner designers should design the signal connector block to equal, the bridge is said to be balanced, and the output V0 is
be as isothermal as possible to minimize the thermal gradi- zero. V0 will vary proportionally with changes in resistance
ents that occur between the cold junction temperature sensor to any resistor in the bridge.
and any of the thermocouple wire terminals. Strain gages can occupy one, two, or four arms of the
bridge, with any remaining positions filled with fixed value
Resistance temperature detectors: Resistance temperature
resistors. Half-bridge and full-bridge strain gage circuits are
detectors (RTDs) are temperature sensors generally made
designed to increase the sensitivity by arranging the strain
from a pure metal whose resistance increases with increasing
gage elements in opposing directions. Figure 19.19 shows
temperature. RTDs are popular for their stability, high preci-
signal-conditioning interfaces for quarter-bridge and full-
sion, and highly linear operation. RTDs of different materi-
bridge configurations. Note that the current carrying lead
als and resistance values are available, but the most common
wires have a resistance RL, which, if uncompensated, adds
type is the platinum film PT100 sensor with a nominal resis-
error to the measurement. Signal conditioners can minimize
tance of 100 Ω at 0°C.
this error through three-wire connections (for quarter-bridge
Because the RTD is a variable resistive device, signal con-
configurations), remote sensing of the excitation voltage, and
ditioning must essentially adapt the DAQ system to measure
the resistance of the RTD. The most common technique for this
is to generate a constant current source and sense the result-
ing voltage drop across the RTD resistance. However, the lead R4 R1
wires connecting the signal conditioner to the RTD have some
finite resistance, which, especially for longer runs of wire, can +
V0 VEx
add significant errors to the measurement. Therefore, RTDs – + –
are commonly available with three-wire and four-wire config-
urations, which reduce or remove these errors with additional R3 R2
wires for sensing that do not carry the excitation current.
Strain gages and load cells: The strain gage is a very com- Fig. 19.18
mon device used in wide range of mechanical and structural Wheatstone bridge circuit used for strain gages and load cells.

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 19 Data Acquisition Fundamentals 341

Signal conditioner/data acquisition

RL Signal conditioner/data acquisition +
VCH
+ –
VCH
– RL
RL R4 R1
R4 +ε –ε
R1 +
(gauge) +ε R
L + V – VEX
–ε +ε
– EX
R3 R2
R3 R2 RL
Shunt Shunt
RS RL
cal A cal A
RL RS
(a) (b)

Fig. 19.19
Signal-conditioning circuitry for (a) quarter-bridge and (b) full-bridge strain gage configurations.

shunt calibration, which can be used to compensate for lead advanced functions and features not discussed in this article.
wire errors and other gain errors. However, the basic concepts covered here are generally uni-
Load cells are simply engineered transducers that utilize versal in the world of DAQ and form the foundation for even
strain gages bonded to a beam or mechanical component that the more sophisticated DAQ systems.
deforms when force is applied. Interfacing a DAQ system to a
strain-gage-based load cell is therefore equivalent to interfac-
ing to a full-bridge strain gage. Similarly, some torque sensors Bibliography
and pressure sensors are also based on strain gage technology.
Bentley, J.P., Principles of Measurement Systems, 4th edn., Upper
Saddle River, London: Prentice Hall, 2005.
Bishop, R., Mechatronic System Control Logic and Data Acquisition,
Conclusions 2nd edn., Boca Raton, FL: CRC Press, 2008.
Blume, P.A., The LabVIEW Style Book, Upper Saddle River,
This chapter has introduced the fundamental components of London: Prentice Hall, 2005.
DAQ systems, including A/Ds and D/As, multichannel archi- Boyer, S.A., SCADA: Supervisory Control and Data Acquisition,
tectures, system timing, signal conditioning, driver software, 2nd edn., Research Triangle Park, NC: ISA, 1999.
and application software. DAQ products come in all shapes James, K., PC Interfacing and Data Acquisition: Techniques for
Measurement, Instrumentation and Control, New South Wales,
and sizes, from very inexpensive and simple single-function
Australia: Newnes, 2000.
devices to high-end sophisticated measurement systems that Mihura, B., LabVIEW Data Acquisition, Upper Saddle River,
have been engineered to deliver top-notch performance, flex- London: Prentice Hall, 2001.
ibility, and reliability in a wide range of environmental con- Taylor, H.R., Data Acquisition for Sensor Systems, London, U.K.:
ditions. These high performance systems may incorporate Chapmen Hall, 1997.

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