OBJECTIVES:

In this lesson, you will learn about Execution of instructions by a processor, the functional units
of a processor and how they are interconnected, hardware for generating control signals and
microprogrammed control and fixed point and floating-point arithmetic for ALU operation
such as adder and subtractor circuits, high-speed adders based on carry-lookahead logic
circuits, the Booth algorithm for multiplication of signed numbers, logic circuits for division
and arithmetic operations on floating-point numbers conforming to the IEEE standard

CONTENTS:

1. Fundamental Concepts

 Execution of a complete instruction, Multiple Bus Organization,

Hardwired control, Micro-programmed control

2. Computer Arithmetic

 Addition and Subtraction, Multiplication Algorithm,Division Algorithm

3. Floating Point Arithmetic operations

 Decimal Arithmetic Unit, Decimal Arithmetic Operations

Introduction

First, we focus on the processing unit, which executes machine-language instructions

and coordinates the activities of other units in a computer. We examine its internal structure
and show how it performs the tasks of fetching, decoding, and executing such instructions. The
processing unit is often called the central processing unit (CPU). Addition and subtraction of
two numbers are basic operations at the machine-instruction level in all computers. And
arithmetic and logic operations, are implemented in ALU of the processor.
1. FUNDAMENTAL CONCEPTS

A typical computing task consists of a series of operations specified by a sequence of

machine-language instructions that constitute a program. The processor fetches one instruction at
a time and performs the operation specified. Instructions are fetched from successive
memory locations until a branch or a jump instruction is encountered. The processor uses the
program counter, PC, to keep track of the address of the next instruction to be fetched and
executed. After fetching an instruction, the contents of the PC are updated to point to the next
instruction in sequence. A branch instruction may cause a different value to be loaded into the
PC.
When an instruction is fetched, it is placed in the instruction register, IR, from where it
is interpreted, or decoded, by the processor’s control circuitry. The IR holds the instruction
until its execution is completed. Consider a 32-bit computer in which each instruction is
contained in one word in the memory, as in RISC-style instruction set architecture. To execute
an instruction, the processor has to perform the following steps:
1. Fetch the contents of the memory location pointed to by the PC. The contents of this location
are the instruction to be executed; hence they are loaded into the IR. In register transfer
notation, the required action is
IR←[[PC]]
2. Increment the PC to point to the next instruction. Assuming that the memory is byte
addressable, the PC is incremented by 4; that is
PC←[PC] + 4
3. Carry out the operation specified by the instruction in the IR.
Fetching an instruction and loading it into the IR is usually referred to as the instruction fetch
phase. Performing the operation specified in the instruction constitutes the instruction
execution phase. With few exceptions, the operation specified by an instruction can be carried
out by performing one or more of the following actions:
• Read the contents of a given memory location and load them into a processor register.
• Read data from one or more processor registers.
• Perform an arithmetic or logic operation and place the result into a processor register.
• Store data from a processor register into a given memory location.
The hardware components needed to perform these actions are shown in Figure. The
processor communicates with the memory through the processor-memory interface, which
transfers data from and to the memory during Read and Write operations. The instruction
address generator updates the contents of the PC after every instruction is fetched. The register
file is a memory unit whose storage locations are organized to form the processor’s general-
purpose registers. During execution, the contents of the registers named in an instruction that
performs an arithmetic or logic operation are sent to the arithmetic and logic unit (ALU), which
performs the required computation. The results of the computation are stored in a register in
the register file.

EXECUTION OF A COMPLETE INSTRUCTION

Atypical computation operates on data stored in registers. These data are processed by
combinational circuits, such as adders, and the results are placed into a register. A clock signal
is used to control the timing of data transfers. The registers comprise edge-triggered flip-flops
into which new data are loaded at the active edge of the clock. In this chapter, we assume that the
rising edge of the clock is the active edge. The clock period, which is the time between two
successive rising edges, must be long enough to allow the combinational circuit to produce the
correct result. Let us now examine the actions involved in fetching and executing instructions.
We illustrate these actions using a few representative RISC-style instructions

SINGLE BUS ORGANIZATION

ALU and all the registers are interconnected via a Single Common Bus. Data & address
lines of the external memory-bus is connected to the internal processor-bus via MDR
and MAR respectively. (MDRà Memory Data Register, MAR à Memory Address Register).
MDR has 2 inputs and 2 outputs. Data may be loaded into MDR either from memory-bus
(external) or from processor-bus (internal).

MAR‟s input is connected to internal-bus; MAR‟s output is connected toexternal-

bus. Instruction Decoder & Control Unit is responsible for issuing the control-signals to all
the units inside the processor. We implement the actions specified by the instruction (loaded
in the IR). Register R0 through R(n-1) are the Processor Registers. The programmer can access
these registers for general-purpose use. Only processor can access 3 registers Y, Z & Temp
for temporary storage during program-execution. The programmer cannot access these 3
registers. In ALU,1) “A‟ input gets the operand from the output of the multiplexer (MUX). 2)
“B‟ input gets the operand directly from the processor-bus. There are 2 options provided for
“A‟ input of the ALU. MUX is used to select one of the 2 inputs. MUX selects either output of
Y or constant-value 4( which is used to increment PC content). An instruction is executedby
performing one or more of the following operations:
1) Transfer a word of data from one register to another or to the ALU.
2) Perform arithmetic or a logic operation and store the result in a register.
3) Fetch the contents of a given memory-location and load them into a register.
4) Store a word of data from a register into a given memory-location.
Disadvantage: Only one data-word can be transferred over the bus in a clock cycle.
Solution: Provide multiple internal-paths. Multiple paths allow several data-transfers to take
place in parallel.

REGISTER TRANSFERS
Instruction execution involves a sequence of steps in which data are transferred from
one register to another. For each register, two control-signals are used: Riin & Riout. These
are called Gating Signals. Riin=1 = data on bus is loaded into Ri. Riout=1 as content of Ri is
placed on bus. Riout=0, makes bus can be used for transferring data from other registers.For
example, Move R1, R2; This transfers the contents of register R1 to register R2. This can be
accomplished as follows:
1) Enable the output of registers R1 by setting R1out to 1 (Figure 7.2). This places the contents
of R1 on processor-bus.
2) Enable the input of register R2 by setting R2out to 1. This loads data from processor-bus
into register R4.
 All operations and data transfers within the processor take place within time-periods
defined by the processor-clock. The control-signals that govern a particular transfer are
asserted at the start of the clock cycle.

Input & Output Gating for one Register Bit

A 2-input multiplexer is used to select the data applied to the input of an edge-
triggered D flip-flop. Riin=1 makes mux selects data on bus. This data will be loaded into flip-
flop at rising-edge of clock. Riin=0 makes mux feeds back the value currently stored in flip-
flop (Figure). Q output of flip-flop is connected to bus via a tri-state gate. Riout=0 makes
gate's output is in the high-impedance state. Riout=1 makesthe gate drives the bus to 0 or 1,
depending on the value of Q.

PERFORMING AN ARITHMETIC OR LOGIC OPERATION

The ALU performs arithmetic operations on the 2 operands applied to its A and B
inputs. One of the operands is output of MUX and, the other operand is obtained directly from
processor-bus. The result (produced by the ALU) is stored temporarily in register Z. The
sequence of operations for [R3][R1]+[R2] is as follows:
1) R1out, Yin
2) R2out, SelectY, Add, Zin
3) Zout, R3in
Instruction execution proceeds as follows:
Step 1 --> Contents from register R1 are loaded into register Y.
Step2 --> Contents from Y and from register R2 are applied to the A and B inputs of ALU;
Addition is performed & Result is stored in the Z register.
Step 3 --> The contents of Z register is stored in the R3 register.
The signals are activated for the duration of the clock cycle corresponding to that
step. All other signals are inactive.

CONTROL-SIGNALS OF MDR
The MDR register has 4 control-signals (Figure). MDRin & MDRout control the
connection to the internal processor data bus & MDRinE & MDRoutE control the connection to
the memory Data bus. MAR register has 2 control-signals. MARin controls the connection to
the internal processor address bus & MARout controls the connection to the memory
address bus.
FETCHING A WORD FROM MEMORY
To fetch instruction/data from memory, processor transfers required address to MAR.
At the same time, processor issues Read signal on control-lines of memory-bus. When
requested-data are received from memory, they are stored in MDR. From MDR, they are
transferred to other registers. The response time of each memory access varies (based on cache
miss, memory-mapped I/O). To accommodate this, MFC is used. (MFC makes Memory
Function Completed). MFC is a signal sent from addressed-device to the processor. MFC
informs the processor that the requested operation has been completed by addressed-device.

Consider the instruction Move (R1),R2. The sequence of steps is (Figure): R1out,
MARin, Read ;desired address is loaded into MAR & Read command is issued. MDRinE,
WMFC; load MDR from memory-bus & Wait for MFC response from memory. MDRout,
R2in; load R2 from MDR where WMFC=control-signal that causes processor's control.
circuitry to wait for arrival of MFC signal.
Storing a Word in Memory
Consider the instruction Move R2,(R1). This requires the following sequence: R1out,
MARin; desired address is loaded into MAR. R2out, MDRin, Write; data to be written are
loaded into MDR & Write command is issued. MDRoutE, WMFC ;load data into memory
location pointed by R1 from MDR.

EXECUTION OF A COMPLETE INSTRUCTION

Consider the instruction Add (R3),R1 which adds the contents of a memory-location
pointed by R3 to register R1. Executing this instruction requires the following actions:
1) Fetch the instruction.
2) Fetch the first operand.
3) Perform the addition &
4) Load the result into R1.

Instruction execution proceeds as follows:

Step1: The instruction-fetch operation is initiated by loading contents of PC into MAR &
sending a Read request to memory. The Select signal is set to Select4, which causes the Mux
to select constant 4. This value is added to operand at input B (PC‟s content), and the result is
stored in Z.
Step2: Updated value in Z is moved to PC. This completes the PC increment operation and PC
will now point to next instruction.
Step3: Fetched instruction is moved into MDR and then to IR. The step 1 through 3 constitutes
the Fetch Phase. At the beginning of step 4, the instruction decoder interprets the contents of
the IR. This enables the control circuitry to activate the control-signals for steps 4 through 7.
The step 4 through 7 constitutes the Execution Phase.
Step4: Contents of R3 are loaded into MAR & a memory read signal is issued.
Step5: Contents of R1 are transferred to Y to prepare for addition.
Step6: When Read operation is completed, memory-operand is available in MDR, and the
addition is performed.
Step7: Sum is stored in Z, then transferred to R1.The End signal causes a new instruction fetch
cycle to begin by returning to step1.

BRANCHING INSTRUCTIONS
Control sequence for an unconditional branch instruction is as follows: Instruction
execution proceeds as follows:

Step 1-3: The processing starts & the fetch phase ends in step3.
Step 4: The offset-value is extracted from IR by instruction-decoding circuit. Since the
updated value of PC is already available in register Y, the offset X is gated onto the bus, and
an addition operation is performed.
Step 5: The result, which is the branch-address, is loaded into the PC.
The branch instruction loads the branch target address in PC so that PC will fetch the
next instruction from the branch target address. The branch target address is usually obtained
by adding the offset in the contents of PC. The offset X is usually the difference between the
branch target-address and the address immediately following the branch instruction.
In case of conditional branch, we have to check the status of the condition-codes
before loading a new value into the PC. e.g.: Offset-field-of-IRout, Add, Zin, If N=0 then End
If N=0, processor returns to step 1 immediately after step 4. If N=1, step 5 is performed to
load a new value into PC.

MULTIPLE BUS ORGANIZATION

The disadvantage of Single-bus organization is only one data-word can be transferred
over the bus in a clock cycle. This increases the steps required to complete the execution of
the instruction. The solution to reduce the number of steps, most processors provide multiple
internal-paths. Multiple paths enable several transfers to take place in parallel.

As shown in figure, three buses can be used to connect registers and the ALU of the
processor. All general-purpose registers are grouped into a single block called the Register
File. Register-file has 3 ports:
1) Two output-ports allow the contents of 2 different registers to be simultaneously placed on
buses A & B.
2) Third input-port allows data on bus C to be loaded into a third register during the same
clock-cycle.
Buses A and B are used to transfer source-operands to A & B inputs of ALU. The
result is transferred to destination over bus C. Incrementer Unit is used to increment PC by 4.
Instruction execution proceeds as follows:
Step 1: Contents of PC are passed through ALU using R=B control-signal & loaded into MAR
to start memory Read operation. At the same time, PC is incremented by 4.
Step2: Processor waits for MFC signal from memory.
Step3: Processor loads requested-data into MDR, and then transfers them to IR.
Step4: The instruction is decoded and add operation takes place in a single step.

COMPLETE PROCESSOR
This has separate processing-units to deal with integer data and floating-point data.
Integer unit has to process integer data. (Figure). Floating unit has to process floating point