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OPA317, OPA2317, OPA4317

SBOS682B – MAY 2013 – REVISED JUNE 2016

OPAx317 Zerø-Drift, Low-Offset, Rail-to-Rail I/O Operational Amplifier

Precision Catalog
1 Features 3 Description
•
1 Supply Voltage: 1.8 V to 5.5 V The OPA317 series of CMOS operational amplifiers
offer precision performance at a very competitive
• microPackages: price. These devices are members of the Zerø-Drift
– Single: SOT23-5, SC-70, SOIC-8 family of amplifiers that use a proprietary
– Dual: VSSOP-8, SOIC-8 autocalibration technique to simultaneously provide
low offset voltage (90 μV maximum) and near-zero
– Quad: SOIC-14, TSSOP-14
drift over time and temperature at only 35 μA
• Low Offset Voltage: 20 μV (Typical) (maximum) of quiescent current.
• CMRR: 108-dB (Typical) PSRR
The OPA317 family features rail-to-rail input and
• Quiescent Current: 35 μA (Maximum) output in addition to near flat 1/f noise, making this
• Gain Bandwidth: 300 kHz amplifier ideal for many applications, and much easier
• Rail-to-Rail Input and Output to design into a system. These devices are optimized
for low-voltage operation as low as 1.8 V (±0.9 V)
• Internal EMI and RFI Filtering and up to 5.5 V (±2.75 V).

2 Applications The OPA317 (single version) is available in the

SC70-5, SOT23-5, and SOIC-8 packages. The
• Battery-Powered Instruments OPA2317 (dual version) is offered in the VSSOP-8
• Temperature Measurements and SOIC-8 packages. The OPA4317 is offered in
• Transducer Applications the standard SOIC-14 and TSSOP-14 packages. All
versions are specified for operation from –40°C to
• Electronic Scales +125°C.
• Medical Instrumentation
• Handheld Test Equipment Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
• Current Sense
SOIC (8) 3.91 mm × 4.90 mm
OPA317 SOT-23 (5) 1.60 mm × 2.90 mm
SC70 (5) 1.25 mm × 2.00 mm
SOIC (8) 3.91 mm × 4.90 mm
OPA2317
VSSOP (8) 3.00 mm × 3.00 mm
SOIC (14) 3.91 mm × 8.65 mm
OPA4317
TSSOP (14) 4.40 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.

Distribution of Offset Voltage

Population
-24.00
-21.00
-18.00
-15.00
-12.00
-9.00
-6.00
-3.00
0
3.00
6.00
9.00
12.00
15.00
18.00
21.00
24.00

Offset Voltage (mV)

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA317, OPA2317, OPA4317
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Table of Contents
1 Features .................................................................. 1 8.4 Device Functional Modes ....................................... 14
2 Applications ........................................................... 1 9 Application and Implementation ........................ 15
3 Description ............................................................. 1 9.1 Application Information............................................ 15
4 Revision History..................................................... 2 9.2 Typical Applications ................................................ 16
9.3 System Example ..................................................... 18
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 5 10 Power Supply Recommendations ..................... 18
6.1 Absolute Maximum Ratings ...................................... 5 11 Layout................................................................... 19
6.2 ESD Ratings.............................................................. 5 11.1 Layout Guidelines ................................................. 19
6.3 Recommended Operating Conditions ...................... 5 11.2 Layout Example .................................................... 19
6.4 Thermal Information: OPA317 .................................. 6 12 Device and Documentation Support ................. 20
6.5 Thermal Information: OPA2317 ................................ 6 12.1 Documentation Support ........................................ 20
6.6 Thermal Information: OPA4317 ................................ 6 12.2 Receiving Notification of Documentation Updates 20
6.7 Electrical Characteristics: VS = 1.8 V to 5.5 V .......... 7 12.3 Related Links ........................................................ 20
6.8 Typical Characteristics .............................................. 8 12.4 Community Resources.......................................... 20
7 Parameter Measurement Information ................ 11 12.5 Trademarks ........................................................... 20
12.6 Electrostatic Discharge Caution ............................ 20
8 Detailed Description ............................................ 12
12.7 Glossary ................................................................ 20
8.1 Overview ................................................................ 12
8.2 Functional Block Diagram ...................................... 12 13 Mechanical, Packaging, and Orderable
8.3 Feature Description................................................. 12
Information ........................................................... 21

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (June 2013) to Revision B Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
• Deleted Ordering Information table; see POA at the end of the data sheet........................................................................... 1

Changes from Original (May 2013) to Revision A Page

• Deleted PSRR Features bullet ............................................................................................................................................... 1

• Changed Quiescent Current Features bullet .......................................................................................................................... 1
• Changed second sentence in Description section ................................................................................................................. 1
• Changed PSRR maximum value............................................................................................................................................ 7

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5 Pin Configuration and Functions

OPA317: DBV Package OPA317: DCK Package

5-Pin SOT-23 5-Pin SC70
Top View Top View

OUT 1 5 V+ +IN 1 5 V+

V- 2 V- 2

+IN 3 4 -IN -IN 3 4 OUT

Pin Functions (5-Pin Packages)

PIN
I/O DESCRIPTION
NAME SOT-23 SC70
+IN 3 1 I Noninverting input
–IN 4 3 I Inverting input
OUT 1 4 O Output
V+ 5 5 — Positive (highest) power supply
V– 2 2 — Negative (lowest) power supply

OPA317: D Package OPA2317: D and DGK Packages

8-Pin SOIC 8-Pin SOIC and VSSOP
Top View Top View

(1) (1)
NC 1 8 NC OUT A 1 8 V+
A
-IN 2 7 V+ -IN A 2 7 OUT B
B
+IN 3 6 OUT +IN A 3 6 -IN B
(1)
V- 4 5 NC V- 4 5 +IN B

(1) NC - No internal connection

Pin Functions (8-Pin Packages)

PIN
OPA2317 I/O DESCRIPTION
OPA317
NAME SOIC and
SOIC
VSSOP
+IN 3 — I Noninverting input
–IN 2 — I Inverting input
+IN A — 3 I Noninverting input, channel A
–IN A — 2 I Inverting input, channel A
+IN B — 5 I Noninverting input, channel B
–IN B — 6 I Inverting input, channel B
1
NC 5 — — No internal connection
8
OUT 6 — O Output
OUT A — 1 O Output, channel A
OUT B — 7 O Output, channel B
V+ 7 8 — Positive (highest) power supply
V– 4 4 — Negative (lowest) power supply

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OPA4317: D Package OPA4317: SW Package

14-Pin SOIC 14-Pin TSSOP
Top View Top View

OUT A 1 14 OUT D OUT A 1 14 OUT D

-IN A 2 13 -IN D -IN A 2 13 -IN D

A D
+IN A 3 12 +IN D +IN A 3 12 +IN D

V+ 4 11 V- V+ 4 11 V-

+IN B 5 10 +IN C +IN B 5 10 +IN C

B C
-IN B 6 9 -IN C -IN B 6 9 -IN C

OUT B 7 8 OUT C OUT B 7 8 OUT C

Pin Functions (14-Pin Packages)

PIN
I/O DESCRIPTION
NAME SOIC, TSSOP
+IN A 3 I Noninverting input, channel A
–IN A 2 I Inverting input, channel A
+IN B 5 I Noninverting input, channel B
–IN B 6 I Inverting input, channel B
+IN C 10 I Noninverting input, channel C
–IN C 9 I Inverting input, channel C
+IN D 12 I Noninverting input, channel D
–IN D 13 I Inverting input, channel D
OUT A 1 O Output, channel A
OUT B 7 O Output, channel B
OUT C 8 O Output, channel C
OUT D 14 O Output, channel D
V+ 4 — Positive (highest) power supply
V– 11 — Negative (lowest) power supply

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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range, unless otherwise noted. (1)
MIN MAX UNIT
VS = (V+) – (V–) Supply voltage 7 V
(2)
Signal input terminals (V–) – 0.3 (V+) + 0.3 V
Signal input terminals (2) –10 10 mA
Output short circuit (3) Continuous
TA Operating temperature –40 150 °C
TJ Junction temperature 150 °C
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.3 V beyond the supply rails must
be current-limited to 10 mA or less.
(3) Short-circuit to ground, one amplifier per package.

6.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±4000
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1000 V
Machine model (MM) ±400

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted).
MIN MAX UNIT
(V+ – V–) Supply voltage 1.8 (±0.9) 5.5 (±2.25) V
TA Specified temperature –40 125 °C

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6.4 Thermal Information: OPA317

OPA317
THERMAL METRIC (1) D (SOIC) DBV (SOT-23) DCK (SC70) UNIT
8 PINS 5 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance 140.1 220.8 298.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 89.8 97.5 65.4 °C/W
RθJB Junction-to-board thermal resistance 80.6 61.7 97.1 °C/W
ψJT Junction-to-top characterization parameter 28.7 7.6 0.8 °C/W
ψJB Junction-to-board characterization parameter 80.1 61.1 95.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — — — °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

6.5 Thermal Information: OPA2317

OPA2317
(1)
THERMAL METRIC D (SOIC) DGK (VSSOP) UNIT
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 124 180.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 73.7 48.1 °C/W
RθJB Junction-to-board thermal resistance 64.4 100.9 °C/W
ψJT Junction-to-top characterization parameter 18 2.4 °C/W
ψJB Junction-to-board characterization parameter 63.9 99.3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — — °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

6.6 Thermal Information: OPA4317

OPA4317
(1)
THERMAL METRIC D (SOIC) PW (TSSOP) UNIT
14 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 83.8 120.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 70.7 34.3 °C/W
RθJB Junction-to-board thermal resistance 59.5 62.8 °C/W
ψJT Junction-to-top characterization parameter 11.6 1 °C/W
ψJB Junction-to-board characterization parameter 37.7 56.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — — °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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6.7 Electrical Characteristics: VS = 1.8 V to 5.5 V

At TA = 25°C, RL = 10 kΩ connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VS = 5 V 20 ±90
VOS Input offset voltage μV
TA = –40°C to +125°C, VS = 5 V ±100
Input offset voltage
dVOS/dT TA = –40°C to +125°C 0.05 μV/°C
vs temperature
Input offset voltage
PSRR TA = –40°C to +125°C, VS = 1.8 V to 5.5 V 1 10 μV/V
vs power supply
Long-term stability (1) See (1)

Channel separation, DC 5 μV/V

INPUT BIAS CURRENT
±275
IB Input bias current OPA4317 ±155 pA
TA = –40°C to +125°C ±300
±400
IOS Input offset current pA
OPA4317 ±140
NOISE
en Input voltage noise density f = 1 kHz 55 nV/√Hz
f = 0.01 Hz to 1 Hz 0.3
Input voltage noise μVPP
f = 0.1 Hz to 10 Hz 1.1
in Input current noise f = 10 Hz 100 fA/√Hz
INPUT VOLTAGE RANGE
VCM Common-mode voltage (V–) – 0.1 (V+) + 0.1 V
TA = –40°C to +125°C
95 108
(V–) – 0.1 V < VCM < (V+) + 0.1 V
CMRR Common-mode rejection ratio OPA4317 dB
TA = –40°C to +125°C 95 108
(V–) – 0.1 V < VCM < (V+) + 0.1 V, VS = 5.5 V
INPUT CAPACITANCE
Differential 2 pF
Common-mode 4 pF
OPEN-LOOP GAIN
TA = –40°C to +125°C, RL = 10 kΩ
AOL Open-loop voltage gain 100 110 dB
(V–) + 100 mV < VO < (V+) – 100 mV
FREQUENCY RESPONSE
GBW Gain-bandwidth product CL = 100 pF 300 kHz
SR Slew rate G=1 0.15 V/μs
OUTPUT
Voltage output swing from rail TA = –40°C to +125°C 30 100 mV
ISC Short-circuit current ±5 mA
CL Capacitive load drive See the Typical Characteristics section
Open-loop output impedance f = 350 kHz, IO = 0 2 kΩ
POWER SUPPLY
VS Specified voltage 1.8 5.5 V
IQ Quiescent current per amplifier TA = –40°C to +125°C, IO = 0 21 35 μA
Turnon time VS = 5 V 100 µs

(1) 300-hour life test at 150°C demonstrated randomly distributed variation of approximately 1 μV.

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6.8 Typical Characteristics

At TA = 25°C, CL = 0 pF, RL = 10 kΩ connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted.

120 250

Open-Loop Voltage Gain (dB)

100 200

80 150
Phase
Population

Phase (°)
60 100

40 50
Gain
20 0

0 -50

-20 -100
10 100 1k 10k 100k 1M
-24.00
-21.00
-18.00
-15.00
-12.00
-9.00
-6.00
-3.00
0
3.00
6.00
9.00
12.00
15.00
18.00
21.00
24.00
Frequency (Hz)

Offset Voltage (mV)

Figure 1. Offset Voltage Production Distribution Figure 2. Open-Loop Gain vs Frequency
140 120
+PSRR
120 100

100 -PSRR
80
CMRR (dB)

PSRR (dB)

80
60
60
40
40

20 20

0 0
1 10 100 1k 10k 100k 1M 1 10 100 1k 10k 100k 1M
Frequency (Hz) Frequency (Hz)

Figure 3. Common-Mode Rejection Ratio vs Frequency Figure 4. Power-Supply Rejection Ratio vs Frequency
3 210
VS = ±2.75V
VS = ±0.9V 205
2
200
Input Bias Current (pA)

-40°C –IB
195
Output Swing (V)

1
+25°C 190
+125°C
0
+25°C
-40°C -190
-1
+125°C -195
+IB
+25°C -200
-2
-205
-40°C
-3 -210
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5
Output Current (mA) Common-Mode Voltage (V)

Figure 5. Output Voltage Swing vs Output Current Figure 6. Input Bias Current vs Common-Mode Voltage

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Typical Characteristics (continued)

At TA = 25°C, CL = 0 pF, RL = 10 kΩ connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted.
250 25
–IB
200 VS = 5.5 V
–IB
150 20
Input Bias Current (pA)

Quiescent Current (µA)

100 VS = 1.8 V
50 15
VS = 5.5 V
0
VS = 1.8 V
-50 10
-100
-150 +IB 5
-200
+IB
-250 0
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Temperature (°C) Temperature (°C)

Figure 7. Input Bias Current vs Temperature Figure 8. Quiescent Current vs Temperature

Output Voltage (50 mV/div)

Output Voltage (1 V/div)

Time (50 µs/div) Time (5 µs/div)

G=1 RL = 10 kΩ G=1 RL = 10 kΩ

Figure 9. Large-Signal Step Response Figure 10. Small-Signal Step Response

2 V/div

0
Input Input
2 V/div

Output 0
1 V/div

Output
1 V/div

Time (50 ms/div) Time (50 ms/div)

See Figure 18 See Figure 18

Figure 11. Positive Overvoltage Recovery Figure 12. Negative Overvoltage Recovery

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Typical Characteristics (continued)

At TA = 25°C, CL = 0 pF, RL = 10 kΩ connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted.
600 40

35
500
30
Settling Time (µs)

400

Overshoot (%)
25

300 20

15
200
0.001% 10
100
5
0.01%
0 0
1 10 100 10 100 1000
Gain (dB) Load Capacitance (pF)
4-V Step

Figure 13. Settling Time vs Closed-Loop Gain Figure 14. Small-Signal Overshoot vs Load Capacitance
1000 1000

Voltage Noise (nV/ÖHz)

Current Noise (fA/ÖHz)

Continues with no 1/f (flicker) noise.
500 nV/div

Current Noise
100 100

Voltage Noise

10 10
1 s/div 1 10 100 1k 10k
Frequency (Hz)

Figure 15. 0.1-Hz to 10-Hz Noise Figure 16. Current and Voltage Noise Spectral Density vs
Frequency
50
Normal Operating Range
40
30
Input Bias Current (uA)

20
10
0
-10
-20
-30
Over-Driven Condition Over-Driven Condition
-40
-50
-1V -800 -600 -400 -200 0 200 400 600 800
Input Differential Voltage (mV)
See the Input Differential Voltage section

Figure 17. Input Bias Current vs

Input Differential Voltage

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7 Parameter Measurement Information

10 kW

2.5 V

1 kW

Device

-2.5 V

Figure 18. Overvoltage Recovery Circuit

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8 Detailed Description

8.1 Overview
The OPAx317 series is a family of low-power, rail-to-rail input and output operational amplifiers. These devices
operate from 1.8 V to 5.5 V, are unity-gain stable, and are suitable for a wide range of general-purpose
applications. The class AB output stage is capable of driving ≤ 10-kΩ loads connected to any point between V+
and ground. The input common-mode voltage range includes both rails and allows the OPA317 series to be used
in virtually any single-supply application. Rail-to-rail input and output swing significantly increases dynamic range,
especially in low-supply applications, and makes them ideal for driving sampling analog-to-digital converters
(ADCs).

8.2 Functional Block Diagram

C2

Notch
CHOP1 GM1 CHOP2 Filter GM2 GM3

+IN OUT

-IN

C1
GM_FF

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8.3 Feature Description

8.3.1 Operating Voltage
The OPA317 series of operational amplifiers can be used with single or dual supplies from an operating range of
VS = 1.8 V (±0.9 V) up to 5.5 V (±2.75 V).

CAUTION
Supply voltages greater than 7 V can permanently damage the device.

See the Absolute Maximum Ratings table. Key parameters that vary over the supply voltage or temperature
range are shown in the Typical Characteristics section.

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Feature Description (continued)

8.3.2 Input Voltage
The OPA317, OPA2317, and OPA4317 input common-mode voltage range extends 0.1 V beyond the supply
rails. The OPA317 device is designed to cover the full range without the troublesome transition region found in
some other rail-to-rail amplifiers.
Typically, input bias current is about 200 pA; however, input voltages exceeding the power supplies can cause
excessive current to flow into or out of the input pins. Momentary voltages greater than the power supply can be
tolerated if the input current is limited to 10 mA. This limitation is easily accomplished with an input resistor, as
shown in Figure 19.

5V

IOVERLOAD
10 mA max
Device VOUT
VIN
5 kW

NOTE: Current limiting resistor required if input voltage exceeds supply rails by ≥ 0.3 V.

Figure 19. Input Current Protection

8.3.3 Input Differential Voltage

The typical input bias current of the OPA317 during normal operation is approximately 200 pA. In overdriven
conditions, the bias current can increase significantly (see Figure 17).The most common cause of an overdriven
condition occurs when the operational amplifier is outside of the linear range of operation. When the output of the
operational amplifier is driven to one of the supply rails, the feedback loop requirements cannot be satisfied, and
a differential input voltage develops across the input pins. This differential input voltage results in activation of
parasitic diodes inside the front-end input chopping switches that combine with 10-kΩ electromagnetic
interference (EMI) filter resistors to create the equivalent circuit shown in Figure 20.

NOTE
The input bias current remains within specification within the linear region.

10 kW Clamp
+IN
CORE
-IN
10 kW

Figure 20. Equivalent Input Circuit

8.3.4 Internal Offset Correction

The OPA317, OPA2317, and OPA4317 operational amplifiers use an auto-calibration technique with a time-
continuous, 125-kHz operational amplifier in the signal path. This amplifier is zero-corrected every 8 μs using a
proprietary technique. Upon power up, the amplifier requires approximately 100 μs to achieve specified VOS
accuracy. This design has no aliasing or flicker noise.

8.3.5 EMI Susceptibility and Input Filtering

Operational amplifiers vary in susceptibility to EMI. If conducted EMI enters the operational amplifier, the DC
offset observed at the amplifier output may shift from its nominal value while the EMI is present. This shift is a
result of signal rectification associated with the internal semiconductor junctions. While all operational amplifier
pin functions can be affected by EMI, the input pins are likely to be the most susceptible. The OPA317
operational amplifier family incorporates an internal input low-pass filter that reduces the amplifier response to
EMI. Both common-mode and differential mode filtering are provided by the input filter. The filter is designed for a
cutoff frequency of approximately 8 MHz (–3 dB), with a roll-off of 20 dB per decade.

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8.4 Device Functional Modes

The OPAx317 family of devices are powered on when the supply is connected. The device can be operated as a
single-supply operational amplifier or a dual-supply amplifier, depending on the application.

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

The OPA317, OPA2317, and OPA4317 are unity-gain stable, precision operational amplifiers free from
unexpected output and phase reversal. Proprietary Zerø-Drift circuitry gives the benefit of low input offset voltage
over time and temperature, as well as lowering the 1/f noise component. As a result of the high PSRR, these
devices work well in applications that run directly from battery power without regulation. The OPA317 family is
optimized for low-voltage, single-supply operation. These miniature, high-precision, low quiescent current
amplifiers offer high impedance inputs that have a common-mode range 100 mV beyond the supplies, and a rail-
to-rail output that swings within 100 mV of the supplies under normal test conditions. The OPA317 series are
precision amplifiers for cost-sensitive applications.

9.1.1 Achieving Output Swing to the Op Amp Negative Rail

Some applications require output voltage swings from 0 V to a positive full-scale voltage (such as 2.5 V) with
excellent accuracy. With most single-supply operational amplifiers, problems arise when the output signal
approaches 0 V, near the lower output swing limit of a single-supply operational amplifier. A good single-supply
operational amplifier may swing close to single-supply ground, but does not reach ground. The output of the
OPA317, OPA2317, and OPA4317 can be made to swing to ground, or slightly below, on a single-supply power
source. To do so requires the use of another resistor and an additional, more negative power supply than the
operational amplifier negative supply. A pulldown resistor can be connected between the output and the
additional negative supply to pull the output down below the value that the output would otherwise achieve, as
shown in Figure 21.
V+ = 5 V

Device VOUT
VIN
RP = 20 kW

Op Amp V- = GND
-5 V
Additional
Negative
Supply

Figure 21. For VOUT Range to Ground

The OPA317, OPA2317, and OPA4317 have an output stage that allows the output voltage to be pulled to its
negative supply rail, or slightly below, using the technique previously described. This technique only works with
some types of output stages. The OPA317, OPA2317, and OPA4317 have been characterized to perform with
this technique; the recommended resistor value is approximately 20 kΩ. This configuration increases the current
consumption by several hundreds of microamps. Accuracy is excellent down to 0 V and as low as –2 mV.
Limiting and nonlinearity occur below –2 mV, but excellent accuracy returns as the output drives back up above
–2 mV. Lowering the resistance of the pulldown resistor allows the operational amplifier to swing even further
below the negative rail. Use resistances as low as 10 kΩ to achieve excellent accuracy down to –10 mV.

Copyright © 2013–2016, Texas Instruments Incorporated Submit Documentation Feedback 15

Product Folder Links: OPA317 OPA2317 OPA4317
OPA317, OPA2317, OPA4317
SBOS682B – MAY 2013 – REVISED JUNE 2016 www.ti.com

9.2 Typical Applications

The circuit shown in Figure 22 is a high-side voltage-to-current (V-I) converter. It translates an input voltage of
0 V to 2 V to an output current of 0 mA to 100 mA. Figure 23 shows the measured transfer function for this
circuit. The low offset voltage and offset drift of the OPA317 facilitate excellent DC accuracy for the circuit.

V+

RS2 IRS2 RS3 IRS3

470 4.7
VRS2 10 k R4 VRS3
C7
2200 pF

R5
A2
+ Q2
V+ 330

+ 200 Q1
A1
R3
+
VIN
± 1000 pF
C6
10 k VRS1 VLOAD
R2
RS1 IRS1 RLOAD ILOAD
2k

Copyright © 2016, Texas Instruments Incorporated

Figure 22. High-Side Voltage-to-Current (V-I) Converter

9.2.1 Design Requirements

The design requirements are as follows:
• Supply Voltage: 5-V DC
• Input: 0-V to 2-V DC
• Output: 0-mA to 100-mA DC

9.2.2 Detailed Design Procedure

The V-I transfer function of the circuit is based on the relationship between the input voltage, VIN, and the three
current-sensing resistors: RS1, RS2, and RS3. The relationship between VIN and RS1 determines the current that
flows through the first stage of the design. The current gain from the first stage to the second stage is based on
the relationship between RS2 and RS3.

16 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated

Product Folder Links: OPA317 OPA2317 OPA4317

 OPA317, OPA2317, OPA4317
www.ti.com SBOS682B – MAY 2013 – REVISED JUNE 2016

Typical Applications (continued)

For a successful design, pay close attention to the DC characteristics of the operational amplifier chosen for the
application. To meet the performance goals, this application benefits from an operational amplifier with low offset
voltage, low temperature drift, and rail-to-rail output. The OPA2317 CMOS operational amplifier is a high-
precision, 5-µV offset, 0.05-μV/°C drift amplifier optimized for low-voltage, single-supply operation with an output
swing to within 50 mV of the positive rail. The OPA2317 family uses chopping techniques to provide low initial
offset voltage and near-zero drift over time and temperature. Low offset voltage and low drift reduce the offset
error in the system, making these devices appropriate for precise DC control. The rail-to-rail output stage of the
OPA2317 ensures that the output swing of the operational amplifier is able to fully control the gate of the
MOSFET devices within the supply rails.

9.2.3 Application Curve

0.1
Load

0.075
Output Current (A)

0.05

0.025

0
0 0.5 1 1.5 2
Input Voltage (V) D001

Figure 23. Measured Transfer Function for High-Side V-I Converter

Copyright © 2013–2016, Texas Instruments Incorporated Submit Documentation Feedback 17

Product Folder Links: OPA317 OPA2317 OPA4317
OPA317, OPA2317, OPA4317
SBOS682B – MAY 2013 – REVISED JUNE 2016 www.ti.com

9.3 System Example

RN are operational resistors used to isolate the ADS1100 from the noise of the digital I2C bus. The ADS1100
device is a 16-bit converter; therefore, a precise reference is essential for maximum accuracy. If absolute
accuracy is not required and the 5-V power supply is sufficiently stable, the REF3130 device may be omitted.
3V
+5 V REF3130
Load
R1 R2
4.99 kW 49.9 kW

R6
71.5 kW RN
V 56 W
ILOAD RSHUNT
Device
1W
R3 R4 ADS1100 RN 2
IC
4.99 kW 48.7 kW 56 W

Stray Ground-Loop Resistance R7 (PGA Gain = 4)

1.18 kW FS = 3.0 V

Copyright © 2016, Texas Instruments Incorporated

NOTE: 1% resistors provide adequate common-mode rejection at small ground-loop errors.

Figure 24. Low-Side Current Monitor

10 Power Supply Recommendations

The OPAx317 device is specified for operation from 1.8 V to 5.5 V (±0.9 V to ±2.75 V); many specifications apply
from –40°C to +125°C. The Electrical Characteristics: VS = 1.8 V to 5.5 V table presents parameters that can
exhibit significant variance with regard to operating voltage or temperature.

CAUTION
Supply voltages larger than 7 V can permanently damage the device (see the Absolute
Maximum Ratings) table.

Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, see the Layout
Guidelines section.

18 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated

Product Folder Links: OPA317 OPA2317 OPA4317

 OPA317, OPA2317, OPA4317
www.ti.com SBOS682B – MAY 2013 – REVISED JUNE 2016

11 Layout

11.1 Layout Guidelines

Attention to good layout practice is always recommended. Keep traces short and, when possible, use a printed-
circuit board (PCB) ground plane with surface-mount components placed as close to the device pins as possible.
Place a 0.1-μF capacitor closely across the supply pins. Apply these guidelines throughout the analog circuit to
improve performance and provide benefits, such as reducing the electromagnetic interference (EMI)
susceptibility.
Optimize circuit layout and mechanical conditions for lowest offset voltage and precision performance. Avoid
temperature gradients that create thermoelectric (Seebeck) effects in the thermocouple junctions formed from
connecting dissimilar conductors. These thermally-generated potentials can be made to cancel by assuring they
are equal on both input terminals. Other layout and design considerations include:
• Use low thermoelectric-coefficient conditions (avoid dissimilar metals).
• Thermally isolate components from power supplies or other heat sources.
• Shield operational amplifier and input circuitry from air currents, such as cooling fans.
Following these guidelines reduces the likelihood of junctions being at different temperatures, which can cause
thermoelectric voltage drift of 0.1 μV/°C or higher, depending on the materials used.

11.2 Layout Example

VS+

VOUT

VS± OUT V+ GND

V±
Use a low-ESR,
Use a low-ESR,
ceramic bypass
ceramic bypass
capacitor.
capacitor. RG
VIN +IN ±IN GND
GND

Run the input traces

as far away from
the supply lines RF Place components
as possible. close to the device
and to each other to
reduce parasitic
errors.

Copyright © 2016, Texas Instruments Incorporated

Figure 25. OPAx317 Layout Example

Copyright © 2013–2016, Texas Instruments Incorporated Submit Documentation Feedback 19

Product Folder Links: OPA317 OPA2317 OPA4317
OPA317, OPA2317, OPA4317
SBOS682B – MAY 2013 – REVISED JUNE 2016 www.ti.com

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation
For related documentation see the following:
• Self-Calibrating, 16-Bit Analog-to-Digital Converter,
• 15ppm/°C Max, 100μA, SOT23-3 Series Voltage Reference,

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

12.3 Related Links

Table 1 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.

Table 1. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
OPA317 Click here Click here Click here Click here Click here
OPA2317 Click here Click here Click here Click here Click here
OPA4317 Click here Click here Click here Click here Click here

12.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

20 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated

Product Folder Links: OPA317 OPA2317 OPA4317

 OPA317, OPA2317, OPA4317
www.ti.com SBOS682B – MAY 2013 – REVISED JUNE 2016

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2013–2016, Texas Instruments Incorporated Submit Documentation Feedback 21

Product Folder Links: OPA317 OPA2317 OPA4317
 PACKAGE OPTION ADDENDUM

www.ti.com 29-Oct-2015

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

OPA2317ID ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 O2317A
& no Sb/Br)
OPA2317IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM -40 to 125 OVBQ
& no Sb/Br)
OPA2317IDGKT ACTIVE VSSOP DGK 8 250 Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM -40 to 125 OVBQ
& no Sb/Br)
OPA2317IDR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 O2317A
& no Sb/Br)
OPA317ID ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 O317A
& no Sb/Br)
OPA317IDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 OVCQ
& no Sb/Br)
OPA317IDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 OVCQ
& no Sb/Br)
OPA317IDCKR ACTIVE SC70 DCK 5 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 SJP
& no Sb/Br)
OPA317IDCKT ACTIVE SC70 DCK 5 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 SJP
& no Sb/Br)
OPA317IDR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 O317A
& no Sb/Br)
OPA4317ID ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 O4317A
& no Sb/Br)
OPA4317IDR ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 O4317A
& no Sb/Br)
OPA4317IPW ACTIVE TSSOP PW 14 90 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 O4317A
& no Sb/Br)
OPA4317IPWR ACTIVE TSSOP PW 14 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 O4317A
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 29-Oct-2015

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 27-Sep-2017

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA2317IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
OPA2317IDGKT VSSOP DGK 8 250 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
OPA2317IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA317IDBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
OPA317IDBVT SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
OPA317IDCKR SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
OPA317IDCKT SC70 DCK 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
OPA317IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA4317IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
OPA4317IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 27-Sep-2017

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OPA2317IDGKR VSSOP DGK 8 2500 364.0 364.0 27.0
OPA2317IDGKT VSSOP DGK 8 250 364.0 364.0 27.0
OPA2317IDR SOIC D 8 2500 367.0 367.0 35.0
OPA317IDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
OPA317IDBVT SOT-23 DBV 5 250 180.0 180.0 18.0
OPA317IDCKR SC70 DCK 5 3000 180.0 180.0 18.0
OPA317IDCKT SC70 DCK 5 250 180.0 180.0 18.0
OPA317IDR SOIC D 8 2500 367.0 367.0 35.0
OPA4317IDR SOIC D 14 2500 367.0 367.0 38.0
OPA4317IPWR TSSOP PW 14 2000 367.0 367.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DBV0005A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

C
3.0
2.6 0.1 C
1.75
B A 1.45 MAX
1.45
PIN 1
INDEX AREA

1 5

2X 0.95
3.05
2.75
1.9 1.9
2

4
3
0.5
5X
0.3
0.15
0.2 C A B (1.1) TYP
0.00

0.25
GAGE PLANE 0.22
TYP
0.08

8
TYP 0.6
0 TYP SEATING PLANE
0.3

4214839/C 04/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.

www.ti.com
 EXAMPLE BOARD LAYOUT
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
(1.9)
2
2X (0.95)

3 4

(R0.05) TYP (2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214839/C 04/2017

NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
2 (1.9)
2X(0.95)

3 4

(R0.05) TYP
(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X

4214839/C 04/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
DBV0005A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

C
3.0
2.6 0.1 C
1.75
B A 1.45 MAX
1.45
PIN 1
INDEX AREA

1 5

2X 0.95
3.05
2.75
1.9 1.9
2

4
3
0.5
5X
0.3
0.15
0.2 C A B (1.1) TYP
0.00

0.25
GAGE PLANE 0.22
TYP
0.08

8
TYP 0.6
0 TYP SEATING PLANE
0.3

4214839/C 04/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.

www.ti.com
 EXAMPLE BOARD LAYOUT
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
(1.9)
2
2X (0.95)

3 4

(R0.05) TYP (2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214839/C 04/2017

NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
2 (1.9)
2X(0.95)

3 4

(R0.05) TYP
(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X

4214839/C 04/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.

www.ti.com
 IMPORTANT NOTICE

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